drivers/spi/spi-falcon.c

   1 /*
   2  *  This program is free software; you can redistribute it and/or modify it
   3  *  under the terms of the GNU General Public License version 2 as published
   4  *  by the Free Software Foundation.
   5  *
   6  *  Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
   7  */
   8
   9 #include <linux/module.h>
  10 #include <linux/device.h>
  11 #include <linux/platform_device.h>
  12 #include <linux/spi/spi.h>
  13 #include <linux/delay.h>
  14 #include <linux/of.h>
  15 #include <linux/of_platform.h>
  16
  17 #include <lantiq_soc.h>
  18
  19 #define DRV_NAME                "sflash-falcon"
  20
  21 #define FALCON_SPI_XFER_BEGIN   (1 << 0)
  22 #define FALCON_SPI_XFER_END     (1 << 1)
  23
  24 /* Bus Read Configuration Register0 */
  25 #define BUSRCON0                0x00000010
  26 /* Bus Write Configuration Register0 */
  27 #define BUSWCON0                0x00000018
  28 /* Serial Flash Configuration Register */
  29 #define SFCON                   0x00000080
  30 /* Serial Flash Time Register */
  31 #define SFTIME                  0x00000084
  32 /* Serial Flash Status Register */
  33 #define SFSTAT                  0x00000088
  34 /* Serial Flash Command Register */
  35 #define SFCMD                   0x0000008C
  36 /* Serial Flash Address Register */
  37 #define SFADDR                  0x00000090
  38 /* Serial Flash Data Register */
  39 #define SFDATA                  0x00000094
  40 /* Serial Flash I/O Control Register */
  41 #define SFIO                    0x00000098
  42 /* EBU Clock Control Register */
  43 #define EBUCC                   0x000000C4
  44
  45 /* Dummy Phase Length */
  46 #define SFCMD_DUMLEN_OFFSET     16
  47 #define SFCMD_DUMLEN_MASK       0x000F0000
  48 /* Chip Select */
  49 #define SFCMD_CS_OFFSET         24
  50 #define SFCMD_CS_MASK           0x07000000
  51 /* field offset */
  52 #define SFCMD_ALEN_OFFSET       20
  53 #define SFCMD_ALEN_MASK         0x00700000
  54 /* SCK Rise-edge Position */
  55 #define SFTIME_SCKR_POS_OFFSET  8
  56 #define SFTIME_SCKR_POS_MASK    0x00000F00
  57 /* SCK Period */
  58 #define SFTIME_SCK_PER_OFFSET   0
  59 #define SFTIME_SCK_PER_MASK     0x0000000F
  60 /* SCK Fall-edge Position */
  61 #define SFTIME_SCKF_POS_OFFSET  12
  62 #define SFTIME_SCKF_POS_MASK    0x0000F000
  63 /* Device Size */
  64 #define SFCON_DEV_SIZE_A23_0    0x03000000
  65 #define SFCON_DEV_SIZE_MASK     0x0F000000
  66 /* Read Data Position */
  67 #define SFTIME_RD_POS_MASK      0x000F0000
  68 /* Data Output */
  69 #define SFIO_UNUSED_WD_MASK     0x0000000F
  70 /* Command Opcode mask */
  71 #define SFCMD_OPC_MASK          0x000000FF
  72 /* dlen bytes of data to write */
  73 #define SFCMD_DIR_WRITE         0x00000100
  74 /* Data Length offset */
  75 #define SFCMD_DLEN_OFFSET       9
  76 /* Command Error */
  77 #define SFSTAT_CMD_ERR          0x20000000
  78 /* Access Command Pending */
  79 #define SFSTAT_CMD_PEND         0x00400000
  80 /* Frequency set to 100MHz. */
  81 #define EBUCC_EBUDIV_SELF100    0x00000001
  82 /* Serial Flash */
  83 #define BUSRCON0_AGEN_SERIAL_FLASH      0xF0000000
  84 /* 8-bit multiplexed */
  85 #define BUSRCON0_PORTW_8_BIT_MUX        0x00000000
  86 /* Serial Flash */
  87 #define BUSWCON0_AGEN_SERIAL_FLASH      0xF0000000
  88 /* Chip Select after opcode */
  89 #define SFCMD_KEEP_CS_KEEP_SELECTED     0x00008000
  90
  91 #define CLOCK_100M      100000000
  92 #define CLOCK_50M       50000000
  93
  94 struct falcon_sflash {
  95         u32 sfcmd; /* for caching of opcode, direction, ... */
  96         struct spi_master *master;
  97 };
  98
  99 int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
 100                 unsigned long flags)
 101 {
 102         struct device *dev = &spi->dev;
 103         struct falcon_sflash *priv = spi_master_get_devdata(spi->master);
 104         const u8 *txp = t->tx_buf;
 105         u8 *rxp = t->rx_buf;
 106         unsigned int bytelen = ((8 * t->len + 7) / 8);
 107         unsigned int len, alen, dumlen;
 108         u32 val;
 109         enum {
 110                 state_init,
 111                 state_command_prepare,
 112                 state_write,
 113                 state_read,
 114                 state_disable_cs,
 115                 state_end
 116         } state = state_init;
 117
 118         do {
 119                 switch (state) {
 120                 case state_init: /* detect phase of upper layer sequence */
 121                 {
 122                         /* initial write ? */
 123                         if (flags & FALCON_SPI_XFER_BEGIN) {
 124                                 if (!txp) {
 125                                         dev_err(dev,
 126                                                 "BEGIN without tx data!\n");
 127                                         return -ENODATA;
 128                                 }
 129                                 /*
 130                                  * Prepare the parts of the sfcmd register,
 131                                  * which should not change during a sequence!
 132                                  * Only exception are the length fields,
 133                                  * especially alen and dumlen.
 134                                  */
 135
 136                                 priv->sfcmd = ((spi->chip_select
 137                                                 << SFCMD_CS_OFFSET)
 138                                                & SFCMD_CS_MASK);
 139                                 priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
 140                                 priv->sfcmd |= *txp;
 141                                 txp++;
 142                                 bytelen--;
 143                                 if (bytelen) {
 144                                         /*
 145                                          * more data:
 146                                          * maybe address and/or dummy
 147                                          */
 148                                         state = state_command_prepare;
 149                                         break;
 150                                 } else {
 151                                         dev_dbg(dev, "write cmd %02X\n",
 152                                                 priv->sfcmd & SFCMD_OPC_MASK);
 153                                 }
 154                         }
 155                         /* continued write ? */
 156                         if (txp && bytelen) {
 157                                 state = state_write;
 158                                 break;
 159                         }
 160                         /* read data? */
 161                         if (rxp && bytelen) {
 162                                 state = state_read;
 163                                 break;
 164                         }
 165                         /* end of sequence? */
 166                         if (flags & FALCON_SPI_XFER_END)
 167                                 state = state_disable_cs;
 168                         else
 169                                 state = state_end;
 170                         break;
 171                 }
 172                 /* collect tx data for address and dummy phase */
 173                 case state_command_prepare:
 174                 {
 175                         /* txp is valid, already checked */
 176                         val = 0;
 177                         alen = 0;
 178                         dumlen = 0;
 179                         while (bytelen > 0) {
 180                                 if (alen < 3) {
 181                                         val = (val << 8) | (*txp++);
 182                                         alen++;
 183                                 } else if ((dumlen < 15) && (*txp == 0)) {
 184                                         /*
 185                                          * assume dummy bytes are set to 0
 186                                          * from upper layer
 187                                          */
 188                                         dumlen++;
 189                                         txp++;
 190                                 } else {
 191                                         break;
 192                                 }
 193                                 bytelen--;
 194                         }
 195                         priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
 196                         priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
 197                                          (dumlen << SFCMD_DUMLEN_OFFSET);
 198                         if (alen > 0)
 199                                 ltq_ebu_w32(val, SFADDR);
 200
 201                         dev_dbg(dev, "wr %02X, alen=%d (addr=%06X) dlen=%d\n",
 202                                 priv->sfcmd & SFCMD_OPC_MASK,
 203                                 alen, val, dumlen);
 204
 205                         if (bytelen > 0) {
 206                                 /* continue with write */
 207                                 state = state_write;
 208                         } else if (flags & FALCON_SPI_XFER_END) {
 209                                 /* end of sequence? */
 210                                 state = state_disable_cs;
 211                         } else {
 212                                 /*
 213                                  * go to end and expect another
 214                                  * call (read or write)
 215                                  */
 216                                 state = state_end;
 217                         }
 218                         break;
 219                 }
 220                 case state_write:
 221                 {
 222                         /* txp still valid */
 223                         priv->sfcmd |= SFCMD_DIR_WRITE;
 224                         len = 0;
 225                         val = 0;
 226                         do {
 227                                 if (bytelen--)
 228                                         val |= (*txp++) << (8 * len++);
 229                                 if ((flags & FALCON_SPI_XFER_END)
 230                                     && (bytelen == 0)) {
 231                                         priv->sfcmd &=
 232                                                 ~SFCMD_KEEP_CS_KEEP_SELECTED;
 233                                 }
 234                                 if ((len == 4) || (bytelen == 0)) {
 235                                         ltq_ebu_w32(val, SFDATA);
 236                                         ltq_ebu_w32(priv->sfcmd
 237                                                 | (len<<SFCMD_DLEN_OFFSET),
 238                                                 SFCMD);
 239                                         len = 0;
 240                                         val = 0;
 241                                         priv->sfcmd &= ~(SFCMD_ALEN_MASK
 242                                                          | SFCMD_DUMLEN_MASK);
 243                                 }
 244                         } while (bytelen);
 245                         state = state_end;
 246                         break;
 247                 }
 248                 case state_read:
 249                 {
 250                         /* read data */
 251                         priv->sfcmd &= ~SFCMD_DIR_WRITE;
 252                         do {
 253                                 if ((flags & FALCON_SPI_XFER_END)
 254                                     && (bytelen <= 4)) {
 255                                         priv->sfcmd &=
 256                                                 ~SFCMD_KEEP_CS_KEEP_SELECTED;
 257                                 }
 258                                 len = (bytelen > 4) ? 4 : bytelen;
 259                                 bytelen -= len;
 260                                 ltq_ebu_w32(priv->sfcmd
 261                                         | (len << SFCMD_DLEN_OFFSET), SFCMD);
 262                                 priv->sfcmd &= ~(SFCMD_ALEN_MASK
 263                                                  | SFCMD_DUMLEN_MASK);
 264                                 do {
 265                                         val = ltq_ebu_r32(SFSTAT);
 266                                         if (val & SFSTAT_CMD_ERR) {
 267                                                 /* reset error status */
 268                                                 dev_err(dev, "SFSTAT: CMD_ERR");
 269                                                 dev_err(dev, " (%x)\n", val);
 270                                                 ltq_ebu_w32(SFSTAT_CMD_ERR,
 271                                                         SFSTAT);
 272                                                 return -EBADE;
 273                                         }
 274                                 } while (val & SFSTAT_CMD_PEND);
 275                                 val = ltq_ebu_r32(SFDATA);
 276                                 do {
 277                                         *rxp = (val & 0xFF);
 278                                         rxp++;
 279                                         val >>= 8;
 280                                         len--;
 281                                 } while (len);
 282                         } while (bytelen);
 283                         state = state_end;
 284                         break;
 285                 }
 286                 case state_disable_cs:
 287                 {
 288                         priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
 289                         ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
 290                                 SFCMD);
 291                         val = ltq_ebu_r32(SFSTAT);
 292                         if (val & SFSTAT_CMD_ERR) {
 293                                 /* reset error status */
 294                                 dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
 295                                 ltq_ebu_w32(SFSTAT_CMD_ERR, SFSTAT);
 296                                 return -EBADE;
 297                         }
 298                         state = state_end;
 299                         break;
 300                 }
 301                 case state_end:
 302                         break;
 303                 }
 304         } while (state != state_end);
 305
 306         return 0;
 307 }
 308
 309 static int falcon_sflash_setup(struct spi_device *spi)
 310 {
 311         unsigned int i;
 312         unsigned long flags;
 313
 314         spin_lock_irqsave(&ebu_lock, flags);
 315
 316         if (spi->max_speed_hz >= CLOCK_100M) {
 317                 /* set EBU clock to 100 MHz */
 318                 ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, EBUCC);
 319                 i = 1; /* divider */
 320         } else {
 321                 /* set EBU clock to 50 MHz */
 322                 ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, EBUCC);
 323
 324                 /* search for suitable divider */
 325                 for (i = 1; i < 7; i++) {
 326                         if (CLOCK_50M / i <= spi->max_speed_hz)
 327                                 break;
 328                 }
 329         }
 330
 331         /* setup period of serial clock */
 332         ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
 333                      | SFTIME_SCKR_POS_MASK
 334                      | SFTIME_SCK_PER_MASK,
 335                      (i << SFTIME_SCKR_POS_OFFSET)
 336                      | (i << (SFTIME_SCK_PER_OFFSET + 1)),
 337                      SFTIME);
 338
 339         /*
 340          * set some bits of unused_wd, to not trigger HOLD/WP
 341          * signals on non QUAD flashes
 342          */
 343         ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), SFIO);
 344
 345         ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
 346                         BUSRCON0);
 347         ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, BUSWCON0);
 348         /* set address wrap around to maximum for 24-bit addresses */
 349         ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, SFCON);
 350
 351         spin_unlock_irqrestore(&ebu_lock, flags);
 352
 353         return 0;
 354 }
 355
 356 static int falcon_sflash_prepare_xfer(struct spi_master *master)
 357 {
 358         return 0;
 359 }
 360
 361 static int falcon_sflash_unprepare_xfer(struct spi_master *master)
 362 {
 363         return 0;
 364 }
 365
 366 static int falcon_sflash_xfer_one(struct spi_master *master,
 367                                         struct spi_message *m)
 368 {
 369         struct falcon_sflash *priv = spi_master_get_devdata(master);
 370         struct spi_transfer *t;
 371         unsigned long spi_flags;
 372         unsigned long flags;
 373         int ret = 0;
 374
 375         priv->sfcmd = 0;
 376         m->actual_length = 0;
 377
 378         spi_flags = FALCON_SPI_XFER_BEGIN;
 379         list_for_each_entry(t, &m->transfers, transfer_list) {
 380                 if (list_is_last(&t->transfer_list, &m->transfers))
 381                         spi_flags |= FALCON_SPI_XFER_END;
 382
 383                 spin_lock_irqsave(&ebu_lock, flags);
 384                 ret = falcon_sflash_xfer(m->spi, t, spi_flags);
 385                 spin_unlock_irqrestore(&ebu_lock, flags);
 386
 387                 if (ret)
 388                         break;
 389
 390                 m->actual_length += t->len;
 391
 392                 WARN_ON(t->delay_usecs || t->cs_change);
 393                 spi_flags = 0;
 394         }
 395
 396         m->status = ret;
 397         spi_finalize_current_message(master);
 398
 399         return 0;
 400 }
 401
 402 static int falcon_sflash_probe(struct platform_device *pdev)
 403 {
 404         struct falcon_sflash *priv;
 405         struct spi_master *master;
 406         int ret;
 407
 408         if (ltq_boot_select() != BS_SPI) {
 409                 dev_err(&pdev->dev, "invalid bootstrap options\n");
 410                 return -ENODEV;
 411         }
 412
 413         master = spi_alloc_master(&pdev->dev, sizeof(*priv));
 414         if (!master)
 415                 return -ENOMEM;
 416
 417         priv = spi_master_get_devdata(master);
 418         priv->master = master;
 419
 420         master->mode_bits = SPI_MODE_3;
 421         master->flags = SPI_MASTER_HALF_DUPLEX;
 422         master->setup = falcon_sflash_setup;
 423         master->prepare_transfer_hardware = falcon_sflash_prepare_xfer;
 424         master->transfer_one_message = falcon_sflash_xfer_one;
 425         master->unprepare_transfer_hardware = falcon_sflash_unprepare_xfer;
 426         master->dev.of_node = pdev->dev.of_node;
 427
 428         ret = devm_spi_register_master(&pdev->dev, master);
 429         if (ret)
 430                 spi_master_put(master);
 431         return ret;
 432 }
 433
 434 static const struct of_device_id falcon_sflash_match[] = {
 435         { .compatible = "lantiq,sflash-falcon" },
 436         {},
 437 };
 438 MODULE_DEVICE_TABLE(of, falcon_sflash_match);
 439
 440 static struct platform_driver falcon_sflash_driver = {
 441         .probe  = falcon_sflash_probe,
 442         .driver = {
 443                 .name   = DRV_NAME,
 444                 .owner  = THIS_MODULE,
 445                 .of_match_table = falcon_sflash_match,
 446         }
 447 };
 448
 449 module_platform_driver(falcon_sflash_driver);
 450
 451 MODULE_LICENSE("GPL");
 452 MODULE_DESCRIPTION("Lantiq Falcon SPI/SFLASH controller driver");