2 * linux/arch/unicore32/kernel/irq.c
4 * Code specific to PKUnity SoC and UniCore ISA
6 * Copyright (C) 2001-2010 GUAN Xue-tao
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/signal.h>
15 #include <linux/ioport.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
18 #include <linux/random.h>
19 #include <linux/smp.h>
20 #include <linux/init.h>
21 #include <linux/seq_file.h>
22 #include <linux/errno.h>
23 #include <linux/list.h>
24 #include <linux/kallsyms.h>
25 #include <linux/proc_fs.h>
26 #include <linux/syscore_ops.h>
27 #include <linux/gpio.h>
29 #include <mach/hardware.h>
34 * PKUnity GPIO edge detection for IRQs:
35 * IRQs are generated on Falling-Edge, Rising-Edge, or both.
36 * Use this instead of directly setting GRER/GFER.
38 static int GPIO_IRQ_rising_edge
;
39 static int GPIO_IRQ_falling_edge
;
40 static int GPIO_IRQ_mask
= 0;
42 #define GPIO_MASK(irq) (1 << (irq - IRQ_GPIO0))
44 static int puv3_gpio_type(struct irq_data
*d
, unsigned int type
)
48 if (d
->irq
< IRQ_GPIOHIGH
)
51 mask
= GPIO_MASK(d
->irq
);
53 if (type
== IRQ_TYPE_PROBE
) {
54 if ((GPIO_IRQ_rising_edge
| GPIO_IRQ_falling_edge
) & mask
)
56 type
= IRQ_TYPE_EDGE_RISING
| IRQ_TYPE_EDGE_FALLING
;
59 if (type
& IRQ_TYPE_EDGE_RISING
)
60 GPIO_IRQ_rising_edge
|= mask
;
62 GPIO_IRQ_rising_edge
&= ~mask
;
63 if (type
& IRQ_TYPE_EDGE_FALLING
)
64 GPIO_IRQ_falling_edge
|= mask
;
66 GPIO_IRQ_falling_edge
&= ~mask
;
68 writel(GPIO_IRQ_rising_edge
& GPIO_IRQ_mask
, GPIO_GRER
);
69 writel(GPIO_IRQ_falling_edge
& GPIO_IRQ_mask
, GPIO_GFER
);
75 * GPIO IRQs must be acknowledged. This is for IRQs from 0 to 7.
77 static void puv3_low_gpio_ack(struct irq_data
*d
)
79 writel((1 << d
->irq
), GPIO_GEDR
);
82 static void puv3_low_gpio_mask(struct irq_data
*d
)
84 writel(readl(INTC_ICMR
) & ~(1 << d
->irq
), INTC_ICMR
);
87 static void puv3_low_gpio_unmask(struct irq_data
*d
)
89 writel(readl(INTC_ICMR
) | (1 << d
->irq
), INTC_ICMR
);
92 static int puv3_low_gpio_wake(struct irq_data
*d
, unsigned int on
)
95 writel(readl(PM_PWER
) | (1 << d
->irq
), PM_PWER
);
97 writel(readl(PM_PWER
) & ~(1 << d
->irq
), PM_PWER
);
101 static struct irq_chip puv3_low_gpio_chip
= {
103 .irq_ack
= puv3_low_gpio_ack
,
104 .irq_mask
= puv3_low_gpio_mask
,
105 .irq_unmask
= puv3_low_gpio_unmask
,
106 .irq_set_type
= puv3_gpio_type
,
107 .irq_set_wake
= puv3_low_gpio_wake
,
111 * IRQ8 (GPIO0 through 27) handler. We enter here with the
112 * irq_controller_lock held, and IRQs disabled. Decode the IRQ
113 * and call the handler.
115 static void puv3_gpio_handler(struct irq_desc
*desc
)
117 unsigned int mask
, irq
;
119 mask
= readl(GPIO_GEDR
);
122 * clear down all currently active IRQ sources.
123 * We will be processing them all.
125 writel(mask
, GPIO_GEDR
);
130 generic_handle_irq(irq
);
134 mask
= readl(GPIO_GEDR
);
139 * GPIO0-27 edge IRQs need to be handled specially.
140 * In addition, the IRQs are all collected up into one bit in the
141 * interrupt controller registers.
143 static void puv3_high_gpio_ack(struct irq_data
*d
)
145 unsigned int mask
= GPIO_MASK(d
->irq
);
147 writel(mask
, GPIO_GEDR
);
150 static void puv3_high_gpio_mask(struct irq_data
*d
)
152 unsigned int mask
= GPIO_MASK(d
->irq
);
154 GPIO_IRQ_mask
&= ~mask
;
156 writel(readl(GPIO_GRER
) & ~mask
, GPIO_GRER
);
157 writel(readl(GPIO_GFER
) & ~mask
, GPIO_GFER
);
160 static void puv3_high_gpio_unmask(struct irq_data
*d
)
162 unsigned int mask
= GPIO_MASK(d
->irq
);
164 GPIO_IRQ_mask
|= mask
;
166 writel(GPIO_IRQ_rising_edge
& GPIO_IRQ_mask
, GPIO_GRER
);
167 writel(GPIO_IRQ_falling_edge
& GPIO_IRQ_mask
, GPIO_GFER
);
170 static int puv3_high_gpio_wake(struct irq_data
*d
, unsigned int on
)
173 writel(readl(PM_PWER
) | PM_PWER_GPIOHIGH
, PM_PWER
);
175 writel(readl(PM_PWER
) & ~PM_PWER_GPIOHIGH
, PM_PWER
);
179 static struct irq_chip puv3_high_gpio_chip
= {
181 .irq_ack
= puv3_high_gpio_ack
,
182 .irq_mask
= puv3_high_gpio_mask
,
183 .irq_unmask
= puv3_high_gpio_unmask
,
184 .irq_set_type
= puv3_gpio_type
,
185 .irq_set_wake
= puv3_high_gpio_wake
,
189 * We don't need to ACK IRQs on the PKUnity unless they're GPIOs
190 * this is for internal IRQs i.e. from 8 to 31.
192 static void puv3_mask_irq(struct irq_data
*d
)
194 writel(readl(INTC_ICMR
) & ~(1 << d
->irq
), INTC_ICMR
);
197 static void puv3_unmask_irq(struct irq_data
*d
)
199 writel(readl(INTC_ICMR
) | (1 << d
->irq
), INTC_ICMR
);
203 * Apart form GPIOs, only the RTC alarm can be a wakeup event.
205 static int puv3_set_wake(struct irq_data
*d
, unsigned int on
)
207 if (d
->irq
== IRQ_RTCAlarm
) {
209 writel(readl(PM_PWER
) | PM_PWER_RTC
, PM_PWER
);
211 writel(readl(PM_PWER
) & ~PM_PWER_RTC
, PM_PWER
);
217 static struct irq_chip puv3_normal_chip
= {
218 .name
= "PKUnity-v3",
219 .irq_ack
= puv3_mask_irq
,
220 .irq_mask
= puv3_mask_irq
,
221 .irq_unmask
= puv3_unmask_irq
,
222 .irq_set_wake
= puv3_set_wake
,
225 static struct resource irq_resource
= {
227 .start
= io_v2p(PKUNITY_INTC_BASE
),
228 .end
= io_v2p(PKUNITY_INTC_BASE
) + 0xFFFFF,
231 static struct puv3_irq_state
{
238 static int puv3_irq_suspend(void)
240 struct puv3_irq_state
*st
= &puv3_irq_state
;
243 st
->icmr
= readl(INTC_ICMR
);
244 st
->iclr
= readl(INTC_ICLR
);
245 st
->iccr
= readl(INTC_ICCR
);
248 * Disable all GPIO-based interrupts.
250 writel(readl(INTC_ICMR
) & ~(0x1ff), INTC_ICMR
);
253 * Set the appropriate edges for wakeup.
255 writel(readl(PM_PWER
) & GPIO_IRQ_rising_edge
, GPIO_GRER
);
256 writel(readl(PM_PWER
) & GPIO_IRQ_falling_edge
, GPIO_GFER
);
259 * Clear any pending GPIO interrupts.
261 writel(readl(GPIO_GEDR
), GPIO_GEDR
);
266 static void puv3_irq_resume(void)
268 struct puv3_irq_state
*st
= &puv3_irq_state
;
271 writel(st
->iccr
, INTC_ICCR
);
272 writel(st
->iclr
, INTC_ICLR
);
274 writel(GPIO_IRQ_rising_edge
& GPIO_IRQ_mask
, GPIO_GRER
);
275 writel(GPIO_IRQ_falling_edge
& GPIO_IRQ_mask
, GPIO_GFER
);
277 writel(st
->icmr
, INTC_ICMR
);
281 static struct syscore_ops puv3_irq_syscore_ops
= {
282 .suspend
= puv3_irq_suspend
,
283 .resume
= puv3_irq_resume
,
286 static int __init
puv3_irq_init_syscore(void)
288 register_syscore_ops(&puv3_irq_syscore_ops
);
292 device_initcall(puv3_irq_init_syscore
);
294 void __init
init_IRQ(void)
298 request_resource(&iomem_resource
, &irq_resource
);
300 /* disable all IRQs */
301 writel(0, INTC_ICMR
);
303 /* all IRQs are IRQ, not REAL */
304 writel(0, INTC_ICLR
);
306 /* clear all GPIO edge detects */
307 writel(FMASK(8, 0) & ~FIELD(1, 1, GPI_SOFF_REQ
), GPIO_GPIR
);
308 writel(0, GPIO_GFER
);
309 writel(0, GPIO_GRER
);
310 writel(0x0FFFFFFF, GPIO_GEDR
);
312 writel(1, INTC_ICCR
);
314 for (irq
= 0; irq
< IRQ_GPIOHIGH
; irq
++) {
315 irq_set_chip(irq
, &puv3_low_gpio_chip
);
316 irq_set_handler(irq
, handle_edge_irq
);
317 irq_modify_status(irq
,
318 IRQ_NOREQUEST
| IRQ_NOPROBE
| IRQ_NOAUTOEN
,
322 for (irq
= IRQ_GPIOHIGH
+ 1; irq
< IRQ_GPIO0
; irq
++) {
323 irq_set_chip(irq
, &puv3_normal_chip
);
324 irq_set_handler(irq
, handle_level_irq
);
325 irq_modify_status(irq
,
326 IRQ_NOREQUEST
| IRQ_NOAUTOEN
,
330 for (irq
= IRQ_GPIO0
; irq
<= IRQ_GPIO27
; irq
++) {
331 irq_set_chip(irq
, &puv3_high_gpio_chip
);
332 irq_set_handler(irq
, handle_edge_irq
);
333 irq_modify_status(irq
,
334 IRQ_NOREQUEST
| IRQ_NOPROBE
| IRQ_NOAUTOEN
,
339 * Install handler for GPIO 0-27 edge detect interrupts
341 irq_set_chip(IRQ_GPIOHIGH
, &puv3_normal_chip
);
342 irq_set_chained_handler(IRQ_GPIOHIGH
, puv3_gpio_handler
);
344 #ifdef CONFIG_PUV3_GPIO
350 * do_IRQ handles all hardware IRQ's. Decoded IRQs should not
351 * come via this function. Instead, they should provide their
354 asmlinkage
void asm_do_IRQ(unsigned int irq
, struct pt_regs
*regs
)
356 struct pt_regs
*old_regs
= set_irq_regs(regs
);
361 * Some hardware gives randomly wrong interrupts. Rather
362 * than crashing, do something sensible.
364 if (unlikely(irq
>= nr_irqs
)) {
365 if (printk_ratelimit())
366 printk(KERN_WARNING
"Bad IRQ%u\n", irq
);
369 generic_handle_irq(irq
);
373 set_irq_regs(old_regs
);