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net: move procfs code to net/core/net-procfs.c
[linux/fpc-iii.git] / drivers / ata / ata_piix.c
blob174eca609b425e06bf788de9ba50f07c17ffbbdc
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 * Documentation
41 * Publicly available from Intel web site. Errata documentation
42 * is also publicly available. As an aide to anyone hacking on this
43 * driver the list of errata that are relevant is below, going back to
44 * PIIX4. Older device documentation is now a bit tricky to find.
45 *
46 * The chipsets all follow very much the same design. The original Triton
47 * series chipsets do _not_ support independent device timings, but this
48 * is fixed in Triton II. With the odd mobile exception the chips then
49 * change little except in gaining more modes until SATA arrives. This
50 * driver supports only the chips with independent timing (that is those
51 * with SITRE and the 0x44 timing register). See pata_oldpiix and pata_mpiix
52 * for the early chip drivers.
53 *
54 * Errata of note:
55 *
56 * Unfixable
57 * PIIX4 errata #9 - Only on ultra obscure hw
58 * ICH3 errata #13 - Not observed to affect real hw
59 * by Intel
60 *
61 * Things we must deal with
62 * PIIX4 errata #10 - BM IDE hang with non UDMA
63 * (must stop/start dma to recover)
64 * 440MX errata #15 - As PIIX4 errata #10
65 * PIIX4 errata #15 - Must not read control registers
66 * during a PIO transfer
67 * 440MX errata #13 - As PIIX4 errata #15
68 * ICH2 errata #21 - DMA mode 0 doesn't work right
69 * ICH0/1 errata #55 - As ICH2 errata #21
70 * ICH2 spec c #9 - Extra operations needed to handle
71 * drive hotswap [NOT YET SUPPORTED]
72 * ICH2 spec c #20 - IDE PRD must not cross a 64K boundary
73 * and must be dword aligned
74 * ICH2 spec c #24 - UDMA mode 4,5 t85/86 should be 6ns not 3.3
75 * ICH7 errata #16 - MWDMA1 timings are incorrect
76 *
77 * Should have been BIOS fixed:
78 * 450NX: errata #19 - DMA hangs on old 450NX
79 * 450NX: errata #20 - DMA hangs on old 450NX
80 * 450NX: errata #25 - Corruption with DMA on old 450NX
81 * ICH3 errata #15 - IDE deadlock under high load
82 * (BIOS must set dev 31 fn 0 bit 23)
83 * ICH3 errata #18 - Don't use native mode
84 */
85
86 #include <linux/kernel.h>
87 #include <linux/module.h>
88 #include <linux/pci.h>
89 #include <linux/init.h>
90 #include <linux/blkdev.h>
91 #include <linux/delay.h>
92 #include <linux/device.h>
93 #include <linux/gfp.h>
94 #include <scsi/scsi_host.h>
95 #include <linux/libata.h>
96 #include <linux/dmi.h>
97
98 #define DRV_NAME "ata_piix"
99 #define DRV_VERSION "2.13"
100
101 enum {
102 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
103 ICH5_PMR = 0x90, /* port mapping register */
104 ICH5_PCS = 0x92, /* port control and status */
105 PIIX_SIDPR_BAR = 5,
106 PIIX_SIDPR_LEN = 16,
107 PIIX_SIDPR_IDX = 0,
108 PIIX_SIDPR_DATA = 4,
109
110 PIIX_FLAG_CHECKINTR = (1 << 28), /* make sure PCI INTx enabled */
111 PIIX_FLAG_SIDPR = (1 << 29), /* SATA idx/data pair regs */
112
113 PIIX_PATA_FLAGS = ATA_FLAG_SLAVE_POSS,
114 PIIX_SATA_FLAGS = ATA_FLAG_SATA | PIIX_FLAG_CHECKINTR,
115
116 PIIX_FLAG_PIO16 = (1 << 30), /*support 16bit PIO only*/
117
118 PIIX_80C_PRI = (1 << 5) | (1 << 4),
119 PIIX_80C_SEC = (1 << 7) | (1 << 6),
120
121 /* constants for mapping table */
122 P0 = 0, /* port 0 */
123 P1 = 1, /* port 1 */
124 P2 = 2, /* port 2 */
125 P3 = 3, /* port 3 */
126 IDE = -1, /* IDE */
127 NA = -2, /* not available */
128 RV = -3, /* reserved */
129
130 PIIX_AHCI_DEVICE = 6,
131
132 /* host->flags bits */
133 PIIX_HOST_BROKEN_SUSPEND = (1 << 24),
134 };
135
136 enum piix_controller_ids {
137 /* controller IDs */
138 piix_pata_mwdma, /* PIIX3 MWDMA only */
139 piix_pata_33, /* PIIX4 at 33Mhz */
140 ich_pata_33, /* ICH up to UDMA 33 only */
141 ich_pata_66, /* ICH up to 66 Mhz */
142 ich_pata_100, /* ICH up to UDMA 100 */
143 ich_pata_100_nomwdma1, /* ICH up to UDMA 100 but with no MWDMA1*/
144 ich5_sata,
145 ich6_sata,
146 ich6m_sata,
147 ich8_sata,
148 ich8_2port_sata,
149 ich8m_apple_sata, /* locks up on second port enable */
150 tolapai_sata,
151 piix_pata_vmw, /* PIIX4 for VMware, spurious DMA_ERR */
152 ich8_sata_snb,
153 };
154
155 struct piix_map_db {
156 const u32 mask;
157 const u16 port_enable;
158 const int map[][4];
159 };
160
161 struct piix_host_priv {
162 const int *map;
163 u32 saved_iocfg;
164 void __iomem *sidpr;
165 };
166
167 static unsigned int in_module_init = 1;
168
169 static const struct pci_device_id piix_pci_tbl[] = {
170 /* Intel PIIX3 for the 430HX etc */
171 { 0x8086, 0x7010, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_mwdma },
172 /* VMware ICH4 */
173 { 0x8086, 0x7111, 0x15ad, 0x1976, 0, 0, piix_pata_vmw },
174 /* Intel PIIX4 for the 430TX/440BX/MX chipset: UDMA 33 */
175 /* Also PIIX4E (fn3 rev 2) and PIIX4M (fn3 rev 3) */
176 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
177 /* Intel PIIX4 */
178 { 0x8086, 0x7199, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
179 /* Intel PIIX4 */
180 { 0x8086, 0x7601, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
181 /* Intel PIIX */
182 { 0x8086, 0x84CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix_pata_33 },
183 /* Intel ICH (i810, i815, i840) UDMA 66*/
184 { 0x8086, 0x2411, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_66 },
185 /* Intel ICH0 : UDMA 33*/
186 { 0x8086, 0x2421, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_33 },
187 /* Intel ICH2M */
188 { 0x8086, 0x244A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
189 /* Intel ICH2 (i810E2, i845, 850, 860) UDMA 100 */
190 { 0x8086, 0x244B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
191 /* Intel ICH3M */
192 { 0x8086, 0x248A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
193 /* Intel ICH3 (E7500/1) UDMA 100 */
194 { 0x8086, 0x248B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
195 /* Intel ICH4-L */
196 { 0x8086, 0x24C1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
197 /* Intel ICH4 (i845GV, i845E, i852, i855) UDMA 100 */
198 { 0x8086, 0x24CA, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
199 { 0x8086, 0x24CB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
200 /* Intel ICH5 */
201 { 0x8086, 0x24DB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
202 /* C-ICH (i810E2) */
203 { 0x8086, 0x245B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
204 /* ESB (855GME/875P + 6300ESB) UDMA 100 */
205 { 0x8086, 0x25A2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
206 /* ICH6 (and 6) (i915) UDMA 100 */
207 { 0x8086, 0x266F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
208 /* ICH7/7-R (i945, i975) UDMA 100*/
209 { 0x8086, 0x27DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
210 { 0x8086, 0x269E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100_nomwdma1 },
211 /* ICH8 Mobile PATA Controller */
212 { 0x8086, 0x2850, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich_pata_100 },
213
214 /* SATA ports */
215
216 /* 82801EB (ICH5) */
217 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
218 /* 82801EB (ICH5) */
219 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
220 /* 6300ESB (ICH5 variant with broken PCS present bits) */
221 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
222 /* 6300ESB pretending RAID */
223 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
224 /* 82801FB/FW (ICH6/ICH6W) */
225 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
226 /* 82801FR/FRW (ICH6R/ICH6RW) */
227 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
228 /* 82801FBM ICH6M (ICH6R with only port 0 and 2 implemented).
229 * Attach iff the controller is in IDE mode. */
230 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID,
231 PCI_CLASS_STORAGE_IDE << 8, 0xffff00, ich6m_sata },
232 /* 82801GB/GR/GH (ICH7, identical to ICH6) */
233 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
234 /* 2801GBM/GHM (ICH7M, identical to ICH6M) */
235 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6m_sata },
236 /* Enterprise Southbridge 2 (631xESB/632xESB) */
237 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
238 /* SATA Controller 1 IDE (ICH8) */
239 { 0x8086, 0x2820, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
240 /* SATA Controller 2 IDE (ICH8) */
241 { 0x8086, 0x2825, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
242 /* Mobile SATA Controller IDE (ICH8M), Apple */
243 { 0x8086, 0x2828, 0x106b, 0x00a0, 0, 0, ich8m_apple_sata },
244 { 0x8086, 0x2828, 0x106b, 0x00a1, 0, 0, ich8m_apple_sata },
245 { 0x8086, 0x2828, 0x106b, 0x00a3, 0, 0, ich8m_apple_sata },
246 /* Mobile SATA Controller IDE (ICH8M) */
247 { 0x8086, 0x2828, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
248 /* SATA Controller IDE (ICH9) */
249 { 0x8086, 0x2920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
250 /* SATA Controller IDE (ICH9) */
251 { 0x8086, 0x2921, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
252 /* SATA Controller IDE (ICH9) */
253 { 0x8086, 0x2926, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
254 /* SATA Controller IDE (ICH9M) */
255 { 0x8086, 0x2928, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
256 /* SATA Controller IDE (ICH9M) */
257 { 0x8086, 0x292d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
258 /* SATA Controller IDE (ICH9M) */
259 { 0x8086, 0x292e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
260 /* SATA Controller IDE (Tolapai) */
261 { 0x8086, 0x5028, PCI_ANY_ID, PCI_ANY_ID, 0, 0, tolapai_sata },
262 /* SATA Controller IDE (ICH10) */
263 { 0x8086, 0x3a00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
264 /* SATA Controller IDE (ICH10) */
265 { 0x8086, 0x3a06, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
266 /* SATA Controller IDE (ICH10) */
267 { 0x8086, 0x3a20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
268 /* SATA Controller IDE (ICH10) */
269 { 0x8086, 0x3a26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
270 /* SATA Controller IDE (PCH) */
271 { 0x8086, 0x3b20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
272 /* SATA Controller IDE (PCH) */
273 { 0x8086, 0x3b21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
274 /* SATA Controller IDE (PCH) */
275 { 0x8086, 0x3b26, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
276 /* SATA Controller IDE (PCH) */
277 { 0x8086, 0x3b28, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
278 /* SATA Controller IDE (PCH) */
279 { 0x8086, 0x3b2d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
280 /* SATA Controller IDE (PCH) */
281 { 0x8086, 0x3b2e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata },
282 /* SATA Controller IDE (CPT) */
283 { 0x8086, 0x1c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
284 /* SATA Controller IDE (CPT) */
285 { 0x8086, 0x1c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
286 /* SATA Controller IDE (CPT) */
287 { 0x8086, 0x1c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
288 /* SATA Controller IDE (CPT) */
289 { 0x8086, 0x1c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
290 /* SATA Controller IDE (PBG) */
291 { 0x8086, 0x1d00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
292 /* SATA Controller IDE (PBG) */
293 { 0x8086, 0x1d08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
294 /* SATA Controller IDE (Panther Point) */
295 { 0x8086, 0x1e00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
296 /* SATA Controller IDE (Panther Point) */
297 { 0x8086, 0x1e01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
298 /* SATA Controller IDE (Panther Point) */
299 { 0x8086, 0x1e08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
300 /* SATA Controller IDE (Panther Point) */
301 { 0x8086, 0x1e09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
302 /* SATA Controller IDE (Lynx Point) */
303 { 0x8086, 0x8c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
304 /* SATA Controller IDE (Lynx Point) */
305 { 0x8086, 0x8c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
306 /* SATA Controller IDE (Lynx Point) */
307 { 0x8086, 0x8c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
308 /* SATA Controller IDE (Lynx Point) */
309 { 0x8086, 0x8c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
310 /* SATA Controller IDE (Lynx Point-LP) */
311 { 0x8086, 0x9c00, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
312 /* SATA Controller IDE (Lynx Point-LP) */
313 { 0x8086, 0x9c01, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
314 /* SATA Controller IDE (Lynx Point-LP) */
315 { 0x8086, 0x9c08, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
316 /* SATA Controller IDE (Lynx Point-LP) */
317 { 0x8086, 0x9c09, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
318 /* SATA Controller IDE (DH89xxCC) */
319 { 0x8086, 0x2326, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
320 { } /* terminate list */
321 };
322
323 static const struct piix_map_db ich5_map_db = {
324 .mask = 0x7,
325 .port_enable = 0x3,
326 .map = {
327 /* PM PS SM SS MAP */
328 { P0, NA, P1, NA }, /* 000b */
329 { P1, NA, P0, NA }, /* 001b */
330 { RV, RV, RV, RV },
331 { RV, RV, RV, RV },
332 { P0, P1, IDE, IDE }, /* 100b */
333 { P1, P0, IDE, IDE }, /* 101b */
334 { IDE, IDE, P0, P1 }, /* 110b */
335 { IDE, IDE, P1, P0 }, /* 111b */
336 },
337 };
338
339 static const struct piix_map_db ich6_map_db = {
340 .mask = 0x3,
341 .port_enable = 0xf,
342 .map = {
343 /* PM PS SM SS MAP */
344 { P0, P2, P1, P3 }, /* 00b */
345 { IDE, IDE, P1, P3 }, /* 01b */
346 { P0, P2, IDE, IDE }, /* 10b */
347 { RV, RV, RV, RV },
348 },
349 };
350
351 static const struct piix_map_db ich6m_map_db = {
352 .mask = 0x3,
353 .port_enable = 0x5,
354
355 /* Map 01b isn't specified in the doc but some notebooks use
356 * it anyway. MAP 01b have been spotted on both ICH6M and
357 * ICH7M.
358 */
359 .map = {
360 /* PM PS SM SS MAP */
361 { P0, P2, NA, NA }, /* 00b */
362 { IDE, IDE, P1, P3 }, /* 01b */
363 { P0, P2, IDE, IDE }, /* 10b */
364 { RV, RV, RV, RV },
365 },
366 };
367
368 static const struct piix_map_db ich8_map_db = {
369 .mask = 0x3,
370 .port_enable = 0xf,
371 .map = {
372 /* PM PS SM SS MAP */
373 { P0, P2, P1, P3 }, /* 00b (hardwired when in AHCI) */
374 { RV, RV, RV, RV },
375 { P0, P2, IDE, IDE }, /* 10b (IDE mode) */
376 { RV, RV, RV, RV },
377 },
378 };
379
380 static const struct piix_map_db ich8_2port_map_db = {
381 .mask = 0x3,
382 .port_enable = 0x3,
383 .map = {
384 /* PM PS SM SS MAP */
385 { P0, NA, P1, NA }, /* 00b */
386 { RV, RV, RV, RV }, /* 01b */
387 { RV, RV, RV, RV }, /* 10b */
388 { RV, RV, RV, RV },
389 },
390 };
391
392 static const struct piix_map_db ich8m_apple_map_db = {
393 .mask = 0x3,
394 .port_enable = 0x1,
395 .map = {
396 /* PM PS SM SS MAP */
397 { P0, NA, NA, NA }, /* 00b */
398 { RV, RV, RV, RV },
399 { P0, P2, IDE, IDE }, /* 10b */
400 { RV, RV, RV, RV },
401 },
402 };
403
404 static const struct piix_map_db tolapai_map_db = {
405 .mask = 0x3,
406 .port_enable = 0x3,
407 .map = {
408 /* PM PS SM SS MAP */
409 { P0, NA, P1, NA }, /* 00b */
410 { RV, RV, RV, RV }, /* 01b */
411 { RV, RV, RV, RV }, /* 10b */
412 { RV, RV, RV, RV },
413 },
414 };
415
416 static const struct piix_map_db *piix_map_db_table[] = {
417 [ich5_sata] = &ich5_map_db,
418 [ich6_sata] = &ich6_map_db,
419 [ich6m_sata] = &ich6m_map_db,
420 [ich8_sata] = &ich8_map_db,
421 [ich8_2port_sata] = &ich8_2port_map_db,
422 [ich8m_apple_sata] = &ich8m_apple_map_db,
423 [tolapai_sata] = &tolapai_map_db,
424 [ich8_sata_snb] = &ich8_map_db,
425 };
426
427 static struct pci_bits piix_enable_bits[] = {
428 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
429 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
430 };
431
432 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
433 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
434 MODULE_LICENSE("GPL");
435 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
436 MODULE_VERSION(DRV_VERSION);
437
438 struct ich_laptop {
439 u16 device;
440 u16 subvendor;
441 u16 subdevice;
442 };
443
444 /*
445 * List of laptops that use short cables rather than 80 wire
446 */
447
448 static const struct ich_laptop ich_laptop[] = {
449 /* devid, subvendor, subdev */
450 { 0x27DF, 0x0005, 0x0280 }, /* ICH7 on Acer 5602WLMi */
451 { 0x27DF, 0x1025, 0x0102 }, /* ICH7 on Acer 5602aWLMi */
452 { 0x27DF, 0x1025, 0x0110 }, /* ICH7 on Acer 3682WLMi */
453 { 0x27DF, 0x1028, 0x02b0 }, /* ICH7 on unknown Dell */
454 { 0x27DF, 0x1043, 0x1267 }, /* ICH7 on Asus W5F */
455 { 0x27DF, 0x103C, 0x30A1 }, /* ICH7 on HP Compaq nc2400 */
456 { 0x27DF, 0x103C, 0x361a }, /* ICH7 on unknown HP */
457 { 0x27DF, 0x1071, 0xD221 }, /* ICH7 on Hercules EC-900 */
458 { 0x27DF, 0x152D, 0x0778 }, /* ICH7 on unknown Intel */
459 { 0x24CA, 0x1025, 0x0061 }, /* ICH4 on ACER Aspire 2023WLMi */
460 { 0x24CA, 0x1025, 0x003d }, /* ICH4 on ACER TM290 */
461 { 0x266F, 0x1025, 0x0066 }, /* ICH6 on ACER Aspire 1694WLMi */
462 { 0x2653, 0x1043, 0x82D8 }, /* ICH6M on Asus Eee 701 */
463 { 0x27df, 0x104d, 0x900e }, /* ICH7 on Sony TZ-90 */
464 /* end marker */
465 { 0, }
466 };
467
468 static int piix_port_start(struct ata_port *ap)
469 {
470 if (!(ap->flags & PIIX_FLAG_PIO16))
471 ap->pflags |= ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
472
473 return ata_bmdma_port_start(ap);
474 }
475
476 /**
477 * ich_pata_cable_detect - Probe host controller cable detect info
478 * @ap: Port for which cable detect info is desired
479 *
480 * Read 80c cable indicator from ATA PCI device's PCI config
481 * register. This register is normally set by firmware (BIOS).
482 *
483 * LOCKING:
484 * None (inherited from caller).
485 */
486
487 static int ich_pata_cable_detect(struct ata_port *ap)
488 {
489 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
490 struct piix_host_priv *hpriv = ap->host->private_data;
491 const struct ich_laptop *lap = &ich_laptop[0];
492 u8 mask;
493
494 /* Check for specials - Acer Aspire 5602WLMi */
495 while (lap->device) {
496 if (lap->device == pdev->device &&
497 lap->subvendor == pdev->subsystem_vendor &&
498 lap->subdevice == pdev->subsystem_device)
499 return ATA_CBL_PATA40_SHORT;
500
501 lap++;
502 }
503
504 /* check BIOS cable detect results */
505 mask = ap->port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
506 if ((hpriv->saved_iocfg & mask) == 0)
507 return ATA_CBL_PATA40;
508 return ATA_CBL_PATA80;
509 }
510
511 /**
512 * piix_pata_prereset - prereset for PATA host controller
513 * @link: Target link
514 * @deadline: deadline jiffies for the operation
515 *
516 * LOCKING:
517 * None (inherited from caller).
518 */
519 static int piix_pata_prereset(struct ata_link *link, unsigned long deadline)
520 {
521 struct ata_port *ap = link->ap;
522 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
523
524 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->port_no]))
525 return -ENOENT;
526 return ata_sff_prereset(link, deadline);
527 }
528
529 static DEFINE_SPINLOCK(piix_lock);
530
531 static void piix_set_timings(struct ata_port *ap, struct ata_device *adev,
532 u8 pio)
533 {
534 struct pci_dev *dev = to_pci_dev(ap->host->dev);
535 unsigned long flags;
536 unsigned int is_slave = (adev->devno != 0);
537 unsigned int master_port= ap->port_no ? 0x42 : 0x40;
538 unsigned int slave_port = 0x44;
539 u16 master_data;
540 u8 slave_data;
541 u8 udma_enable;
542 int control = 0;
543
544 /*
545 * See Intel Document 298600-004 for the timing programing rules
546 * for ICH controllers.
547 */
548
549 static const /* ISP RTC */
550 u8 timings[][2] = { { 0, 0 },
551 { 0, 0 },
552 { 1, 0 },
553 { 2, 1 },
554 { 2, 3 }, };
555
556 if (pio >= 2)
557 control |= 1; /* TIME1 enable */
558 if (ata_pio_need_iordy(adev))
559 control |= 2; /* IE enable */
560 /* Intel specifies that the PPE functionality is for disk only */
561 if (adev->class == ATA_DEV_ATA)
562 control |= 4; /* PPE enable */
563 /*
564 * If the drive MWDMA is faster than it can do PIO then
565 * we must force PIO into PIO0
566 */
567 if (adev->pio_mode < XFER_PIO_0 + pio)
568 /* Enable DMA timing only */
569 control |= 8; /* PIO cycles in PIO0 */
570
571 spin_lock_irqsave(&piix_lock, flags);
572
573 /* PIO configuration clears DTE unconditionally. It will be
574 * programmed in set_dmamode which is guaranteed to be called
575 * after set_piomode if any DMA mode is available.
576 */
577 pci_read_config_word(dev, master_port, &master_data);
578 if (is_slave) {
579 /* clear TIME1|IE1|PPE1|DTE1 */
580 master_data &= 0xff0f;
581 /* enable PPE1, IE1 and TIME1 as needed */
582 master_data |= (control << 4);
583 pci_read_config_byte(dev, slave_port, &slave_data);
584 slave_data &= (ap->port_no ? 0x0f : 0xf0);
585 /* Load the timing nibble for this slave */
586 slave_data |= ((timings[pio][0] << 2) | timings[pio][1])
587 << (ap->port_no ? 4 : 0);
588 } else {
589 /* clear ISP|RCT|TIME0|IE0|PPE0|DTE0 */
590 master_data &= 0xccf0;
591 /* Enable PPE, IE and TIME as appropriate */
592 master_data |= control;
593 /* load ISP and RCT */
594 master_data |=
595 (timings[pio][0] << 12) |
596 (timings[pio][1] << 8);
597 }
598
599 /* Enable SITRE (separate slave timing register) */
600 master_data |= 0x4000;
601 pci_write_config_word(dev, master_port, master_data);
602 if (is_slave)
603 pci_write_config_byte(dev, slave_port, slave_data);
604
605 /* Ensure the UDMA bit is off - it will be turned back on if
606 UDMA is selected */
607
608 if (ap->udma_mask) {
609 pci_read_config_byte(dev, 0x48, &udma_enable);
610 udma_enable &= ~(1 << (2 * ap->port_no + adev->devno));
611 pci_write_config_byte(dev, 0x48, udma_enable);
612 }
613
614 spin_unlock_irqrestore(&piix_lock, flags);
615 }
616
617 /**
618 * piix_set_piomode - Initialize host controller PATA PIO timings
619 * @ap: Port whose timings we are configuring
620 * @adev: Drive in question
621 *
622 * Set PIO mode for device, in host controller PCI config space.
623 *
624 * LOCKING:
625 * None (inherited from caller).
626 */
627
628 static void piix_set_piomode(struct ata_port *ap, struct ata_device *adev)
629 {
630 piix_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0);
631 }
632
633 /**
634 * do_pata_set_dmamode - Initialize host controller PATA PIO timings
635 * @ap: Port whose timings we are configuring
636 * @adev: Drive in question
637 * @isich: set if the chip is an ICH device
638 *
639 * Set UDMA mode for device, in host controller PCI config space.
640 *
641 * LOCKING:
642 * None (inherited from caller).
643 */
644
645 static void do_pata_set_dmamode(struct ata_port *ap, struct ata_device *adev, int isich)
646 {
647 struct pci_dev *dev = to_pci_dev(ap->host->dev);
648 unsigned long flags;
649 u8 speed = adev->dma_mode;
650 int devid = adev->devno + 2 * ap->port_no;
651 u8 udma_enable = 0;
652
653 if (speed >= XFER_UDMA_0) {
654 unsigned int udma = speed - XFER_UDMA_0;
655 u16 udma_timing;
656 u16 ideconf;
657 int u_clock, u_speed;
658
659 spin_lock_irqsave(&piix_lock, flags);
660
661 pci_read_config_byte(dev, 0x48, &udma_enable);
662
663 /*
664 * UDMA is handled by a combination of clock switching and
665 * selection of dividers
666 *
667 * Handy rule: Odd modes are UDMATIMx 01, even are 02
668 * except UDMA0 which is 00
669 */
670 u_speed = min(2 - (udma & 1), udma);
671 if (udma == 5)
672 u_clock = 0x1000; /* 100Mhz */
673 else if (udma > 2)
674 u_clock = 1; /* 66Mhz */
675 else
676 u_clock = 0; /* 33Mhz */
677
678 udma_enable |= (1 << devid);
679
680 /* Load the CT/RP selection */
681 pci_read_config_word(dev, 0x4A, &udma_timing);
682 udma_timing &= ~(3 << (4 * devid));
683 udma_timing |= u_speed << (4 * devid);
684 pci_write_config_word(dev, 0x4A, udma_timing);
685
686 if (isich) {
687 /* Select a 33/66/100Mhz clock */
688 pci_read_config_word(dev, 0x54, &ideconf);
689 ideconf &= ~(0x1001 << devid);
690 ideconf |= u_clock << devid;
691 /* For ICH or later we should set bit 10 for better
692 performance (WR_PingPong_En) */
693 pci_write_config_word(dev, 0x54, ideconf);
694 }
695
696 pci_write_config_byte(dev, 0x48, udma_enable);
697
698 spin_unlock_irqrestore(&piix_lock, flags);
699 } else {
700 /* MWDMA is driven by the PIO timings. */
701 unsigned int mwdma = speed - XFER_MW_DMA_0;
702 const unsigned int needed_pio[3] = {
703 XFER_PIO_0, XFER_PIO_3, XFER_PIO_4
704 };
705 int pio = needed_pio[mwdma] - XFER_PIO_0;
706
707 /* XFER_PIO_0 is never used currently */
708 piix_set_timings(ap, adev, pio);
709 }
710 }
711
712 /**
713 * piix_set_dmamode - Initialize host controller PATA DMA timings
714 * @ap: Port whose timings we are configuring
715 * @adev: um
716 *
717 * Set MW/UDMA mode for device, in host controller PCI config space.
718 *
719 * LOCKING:
720 * None (inherited from caller).
721 */
722
723 static void piix_set_dmamode(struct ata_port *ap, struct ata_device *adev)
724 {
725 do_pata_set_dmamode(ap, adev, 0);
726 }
727
728 /**
729 * ich_set_dmamode - Initialize host controller PATA DMA timings
730 * @ap: Port whose timings we are configuring
731 * @adev: um
732 *
733 * Set MW/UDMA mode for device, in host controller PCI config space.
734 *
735 * LOCKING:
736 * None (inherited from caller).
737 */
738
739 static void ich_set_dmamode(struct ata_port *ap, struct ata_device *adev)
740 {
741 do_pata_set_dmamode(ap, adev, 1);
742 }
743
744 /*
745 * Serial ATA Index/Data Pair Superset Registers access
746 *
747 * Beginning from ICH8, there's a sane way to access SCRs using index
748 * and data register pair located at BAR5 which means that we have
749 * separate SCRs for master and slave. This is handled using libata
750 * slave_link facility.
751 */
752 static const int piix_sidx_map[] = {
753 [SCR_STATUS] = 0,
754 [SCR_ERROR] = 2,
755 [SCR_CONTROL] = 1,
756 };
757
758 static void piix_sidpr_sel(struct ata_link *link, unsigned int reg)
759 {
760 struct ata_port *ap = link->ap;
761 struct piix_host_priv *hpriv = ap->host->private_data;
762
763 iowrite32(((ap->port_no * 2 + link->pmp) << 8) | piix_sidx_map[reg],
764 hpriv->sidpr + PIIX_SIDPR_IDX);
765 }
766
767 static int piix_sidpr_scr_read(struct ata_link *link,
768 unsigned int reg, u32 *val)
769 {
770 struct piix_host_priv *hpriv = link->ap->host->private_data;
771
772 if (reg >= ARRAY_SIZE(piix_sidx_map))
773 return -EINVAL;
774
775 piix_sidpr_sel(link, reg);
776 *val = ioread32(hpriv->sidpr + PIIX_SIDPR_DATA);
777 return 0;
778 }
779
780 static int piix_sidpr_scr_write(struct ata_link *link,
781 unsigned int reg, u32 val)
782 {
783 struct piix_host_priv *hpriv = link->ap->host->private_data;
784
785 if (reg >= ARRAY_SIZE(piix_sidx_map))
786 return -EINVAL;
787
788 piix_sidpr_sel(link, reg);
789 iowrite32(val, hpriv->sidpr + PIIX_SIDPR_DATA);
790 return 0;
791 }
792
793 static int piix_sidpr_set_lpm(struct ata_link *link, enum ata_lpm_policy policy,
794 unsigned hints)
795 {
796 return sata_link_scr_lpm(link, policy, false);
797 }
798
799 static bool piix_irq_check(struct ata_port *ap)
800 {
801 if (unlikely(!ap->ioaddr.bmdma_addr))
802 return false;
803
804 return ap->ops->bmdma_status(ap) & ATA_DMA_INTR;
805 }
806
807 #ifdef CONFIG_PM
808 static int piix_broken_suspend(void)
809 {
810 static const struct dmi_system_id sysids[] = {
811 {
812 .ident = "TECRA M3",
813 .matches = {
814 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
815 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M3"),
816 },
817 },
818 {
819 .ident = "TECRA M3",
820 .matches = {
821 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
822 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M3"),
823 },
824 },
825 {
826 .ident = "TECRA M4",
827 .matches = {
828 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
829 DMI_MATCH(DMI_PRODUCT_NAME, "Tecra M4"),
830 },
831 },
832 {
833 .ident = "TECRA M4",
834 .matches = {
835 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
836 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M4"),
837 },
838 },
839 {
840 .ident = "TECRA M5",
841 .matches = {
842 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
843 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M5"),
844 },
845 },
846 {
847 .ident = "TECRA M6",
848 .matches = {
849 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
850 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M6"),
851 },
852 },
853 {
854 .ident = "TECRA M7",
855 .matches = {
856 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
857 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA M7"),
858 },
859 },
860 {
861 .ident = "TECRA A8",
862 .matches = {
863 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
864 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A8"),
865 },
866 },
867 {
868 .ident = "Satellite R20",
869 .matches = {
870 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
871 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R20"),
872 },
873 },
874 {
875 .ident = "Satellite R25",
876 .matches = {
877 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
878 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite R25"),
879 },
880 },
881 {
882 .ident = "Satellite U200",
883 .matches = {
884 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
885 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U200"),
886 },
887 },
888 {
889 .ident = "Satellite U200",
890 .matches = {
891 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
892 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U200"),
893 },
894 },
895 {
896 .ident = "Satellite Pro U200",
897 .matches = {
898 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
899 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE PRO U200"),
900 },
901 },
902 {
903 .ident = "Satellite U205",
904 .matches = {
905 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
906 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite U205"),
907 },
908 },
909 {
910 .ident = "SATELLITE U205",
911 .matches = {
912 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
913 DMI_MATCH(DMI_PRODUCT_NAME, "SATELLITE U205"),
914 },
915 },
916 {
917 .ident = "Satellite Pro A120",
918 .matches = {
919 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
920 DMI_MATCH(DMI_PRODUCT_NAME, "Satellite Pro A120"),
921 },
922 },
923 {
924 .ident = "Portege M500",
925 .matches = {
926 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
927 DMI_MATCH(DMI_PRODUCT_NAME, "PORTEGE M500"),
928 },
929 },
930 {
931 .ident = "VGN-BX297XP",
932 .matches = {
933 DMI_MATCH(DMI_SYS_VENDOR, "Sony Corporation"),
934 DMI_MATCH(DMI_PRODUCT_NAME, "VGN-BX297XP"),
935 },
936 },
937
938 { } /* terminate list */
939 };
940 static const char *oemstrs[] = {
941 "Tecra M3,",
942 };
943 int i;
944
945 if (dmi_check_system(sysids))
946 return 1;
947
948 for (i = 0; i < ARRAY_SIZE(oemstrs); i++)
949 if (dmi_find_device(DMI_DEV_TYPE_OEM_STRING, oemstrs[i], NULL))
950 return 1;
951
952 /* TECRA M4 sometimes forgets its identify and reports bogus
953 * DMI information. As the bogus information is a bit
954 * generic, match as many entries as possible. This manual
955 * matching is necessary because dmi_system_id.matches is
956 * limited to four entries.
957 */
958 if (dmi_match(DMI_SYS_VENDOR, "TOSHIBA") &&
959 dmi_match(DMI_PRODUCT_NAME, "000000") &&
960 dmi_match(DMI_PRODUCT_VERSION, "000000") &&
961 dmi_match(DMI_PRODUCT_SERIAL, "000000") &&
962 dmi_match(DMI_BOARD_VENDOR, "TOSHIBA") &&
963 dmi_match(DMI_BOARD_NAME, "Portable PC") &&
964 dmi_match(DMI_BOARD_VERSION, "Version A0"))
965 return 1;
966
967 return 0;
968 }
969
970 static int piix_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
971 {
972 struct ata_host *host = dev_get_drvdata(&pdev->dev);
973 unsigned long flags;
974 int rc = 0;
975
976 rc = ata_host_suspend(host, mesg);
977 if (rc)
978 return rc;
979
980 /* Some braindamaged ACPI suspend implementations expect the
981 * controller to be awake on entry; otherwise, it burns cpu
982 * cycles and power trying to do something to the sleeping
983 * beauty.
984 */
985 if (piix_broken_suspend() && (mesg.event & PM_EVENT_SLEEP)) {
986 pci_save_state(pdev);
987
988 /* mark its power state as "unknown", since we don't
989 * know if e.g. the BIOS will change its device state
990 * when we suspend.
991 */
992 if (pdev->current_state == PCI_D0)
993 pdev->current_state = PCI_UNKNOWN;
994
995 /* tell resume that it's waking up from broken suspend */
996 spin_lock_irqsave(&host->lock, flags);
997 host->flags |= PIIX_HOST_BROKEN_SUSPEND;
998 spin_unlock_irqrestore(&host->lock, flags);
999 } else
1000 ata_pci_device_do_suspend(pdev, mesg);
1001
1002 return 0;
1003 }
1004
1005 static int piix_pci_device_resume(struct pci_dev *pdev)
1006 {
1007 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1008 unsigned long flags;
1009 int rc;
1010
1011 if (host->flags & PIIX_HOST_BROKEN_SUSPEND) {
1012 spin_lock_irqsave(&host->lock, flags);
1013 host->flags &= ~PIIX_HOST_BROKEN_SUSPEND;
1014 spin_unlock_irqrestore(&host->lock, flags);
1015
1016 pci_set_power_state(pdev, PCI_D0);
1017 pci_restore_state(pdev);
1018
1019 /* PCI device wasn't disabled during suspend. Use
1020 * pci_reenable_device() to avoid affecting the enable
1021 * count.
1022 */
1023 rc = pci_reenable_device(pdev);
1024 if (rc)
1025 dev_err(&pdev->dev,
1026 "failed to enable device after resume (%d)\n",
1027 rc);
1028 } else
1029 rc = ata_pci_device_do_resume(pdev);
1030
1031 if (rc == 0)
1032 ata_host_resume(host);
1033
1034 return rc;
1035 }
1036 #endif
1037
1038 static u8 piix_vmw_bmdma_status(struct ata_port *ap)
1039 {
1040 return ata_bmdma_status(ap) & ~ATA_DMA_ERR;
1041 }
1042
1043 static struct scsi_host_template piix_sht = {
1044 ATA_BMDMA_SHT(DRV_NAME),
1045 };
1046
1047 static struct ata_port_operations piix_sata_ops = {
1048 .inherits = &ata_bmdma32_port_ops,
1049 .sff_irq_check = piix_irq_check,
1050 .port_start = piix_port_start,
1051 };
1052
1053 static struct ata_port_operations piix_pata_ops = {
1054 .inherits = &piix_sata_ops,
1055 .cable_detect = ata_cable_40wire,
1056 .set_piomode = piix_set_piomode,
1057 .set_dmamode = piix_set_dmamode,
1058 .prereset = piix_pata_prereset,
1059 };
1060
1061 static struct ata_port_operations piix_vmw_ops = {
1062 .inherits = &piix_pata_ops,
1063 .bmdma_status = piix_vmw_bmdma_status,
1064 };
1065
1066 static struct ata_port_operations ich_pata_ops = {
1067 .inherits = &piix_pata_ops,
1068 .cable_detect = ich_pata_cable_detect,
1069 .set_dmamode = ich_set_dmamode,
1070 };
1071
1072 static struct device_attribute *piix_sidpr_shost_attrs[] = {
1073 &dev_attr_link_power_management_policy,
1074 NULL
1075 };
1076
1077 static struct scsi_host_template piix_sidpr_sht = {
1078 ATA_BMDMA_SHT(DRV_NAME),
1079 .shost_attrs = piix_sidpr_shost_attrs,
1080 };
1081
1082 static struct ata_port_operations piix_sidpr_sata_ops = {
1083 .inherits = &piix_sata_ops,
1084 .hardreset = sata_std_hardreset,
1085 .scr_read = piix_sidpr_scr_read,
1086 .scr_write = piix_sidpr_scr_write,
1087 .set_lpm = piix_sidpr_set_lpm,
1088 };
1089
1090 static struct ata_port_info piix_port_info[] = {
1091 [piix_pata_mwdma] = /* PIIX3 MWDMA only */
1092 {
1093 .flags = PIIX_PATA_FLAGS,
1094 .pio_mask = ATA_PIO4,
1095 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1096 .port_ops = &piix_pata_ops,
1097 },
1098
1099 [piix_pata_33] = /* PIIX4 at 33MHz */
1100 {
1101 .flags = PIIX_PATA_FLAGS,
1102 .pio_mask = ATA_PIO4,
1103 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1104 .udma_mask = ATA_UDMA2,
1105 .port_ops = &piix_pata_ops,
1106 },
1107
1108 [ich_pata_33] = /* ICH0 - ICH at 33Mhz*/
1109 {
1110 .flags = PIIX_PATA_FLAGS,
1111 .pio_mask = ATA_PIO4,
1112 .mwdma_mask = ATA_MWDMA12_ONLY, /* Check: maybe MWDMA0 is ok */
1113 .udma_mask = ATA_UDMA2,
1114 .port_ops = &ich_pata_ops,
1115 },
1116
1117 [ich_pata_66] = /* ICH controllers up to 66MHz */
1118 {
1119 .flags = PIIX_PATA_FLAGS,
1120 .pio_mask = ATA_PIO4,
1121 .mwdma_mask = ATA_MWDMA12_ONLY, /* MWDMA0 is broken on chip */
1122 .udma_mask = ATA_UDMA4,
1123 .port_ops = &ich_pata_ops,
1124 },
1125
1126 [ich_pata_100] =
1127 {
1128 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1129 .pio_mask = ATA_PIO4,
1130 .mwdma_mask = ATA_MWDMA12_ONLY,
1131 .udma_mask = ATA_UDMA5,
1132 .port_ops = &ich_pata_ops,
1133 },
1134
1135 [ich_pata_100_nomwdma1] =
1136 {
1137 .flags = PIIX_PATA_FLAGS | PIIX_FLAG_CHECKINTR,
1138 .pio_mask = ATA_PIO4,
1139 .mwdma_mask = ATA_MWDMA2_ONLY,
1140 .udma_mask = ATA_UDMA5,
1141 .port_ops = &ich_pata_ops,
1142 },
1143
1144 [ich5_sata] =
1145 {
1146 .flags = PIIX_SATA_FLAGS,
1147 .pio_mask = ATA_PIO4,
1148 .mwdma_mask = ATA_MWDMA2,
1149 .udma_mask = ATA_UDMA6,
1150 .port_ops = &piix_sata_ops,
1151 },
1152
1153 [ich6_sata] =
1154 {
1155 .flags = PIIX_SATA_FLAGS,
1156 .pio_mask = ATA_PIO4,
1157 .mwdma_mask = ATA_MWDMA2,
1158 .udma_mask = ATA_UDMA6,
1159 .port_ops = &piix_sata_ops,
1160 },
1161
1162 [ich6m_sata] =
1163 {
1164 .flags = PIIX_SATA_FLAGS,
1165 .pio_mask = ATA_PIO4,
1166 .mwdma_mask = ATA_MWDMA2,
1167 .udma_mask = ATA_UDMA6,
1168 .port_ops = &piix_sata_ops,
1169 },
1170
1171 [ich8_sata] =
1172 {
1173 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1174 .pio_mask = ATA_PIO4,
1175 .mwdma_mask = ATA_MWDMA2,
1176 .udma_mask = ATA_UDMA6,
1177 .port_ops = &piix_sata_ops,
1178 },
1179
1180 [ich8_2port_sata] =
1181 {
1182 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR,
1183 .pio_mask = ATA_PIO4,
1184 .mwdma_mask = ATA_MWDMA2,
1185 .udma_mask = ATA_UDMA6,
1186 .port_ops = &piix_sata_ops,
1187 },
1188
1189 [tolapai_sata] =
1190 {
1191 .flags = PIIX_SATA_FLAGS,
1192 .pio_mask = ATA_PIO4,
1193 .mwdma_mask = ATA_MWDMA2,
1194 .udma_mask = ATA_UDMA6,
1195 .port_ops = &piix_sata_ops,
1196 },
1197
1198 [ich8m_apple_sata] =
1199 {
1200 .flags = PIIX_SATA_FLAGS,
1201 .pio_mask = ATA_PIO4,
1202 .mwdma_mask = ATA_MWDMA2,
1203 .udma_mask = ATA_UDMA6,
1204 .port_ops = &piix_sata_ops,
1205 },
1206
1207 [piix_pata_vmw] =
1208 {
1209 .flags = PIIX_PATA_FLAGS,
1210 .pio_mask = ATA_PIO4,
1211 .mwdma_mask = ATA_MWDMA12_ONLY, /* mwdma1-2 ?? CHECK 0 should be ok but slow */
1212 .udma_mask = ATA_UDMA2,
1213 .port_ops = &piix_vmw_ops,
1214 },
1215
1216 /*
1217 * some Sandybridge chipsets have broken 32 mode up to now,
1218 * see https://bugzilla.kernel.org/show_bug.cgi?id=40592
1219 */
1220 [ich8_sata_snb] =
1221 {
1222 .flags = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
1223 .pio_mask = ATA_PIO4,
1224 .mwdma_mask = ATA_MWDMA2,
1225 .udma_mask = ATA_UDMA6,
1226 .port_ops = &piix_sata_ops,
1227 },
1228 };
1229
1230 #define AHCI_PCI_BAR 5
1231 #define AHCI_GLOBAL_CTL 0x04
1232 #define AHCI_ENABLE (1 << 31)
1233 static int piix_disable_ahci(struct pci_dev *pdev)
1234 {
1235 void __iomem *mmio;
1236 u32 tmp;
1237 int rc = 0;
1238
1239 /* BUG: pci_enable_device has not yet been called. This
1240 * works because this device is usually set up by BIOS.
1241 */
1242
1243 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
1244 !pci_resource_len(pdev, AHCI_PCI_BAR))
1245 return 0;
1246
1247 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
1248 if (!mmio)
1249 return -ENOMEM;
1250
1251 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1252 if (tmp & AHCI_ENABLE) {
1253 tmp &= ~AHCI_ENABLE;
1254 iowrite32(tmp, mmio + AHCI_GLOBAL_CTL);
1255
1256 tmp = ioread32(mmio + AHCI_GLOBAL_CTL);
1257 if (tmp & AHCI_ENABLE)
1258 rc = -EIO;
1259 }
1260
1261 pci_iounmap(pdev, mmio);
1262 return rc;
1263 }
1264
1265 /**
1266 * piix_check_450nx_errata - Check for problem 450NX setup
1267 * @ata_dev: the PCI device to check
1268 *
1269 * Check for the present of 450NX errata #19 and errata #25. If
1270 * they are found return an error code so we can turn off DMA
1271 */
1272
1273 static int piix_check_450nx_errata(struct pci_dev *ata_dev)
1274 {
1275 struct pci_dev *pdev = NULL;
1276 u16 cfg;
1277 int no_piix_dma = 0;
1278
1279 while ((pdev = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, pdev)) != NULL) {
1280 /* Look for 450NX PXB. Check for problem configurations
1281 A PCI quirk checks bit 6 already */
1282 pci_read_config_word(pdev, 0x41, &cfg);
1283 /* Only on the original revision: IDE DMA can hang */
1284 if (pdev->revision == 0x00)
1285 no_piix_dma = 1;
1286 /* On all revisions below 5 PXB bus lock must be disabled for IDE */
1287 else if (cfg & (1<<14) && pdev->revision < 5)
1288 no_piix_dma = 2;
1289 }
1290 if (no_piix_dma)
1291 dev_warn(&ata_dev->dev,
1292 "450NX errata present, disabling IDE DMA%s\n",
1293 no_piix_dma == 2 ? " - a BIOS update may resolve this"
1294 : "");
1295
1296 return no_piix_dma;
1297 }
1298
1299 static void piix_init_pcs(struct ata_host *host,
1300 const struct piix_map_db *map_db)
1301 {
1302 struct pci_dev *pdev = to_pci_dev(host->dev);
1303 u16 pcs, new_pcs;
1304
1305 pci_read_config_word(pdev, ICH5_PCS, &pcs);
1306
1307 new_pcs = pcs | map_db->port_enable;
1308
1309 if (new_pcs != pcs) {
1310 DPRINTK("updating PCS from 0x%x to 0x%x\n", pcs, new_pcs);
1311 pci_write_config_word(pdev, ICH5_PCS, new_pcs);
1312 msleep(150);
1313 }
1314 }
1315
1316 static const int *piix_init_sata_map(struct pci_dev *pdev,
1317 struct ata_port_info *pinfo,
1318 const struct piix_map_db *map_db)
1319 {
1320 const int *map;
1321 int i, invalid_map = 0;
1322 u8 map_value;
1323
1324 pci_read_config_byte(pdev, ICH5_PMR, &map_value);
1325
1326 map = map_db->map[map_value & map_db->mask];
1327
1328 dev_info(&pdev->dev, "MAP [");
1329 for (i = 0; i < 4; i++) {
1330 switch (map[i]) {
1331 case RV:
1332 invalid_map = 1;
1333 pr_cont(" XX");
1334 break;
1335
1336 case NA:
1337 pr_cont(" --");
1338 break;
1339
1340 case IDE:
1341 WARN_ON((i & 1) || map[i + 1] != IDE);
1342 pinfo[i / 2] = piix_port_info[ich_pata_100];
1343 i++;
1344 pr_cont(" IDE IDE");
1345 break;
1346
1347 default:
1348 pr_cont(" P%d", map[i]);
1349 if (i & 1)
1350 pinfo[i / 2].flags |= ATA_FLAG_SLAVE_POSS;
1351 break;
1352 }
1353 }
1354 pr_cont(" ]\n");
1355
1356 if (invalid_map)
1357 dev_err(&pdev->dev, "invalid MAP value %u\n", map_value);
1358
1359 return map;
1360 }
1361
1362 static bool piix_no_sidpr(struct ata_host *host)
1363 {
1364 struct pci_dev *pdev = to_pci_dev(host->dev);
1365
1366 /*
1367 * Samsung DB-P70 only has three ATA ports exposed and
1368 * curiously the unconnected first port reports link online
1369 * while not responding to SRST protocol causing excessive
1370 * detection delay.
1371 *
1372 * Unfortunately, the system doesn't carry enough DMI
1373 * information to identify the machine but does have subsystem
1374 * vendor and device set. As it's unclear whether the
1375 * subsystem vendor/device is used only for this specific
1376 * board, the port can't be disabled solely with the
1377 * information; however, turning off SIDPR access works around
1378 * the problem. Turn it off.
1379 *
1380 * This problem is reported in bnc#441240.
1381 *
1382 * https://bugzilla.novell.com/show_bug.cgi?id=441420
1383 */
1384 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2920 &&
1385 pdev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG &&
1386 pdev->subsystem_device == 0xb049) {
1387 dev_warn(host->dev,
1388 "Samsung DB-P70 detected, disabling SIDPR\n");
1389 return true;
1390 }
1391
1392 return false;
1393 }
1394
1395 static int piix_init_sidpr(struct ata_host *host)
1396 {
1397 struct pci_dev *pdev = to_pci_dev(host->dev);
1398 struct piix_host_priv *hpriv = host->private_data;
1399 struct ata_link *link0 = &host->ports[0]->link;
1400 u32 scontrol;
1401 int i, rc;
1402
1403 /* check for availability */
1404 for (i = 0; i < 4; i++)
1405 if (hpriv->map[i] == IDE)
1406 return 0;
1407
1408 /* is it blacklisted? */
1409 if (piix_no_sidpr(host))
1410 return 0;
1411
1412 if (!(host->ports[0]->flags & PIIX_FLAG_SIDPR))
1413 return 0;
1414
1415 if (pci_resource_start(pdev, PIIX_SIDPR_BAR) == 0 ||
1416 pci_resource_len(pdev, PIIX_SIDPR_BAR) != PIIX_SIDPR_LEN)
1417 return 0;
1418
1419 if (pcim_iomap_regions(pdev, 1 << PIIX_SIDPR_BAR, DRV_NAME))
1420 return 0;
1421
1422 hpriv->sidpr = pcim_iomap_table(pdev)[PIIX_SIDPR_BAR];
1423
1424 /* SCR access via SIDPR doesn't work on some configurations.
1425 * Give it a test drive by inhibiting power save modes which
1426 * we'll do anyway.
1427 */
1428 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1429
1430 /* if IPM is already 3, SCR access is probably working. Don't
1431 * un-inhibit power save modes as BIOS might have inhibited
1432 * them for a reason.
1433 */
1434 if ((scontrol & 0xf00) != 0x300) {
1435 scontrol |= 0x300;
1436 piix_sidpr_scr_write(link0, SCR_CONTROL, scontrol);
1437 piix_sidpr_scr_read(link0, SCR_CONTROL, &scontrol);
1438
1439 if ((scontrol & 0xf00) != 0x300) {
1440 dev_info(host->dev,
1441 "SCR access via SIDPR is available but doesn't work\n");
1442 return 0;
1443 }
1444 }
1445
1446 /* okay, SCRs available, set ops and ask libata for slave_link */
1447 for (i = 0; i < 2; i++) {
1448 struct ata_port *ap = host->ports[i];
1449
1450 ap->ops = &piix_sidpr_sata_ops;
1451
1452 if (ap->flags & ATA_FLAG_SLAVE_POSS) {
1453 rc = ata_slave_link_init(ap);
1454 if (rc)
1455 return rc;
1456 }
1457 }
1458
1459 return 0;
1460 }
1461
1462 static void piix_iocfg_bit18_quirk(struct ata_host *host)
1463 {
1464 static const struct dmi_system_id sysids[] = {
1465 {
1466 /* Clevo M570U sets IOCFG bit 18 if the cdrom
1467 * isn't used to boot the system which
1468 * disables the channel.
1469 */
1470 .ident = "M570U",
1471 .matches = {
1472 DMI_MATCH(DMI_SYS_VENDOR, "Clevo Co."),
1473 DMI_MATCH(DMI_PRODUCT_NAME, "M570U"),
1474 },
1475 },
1476
1477 { } /* terminate list */
1478 };
1479 struct pci_dev *pdev = to_pci_dev(host->dev);
1480 struct piix_host_priv *hpriv = host->private_data;
1481
1482 if (!dmi_check_system(sysids))
1483 return;
1484
1485 /* The datasheet says that bit 18 is NOOP but certain systems
1486 * seem to use it to disable a channel. Clear the bit on the
1487 * affected systems.
1488 */
1489 if (hpriv->saved_iocfg & (1 << 18)) {
1490 dev_info(&pdev->dev, "applying IOCFG bit18 quirk\n");
1491 pci_write_config_dword(pdev, PIIX_IOCFG,
1492 hpriv->saved_iocfg & ~(1 << 18));
1493 }
1494 }
1495
1496 static bool piix_broken_system_poweroff(struct pci_dev *pdev)
1497 {
1498 static const struct dmi_system_id broken_systems[] = {
1499 {
1500 .ident = "HP Compaq 2510p",
1501 .matches = {
1502 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1503 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 2510p"),
1504 },
1505 /* PCI slot number of the controller */
1506 .driver_data = (void *)0x1FUL,
1507 },
1508 {
1509 .ident = "HP Compaq nc6000",
1510 .matches = {
1511 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1512 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nc6000"),
1513 },
1514 /* PCI slot number of the controller */
1515 .driver_data = (void *)0x1FUL,
1516 },
1517
1518 { } /* terminate list */
1519 };
1520 const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1521
1522 if (dmi) {
1523 unsigned long slot = (unsigned long)dmi->driver_data;
1524 /* apply the quirk only to on-board controllers */
1525 return slot == PCI_SLOT(pdev->devfn);
1526 }
1527
1528 return false;
1529 }
1530
1531 static int prefer_ms_hyperv = 1;
1532 module_param(prefer_ms_hyperv, int, 0);
1533
1534 static void piix_ignore_devices_quirk(struct ata_host *host)
1535 {
1536 #if IS_ENABLED(CONFIG_HYPERV_STORAGE)
1537 static const struct dmi_system_id ignore_hyperv[] = {
1538 {
1539 /* On Hyper-V hypervisors the disks are exposed on
1540 * both the emulated SATA controller and on the
1541 * paravirtualised drivers. The CD/DVD devices
1542 * are only exposed on the emulated controller.
1543 * Request we ignore ATA devices on this host.
1544 */
1545 .ident = "Hyper-V Virtual Machine",
1546 .matches = {
1547 DMI_MATCH(DMI_SYS_VENDOR,
1548 "Microsoft Corporation"),
1549 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1550 },
1551 },
1552 { } /* terminate list */
1553 };
1554 static const struct dmi_system_id allow_virtual_pc[] = {
1555 {
1556 /* In MS Virtual PC guests the DMI ident is nearly
1557 * identical to a Hyper-V guest. One difference is the
1558 * product version which is used here to identify
1559 * a Virtual PC guest. This entry allows ata_piix to
1560 * drive the emulated hardware.
1561 */
1562 .ident = "MS Virtual PC 2007",
1563 .matches = {
1564 DMI_MATCH(DMI_SYS_VENDOR,
1565 "Microsoft Corporation"),
1566 DMI_MATCH(DMI_PRODUCT_NAME, "Virtual Machine"),
1567 DMI_MATCH(DMI_PRODUCT_VERSION, "VS2005R2"),
1568 },
1569 },
1570 { } /* terminate list */
1571 };
1572 const struct dmi_system_id *ignore = dmi_first_match(ignore_hyperv);
1573 const struct dmi_system_id *allow = dmi_first_match(allow_virtual_pc);
1574
1575 if (ignore && !allow && prefer_ms_hyperv) {
1576 host->flags |= ATA_HOST_IGNORE_ATA;
1577 dev_info(host->dev, "%s detected, ATA device ignore set\n",
1578 ignore->ident);
1579 }
1580 #endif
1581 }
1582
1583 /**
1584 * piix_init_one - Register PIIX ATA PCI device with kernel services
1585 * @pdev: PCI device to register
1586 * @ent: Entry in piix_pci_tbl matching with @pdev
1587 *
1588 * Called from kernel PCI layer. We probe for combined mode (sigh),
1589 * and then hand over control to libata, for it to do the rest.
1590 *
1591 * LOCKING:
1592 * Inherited from PCI layer (may sleep).
1593 *
1594 * RETURNS:
1595 * Zero on success, or -ERRNO value.
1596 */
1597
1598 static int piix_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1599 {
1600 struct device *dev = &pdev->dev;
1601 struct ata_port_info port_info[2];
1602 const struct ata_port_info *ppi[] = { &port_info[0], &port_info[1] };
1603 struct scsi_host_template *sht = &piix_sht;
1604 unsigned long port_flags;
1605 struct ata_host *host;
1606 struct piix_host_priv *hpriv;
1607 int rc;
1608
1609 ata_print_version_once(&pdev->dev, DRV_VERSION);
1610
1611 /* no hotplugging support for later devices (FIXME) */
1612 if (!in_module_init && ent->driver_data >= ich5_sata)
1613 return -ENODEV;
1614
1615 if (piix_broken_system_poweroff(pdev)) {
1616 piix_port_info[ent->driver_data].flags |=
1617 ATA_FLAG_NO_POWEROFF_SPINDOWN |
1618 ATA_FLAG_NO_HIBERNATE_SPINDOWN;
1619 dev_info(&pdev->dev, "quirky BIOS, skipping spindown "
1620 "on poweroff and hibernation\n");
1621 }
1622
1623 port_info[0] = piix_port_info[ent->driver_data];
1624 port_info[1] = piix_port_info[ent->driver_data];
1625
1626 port_flags = port_info[0].flags;
1627
1628 /* enable device and prepare host */
1629 rc = pcim_enable_device(pdev);
1630 if (rc)
1631 return rc;
1632
1633 hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1634 if (!hpriv)
1635 return -ENOMEM;
1636
1637 /* Save IOCFG, this will be used for cable detection, quirk
1638 * detection and restoration on detach. This is necessary
1639 * because some ACPI implementations mess up cable related
1640 * bits on _STM. Reported on kernel bz#11879.
1641 */
1642 pci_read_config_dword(pdev, PIIX_IOCFG, &hpriv->saved_iocfg);
1643
1644 /* ICH6R may be driven by either ata_piix or ahci driver
1645 * regardless of BIOS configuration. Make sure AHCI mode is
1646 * off.
1647 */
1648 if (pdev->vendor == PCI_VENDOR_ID_INTEL && pdev->device == 0x2652) {
1649 rc = piix_disable_ahci(pdev);
1650 if (rc)
1651 return rc;
1652 }
1653
1654 /* SATA map init can change port_info, do it before prepping host */
1655 if (port_flags & ATA_FLAG_SATA)
1656 hpriv->map = piix_init_sata_map(pdev, port_info,
1657 piix_map_db_table[ent->driver_data]);
1658
1659 rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
1660 if (rc)
1661 return rc;
1662 host->private_data = hpriv;
1663
1664 /* initialize controller */
1665 if (port_flags & ATA_FLAG_SATA) {
1666 piix_init_pcs(host, piix_map_db_table[ent->driver_data]);
1667 rc = piix_init_sidpr(host);
1668 if (rc)
1669 return rc;
1670 if (host->ports[0]->ops == &piix_sidpr_sata_ops)
1671 sht = &piix_sidpr_sht;
1672 }
1673
1674 /* apply IOCFG bit18 quirk */
1675 piix_iocfg_bit18_quirk(host);
1676
1677 /* On ICH5, some BIOSen disable the interrupt using the
1678 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
1679 * On ICH6, this bit has the same effect, but only when
1680 * MSI is disabled (and it is disabled, as we don't use
1681 * message-signalled interrupts currently).
1682 */
1683 if (port_flags & PIIX_FLAG_CHECKINTR)
1684 pci_intx(pdev, 1);
1685
1686 if (piix_check_450nx_errata(pdev)) {
1687 /* This writes into the master table but it does not
1688 really matter for this errata as we will apply it to
1689 all the PIIX devices on the board */
1690 host->ports[0]->mwdma_mask = 0;
1691 host->ports[0]->udma_mask = 0;
1692 host->ports[1]->mwdma_mask = 0;
1693 host->ports[1]->udma_mask = 0;
1694 }
1695 host->flags |= ATA_HOST_PARALLEL_SCAN;
1696
1697 /* Allow hosts to specify device types to ignore when scanning. */
1698 piix_ignore_devices_quirk(host);
1699
1700 pci_set_master(pdev);
1701 return ata_pci_sff_activate_host(host, ata_bmdma_interrupt, sht);
1702 }
1703
1704 static void piix_remove_one(struct pci_dev *pdev)
1705 {
1706 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1707 struct piix_host_priv *hpriv = host->private_data;
1708
1709 pci_write_config_dword(pdev, PIIX_IOCFG, hpriv->saved_iocfg);
1710
1711 ata_pci_remove_one(pdev);
1712 }
1713
1714 static struct pci_driver piix_pci_driver = {
1715 .name = DRV_NAME,
1716 .id_table = piix_pci_tbl,
1717 .probe = piix_init_one,
1718 .remove = piix_remove_one,
1719 #ifdef CONFIG_PM
1720 .suspend = piix_pci_device_suspend,
1721 .resume = piix_pci_device_resume,
1722 #endif
1723 };
1724
1725 static int __init piix_init(void)
1726 {
1727 int rc;
1728
1729 DPRINTK("pci_register_driver\n");
1730 rc = pci_register_driver(&piix_pci_driver);
1731 if (rc)
1732 return rc;
1733
1734 in_module_init = 0;
1735
1736 DPRINTK("done\n");
1737 return 0;
1738 }
1739
1740 static void __exit piix_exit(void)
1741 {
1742 pci_unregister_driver(&piix_pci_driver);
1743 }
1744
1745 module_init(piix_init);
1746 module_exit(piix_exit);
Linux with added FPC-III support