drivers/clk/mmp/clk-mmp2.c

   1 /*
   2  * mmp2 clock framework source file
   3  *
   4  * Copyright (C) 2012 Marvell
   5  * Chao Xie <xiechao.mail@gmail.com>
   6  *
   7  * This file is licensed under the terms of the GNU General Public
   8  * License version 2. This program is licensed "as is" without any
   9  * warranty of any kind, whether express or implied.
  10  */
  11
  12 #include <linux/module.h>
  13 #include <linux/kernel.h>
  14 #include <linux/spinlock.h>
  15 #include <linux/io.h>
  16 #include <linux/delay.h>
  17 #include <linux/err.h>
  18
  19 #include <mach/addr-map.h>
  20
  21 #include "clk.h"
  22
  23 #define APBC_RTC        0x0
  24 #define APBC_TWSI0      0x4
  25 #define APBC_TWSI1      0x8
  26 #define APBC_TWSI2      0xc
  27 #define APBC_TWSI3      0x10
  28 #define APBC_TWSI4      0x7c
  29 #define APBC_TWSI5      0x80
  30 #define APBC_KPC        0x18
  31 #define APBC_UART0      0x2c
  32 #define APBC_UART1      0x30
  33 #define APBC_UART2      0x34
  34 #define APBC_UART3      0x88
  35 #define APBC_GPIO       0x38
  36 #define APBC_PWM0       0x3c
  37 #define APBC_PWM1       0x40
  38 #define APBC_PWM2       0x44
  39 #define APBC_PWM3       0x48
  40 #define APBC_SSP0       0x50
  41 #define APBC_SSP1       0x54
  42 #define APBC_SSP2       0x58
  43 #define APBC_SSP3       0x5c
  44 #define APMU_SDH0       0x54
  45 #define APMU_SDH1       0x58
  46 #define APMU_SDH2       0xe8
  47 #define APMU_SDH3       0xec
  48 #define APMU_USB        0x5c
  49 #define APMU_DISP0      0x4c
  50 #define APMU_DISP1      0x110
  51 #define APMU_CCIC0      0x50
  52 #define APMU_CCIC1      0xf4
  53 #define MPMU_UART_PLL   0x14
  54
  55 static DEFINE_SPINLOCK(clk_lock);
  56
  57 static struct clk_factor_masks uart_factor_masks = {
  58         .factor = 2,
  59         .num_mask = 0x1fff,
  60         .den_mask = 0x1fff,
  61         .num_shift = 16,
  62         .den_shift = 0,
  63 };
  64
  65 static struct clk_factor_tbl uart_factor_tbl[] = {
  66         {.num = 14634, .den = 2165},    /*14.745MHZ */
  67         {.num = 3521, .den = 689},      /*19.23MHZ */
  68         {.num = 9679, .den = 5728},     /*58.9824MHZ */
  69         {.num = 15850, .den = 9451},    /*59.429MHZ */
  70 };
  71
  72 static const char *uart_parent[] = {"uart_pll", "vctcxo"};
  73 static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
  74 static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
  75 static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
  76 static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
  77
  78 void __init mmp2_clk_init(void)
  79 {
  80         struct clk *clk;
  81         struct clk *vctcxo;
  82         void __iomem *mpmu_base;
  83         void __iomem *apmu_base;
  84         void __iomem *apbc_base;
  85
  86         mpmu_base = ioremap(APB_PHYS_BASE + 0x50000, SZ_4K);
  87         if (mpmu_base == NULL) {
  88                 pr_err("error to ioremap MPMU base\n");
  89                 return;
  90         }
  91
  92         apmu_base = ioremap(AXI_PHYS_BASE + 0x82800, SZ_4K);
  93         if (apmu_base == NULL) {
  94                 pr_err("error to ioremap APMU base\n");
  95                 return;
  96         }
  97
  98         apbc_base = ioremap(APB_PHYS_BASE + 0x15000, SZ_4K);
  99         if (apbc_base == NULL) {
 100                 pr_err("error to ioremap APBC base\n");
 101                 return;
 102         }
 103
 104         clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
 105         clk_register_clkdev(clk, "clk32", NULL);
 106
 107         vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
 108                                 26000000);
 109         clk_register_clkdev(vctcxo, "vctcxo", NULL);
 110
 111         clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
 112                                 800000000);
 113         clk_register_clkdev(clk, "pll1", NULL);
 114
 115         clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
 116                                 480000000);
 117         clk_register_clkdev(clk, "usb_pll", NULL);
 118
 119         clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
 120                                 960000000);
 121         clk_register_clkdev(clk, "pll2", NULL);
 122
 123         clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
 124                                 CLK_SET_RATE_PARENT, 1, 2);
 125         clk_register_clkdev(clk, "pll1_2", NULL);
 126
 127         clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
 128                                 CLK_SET_RATE_PARENT, 1, 2);
 129         clk_register_clkdev(clk, "pll1_4", NULL);
 130
 131         clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
 132                                 CLK_SET_RATE_PARENT, 1, 2);
 133         clk_register_clkdev(clk, "pll1_8", NULL);
 134
 135         clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
 136                                 CLK_SET_RATE_PARENT, 1, 2);
 137         clk_register_clkdev(clk, "pll1_16", NULL);
 138
 139         clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
 140                                 CLK_SET_RATE_PARENT, 1, 5);
 141         clk_register_clkdev(clk, "pll1_20", NULL);
 142
 143         clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
 144                                 CLK_SET_RATE_PARENT, 1, 3);
 145         clk_register_clkdev(clk, "pll1_3", NULL);
 146
 147         clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
 148                                 CLK_SET_RATE_PARENT, 1, 2);
 149         clk_register_clkdev(clk, "pll1_6", NULL);
 150
 151         clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
 152                                 CLK_SET_RATE_PARENT, 1, 2);
 153         clk_register_clkdev(clk, "pll1_12", NULL);
 154
 155         clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
 156                                 CLK_SET_RATE_PARENT, 1, 2);
 157         clk_register_clkdev(clk, "pll2_2", NULL);
 158
 159         clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
 160                                 CLK_SET_RATE_PARENT, 1, 2);
 161         clk_register_clkdev(clk, "pll2_4", NULL);
 162
 163         clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
 164                                 CLK_SET_RATE_PARENT, 1, 2);
 165         clk_register_clkdev(clk, "pll2_8", NULL);
 166
 167         clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
 168                                 CLK_SET_RATE_PARENT, 1, 2);
 169         clk_register_clkdev(clk, "pll2_16", NULL);
 170
 171         clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
 172                                 CLK_SET_RATE_PARENT, 1, 3);
 173         clk_register_clkdev(clk, "pll2_3", NULL);
 174
 175         clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
 176                                 CLK_SET_RATE_PARENT, 1, 2);
 177         clk_register_clkdev(clk, "pll2_6", NULL);
 178
 179         clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
 180                                 CLK_SET_RATE_PARENT, 1, 2);
 181         clk_register_clkdev(clk, "pll2_12", NULL);
 182
 183         clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
 184                                 CLK_SET_RATE_PARENT, 1, 2);
 185         clk_register_clkdev(clk, "vctcxo_2", NULL);
 186
 187         clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
 188                                 CLK_SET_RATE_PARENT, 1, 2);
 189         clk_register_clkdev(clk, "vctcxo_4", NULL);
 190
 191         clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
 192                                 mpmu_base + MPMU_UART_PLL,
 193                                 &uart_factor_masks, uart_factor_tbl,
 194                                 ARRAY_SIZE(uart_factor_tbl));
 195         clk_set_rate(clk, 14745600);
 196         clk_register_clkdev(clk, "uart_pll", NULL);
 197
 198         clk = mmp_clk_register_apbc("twsi0", "vctcxo",
 199                                 apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
 200         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
 201
 202         clk = mmp_clk_register_apbc("twsi1", "vctcxo",
 203                                 apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
 204         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
 205
 206         clk = mmp_clk_register_apbc("twsi2", "vctcxo",
 207                                 apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
 208         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
 209
 210         clk = mmp_clk_register_apbc("twsi3", "vctcxo",
 211                                 apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
 212         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
 213
 214         clk = mmp_clk_register_apbc("twsi4", "vctcxo",
 215                                 apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
 216         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
 217
 218         clk = mmp_clk_register_apbc("twsi5", "vctcxo",
 219                                 apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
 220         clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
 221
 222         clk = mmp_clk_register_apbc("gpio", "vctcxo",
 223                                 apbc_base + APBC_GPIO, 10, 0, &clk_lock);
 224         clk_register_clkdev(clk, NULL, "pxa-gpio");
 225
 226         clk = mmp_clk_register_apbc("kpc", "clk32",
 227                                 apbc_base + APBC_KPC, 10, 0, &clk_lock);
 228         clk_register_clkdev(clk, NULL, "pxa27x-keypad");
 229
 230         clk = mmp_clk_register_apbc("rtc", "clk32",
 231                                 apbc_base + APBC_RTC, 10, 0, &clk_lock);
 232         clk_register_clkdev(clk, NULL, "mmp-rtc");
 233
 234         clk = mmp_clk_register_apbc("pwm0", "vctcxo",
 235                                 apbc_base + APBC_PWM0, 10, 0, &clk_lock);
 236         clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
 237
 238         clk = mmp_clk_register_apbc("pwm1", "vctcxo",
 239                                 apbc_base + APBC_PWM1, 10, 0, &clk_lock);
 240         clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
 241
 242         clk = mmp_clk_register_apbc("pwm2", "vctcxo",
 243                                 apbc_base + APBC_PWM2, 10, 0, &clk_lock);
 244         clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
 245
 246         clk = mmp_clk_register_apbc("pwm3", "vctcxo",
 247                                 apbc_base + APBC_PWM3, 10, 0, &clk_lock);
 248         clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
 249
 250         clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
 251                                 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
 252                                 apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
 253         clk_set_parent(clk, vctcxo);
 254         clk_register_clkdev(clk, "uart_mux.0", NULL);
 255
 256         clk = mmp_clk_register_apbc("uart0", "uart0_mux",
 257                                 apbc_base + APBC_UART0, 10, 0, &clk_lock);
 258         clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
 259
 260         clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
 261                                 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
 262                                 apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
 263         clk_set_parent(clk, vctcxo);
 264         clk_register_clkdev(clk, "uart_mux.1", NULL);
 265
 266         clk = mmp_clk_register_apbc("uart1", "uart1_mux",
 267                                 apbc_base + APBC_UART1, 10, 0, &clk_lock);
 268         clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
 269
 270         clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
 271                                 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
 272                                 apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
 273         clk_set_parent(clk, vctcxo);
 274         clk_register_clkdev(clk, "uart_mux.2", NULL);
 275
 276         clk = mmp_clk_register_apbc("uart2", "uart2_mux",
 277                                 apbc_base + APBC_UART2, 10, 0, &clk_lock);
 278         clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
 279
 280         clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
 281                                 ARRAY_SIZE(uart_parent), CLK_SET_RATE_PARENT,
 282                                 apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
 283         clk_set_parent(clk, vctcxo);
 284         clk_register_clkdev(clk, "uart_mux.3", NULL);
 285
 286         clk = mmp_clk_register_apbc("uart3", "uart3_mux",
 287                                 apbc_base + APBC_UART3, 10, 0, &clk_lock);
 288         clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
 289
 290         clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
 291                                 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
 292                                 apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
 293         clk_register_clkdev(clk, "uart_mux.0", NULL);
 294
 295         clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
 296                                 apbc_base + APBC_SSP0, 10, 0, &clk_lock);
 297         clk_register_clkdev(clk, NULL, "mmp-ssp.0");
 298
 299         clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
 300                                 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
 301                                 apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
 302         clk_register_clkdev(clk, "ssp_mux.1", NULL);
 303
 304         clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
 305                                 apbc_base + APBC_SSP1, 10, 0, &clk_lock);
 306         clk_register_clkdev(clk, NULL, "mmp-ssp.1");
 307
 308         clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
 309                                 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
 310                                 apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
 311         clk_register_clkdev(clk, "ssp_mux.2", NULL);
 312
 313         clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
 314                                 apbc_base + APBC_SSP2, 10, 0, &clk_lock);
 315         clk_register_clkdev(clk, NULL, "mmp-ssp.2");
 316
 317         clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
 318                                 ARRAY_SIZE(ssp_parent), CLK_SET_RATE_PARENT,
 319                                 apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
 320         clk_register_clkdev(clk, "ssp_mux.3", NULL);
 321
 322         clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
 323                                 apbc_base + APBC_SSP3, 10, 0, &clk_lock);
 324         clk_register_clkdev(clk, NULL, "mmp-ssp.3");
 325
 326         clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
 327                                 ARRAY_SIZE(sdh_parent), CLK_SET_RATE_PARENT,
 328                                 apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
 329         clk_register_clkdev(clk, "sdh_mux", NULL);
 330
 331         clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
 332                                 CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
 333                                 10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 334         clk_register_clkdev(clk, "sdh_div", NULL);
 335
 336         clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
 337                                 0x1b, &clk_lock);
 338         clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
 339
 340         clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
 341                                 0x1b, &clk_lock);
 342         clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
 343
 344         clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
 345                                 0x1b, &clk_lock);
 346         clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
 347
 348         clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
 349                                 0x1b, &clk_lock);
 350         clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
 351
 352         clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
 353                                 0x9, &clk_lock);
 354         clk_register_clkdev(clk, "usb_clk", NULL);
 355
 356         clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
 357                                 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
 358                                 apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
 359         clk_register_clkdev(clk, "disp_mux.0", NULL);
 360
 361         clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
 362                                 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
 363                                 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 364         clk_register_clkdev(clk, "disp_div.0", NULL);
 365
 366         clk = mmp_clk_register_apmu("disp0", "disp0_div",
 367                                 apmu_base + APMU_DISP0, 0x1b, &clk_lock);
 368         clk_register_clkdev(clk, NULL, "mmp-disp.0");
 369
 370         clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
 371                                 apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
 372         clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
 373
 374         clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
 375                                 apmu_base + APMU_DISP0, 0x1024, &clk_lock);
 376         clk_register_clkdev(clk, "disp_sphy.0", NULL);
 377
 378         clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
 379                                 ARRAY_SIZE(disp_parent), CLK_SET_RATE_PARENT,
 380                                 apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
 381         clk_register_clkdev(clk, "disp_mux.1", NULL);
 382
 383         clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
 384                                 CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
 385                                 8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 386         clk_register_clkdev(clk, "disp_div.1", NULL);
 387
 388         clk = mmp_clk_register_apmu("disp1", "disp1_div",
 389                                 apmu_base + APMU_DISP1, 0x1b, &clk_lock);
 390         clk_register_clkdev(clk, NULL, "mmp-disp.1");
 391
 392         clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
 393                                 apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
 394         clk_register_clkdev(clk, "ccic_arbiter", NULL);
 395
 396         clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
 397                                 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
 398                                 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
 399         clk_register_clkdev(clk, "ccic_mux.0", NULL);
 400
 401         clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
 402                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
 403                                 17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 404         clk_register_clkdev(clk, "ccic_div.0", NULL);
 405
 406         clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
 407                                 apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
 408         clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
 409
 410         clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
 411                                 apmu_base + APMU_CCIC0, 0x24, &clk_lock);
 412         clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
 413
 414         clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
 415                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
 416                                 10, 5, 0, &clk_lock);
 417         clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
 418
 419         clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
 420                                 apmu_base + APMU_CCIC0, 0x300, &clk_lock);
 421         clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
 422
 423         clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
 424                                 ARRAY_SIZE(ccic_parent), CLK_SET_RATE_PARENT,
 425                                 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
 426         clk_register_clkdev(clk, "ccic_mux.1", NULL);
 427
 428         clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
 429                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
 430                                 16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
 431         clk_register_clkdev(clk, "ccic_div.1", NULL);
 432
 433         clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
 434                                 apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
 435         clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
 436
 437         clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
 438                                 apmu_base + APMU_CCIC1, 0x24, &clk_lock);
 439         clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
 440
 441         clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
 442                                 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
 443                                 10, 5, 0, &clk_lock);
 444         clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
 445
 446         clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
 447                                 apmu_base + APMU_CCIC1, 0x300, &clk_lock);
 448         clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
 449 }