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net: move procfs code to net/core/net-procfs.c
[linux/fpc-iii.git] / drivers / infiniband / hw / cxgb4 / qp.c
blob05bfe53bff647b8e47ed1d6ef361734ce69b4e8e
1 /*
2 * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 */
32
33 #include <linux/module.h>
34
35 #include "iw_cxgb4.h"
36
37 static int db_delay_usecs = 1;
38 module_param(db_delay_usecs, int, 0644);
39 MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
40
41 static int ocqp_support = 1;
42 module_param(ocqp_support, int, 0644);
43 MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
44
45 int db_fc_threshold = 2000;
46 module_param(db_fc_threshold, int, 0644);
47 MODULE_PARM_DESC(db_fc_threshold, "QP count/threshold that triggers automatic "
48 "db flow control mode (default = 2000)");
49
50 static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
51 {
52 unsigned long flag;
53 spin_lock_irqsave(&qhp->lock, flag);
54 qhp->attr.state = state;
55 spin_unlock_irqrestore(&qhp->lock, flag);
56 }
57
58 static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
59 {
60 c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
61 }
62
63 static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
64 {
65 dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
66 pci_unmap_addr(sq, mapping));
67 }
68
69 static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
70 {
71 if (t4_sq_onchip(sq))
72 dealloc_oc_sq(rdev, sq);
73 else
74 dealloc_host_sq(rdev, sq);
75 }
76
77 static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
78 {
79 if (!ocqp_support || !t4_ocqp_supported())
80 return -ENOSYS;
81 sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
82 if (!sq->dma_addr)
83 return -ENOMEM;
84 sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
85 rdev->lldi.vr->ocq.start;
86 sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
87 rdev->lldi.vr->ocq.start);
88 sq->flags |= T4_SQ_ONCHIP;
89 return 0;
90 }
91
92 static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
93 {
94 sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
95 &(sq->dma_addr), GFP_KERNEL);
96 if (!sq->queue)
97 return -ENOMEM;
98 sq->phys_addr = virt_to_phys(sq->queue);
99 pci_unmap_addr_set(sq, mapping, sq->dma_addr);
100 return 0;
101 }
102
103 static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
104 struct c4iw_dev_ucontext *uctx)
105 {
106 /*
107 * uP clears EQ contexts when the connection exits rdma mode,
108 * so no need to post a RESET WR for these EQs.
109 */
110 dma_free_coherent(&(rdev->lldi.pdev->dev),
111 wq->rq.memsize, wq->rq.queue,
112 dma_unmap_addr(&wq->rq, mapping));
113 dealloc_sq(rdev, &wq->sq);
114 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
115 kfree(wq->rq.sw_rq);
116 kfree(wq->sq.sw_sq);
117 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
118 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
119 return 0;
120 }
121
122 static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
123 struct t4_cq *rcq, struct t4_cq *scq,
124 struct c4iw_dev_ucontext *uctx)
125 {
126 int user = (uctx != &rdev->uctx);
127 struct fw_ri_res_wr *res_wr;
128 struct fw_ri_res *res;
129 int wr_len;
130 struct c4iw_wr_wait wr_wait;
131 struct sk_buff *skb;
132 int ret;
133 int eqsize;
134
135 wq->sq.qid = c4iw_get_qpid(rdev, uctx);
136 if (!wq->sq.qid)
137 return -ENOMEM;
138
139 wq->rq.qid = c4iw_get_qpid(rdev, uctx);
140 if (!wq->rq.qid) {
141 ret = -ENOMEM;
142 goto free_sq_qid;
143 }
144
145 if (!user) {
146 wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
147 GFP_KERNEL);
148 if (!wq->sq.sw_sq) {
149 ret = -ENOMEM;
150 goto free_rq_qid;
151 }
152
153 wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
154 GFP_KERNEL);
155 if (!wq->rq.sw_rq) {
156 ret = -ENOMEM;
157 goto free_sw_sq;
158 }
159 }
160
161 /*
162 * RQT must be a power of 2.
163 */
164 wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
165 wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
166 if (!wq->rq.rqt_hwaddr) {
167 ret = -ENOMEM;
168 goto free_sw_rq;
169 }
170
171 if (user) {
172 ret = alloc_oc_sq(rdev, &wq->sq);
173 if (ret)
174 goto free_hwaddr;
175
176 ret = alloc_host_sq(rdev, &wq->sq);
177 if (ret)
178 goto free_sq;
179 } else
180 ret = alloc_host_sq(rdev, &wq->sq);
181 if (ret)
182 goto free_hwaddr;
183 memset(wq->sq.queue, 0, wq->sq.memsize);
184 dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
185
186 wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
187 wq->rq.memsize, &(wq->rq.dma_addr),
188 GFP_KERNEL);
189 if (!wq->rq.queue)
190 goto free_sq;
191 PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
192 __func__, wq->sq.queue,
193 (unsigned long long)virt_to_phys(wq->sq.queue),
194 wq->rq.queue,
195 (unsigned long long)virt_to_phys(wq->rq.queue));
196 memset(wq->rq.queue, 0, wq->rq.memsize);
197 dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
198
199 wq->db = rdev->lldi.db_reg;
200 wq->gts = rdev->lldi.gts_reg;
201 if (user) {
202 wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
203 (wq->sq.qid << rdev->qpshift);
204 wq->sq.udb &= PAGE_MASK;
205 wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
206 (wq->rq.qid << rdev->qpshift);
207 wq->rq.udb &= PAGE_MASK;
208 }
209 wq->rdev = rdev;
210 wq->rq.msn = 1;
211
212 /* build fw_ri_res_wr */
213 wr_len = sizeof *res_wr + 2 * sizeof *res;
214
215 skb = alloc_skb(wr_len, GFP_KERNEL);
216 if (!skb) {
217 ret = -ENOMEM;
218 goto free_dma;
219 }
220 set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
221
222 res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
223 memset(res_wr, 0, wr_len);
224 res_wr->op_nres = cpu_to_be32(
225 FW_WR_OP(FW_RI_RES_WR) |
226 V_FW_RI_RES_WR_NRES(2) |
227 FW_WR_COMPL(1));
228 res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
229 res_wr->cookie = (unsigned long) &wr_wait;
230 res = res_wr->res;
231 res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
232 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
233
234 /*
235 * eqsize is the number of 64B entries plus the status page size.
236 */
237 eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
238
239 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
240 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
241 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
242 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
243 (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
244 V_FW_RI_RES_WR_IQID(scq->cqid));
245 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
246 V_FW_RI_RES_WR_DCAEN(0) |
247 V_FW_RI_RES_WR_DCACPU(0) |
248 V_FW_RI_RES_WR_FBMIN(2) |
249 V_FW_RI_RES_WR_FBMAX(2) |
250 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
251 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
252 V_FW_RI_RES_WR_EQSIZE(eqsize));
253 res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
254 res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
255 res++;
256 res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
257 res->u.sqrq.op = FW_RI_RES_OP_WRITE;
258
259 /*
260 * eqsize is the number of 64B entries plus the status page size.
261 */
262 eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
263 res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
264 V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
265 V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
266 V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
267 V_FW_RI_RES_WR_IQID(rcq->cqid));
268 res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
269 V_FW_RI_RES_WR_DCAEN(0) |
270 V_FW_RI_RES_WR_DCACPU(0) |
271 V_FW_RI_RES_WR_FBMIN(2) |
272 V_FW_RI_RES_WR_FBMAX(2) |
273 V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
274 V_FW_RI_RES_WR_CIDXFTHRESH(0) |
275 V_FW_RI_RES_WR_EQSIZE(eqsize));
276 res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
277 res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
278
279 c4iw_init_wr_wait(&wr_wait);
280
281 ret = c4iw_ofld_send(rdev, skb);
282 if (ret)
283 goto free_dma;
284 ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
285 if (ret)
286 goto free_dma;
287
288 PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
289 __func__, wq->sq.qid, wq->rq.qid, wq->db,
290 (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
291
292 return 0;
293 free_dma:
294 dma_free_coherent(&(rdev->lldi.pdev->dev),
295 wq->rq.memsize, wq->rq.queue,
296 dma_unmap_addr(&wq->rq, mapping));
297 free_sq:
298 dealloc_sq(rdev, &wq->sq);
299 free_hwaddr:
300 c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
301 free_sw_rq:
302 kfree(wq->rq.sw_rq);
303 free_sw_sq:
304 kfree(wq->sq.sw_sq);
305 free_rq_qid:
306 c4iw_put_qpid(rdev, wq->rq.qid, uctx);
307 free_sq_qid:
308 c4iw_put_qpid(rdev, wq->sq.qid, uctx);
309 return ret;
310 }
311
312 static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
313 struct ib_send_wr *wr, int max, u32 *plenp)
314 {
315 u8 *dstp, *srcp;
316 u32 plen = 0;
317 int i;
318 int rem, len;
319
320 dstp = (u8 *)immdp->data;
321 for (i = 0; i < wr->num_sge; i++) {
322 if ((plen + wr->sg_list[i].length) > max)
323 return -EMSGSIZE;
324 srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
325 plen += wr->sg_list[i].length;
326 rem = wr->sg_list[i].length;
327 while (rem) {
328 if (dstp == (u8 *)&sq->queue[sq->size])
329 dstp = (u8 *)sq->queue;
330 if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
331 len = rem;
332 else
333 len = (u8 *)&sq->queue[sq->size] - dstp;
334 memcpy(dstp, srcp, len);
335 dstp += len;
336 srcp += len;
337 rem -= len;
338 }
339 }
340 len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
341 if (len)
342 memset(dstp, 0, len);
343 immdp->op = FW_RI_DATA_IMMD;
344 immdp->r1 = 0;
345 immdp->r2 = 0;
346 immdp->immdlen = cpu_to_be32(plen);
347 *plenp = plen;
348 return 0;
349 }
350
351 static int build_isgl(__be64 *queue_start, __be64 *queue_end,
352 struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
353 int num_sge, u32 *plenp)
354
355 {
356 int i;
357 u32 plen = 0;
358 __be64 *flitp = (__be64 *)isglp->sge;
359
360 for (i = 0; i < num_sge; i++) {
361 if ((plen + sg_list[i].length) < plen)
362 return -EMSGSIZE;
363 plen += sg_list[i].length;
364 *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
365 sg_list[i].length);
366 if (++flitp == queue_end)
367 flitp = queue_start;
368 *flitp = cpu_to_be64(sg_list[i].addr);
369 if (++flitp == queue_end)
370 flitp = queue_start;
371 }
372 *flitp = (__force __be64)0;
373 isglp->op = FW_RI_DATA_ISGL;
374 isglp->r1 = 0;
375 isglp->nsge = cpu_to_be16(num_sge);
376 isglp->r2 = 0;
377 if (plenp)
378 *plenp = plen;
379 return 0;
380 }
381
382 static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
383 struct ib_send_wr *wr, u8 *len16)
384 {
385 u32 plen;
386 int size;
387 int ret;
388
389 if (wr->num_sge > T4_MAX_SEND_SGE)
390 return -EINVAL;
391 switch (wr->opcode) {
392 case IB_WR_SEND:
393 if (wr->send_flags & IB_SEND_SOLICITED)
394 wqe->send.sendop_pkd = cpu_to_be32(
395 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
396 else
397 wqe->send.sendop_pkd = cpu_to_be32(
398 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
399 wqe->send.stag_inv = 0;
400 break;
401 case IB_WR_SEND_WITH_INV:
402 if (wr->send_flags & IB_SEND_SOLICITED)
403 wqe->send.sendop_pkd = cpu_to_be32(
404 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
405 else
406 wqe->send.sendop_pkd = cpu_to_be32(
407 V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
408 wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
409 break;
410
411 default:
412 return -EINVAL;
413 }
414
415 plen = 0;
416 if (wr->num_sge) {
417 if (wr->send_flags & IB_SEND_INLINE) {
418 ret = build_immd(sq, wqe->send.u.immd_src, wr,
419 T4_MAX_SEND_INLINE, &plen);
420 if (ret)
421 return ret;
422 size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
423 plen;
424 } else {
425 ret = build_isgl((__be64 *)sq->queue,
426 (__be64 *)&sq->queue[sq->size],
427 wqe->send.u.isgl_src,
428 wr->sg_list, wr->num_sge, &plen);
429 if (ret)
430 return ret;
431 size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
432 wr->num_sge * sizeof(struct fw_ri_sge);
433 }
434 } else {
435 wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
436 wqe->send.u.immd_src[0].r1 = 0;
437 wqe->send.u.immd_src[0].r2 = 0;
438 wqe->send.u.immd_src[0].immdlen = 0;
439 size = sizeof wqe->send + sizeof(struct fw_ri_immd);
440 plen = 0;
441 }
442 *len16 = DIV_ROUND_UP(size, 16);
443 wqe->send.plen = cpu_to_be32(plen);
444 return 0;
445 }
446
447 static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
448 struct ib_send_wr *wr, u8 *len16)
449 {
450 u32 plen;
451 int size;
452 int ret;
453
454 if (wr->num_sge > T4_MAX_SEND_SGE)
455 return -EINVAL;
456 wqe->write.r2 = 0;
457 wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
458 wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
459 if (wr->num_sge) {
460 if (wr->send_flags & IB_SEND_INLINE) {
461 ret = build_immd(sq, wqe->write.u.immd_src, wr,
462 T4_MAX_WRITE_INLINE, &plen);
463 if (ret)
464 return ret;
465 size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
466 plen;
467 } else {
468 ret = build_isgl((__be64 *)sq->queue,
469 (__be64 *)&sq->queue[sq->size],
470 wqe->write.u.isgl_src,
471 wr->sg_list, wr->num_sge, &plen);
472 if (ret)
473 return ret;
474 size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
475 wr->num_sge * sizeof(struct fw_ri_sge);
476 }
477 } else {
478 wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
479 wqe->write.u.immd_src[0].r1 = 0;
480 wqe->write.u.immd_src[0].r2 = 0;
481 wqe->write.u.immd_src[0].immdlen = 0;
482 size = sizeof wqe->write + sizeof(struct fw_ri_immd);
483 plen = 0;
484 }
485 *len16 = DIV_ROUND_UP(size, 16);
486 wqe->write.plen = cpu_to_be32(plen);
487 return 0;
488 }
489
490 static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
491 {
492 if (wr->num_sge > 1)
493 return -EINVAL;
494 if (wr->num_sge) {
495 wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
496 wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
497 >> 32));
498 wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
499 wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
500 wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
501 wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
502 >> 32));
503 wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
504 } else {
505 wqe->read.stag_src = cpu_to_be32(2);
506 wqe->read.to_src_hi = 0;
507 wqe->read.to_src_lo = 0;
508 wqe->read.stag_sink = cpu_to_be32(2);
509 wqe->read.plen = 0;
510 wqe->read.to_sink_hi = 0;
511 wqe->read.to_sink_lo = 0;
512 }
513 wqe->read.r2 = 0;
514 wqe->read.r5 = 0;
515 *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
516 return 0;
517 }
518
519 static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
520 struct ib_recv_wr *wr, u8 *len16)
521 {
522 int ret;
523
524 ret = build_isgl((__be64 *)qhp->wq.rq.queue,
525 (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
526 &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
527 if (ret)
528 return ret;
529 *len16 = DIV_ROUND_UP(sizeof wqe->recv +
530 wr->num_sge * sizeof(struct fw_ri_sge), 16);
531 return 0;
532 }
533
534 static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
535 struct ib_send_wr *wr, u8 *len16)
536 {
537
538 struct fw_ri_immd *imdp;
539 __be64 *p;
540 int i;
541 int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
542 int rem;
543
544 if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
545 return -EINVAL;
546
547 wqe->fr.qpbinde_to_dcacpu = 0;
548 wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
549 wqe->fr.addr_type = FW_RI_VA_BASED_TO;
550 wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
551 wqe->fr.len_hi = 0;
552 wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
553 wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
554 wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
555 wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
556 0xffffffff);
557 WARN_ON(pbllen > T4_MAX_FR_IMMD);
558 imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
559 imdp->op = FW_RI_DATA_IMMD;
560 imdp->r1 = 0;
561 imdp->r2 = 0;
562 imdp->immdlen = cpu_to_be32(pbllen);
563 p = (__be64 *)(imdp + 1);
564 rem = pbllen;
565 for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
566 *p = cpu_to_be64((u64)wr->wr.fast_reg.page_list->page_list[i]);
567 rem -= sizeof *p;
568 if (++p == (__be64 *)&sq->queue[sq->size])
569 p = (__be64 *)sq->queue;
570 }
571 BUG_ON(rem < 0);
572 while (rem) {
573 *p = 0;
574 rem -= sizeof *p;
575 if (++p == (__be64 *)&sq->queue[sq->size])
576 p = (__be64 *)sq->queue;
577 }
578 *len16 = DIV_ROUND_UP(sizeof wqe->fr + sizeof *imdp + pbllen, 16);
579 return 0;
580 }
581
582 static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
583 u8 *len16)
584 {
585 wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
586 wqe->inv.r2 = 0;
587 *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
588 return 0;
589 }
590
591 void c4iw_qp_add_ref(struct ib_qp *qp)
592 {
593 PDBG("%s ib_qp %p\n", __func__, qp);
594 atomic_inc(&(to_c4iw_qp(qp)->refcnt));
595 }
596
597 void c4iw_qp_rem_ref(struct ib_qp *qp)
598 {
599 PDBG("%s ib_qp %p\n", __func__, qp);
600 if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
601 wake_up(&(to_c4iw_qp(qp)->wait));
602 }
603
604 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
605 struct ib_send_wr **bad_wr)
606 {
607 int err = 0;
608 u8 len16 = 0;
609 enum fw_wr_opcodes fw_opcode = 0;
610 enum fw_ri_wr_flags fw_flags;
611 struct c4iw_qp *qhp;
612 union t4_wr *wqe;
613 u32 num_wrs;
614 struct t4_swsqe *swsqe;
615 unsigned long flag;
616 u16 idx = 0;
617
618 qhp = to_c4iw_qp(ibqp);
619 spin_lock_irqsave(&qhp->lock, flag);
620 if (t4_wq_in_error(&qhp->wq)) {
621 spin_unlock_irqrestore(&qhp->lock, flag);
622 return -EINVAL;
623 }
624 num_wrs = t4_sq_avail(&qhp->wq);
625 if (num_wrs == 0) {
626 spin_unlock_irqrestore(&qhp->lock, flag);
627 return -ENOMEM;
628 }
629 while (wr) {
630 if (num_wrs == 0) {
631 err = -ENOMEM;
632 *bad_wr = wr;
633 break;
634 }
635 wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
636 qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
637
638 fw_flags = 0;
639 if (wr->send_flags & IB_SEND_SOLICITED)
640 fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
641 if (wr->send_flags & IB_SEND_SIGNALED)
642 fw_flags |= FW_RI_COMPLETION_FLAG;
643 swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
644 switch (wr->opcode) {
645 case IB_WR_SEND_WITH_INV:
646 case IB_WR_SEND:
647 if (wr->send_flags & IB_SEND_FENCE)
648 fw_flags |= FW_RI_READ_FENCE_FLAG;
649 fw_opcode = FW_RI_SEND_WR;
650 if (wr->opcode == IB_WR_SEND)
651 swsqe->opcode = FW_RI_SEND;
652 else
653 swsqe->opcode = FW_RI_SEND_WITH_INV;
654 err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
655 break;
656 case IB_WR_RDMA_WRITE:
657 fw_opcode = FW_RI_RDMA_WRITE_WR;
658 swsqe->opcode = FW_RI_RDMA_WRITE;
659 err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
660 break;
661 case IB_WR_RDMA_READ:
662 case IB_WR_RDMA_READ_WITH_INV:
663 fw_opcode = FW_RI_RDMA_READ_WR;
664 swsqe->opcode = FW_RI_READ_REQ;
665 if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
666 fw_flags = FW_RI_RDMA_READ_INVALIDATE;
667 else
668 fw_flags = 0;
669 err = build_rdma_read(wqe, wr, &len16);
670 if (err)
671 break;
672 swsqe->read_len = wr->sg_list[0].length;
673 if (!qhp->wq.sq.oldest_read)
674 qhp->wq.sq.oldest_read = swsqe;
675 break;
676 case IB_WR_FAST_REG_MR:
677 fw_opcode = FW_RI_FR_NSMR_WR;
678 swsqe->opcode = FW_RI_FAST_REGISTER;
679 err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16);
680 break;
681 case IB_WR_LOCAL_INV:
682 if (wr->send_flags & IB_SEND_FENCE)
683 fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
684 fw_opcode = FW_RI_INV_LSTAG_WR;
685 swsqe->opcode = FW_RI_LOCAL_INV;
686 err = build_inv_stag(wqe, wr, &len16);
687 break;
688 default:
689 PDBG("%s post of type=%d TBD!\n", __func__,
690 wr->opcode);
691 err = -EINVAL;
692 }
693 if (err) {
694 *bad_wr = wr;
695 break;
696 }
697 swsqe->idx = qhp->wq.sq.pidx;
698 swsqe->complete = 0;
699 swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
700 swsqe->wr_id = wr->wr_id;
701
702 init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
703
704 PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
705 __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
706 swsqe->opcode, swsqe->read_len);
707 wr = wr->next;
708 num_wrs--;
709 t4_sq_produce(&qhp->wq, len16);
710 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
711 }
712 if (t4_wq_db_enabled(&qhp->wq))
713 t4_ring_sq_db(&qhp->wq, idx);
714 spin_unlock_irqrestore(&qhp->lock, flag);
715 return err;
716 }
717
718 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
719 struct ib_recv_wr **bad_wr)
720 {
721 int err = 0;
722 struct c4iw_qp *qhp;
723 union t4_recv_wr *wqe;
724 u32 num_wrs;
725 u8 len16 = 0;
726 unsigned long flag;
727 u16 idx = 0;
728
729 qhp = to_c4iw_qp(ibqp);
730 spin_lock_irqsave(&qhp->lock, flag);
731 if (t4_wq_in_error(&qhp->wq)) {
732 spin_unlock_irqrestore(&qhp->lock, flag);
733 return -EINVAL;
734 }
735 num_wrs = t4_rq_avail(&qhp->wq);
736 if (num_wrs == 0) {
737 spin_unlock_irqrestore(&qhp->lock, flag);
738 return -ENOMEM;
739 }
740 while (wr) {
741 if (wr->num_sge > T4_MAX_RECV_SGE) {
742 err = -EINVAL;
743 *bad_wr = wr;
744 break;
745 }
746 wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
747 qhp->wq.rq.wq_pidx *
748 T4_EQ_ENTRY_SIZE);
749 if (num_wrs)
750 err = build_rdma_recv(qhp, wqe, wr, &len16);
751 else
752 err = -ENOMEM;
753 if (err) {
754 *bad_wr = wr;
755 break;
756 }
757
758 qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
759
760 wqe->recv.opcode = FW_RI_RECV_WR;
761 wqe->recv.r1 = 0;
762 wqe->recv.wrid = qhp->wq.rq.pidx;
763 wqe->recv.r2[0] = 0;
764 wqe->recv.r2[1] = 0;
765 wqe->recv.r2[2] = 0;
766 wqe->recv.len16 = len16;
767 PDBG("%s cookie 0x%llx pidx %u\n", __func__,
768 (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
769 t4_rq_produce(&qhp->wq, len16);
770 idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
771 wr = wr->next;
772 num_wrs--;
773 }
774 if (t4_wq_db_enabled(&qhp->wq))
775 t4_ring_rq_db(&qhp->wq, idx);
776 spin_unlock_irqrestore(&qhp->lock, flag);
777 return err;
778 }
779
780 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
781 {
782 return -ENOSYS;
783 }
784
785 static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
786 u8 *ecode)
787 {
788 int status;
789 int tagged;
790 int opcode;
791 int rqtype;
792 int send_inv;
793
794 if (!err_cqe) {
795 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
796 *ecode = 0;
797 return;
798 }
799
800 status = CQE_STATUS(err_cqe);
801 opcode = CQE_OPCODE(err_cqe);
802 rqtype = RQ_TYPE(err_cqe);
803 send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
804 (opcode == FW_RI_SEND_WITH_SE_INV);
805 tagged = (opcode == FW_RI_RDMA_WRITE) ||
806 (rqtype && (opcode == FW_RI_READ_RESP));
807
808 switch (status) {
809 case T4_ERR_STAG:
810 if (send_inv) {
811 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
812 *ecode = RDMAP_CANT_INV_STAG;
813 } else {
814 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
815 *ecode = RDMAP_INV_STAG;
816 }
817 break;
818 case T4_ERR_PDID:
819 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
820 if ((opcode == FW_RI_SEND_WITH_INV) ||
821 (opcode == FW_RI_SEND_WITH_SE_INV))
822 *ecode = RDMAP_CANT_INV_STAG;
823 else
824 *ecode = RDMAP_STAG_NOT_ASSOC;
825 break;
826 case T4_ERR_QPID:
827 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
828 *ecode = RDMAP_STAG_NOT_ASSOC;
829 break;
830 case T4_ERR_ACCESS:
831 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
832 *ecode = RDMAP_ACC_VIOL;
833 break;
834 case T4_ERR_WRAP:
835 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
836 *ecode = RDMAP_TO_WRAP;
837 break;
838 case T4_ERR_BOUND:
839 if (tagged) {
840 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
841 *ecode = DDPT_BASE_BOUNDS;
842 } else {
843 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
844 *ecode = RDMAP_BASE_BOUNDS;
845 }
846 break;
847 case T4_ERR_INVALIDATE_SHARED_MR:
848 case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
849 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
850 *ecode = RDMAP_CANT_INV_STAG;
851 break;
852 case T4_ERR_ECC:
853 case T4_ERR_ECC_PSTAG:
854 case T4_ERR_INTERNAL_ERR:
855 *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
856 *ecode = 0;
857 break;
858 case T4_ERR_OUT_OF_RQE:
859 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
860 *ecode = DDPU_INV_MSN_NOBUF;
861 break;
862 case T4_ERR_PBL_ADDR_BOUND:
863 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
864 *ecode = DDPT_BASE_BOUNDS;
865 break;
866 case T4_ERR_CRC:
867 *layer_type = LAYER_MPA|DDP_LLP;
868 *ecode = MPA_CRC_ERR;
869 break;
870 case T4_ERR_MARKER:
871 *layer_type = LAYER_MPA|DDP_LLP;
872 *ecode = MPA_MARKER_ERR;
873 break;
874 case T4_ERR_PDU_LEN_ERR:
875 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
876 *ecode = DDPU_MSG_TOOBIG;
877 break;
878 case T4_ERR_DDP_VERSION:
879 if (tagged) {
880 *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
881 *ecode = DDPT_INV_VERS;
882 } else {
883 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
884 *ecode = DDPU_INV_VERS;
885 }
886 break;
887 case T4_ERR_RDMA_VERSION:
888 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
889 *ecode = RDMAP_INV_VERS;
890 break;
891 case T4_ERR_OPCODE:
892 *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
893 *ecode = RDMAP_INV_OPCODE;
894 break;
895 case T4_ERR_DDP_QUEUE_NUM:
896 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
897 *ecode = DDPU_INV_QN;
898 break;
899 case T4_ERR_MSN:
900 case T4_ERR_MSN_GAP:
901 case T4_ERR_MSN_RANGE:
902 case T4_ERR_IRD_OVERFLOW:
903 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
904 *ecode = DDPU_INV_MSN_RANGE;
905 break;
906 case T4_ERR_TBIT:
907 *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
908 *ecode = 0;
909 break;
910 case T4_ERR_MO:
911 *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
912 *ecode = DDPU_INV_MO;
913 break;
914 default:
915 *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
916 *ecode = 0;
917 break;
918 }
919 }
920
921 static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
922 gfp_t gfp)
923 {
924 struct fw_ri_wr *wqe;
925 struct sk_buff *skb;
926 struct terminate_message *term;
927
928 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
929 qhp->ep->hwtid);
930
931 skb = alloc_skb(sizeof *wqe, gfp);
932 if (!skb)
933 return;
934 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
935
936 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
937 memset(wqe, 0, sizeof *wqe);
938 wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
939 wqe->flowid_len16 = cpu_to_be32(
940 FW_WR_FLOWID(qhp->ep->hwtid) |
941 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
942
943 wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
944 wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
945 term = (struct terminate_message *)wqe->u.terminate.termmsg;
946 if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
947 term->layer_etype = qhp->attr.layer_etype;
948 term->ecode = qhp->attr.ecode;
949 } else
950 build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
951 c4iw_ofld_send(&qhp->rhp->rdev, skb);
952 }
953
954 /*
955 * Assumes qhp lock is held.
956 */
957 static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
958 struct c4iw_cq *schp)
959 {
960 int count;
961 int flushed;
962 unsigned long flag;
963
964 PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
965
966 /* locking hierarchy: cq lock first, then qp lock. */
967 spin_lock_irqsave(&rchp->lock, flag);
968 spin_lock(&qhp->lock);
969 c4iw_flush_hw_cq(&rchp->cq);
970 c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
971 flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
972 spin_unlock(&qhp->lock);
973 spin_unlock_irqrestore(&rchp->lock, flag);
974 if (flushed) {
975 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
976 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
977 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
978 }
979
980 /* locking hierarchy: cq lock first, then qp lock. */
981 spin_lock_irqsave(&schp->lock, flag);
982 spin_lock(&qhp->lock);
983 c4iw_flush_hw_cq(&schp->cq);
984 c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
985 flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
986 spin_unlock(&qhp->lock);
987 spin_unlock_irqrestore(&schp->lock, flag);
988 if (flushed) {
989 spin_lock_irqsave(&schp->comp_handler_lock, flag);
990 (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
991 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
992 }
993 }
994
995 static void flush_qp(struct c4iw_qp *qhp)
996 {
997 struct c4iw_cq *rchp, *schp;
998 unsigned long flag;
999
1000 rchp = get_chp(qhp->rhp, qhp->attr.rcq);
1001 schp = get_chp(qhp->rhp, qhp->attr.scq);
1002
1003 if (qhp->ibqp.uobject) {
1004 t4_set_wq_in_error(&qhp->wq);
1005 t4_set_cq_in_error(&rchp->cq);
1006 spin_lock_irqsave(&rchp->comp_handler_lock, flag);
1007 (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
1008 spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
1009 if (schp != rchp) {
1010 t4_set_cq_in_error(&schp->cq);
1011 spin_lock_irqsave(&schp->comp_handler_lock, flag);
1012 (*schp->ibcq.comp_handler)(&schp->ibcq,
1013 schp->ibcq.cq_context);
1014 spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
1015 }
1016 return;
1017 }
1018 __flush_qp(qhp, rchp, schp);
1019 }
1020
1021 static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1022 struct c4iw_ep *ep)
1023 {
1024 struct fw_ri_wr *wqe;
1025 int ret;
1026 struct sk_buff *skb;
1027
1028 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1029 ep->hwtid);
1030
1031 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1032 if (!skb)
1033 return -ENOMEM;
1034 set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
1035
1036 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1037 memset(wqe, 0, sizeof *wqe);
1038 wqe->op_compl = cpu_to_be32(
1039 FW_WR_OP(FW_RI_INIT_WR) |
1040 FW_WR_COMPL(1));
1041 wqe->flowid_len16 = cpu_to_be32(
1042 FW_WR_FLOWID(ep->hwtid) |
1043 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1044 wqe->cookie = (unsigned long) &ep->com.wr_wait;
1045
1046 wqe->u.fini.type = FW_RI_TYPE_FINI;
1047 ret = c4iw_ofld_send(&rhp->rdev, skb);
1048 if (ret)
1049 goto out;
1050
1051 ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
1052 qhp->wq.sq.qid, __func__);
1053 out:
1054 PDBG("%s ret %d\n", __func__, ret);
1055 return ret;
1056 }
1057
1058 static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
1059 {
1060 PDBG("%s p2p_type = %d\n", __func__, p2p_type);
1061 memset(&init->u, 0, sizeof init->u);
1062 switch (p2p_type) {
1063 case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
1064 init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
1065 init->u.write.stag_sink = cpu_to_be32(1);
1066 init->u.write.to_sink = cpu_to_be64(1);
1067 init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
1068 init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
1069 sizeof(struct fw_ri_immd),
1070 16);
1071 break;
1072 case FW_RI_INIT_P2PTYPE_READ_REQ:
1073 init->u.write.opcode = FW_RI_RDMA_READ_WR;
1074 init->u.read.stag_src = cpu_to_be32(1);
1075 init->u.read.to_src_lo = cpu_to_be32(1);
1076 init->u.read.stag_sink = cpu_to_be32(1);
1077 init->u.read.to_sink_lo = cpu_to_be32(1);
1078 init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
1079 break;
1080 }
1081 }
1082
1083 static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
1084 {
1085 struct fw_ri_wr *wqe;
1086 int ret;
1087 struct sk_buff *skb;
1088
1089 PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
1090 qhp->ep->hwtid);
1091
1092 skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
1093 if (!skb)
1094 return -ENOMEM;
1095 set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
1096
1097 wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
1098 memset(wqe, 0, sizeof *wqe);
1099 wqe->op_compl = cpu_to_be32(
1100 FW_WR_OP(FW_RI_INIT_WR) |
1101 FW_WR_COMPL(1));
1102 wqe->flowid_len16 = cpu_to_be32(
1103 FW_WR_FLOWID(qhp->ep->hwtid) |
1104 FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
1105
1106 wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
1107
1108 wqe->u.init.type = FW_RI_TYPE_INIT;
1109 wqe->u.init.mpareqbit_p2ptype =
1110 V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
1111 V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
1112 wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
1113 if (qhp->attr.mpa_attr.recv_marker_enabled)
1114 wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
1115 if (qhp->attr.mpa_attr.xmit_marker_enabled)
1116 wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
1117 if (qhp->attr.mpa_attr.crc_enabled)
1118 wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
1119
1120 wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
1121 FW_RI_QP_RDMA_WRITE_ENABLE |
1122 FW_RI_QP_BIND_ENABLE;
1123 if (!qhp->ibqp.uobject)
1124 wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
1125 FW_RI_QP_STAG0_ENABLE;
1126 wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
1127 wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
1128 wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
1129 wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
1130 wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
1131 wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
1132 wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
1133 wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
1134 wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
1135 wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
1136 wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
1137 wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
1138 wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
1139 rhp->rdev.lldi.vr->rq.start);
1140 if (qhp->attr.mpa_attr.initiator)
1141 build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
1142
1143 ret = c4iw_ofld_send(&rhp->rdev, skb);
1144 if (ret)
1145 goto out;
1146
1147 ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
1148 qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
1149 out:
1150 PDBG("%s ret %d\n", __func__, ret);
1151 return ret;
1152 }
1153
1154 /*
1155 * Called by the library when the qp has user dbs disabled due to
1156 * a DB_FULL condition. This function will single-thread all user
1157 * DB rings to avoid overflowing the hw db-fifo.
1158 */
1159 static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
1160 {
1161 int delay = db_delay_usecs;
1162
1163 mutex_lock(&qhp->rhp->db_mutex);
1164 do {
1165
1166 /*
1167 * The interrupt threshold is dbfifo_int_thresh << 6. So
1168 * make sure we don't cross that and generate an interrupt.
1169 */
1170 if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) <
1171 (qhp->rhp->rdev.lldi.dbfifo_int_thresh << 5)) {
1172 writel(QID(qid) | PIDX(inc), qhp->wq.db);
1173 break;
1174 }
1175 set_current_state(TASK_UNINTERRUPTIBLE);
1176 schedule_timeout(usecs_to_jiffies(delay));
1177 delay = min(delay << 1, 2000);
1178 } while (1);
1179 mutex_unlock(&qhp->rhp->db_mutex);
1180 return 0;
1181 }
1182
1183 int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
1184 enum c4iw_qp_attr_mask mask,
1185 struct c4iw_qp_attributes *attrs,
1186 int internal)
1187 {
1188 int ret = 0;
1189 struct c4iw_qp_attributes newattr = qhp->attr;
1190 int disconnect = 0;
1191 int terminate = 0;
1192 int abort = 0;
1193 int free = 0;
1194 struct c4iw_ep *ep = NULL;
1195
1196 PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
1197 qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
1198 (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
1199
1200 mutex_lock(&qhp->mutex);
1201
1202 /* Process attr changes if in IDLE */
1203 if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
1204 if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
1205 ret = -EIO;
1206 goto out;
1207 }
1208 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
1209 newattr.enable_rdma_read = attrs->enable_rdma_read;
1210 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
1211 newattr.enable_rdma_write = attrs->enable_rdma_write;
1212 if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
1213 newattr.enable_bind = attrs->enable_bind;
1214 if (mask & C4IW_QP_ATTR_MAX_ORD) {
1215 if (attrs->max_ord > c4iw_max_read_depth) {
1216 ret = -EINVAL;
1217 goto out;
1218 }
1219 newattr.max_ord = attrs->max_ord;
1220 }
1221 if (mask & C4IW_QP_ATTR_MAX_IRD) {
1222 if (attrs->max_ird > c4iw_max_read_depth) {
1223 ret = -EINVAL;
1224 goto out;
1225 }
1226 newattr.max_ird = attrs->max_ird;
1227 }
1228 qhp->attr = newattr;
1229 }
1230
1231 if (mask & C4IW_QP_ATTR_SQ_DB) {
1232 ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
1233 goto out;
1234 }
1235 if (mask & C4IW_QP_ATTR_RQ_DB) {
1236 ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
1237 goto out;
1238 }
1239
1240 if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
1241 goto out;
1242 if (qhp->attr.state == attrs->next_state)
1243 goto out;
1244
1245 switch (qhp->attr.state) {
1246 case C4IW_QP_STATE_IDLE:
1247 switch (attrs->next_state) {
1248 case C4IW_QP_STATE_RTS:
1249 if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
1250 ret = -EINVAL;
1251 goto out;
1252 }
1253 if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
1254 ret = -EINVAL;
1255 goto out;
1256 }
1257 qhp->attr.mpa_attr = attrs->mpa_attr;
1258 qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
1259 qhp->ep = qhp->attr.llp_stream_handle;
1260 set_state(qhp, C4IW_QP_STATE_RTS);
1261
1262 /*
1263 * Ref the endpoint here and deref when we
1264 * disassociate the endpoint from the QP. This
1265 * happens in CLOSING->IDLE transition or *->ERROR
1266 * transition.
1267 */
1268 c4iw_get_ep(&qhp->ep->com);
1269 ret = rdma_init(rhp, qhp);
1270 if (ret)
1271 goto err;
1272 break;
1273 case C4IW_QP_STATE_ERROR:
1274 set_state(qhp, C4IW_QP_STATE_ERROR);
1275 flush_qp(qhp);
1276 break;
1277 default:
1278 ret = -EINVAL;
1279 goto out;
1280 }
1281 break;
1282 case C4IW_QP_STATE_RTS:
1283 switch (attrs->next_state) {
1284 case C4IW_QP_STATE_CLOSING:
1285 BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
1286 set_state(qhp, C4IW_QP_STATE_CLOSING);
1287 ep = qhp->ep;
1288 if (!internal) {
1289 abort = 0;
1290 disconnect = 1;
1291 c4iw_get_ep(&qhp->ep->com);
1292 }
1293 if (qhp->ibqp.uobject)
1294 t4_set_wq_in_error(&qhp->wq);
1295 ret = rdma_fini(rhp, qhp, ep);
1296 if (ret)
1297 goto err;
1298 break;
1299 case C4IW_QP_STATE_TERMINATE:
1300 set_state(qhp, C4IW_QP_STATE_TERMINATE);
1301 qhp->attr.layer_etype = attrs->layer_etype;
1302 qhp->attr.ecode = attrs->ecode;
1303 if (qhp->ibqp.uobject)
1304 t4_set_wq_in_error(&qhp->wq);
1305 ep = qhp->ep;
1306 if (!internal)
1307 terminate = 1;
1308 disconnect = 1;
1309 c4iw_get_ep(&qhp->ep->com);
1310 break;
1311 case C4IW_QP_STATE_ERROR:
1312 set_state(qhp, C4IW_QP_STATE_ERROR);
1313 if (qhp->ibqp.uobject)
1314 t4_set_wq_in_error(&qhp->wq);
1315 if (!internal) {
1316 abort = 1;
1317 disconnect = 1;
1318 ep = qhp->ep;
1319 c4iw_get_ep(&qhp->ep->com);
1320 }
1321 goto err;
1322 break;
1323 default:
1324 ret = -EINVAL;
1325 goto out;
1326 }
1327 break;
1328 case C4IW_QP_STATE_CLOSING:
1329 if (!internal) {
1330 ret = -EINVAL;
1331 goto out;
1332 }
1333 switch (attrs->next_state) {
1334 case C4IW_QP_STATE_IDLE:
1335 flush_qp(qhp);
1336 set_state(qhp, C4IW_QP_STATE_IDLE);
1337 qhp->attr.llp_stream_handle = NULL;
1338 c4iw_put_ep(&qhp->ep->com);
1339 qhp->ep = NULL;
1340 wake_up(&qhp->wait);
1341 break;
1342 case C4IW_QP_STATE_ERROR:
1343 goto err;
1344 default:
1345 ret = -EINVAL;
1346 goto err;
1347 }
1348 break;
1349 case C4IW_QP_STATE_ERROR:
1350 if (attrs->next_state != C4IW_QP_STATE_IDLE) {
1351 ret = -EINVAL;
1352 goto out;
1353 }
1354 if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
1355 ret = -EINVAL;
1356 goto out;
1357 }
1358 set_state(qhp, C4IW_QP_STATE_IDLE);
1359 break;
1360 case C4IW_QP_STATE_TERMINATE:
1361 if (!internal) {
1362 ret = -EINVAL;
1363 goto out;
1364 }
1365 goto err;
1366 break;
1367 default:
1368 printk(KERN_ERR "%s in a bad state %d\n",
1369 __func__, qhp->attr.state);
1370 ret = -EINVAL;
1371 goto err;
1372 break;
1373 }
1374 goto out;
1375 err:
1376 PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
1377 qhp->wq.sq.qid);
1378
1379 /* disassociate the LLP connection */
1380 qhp->attr.llp_stream_handle = NULL;
1381 if (!ep)
1382 ep = qhp->ep;
1383 qhp->ep = NULL;
1384 set_state(qhp, C4IW_QP_STATE_ERROR);
1385 free = 1;
1386 wake_up(&qhp->wait);
1387 BUG_ON(!ep);
1388 flush_qp(qhp);
1389 out:
1390 mutex_unlock(&qhp->mutex);
1391
1392 if (terminate)
1393 post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
1394
1395 /*
1396 * If disconnect is 1, then we need to initiate a disconnect
1397 * on the EP. This can be a normal close (RTS->CLOSING) or
1398 * an abnormal close (RTS/CLOSING->ERROR).
1399 */
1400 if (disconnect) {
1401 c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
1402 GFP_KERNEL);
1403 c4iw_put_ep(&ep->com);
1404 }
1405
1406 /*
1407 * If free is 1, then we've disassociated the EP from the QP
1408 * and we need to dereference the EP.
1409 */
1410 if (free)
1411 c4iw_put_ep(&ep->com);
1412 PDBG("%s exit state %d\n", __func__, qhp->attr.state);
1413 return ret;
1414 }
1415
1416 static int enable_qp_db(int id, void *p, void *data)
1417 {
1418 struct c4iw_qp *qp = p;
1419
1420 t4_enable_wq_db(&qp->wq);
1421 return 0;
1422 }
1423
1424 int c4iw_destroy_qp(struct ib_qp *ib_qp)
1425 {
1426 struct c4iw_dev *rhp;
1427 struct c4iw_qp *qhp;
1428 struct c4iw_qp_attributes attrs;
1429 struct c4iw_ucontext *ucontext;
1430
1431 qhp = to_c4iw_qp(ib_qp);
1432 rhp = qhp->rhp;
1433
1434 attrs.next_state = C4IW_QP_STATE_ERROR;
1435 if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
1436 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
1437 else
1438 c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
1439 wait_event(qhp->wait, !qhp->ep);
1440
1441 spin_lock_irq(&rhp->lock);
1442 remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1443 rhp->qpcnt--;
1444 BUG_ON(rhp->qpcnt < 0);
1445 if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
1446 rhp->rdev.stats.db_state_transitions++;
1447 rhp->db_state = NORMAL;
1448 idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
1449 }
1450 spin_unlock_irq(&rhp->lock);
1451 atomic_dec(&qhp->refcnt);
1452 wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
1453
1454 ucontext = ib_qp->uobject ?
1455 to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
1456 destroy_qp(&rhp->rdev, &qhp->wq,
1457 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1458
1459 PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
1460 kfree(qhp);
1461 return 0;
1462 }
1463
1464 static int disable_qp_db(int id, void *p, void *data)
1465 {
1466 struct c4iw_qp *qp = p;
1467
1468 t4_disable_wq_db(&qp->wq);
1469 return 0;
1470 }
1471
1472 struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
1473 struct ib_udata *udata)
1474 {
1475 struct c4iw_dev *rhp;
1476 struct c4iw_qp *qhp;
1477 struct c4iw_pd *php;
1478 struct c4iw_cq *schp;
1479 struct c4iw_cq *rchp;
1480 struct c4iw_create_qp_resp uresp;
1481 int sqsize, rqsize;
1482 struct c4iw_ucontext *ucontext;
1483 int ret;
1484 struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
1485
1486 PDBG("%s ib_pd %p\n", __func__, pd);
1487
1488 if (attrs->qp_type != IB_QPT_RC)
1489 return ERR_PTR(-EINVAL);
1490
1491 php = to_c4iw_pd(pd);
1492 rhp = php->rhp;
1493 schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
1494 rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
1495 if (!schp || !rchp)
1496 return ERR_PTR(-EINVAL);
1497
1498 if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
1499 return ERR_PTR(-EINVAL);
1500
1501 rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
1502 if (rqsize > T4_MAX_RQ_SIZE)
1503 return ERR_PTR(-E2BIG);
1504
1505 sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
1506 if (sqsize > T4_MAX_SQ_SIZE)
1507 return ERR_PTR(-E2BIG);
1508
1509 ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
1510
1511
1512 qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
1513 if (!qhp)
1514 return ERR_PTR(-ENOMEM);
1515 qhp->wq.sq.size = sqsize;
1516 qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
1517 qhp->wq.rq.size = rqsize;
1518 qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
1519
1520 if (ucontext) {
1521 qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
1522 qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
1523 }
1524
1525 PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
1526 __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
1527
1528 ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
1529 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1530 if (ret)
1531 goto err1;
1532
1533 attrs->cap.max_recv_wr = rqsize - 1;
1534 attrs->cap.max_send_wr = sqsize - 1;
1535 attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
1536
1537 qhp->rhp = rhp;
1538 qhp->attr.pd = php->pdid;
1539 qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
1540 qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
1541 qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
1542 qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
1543 qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
1544 qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
1545 qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
1546 qhp->attr.state = C4IW_QP_STATE_IDLE;
1547 qhp->attr.next_state = C4IW_QP_STATE_IDLE;
1548 qhp->attr.enable_rdma_read = 1;
1549 qhp->attr.enable_rdma_write = 1;
1550 qhp->attr.enable_bind = 1;
1551 qhp->attr.max_ord = 1;
1552 qhp->attr.max_ird = 1;
1553 spin_lock_init(&qhp->lock);
1554 mutex_init(&qhp->mutex);
1555 init_waitqueue_head(&qhp->wait);
1556 atomic_set(&qhp->refcnt, 1);
1557
1558 spin_lock_irq(&rhp->lock);
1559 if (rhp->db_state != NORMAL)
1560 t4_disable_wq_db(&qhp->wq);
1561 if (++rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
1562 rhp->rdev.stats.db_state_transitions++;
1563 rhp->db_state = FLOW_CONTROL;
1564 idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
1565 }
1566 ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
1567 spin_unlock_irq(&rhp->lock);
1568 if (ret)
1569 goto err2;
1570
1571 if (udata) {
1572 mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
1573 if (!mm1) {
1574 ret = -ENOMEM;
1575 goto err3;
1576 }
1577 mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
1578 if (!mm2) {
1579 ret = -ENOMEM;
1580 goto err4;
1581 }
1582 mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
1583 if (!mm3) {
1584 ret = -ENOMEM;
1585 goto err5;
1586 }
1587 mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
1588 if (!mm4) {
1589 ret = -ENOMEM;
1590 goto err6;
1591 }
1592 if (t4_sq_onchip(&qhp->wq.sq)) {
1593 mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
1594 if (!mm5) {
1595 ret = -ENOMEM;
1596 goto err7;
1597 }
1598 uresp.flags = C4IW_QPF_ONCHIP;
1599 } else
1600 uresp.flags = 0;
1601 uresp.qid_mask = rhp->rdev.qpmask;
1602 uresp.sqid = qhp->wq.sq.qid;
1603 uresp.sq_size = qhp->wq.sq.size;
1604 uresp.sq_memsize = qhp->wq.sq.memsize;
1605 uresp.rqid = qhp->wq.rq.qid;
1606 uresp.rq_size = qhp->wq.rq.size;
1607 uresp.rq_memsize = qhp->wq.rq.memsize;
1608 spin_lock(&ucontext->mmap_lock);
1609 if (mm5) {
1610 uresp.ma_sync_key = ucontext->key;
1611 ucontext->key += PAGE_SIZE;
1612 }
1613 uresp.sq_key = ucontext->key;
1614 ucontext->key += PAGE_SIZE;
1615 uresp.rq_key = ucontext->key;
1616 ucontext->key += PAGE_SIZE;
1617 uresp.sq_db_gts_key = ucontext->key;
1618 ucontext->key += PAGE_SIZE;
1619 uresp.rq_db_gts_key = ucontext->key;
1620 ucontext->key += PAGE_SIZE;
1621 spin_unlock(&ucontext->mmap_lock);
1622 ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
1623 if (ret)
1624 goto err8;
1625 mm1->key = uresp.sq_key;
1626 mm1->addr = qhp->wq.sq.phys_addr;
1627 mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
1628 insert_mmap(ucontext, mm1);
1629 mm2->key = uresp.rq_key;
1630 mm2->addr = virt_to_phys(qhp->wq.rq.queue);
1631 mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
1632 insert_mmap(ucontext, mm2);
1633 mm3->key = uresp.sq_db_gts_key;
1634 mm3->addr = qhp->wq.sq.udb;
1635 mm3->len = PAGE_SIZE;
1636 insert_mmap(ucontext, mm3);
1637 mm4->key = uresp.rq_db_gts_key;
1638 mm4->addr = qhp->wq.rq.udb;
1639 mm4->len = PAGE_SIZE;
1640 insert_mmap(ucontext, mm4);
1641 if (mm5) {
1642 mm5->key = uresp.ma_sync_key;
1643 mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
1644 + A_PCIE_MA_SYNC) & PAGE_MASK;
1645 mm5->len = PAGE_SIZE;
1646 insert_mmap(ucontext, mm5);
1647 }
1648 }
1649 qhp->ibqp.qp_num = qhp->wq.sq.qid;
1650 init_timer(&(qhp->timer));
1651 PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
1652 __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
1653 qhp->wq.sq.qid);
1654 return &qhp->ibqp;
1655 err8:
1656 kfree(mm5);
1657 err7:
1658 kfree(mm4);
1659 err6:
1660 kfree(mm3);
1661 err5:
1662 kfree(mm2);
1663 err4:
1664 kfree(mm1);
1665 err3:
1666 remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
1667 err2:
1668 destroy_qp(&rhp->rdev, &qhp->wq,
1669 ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
1670 err1:
1671 kfree(qhp);
1672 return ERR_PTR(ret);
1673 }
1674
1675 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1676 int attr_mask, struct ib_udata *udata)
1677 {
1678 struct c4iw_dev *rhp;
1679 struct c4iw_qp *qhp;
1680 enum c4iw_qp_attr_mask mask = 0;
1681 struct c4iw_qp_attributes attrs;
1682
1683 PDBG("%s ib_qp %p\n", __func__, ibqp);
1684
1685 /* iwarp does not support the RTR state */
1686 if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
1687 attr_mask &= ~IB_QP_STATE;
1688
1689 /* Make sure we still have something left to do */
1690 if (!attr_mask)
1691 return 0;
1692
1693 memset(&attrs, 0, sizeof attrs);
1694 qhp = to_c4iw_qp(ibqp);
1695 rhp = qhp->rhp;
1696
1697 attrs.next_state = c4iw_convert_state(attr->qp_state);
1698 attrs.enable_rdma_read = (attr->qp_access_flags &
1699 IB_ACCESS_REMOTE_READ) ? 1 : 0;
1700 attrs.enable_rdma_write = (attr->qp_access_flags &
1701 IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
1702 attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
1703
1704
1705 mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
1706 mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
1707 (C4IW_QP_ATTR_ENABLE_RDMA_READ |
1708 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
1709 C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
1710
1711 /*
1712 * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
1713 * ringing the queue db when we're in DB_FULL mode.
1714 */
1715 attrs.sq_db_inc = attr->sq_psn;
1716 attrs.rq_db_inc = attr->rq_psn;
1717 mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
1718 mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
1719
1720 return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
1721 }
1722
1723 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
1724 {
1725 PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
1726 return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
1727 }
1728
1729 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1730 int attr_mask, struct ib_qp_init_attr *init_attr)
1731 {
1732 struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
1733
1734 memset(attr, 0, sizeof *attr);
1735 memset(init_attr, 0, sizeof *init_attr);
1736 attr->qp_state = to_ib_qp_state(qhp->attr.state);
1737 return 0;
1738 }
Linux with added FPC-III support