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Merge branch 'r6040-next'
[linux/fpc-iii.git] / drivers / clk / clk-vt8500.c
blobb0f76a84f1e9fec9d3f2bcc7ec0f41eec37fbf93
1 /*
2 * Clock implementation for VIA/Wondermedia SoC's
3 * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
4 *
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 */
15
16 #include <linux/io.h>
17 #include <linux/of.h>
18 #include <linux/of_address.h>
19 #include <linux/slab.h>
20 #include <linux/bitops.h>
21 #include <linux/clkdev.h>
22 #include <linux/clk-provider.h>
23
24 #define LEGACY_PMC_BASE 0xD8130000
25
26 /* All clocks share the same lock as none can be changed concurrently */
27 static DEFINE_SPINLOCK(_lock);
28
29 struct clk_device {
30 struct clk_hw hw;
31 void __iomem *div_reg;
32 unsigned int div_mask;
33 void __iomem *en_reg;
34 int en_bit;
35 spinlock_t *lock;
36 };
37
38 /*
39 * Add new PLL_TYPE_x definitions here as required. Use the first known model
40 * to support the new type as the name.
41 * Add case statements to vtwm_pll_recalc_rate(), vtwm_pll_round_round() and
42 * vtwm_pll_set_rate() to handle the new PLL_TYPE_x
43 */
44
45 #define PLL_TYPE_VT8500 0
46 #define PLL_TYPE_WM8650 1
47 #define PLL_TYPE_WM8750 2
48 #define PLL_TYPE_WM8850 3
49
50 struct clk_pll {
51 struct clk_hw hw;
52 void __iomem *reg;
53 spinlock_t *lock;
54 int type;
55 };
56
57 static void __iomem *pmc_base;
58
59 static __init void vtwm_set_pmc_base(void)
60 {
61 struct device_node *np =
62 of_find_compatible_node(NULL, NULL, "via,vt8500-pmc");
63
64 if (np)
65 pmc_base = of_iomap(np, 0);
66 else
67 pmc_base = ioremap(LEGACY_PMC_BASE, 0x1000);
68 of_node_put(np);
69
70 if (!pmc_base)
71 pr_err("%s:of_iomap(pmc) failed\n", __func__);
72 }
73
74 #define to_clk_device(_hw) container_of(_hw, struct clk_device, hw)
75
76 #define VT8500_PMC_BUSY_MASK 0x18
77
78 static void vt8500_pmc_wait_busy(void)
79 {
80 while (readl(pmc_base) & VT8500_PMC_BUSY_MASK)
81 cpu_relax();
82 }
83
84 static int vt8500_dclk_enable(struct clk_hw *hw)
85 {
86 struct clk_device *cdev = to_clk_device(hw);
87 u32 en_val;
88 unsigned long flags = 0;
89
90 spin_lock_irqsave(cdev->lock, flags);
91
92 en_val = readl(cdev->en_reg);
93 en_val |= BIT(cdev->en_bit);
94 writel(en_val, cdev->en_reg);
95
96 spin_unlock_irqrestore(cdev->lock, flags);
97 return 0;
98 }
99
100 static void vt8500_dclk_disable(struct clk_hw *hw)
101 {
102 struct clk_device *cdev = to_clk_device(hw);
103 u32 en_val;
104 unsigned long flags = 0;
105
106 spin_lock_irqsave(cdev->lock, flags);
107
108 en_val = readl(cdev->en_reg);
109 en_val &= ~BIT(cdev->en_bit);
110 writel(en_val, cdev->en_reg);
111
112 spin_unlock_irqrestore(cdev->lock, flags);
113 }
114
115 static int vt8500_dclk_is_enabled(struct clk_hw *hw)
116 {
117 struct clk_device *cdev = to_clk_device(hw);
118 u32 en_val = (readl(cdev->en_reg) & BIT(cdev->en_bit));
119
120 return en_val ? 1 : 0;
121 }
122
123 static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
124 unsigned long parent_rate)
125 {
126 struct clk_device *cdev = to_clk_device(hw);
127 u32 div = readl(cdev->div_reg) & cdev->div_mask;
128
129 /* Special case for SDMMC devices */
130 if ((cdev->div_mask == 0x3F) && (div & BIT(5)))
131 div = 64 * (div & 0x1f);
132
133 /* div == 0 is actually the highest divisor */
134 if (div == 0)
135 div = (cdev->div_mask + 1);
136
137 return parent_rate / div;
138 }
139
140 static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
141 unsigned long *prate)
142 {
143 struct clk_device *cdev = to_clk_device(hw);
144 u32 divisor;
145
146 if (rate == 0)
147 return 0;
148
149 divisor = *prate / rate;
150
151 /* If prate / rate would be decimal, incr the divisor */
152 if (rate * divisor < *prate)
153 divisor++;
154
155 /*
156 * If this is a request for SDMMC we have to adjust the divisor
157 * when >31 to use the fixed predivisor
158 */
159 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
160 divisor = 64 * ((divisor / 64) + 1);
161 }
162
163 return *prate / divisor;
164 }
165
166 static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
167 unsigned long parent_rate)
168 {
169 struct clk_device *cdev = to_clk_device(hw);
170 u32 divisor;
171 unsigned long flags = 0;
172
173 if (rate == 0)
174 return 0;
175
176 divisor = parent_rate / rate;
177
178 if (divisor == cdev->div_mask + 1)
179 divisor = 0;
180
181 /* SDMMC mask may need to be corrected before testing if its valid */
182 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
183 /*
184 * Bit 5 is a fixed /64 predivisor. If the requested divisor
185 * is >31 then correct for the fixed divisor being required.
186 */
187 divisor = 0x20 + (divisor / 64);
188 }
189
190 if (divisor > cdev->div_mask) {
191 pr_err("%s: invalid divisor for clock\n", __func__);
192 return -EINVAL;
193 }
194
195 spin_lock_irqsave(cdev->lock, flags);
196
197 vt8500_pmc_wait_busy();
198 writel(divisor, cdev->div_reg);
199 vt8500_pmc_wait_busy();
200
201 spin_unlock_irqrestore(cdev->lock, flags);
202
203 return 0;
204 }
205
206
207 static const struct clk_ops vt8500_gated_clk_ops = {
208 .enable = vt8500_dclk_enable,
209 .disable = vt8500_dclk_disable,
210 .is_enabled = vt8500_dclk_is_enabled,
211 };
212
213 static const struct clk_ops vt8500_divisor_clk_ops = {
214 .round_rate = vt8500_dclk_round_rate,
215 .set_rate = vt8500_dclk_set_rate,
216 .recalc_rate = vt8500_dclk_recalc_rate,
217 };
218
219 static const struct clk_ops vt8500_gated_divisor_clk_ops = {
220 .enable = vt8500_dclk_enable,
221 .disable = vt8500_dclk_disable,
222 .is_enabled = vt8500_dclk_is_enabled,
223 .round_rate = vt8500_dclk_round_rate,
224 .set_rate = vt8500_dclk_set_rate,
225 .recalc_rate = vt8500_dclk_recalc_rate,
226 };
227
228 #define CLK_INIT_GATED BIT(0)
229 #define CLK_INIT_DIVISOR BIT(1)
230 #define CLK_INIT_GATED_DIVISOR (CLK_INIT_DIVISOR | CLK_INIT_GATED)
231
232 static __init void vtwm_device_clk_init(struct device_node *node)
233 {
234 u32 en_reg, div_reg;
235 struct clk *clk;
236 struct clk_device *dev_clk;
237 const char *clk_name = node->name;
238 const char *parent_name;
239 struct clk_init_data init;
240 int rc;
241 int clk_init_flags = 0;
242
243 if (!pmc_base)
244 vtwm_set_pmc_base();
245
246 dev_clk = kzalloc(sizeof(*dev_clk), GFP_KERNEL);
247 if (WARN_ON(!dev_clk))
248 return;
249
250 dev_clk->lock = &_lock;
251
252 rc = of_property_read_u32(node, "enable-reg", &en_reg);
253 if (!rc) {
254 dev_clk->en_reg = pmc_base + en_reg;
255 rc = of_property_read_u32(node, "enable-bit", &dev_clk->en_bit);
256 if (rc) {
257 pr_err("%s: enable-bit property required for gated clock\n",
258 __func__);
259 return;
260 }
261 clk_init_flags |= CLK_INIT_GATED;
262 }
263
264 rc = of_property_read_u32(node, "divisor-reg", &div_reg);
265 if (!rc) {
266 dev_clk->div_reg = pmc_base + div_reg;
267 /*
268 * use 0x1f as the default mask since it covers
269 * almost all the clocks and reduces dts properties
270 */
271 dev_clk->div_mask = 0x1f;
272
273 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask);
274 clk_init_flags |= CLK_INIT_DIVISOR;
275 }
276
277 of_property_read_string(node, "clock-output-names", &clk_name);
278
279 switch (clk_init_flags) {
280 case CLK_INIT_GATED:
281 init.ops = &vt8500_gated_clk_ops;
282 break;
283 case CLK_INIT_DIVISOR:
284 init.ops = &vt8500_divisor_clk_ops;
285 break;
286 case CLK_INIT_GATED_DIVISOR:
287 init.ops = &vt8500_gated_divisor_clk_ops;
288 break;
289 default:
290 pr_err("%s: Invalid clock description in device tree\n",
291 __func__);
292 kfree(dev_clk);
293 return;
294 }
295
296 init.name = clk_name;
297 init.flags = 0;
298 parent_name = of_clk_get_parent_name(node, 0);
299 init.parent_names = &parent_name;
300 init.num_parents = 1;
301
302 dev_clk->hw.init = &init;
303
304 clk = clk_register(NULL, &dev_clk->hw);
305 if (WARN_ON(IS_ERR(clk))) {
306 kfree(dev_clk);
307 return;
308 }
309 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
310 clk_register_clkdev(clk, clk_name, NULL);
311 }
312 CLK_OF_DECLARE(vt8500_device, "via,vt8500-device-clock", vtwm_device_clk_init);
313
314 /* PLL clock related functions */
315
316 #define to_clk_pll(_hw) container_of(_hw, struct clk_pll, hw)
317
318 /* Helper macros for PLL_VT8500 */
319 #define VT8500_PLL_MUL(x) ((x & 0x1F) << 1)
320 #define VT8500_PLL_DIV(x) ((x & 0x100) ? 1 : 2)
321
322 #define VT8500_BITS_TO_FREQ(r, m, d) \
323 ((r / d) * m)
324
325 #define VT8500_BITS_TO_VAL(m, d) \
326 ((d == 2 ? 0 : 0x100) | ((m >> 1) & 0x1F))
327
328 /* Helper macros for PLL_WM8650 */
329 #define WM8650_PLL_MUL(x) (x & 0x3FF)
330 #define WM8650_PLL_DIV(x) (((x >> 10) & 7) * (1 << ((x >> 13) & 3)))
331
332 #define WM8650_BITS_TO_FREQ(r, m, d1, d2) \
333 (r * m / (d1 * (1 << d2)))
334
335 #define WM8650_BITS_TO_VAL(m, d1, d2) \
336 ((d2 << 13) | (d1 << 10) | (m & 0x3FF))
337
338 /* Helper macros for PLL_WM8750 */
339 #define WM8750_PLL_MUL(x) (((x >> 16) & 0xFF) + 1)
340 #define WM8750_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 7)))
341
342 #define WM8750_BITS_TO_FREQ(r, m, d1, d2) \
343 (r * (m+1) / ((d1+1) * (1 << d2)))
344
345 #define WM8750_BITS_TO_VAL(f, m, d1, d2) \
346 ((f << 24) | ((m - 1) << 16) | ((d1 - 1) << 8) | d2)
347
348 /* Helper macros for PLL_WM8850 */
349 #define WM8850_PLL_MUL(x) ((((x >> 16) & 0x7F) + 1) * 2)
350 #define WM8850_PLL_DIV(x) ((((x >> 8) & 1) + 1) * (1 << (x & 3)))
351
352 #define WM8850_BITS_TO_FREQ(r, m, d1, d2) \
353 (r * ((m + 1) * 2) / ((d1+1) * (1 << d2)))
354
355 #define WM8850_BITS_TO_VAL(m, d1, d2) \
356 ((((m / 2) - 1) << 16) | ((d1 - 1) << 8) | d2)
357
358 static int vt8500_find_pll_bits(unsigned long rate, unsigned long parent_rate,
359 u32 *multiplier, u32 *prediv)
360 {
361 unsigned long tclk;
362
363 /* sanity check */
364 if ((rate < parent_rate * 4) || (rate > parent_rate * 62)) {
365 pr_err("%s: requested rate out of range\n", __func__);
366 *multiplier = 0;
367 *prediv = 1;
368 return -EINVAL;
369 }
370 if (rate <= parent_rate * 31)
371 /* use the prediv to double the resolution */
372 *prediv = 2;
373 else
374 *prediv = 1;
375
376 *multiplier = rate / (parent_rate / *prediv);
377 tclk = (parent_rate / *prediv) * *multiplier;
378
379 if (tclk != rate)
380 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__,
381 rate, tclk);
382
383 return 0;
384 }
385
386 static int wm8650_find_pll_bits(unsigned long rate, unsigned long parent_rate,
387 u32 *multiplier, u32 *divisor1, u32 *divisor2)
388 {
389 u32 mul, div1;
390 int div2;
391 u32 best_mul, best_div1, best_div2;
392 unsigned long tclk, rate_err, best_err;
393
394 best_err = (unsigned long)-1;
395
396 /* Find the closest match (lower or equal to requested) */
397 for (div1 = 5; div1 >= 3; div1--)
398 for (div2 = 3; div2 >= 0; div2--)
399 for (mul = 3; mul <= 1023; mul++) {
400 tclk = parent_rate * mul / (div1 * (1 << div2));
401 if (tclk > rate)
402 continue;
403 /* error will always be +ve */
404 rate_err = rate - tclk;
405 if (rate_err == 0) {
406 *multiplier = mul;
407 *divisor1 = div1;
408 *divisor2 = div2;
409 return 0;
410 }
411
412 if (rate_err < best_err) {
413 best_err = rate_err;
414 best_mul = mul;
415 best_div1 = div1;
416 best_div2 = div2;
417 }
418 }
419
420 if (best_err == (unsigned long)-1) {
421 pr_warn("%s: impossible rate %lu\n", __func__, rate);
422 return -EINVAL;
423 }
424
425 /* if we got here, it wasn't an exact match */
426 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
427 rate - best_err);
428 *multiplier = best_mul;
429 *divisor1 = best_div1;
430 *divisor2 = best_div2;
431
432 return 0;
433 }
434
435 static u32 wm8750_get_filter(u32 parent_rate, u32 divisor1)
436 {
437 /* calculate frequency (MHz) after pre-divisor */
438 u32 freq = (parent_rate / 1000000) / (divisor1 + 1);
439
440 if ((freq < 10) || (freq > 200))
441 pr_warn("%s: PLL recommended input frequency 10..200Mhz (requested %d Mhz)\n",
442 __func__, freq);
443
444 if (freq >= 166)
445 return 7;
446 else if (freq >= 104)
447 return 6;
448 else if (freq >= 65)
449 return 5;
450 else if (freq >= 42)
451 return 4;
452 else if (freq >= 26)
453 return 3;
454 else if (freq >= 16)
455 return 2;
456 else if (freq >= 10)
457 return 1;
458
459 return 0;
460 }
461
462 static int wm8750_find_pll_bits(unsigned long rate, unsigned long parent_rate,
463 u32 *filter, u32 *multiplier, u32 *divisor1, u32 *divisor2)
464 {
465 u32 mul;
466 int div1, div2;
467 u32 best_mul, best_div1, best_div2;
468 unsigned long tclk, rate_err, best_err;
469
470 best_err = (unsigned long)-1;
471
472 /* Find the closest match (lower or equal to requested) */
473 for (div1 = 1; div1 >= 0; div1--)
474 for (div2 = 7; div2 >= 0; div2--)
475 for (mul = 0; mul <= 255; mul++) {
476 tclk = parent_rate * (mul + 1) / ((div1 + 1) * (1 << div2));
477 if (tclk > rate)
478 continue;
479 /* error will always be +ve */
480 rate_err = rate - tclk;
481 if (rate_err == 0) {
482 *filter = wm8750_get_filter(parent_rate, div1);
483 *multiplier = mul;
484 *divisor1 = div1;
485 *divisor2 = div2;
486 return 0;
487 }
488
489 if (rate_err < best_err) {
490 best_err = rate_err;
491 best_mul = mul;
492 best_div1 = div1;
493 best_div2 = div2;
494 }
495 }
496
497 if (best_err == (unsigned long)-1) {
498 pr_warn("%s: impossible rate %lu\n", __func__, rate);
499 return -EINVAL;
500 }
501
502 /* if we got here, it wasn't an exact match */
503 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
504 rate - best_err);
505
506 *filter = wm8750_get_filter(parent_rate, best_div1);
507 *multiplier = best_mul;
508 *divisor1 = best_div1;
509 *divisor2 = best_div2;
510
511 return 0;
512 }
513
514 static int wm8850_find_pll_bits(unsigned long rate, unsigned long parent_rate,
515 u32 *multiplier, u32 *divisor1, u32 *divisor2)
516 {
517 u32 mul;
518 int div1, div2;
519 u32 best_mul, best_div1, best_div2;
520 unsigned long tclk, rate_err, best_err;
521
522 best_err = (unsigned long)-1;
523
524 /* Find the closest match (lower or equal to requested) */
525 for (div1 = 1; div1 >= 0; div1--)
526 for (div2 = 3; div2 >= 0; div2--)
527 for (mul = 0; mul <= 127; mul++) {
528 tclk = parent_rate * ((mul + 1) * 2) /
529 ((div1 + 1) * (1 << div2));
530 if (tclk > rate)
531 continue;
532 /* error will always be +ve */
533 rate_err = rate - tclk;
534 if (rate_err == 0) {
535 *multiplier = mul;
536 *divisor1 = div1;
537 *divisor2 = div2;
538 return 0;
539 }
540
541 if (rate_err < best_err) {
542 best_err = rate_err;
543 best_mul = mul;
544 best_div1 = div1;
545 best_div2 = div2;
546 }
547 }
548
549 if (best_err == (unsigned long)-1) {
550 pr_warn("%s: impossible rate %lu\n", __func__, rate);
551 return -EINVAL;
552 }
553
554 /* if we got here, it wasn't an exact match */
555 pr_warn("%s: requested rate %lu, found rate %lu\n", __func__, rate,
556 rate - best_err);
557
558 *multiplier = best_mul;
559 *divisor1 = best_div1;
560 *divisor2 = best_div2;
561
562 return 0;
563 }
564
565 static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
566 unsigned long parent_rate)
567 {
568 struct clk_pll *pll = to_clk_pll(hw);
569 u32 filter, mul, div1, div2;
570 u32 pll_val;
571 unsigned long flags = 0;
572 int ret;
573
574 /* sanity check */
575
576 switch (pll->type) {
577 case PLL_TYPE_VT8500:
578 ret = vt8500_find_pll_bits(rate, parent_rate, &mul, &div1);
579 if (!ret)
580 pll_val = VT8500_BITS_TO_VAL(mul, div1);
581 break;
582 case PLL_TYPE_WM8650:
583 ret = wm8650_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
584 if (!ret)
585 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2);
586 break;
587 case PLL_TYPE_WM8750:
588 ret = wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
589 if (!ret)
590 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
591 break;
592 case PLL_TYPE_WM8850:
593 ret = wm8850_find_pll_bits(rate, parent_rate, &mul, &div1, &div2);
594 if (!ret)
595 pll_val = WM8850_BITS_TO_VAL(mul, div1, div2);
596 break;
597 default:
598 pr_err("%s: invalid pll type\n", __func__);
599 ret = -EINVAL;
600 }
601
602 if (ret)
603 return ret;
604
605 spin_lock_irqsave(pll->lock, flags);
606
607 vt8500_pmc_wait_busy();
608 writel(pll_val, pll->reg);
609 vt8500_pmc_wait_busy();
610
611 spin_unlock_irqrestore(pll->lock, flags);
612
613 return 0;
614 }
615
616 static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
617 unsigned long *prate)
618 {
619 struct clk_pll *pll = to_clk_pll(hw);
620 u32 filter, mul, div1, div2;
621 long round_rate;
622 int ret;
623
624 switch (pll->type) {
625 case PLL_TYPE_VT8500:
626 ret = vt8500_find_pll_bits(rate, *prate, &mul, &div1);
627 if (!ret)
628 round_rate = VT8500_BITS_TO_FREQ(*prate, mul, div1);
629 break;
630 case PLL_TYPE_WM8650:
631 ret = wm8650_find_pll_bits(rate, *prate, &mul, &div1, &div2);
632 if (!ret)
633 round_rate = WM8650_BITS_TO_FREQ(*prate, mul, div1, div2);
634 break;
635 case PLL_TYPE_WM8750:
636 ret = wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
637 if (!ret)
638 round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
639 break;
640 case PLL_TYPE_WM8850:
641 ret = wm8850_find_pll_bits(rate, *prate, &mul, &div1, &div2);
642 if (!ret)
643 round_rate = WM8850_BITS_TO_FREQ(*prate, mul, div1, div2);
644 break;
645 default:
646 ret = -EINVAL;
647 }
648
649 if (ret)
650 return ret;
651
652 return round_rate;
653 }
654
655 static unsigned long vtwm_pll_recalc_rate(struct clk_hw *hw,
656 unsigned long parent_rate)
657 {
658 struct clk_pll *pll = to_clk_pll(hw);
659 u32 pll_val = readl(pll->reg);
660 unsigned long pll_freq;
661
662 switch (pll->type) {
663 case PLL_TYPE_VT8500:
664 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val);
665 pll_freq /= VT8500_PLL_DIV(pll_val);
666 break;
667 case PLL_TYPE_WM8650:
668 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val);
669 pll_freq /= WM8650_PLL_DIV(pll_val);
670 break;
671 case PLL_TYPE_WM8750:
672 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val);
673 pll_freq /= WM8750_PLL_DIV(pll_val);
674 break;
675 case PLL_TYPE_WM8850:
676 pll_freq = parent_rate * WM8850_PLL_MUL(pll_val);
677 pll_freq /= WM8850_PLL_DIV(pll_val);
678 break;
679 default:
680 pll_freq = 0;
681 }
682
683 return pll_freq;
684 }
685
686 static const struct clk_ops vtwm_pll_ops = {
687 .round_rate = vtwm_pll_round_rate,
688 .set_rate = vtwm_pll_set_rate,
689 .recalc_rate = vtwm_pll_recalc_rate,
690 };
691
692 static __init void vtwm_pll_clk_init(struct device_node *node, int pll_type)
693 {
694 u32 reg;
695 struct clk *clk;
696 struct clk_pll *pll_clk;
697 const char *clk_name = node->name;
698 const char *parent_name;
699 struct clk_init_data init;
700 int rc;
701
702 if (!pmc_base)
703 vtwm_set_pmc_base();
704
705 rc = of_property_read_u32(node, "reg", &reg);
706 if (WARN_ON(rc))
707 return;
708
709 pll_clk = kzalloc(sizeof(*pll_clk), GFP_KERNEL);
710 if (WARN_ON(!pll_clk))
711 return;
712
713 pll_clk->reg = pmc_base + reg;
714 pll_clk->lock = &_lock;
715 pll_clk->type = pll_type;
716
717 of_property_read_string(node, "clock-output-names", &clk_name);
718
719 init.name = clk_name;
720 init.ops = &vtwm_pll_ops;
721 init.flags = 0;
722 parent_name = of_clk_get_parent_name(node, 0);
723 init.parent_names = &parent_name;
724 init.num_parents = 1;
725
726 pll_clk->hw.init = &init;
727
728 clk = clk_register(NULL, &pll_clk->hw);
729 if (WARN_ON(IS_ERR(clk))) {
730 kfree(pll_clk);
731 return;
732 }
733 rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
734 clk_register_clkdev(clk, clk_name, NULL);
735 }
736
737
738 /* Wrappers for initialization functions */
739
740 static void __init vt8500_pll_init(struct device_node *node)
741 {
742 vtwm_pll_clk_init(node, PLL_TYPE_VT8500);
743 }
744 CLK_OF_DECLARE(vt8500_pll, "via,vt8500-pll-clock", vt8500_pll_init);
745
746 static void __init wm8650_pll_init(struct device_node *node)
747 {
748 vtwm_pll_clk_init(node, PLL_TYPE_WM8650);
749 }
750 CLK_OF_DECLARE(wm8650_pll, "wm,wm8650-pll-clock", wm8650_pll_init);
751
752 static void __init wm8750_pll_init(struct device_node *node)
753 {
754 vtwm_pll_clk_init(node, PLL_TYPE_WM8750);
755 }
756 CLK_OF_DECLARE(wm8750_pll, "wm,wm8750-pll-clock", wm8750_pll_init);
757
758 static void __init wm8850_pll_init(struct device_node *node)
759 {
760 vtwm_pll_clk_init(node, PLL_TYPE_WM8850);
761 }
762 CLK_OF_DECLARE(wm8850_pll, "wm,wm8850-pll-clock", wm8850_pll_init);
Linux with added FPC-III support