drivers/cpufreq/s5pv210-cpufreq.c

   1 /*
   2  * Copyright (c) 2010 Samsung Electronics Co., Ltd.
   3  *              http://www.samsung.com
   4  *
   5  * CPU frequency scaling for S5PC110/S5PV210
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10 */
  11
  12 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13
  14 #include <linux/types.h>
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/err.h>
  18 #include <linux/clk.h>
  19 #include <linux/io.h>
  20 #include <linux/cpufreq.h>
  21 #include <linux/of.h>
  22 #include <linux/of_address.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/reboot.h>
  25 #include <linux/regulator/consumer.h>
  26
  27 static void __iomem *clk_base;
  28 static void __iomem *dmc_base[2];
  29
  30 #define S5P_CLKREG(x)           (clk_base + (x))
  31
  32 #define S5P_APLL_LOCK           S5P_CLKREG(0x00)
  33 #define S5P_APLL_CON            S5P_CLKREG(0x100)
  34 #define S5P_CLK_SRC0            S5P_CLKREG(0x200)
  35 #define S5P_CLK_SRC2            S5P_CLKREG(0x208)
  36 #define S5P_CLK_DIV0            S5P_CLKREG(0x300)
  37 #define S5P_CLK_DIV2            S5P_CLKREG(0x308)
  38 #define S5P_CLK_DIV6            S5P_CLKREG(0x318)
  39 #define S5P_CLKDIV_STAT0        S5P_CLKREG(0x1000)
  40 #define S5P_CLKDIV_STAT1        S5P_CLKREG(0x1004)
  41 #define S5P_CLKMUX_STAT0        S5P_CLKREG(0x1100)
  42 #define S5P_CLKMUX_STAT1        S5P_CLKREG(0x1104)
  43
  44 #define S5P_ARM_MCS_CON         S5P_CLKREG(0x6100)
  45
  46 /* CLKSRC0 */
  47 #define S5P_CLKSRC0_MUX200_SHIFT        (16)
  48 #define S5P_CLKSRC0_MUX200_MASK         (0x1 << S5P_CLKSRC0_MUX200_SHIFT)
  49 #define S5P_CLKSRC0_MUX166_MASK         (0x1<<20)
  50 #define S5P_CLKSRC0_MUX133_MASK         (0x1<<24)
  51
  52 /* CLKSRC2 */
  53 #define S5P_CLKSRC2_G3D_SHIFT           (0)
  54 #define S5P_CLKSRC2_G3D_MASK            (0x3 << S5P_CLKSRC2_G3D_SHIFT)
  55 #define S5P_CLKSRC2_MFC_SHIFT           (4)
  56 #define S5P_CLKSRC2_MFC_MASK            (0x3 << S5P_CLKSRC2_MFC_SHIFT)
  57
  58 /* CLKDIV0 */
  59 #define S5P_CLKDIV0_APLL_SHIFT          (0)
  60 #define S5P_CLKDIV0_APLL_MASK           (0x7 << S5P_CLKDIV0_APLL_SHIFT)
  61 #define S5P_CLKDIV0_A2M_SHIFT           (4)
  62 #define S5P_CLKDIV0_A2M_MASK            (0x7 << S5P_CLKDIV0_A2M_SHIFT)
  63 #define S5P_CLKDIV0_HCLK200_SHIFT       (8)
  64 #define S5P_CLKDIV0_HCLK200_MASK        (0x7 << S5P_CLKDIV0_HCLK200_SHIFT)
  65 #define S5P_CLKDIV0_PCLK100_SHIFT       (12)
  66 #define S5P_CLKDIV0_PCLK100_MASK        (0x7 << S5P_CLKDIV0_PCLK100_SHIFT)
  67 #define S5P_CLKDIV0_HCLK166_SHIFT       (16)
  68 #define S5P_CLKDIV0_HCLK166_MASK        (0xF << S5P_CLKDIV0_HCLK166_SHIFT)
  69 #define S5P_CLKDIV0_PCLK83_SHIFT        (20)
  70 #define S5P_CLKDIV0_PCLK83_MASK         (0x7 << S5P_CLKDIV0_PCLK83_SHIFT)
  71 #define S5P_CLKDIV0_HCLK133_SHIFT       (24)
  72 #define S5P_CLKDIV0_HCLK133_MASK        (0xF << S5P_CLKDIV0_HCLK133_SHIFT)
  73 #define S5P_CLKDIV0_PCLK66_SHIFT        (28)
  74 #define S5P_CLKDIV0_PCLK66_MASK         (0x7 << S5P_CLKDIV0_PCLK66_SHIFT)
  75
  76 /* CLKDIV2 */
  77 #define S5P_CLKDIV2_G3D_SHIFT           (0)
  78 #define S5P_CLKDIV2_G3D_MASK            (0xF << S5P_CLKDIV2_G3D_SHIFT)
  79 #define S5P_CLKDIV2_MFC_SHIFT           (4)
  80 #define S5P_CLKDIV2_MFC_MASK            (0xF << S5P_CLKDIV2_MFC_SHIFT)
  81
  82 /* CLKDIV6 */
  83 #define S5P_CLKDIV6_ONEDRAM_SHIFT       (28)
  84 #define S5P_CLKDIV6_ONEDRAM_MASK        (0xF << S5P_CLKDIV6_ONEDRAM_SHIFT)
  85
  86 static struct clk *dmc0_clk;
  87 static struct clk *dmc1_clk;
  88 static DEFINE_MUTEX(set_freq_lock);
  89
  90 /* APLL M,P,S values for 1G/800Mhz */
  91 #define APLL_VAL_1000   ((1 << 31) | (125 << 16) | (3 << 8) | 1)
  92 #define APLL_VAL_800    ((1 << 31) | (100 << 16) | (3 << 8) | 1)
  93
  94 /* Use 800MHz when entering sleep mode */
  95 #define SLEEP_FREQ      (800 * 1000)
  96
  97 /* Tracks if cpu freqency can be updated anymore */
  98 static bool no_cpufreq_access;
  99
 100 /*
 101  * DRAM configurations to calculate refresh counter for changing
 102  * frequency of memory.
 103  */
 104 struct dram_conf {
 105         unsigned long freq;     /* HZ */
 106         unsigned long refresh;  /* DRAM refresh counter * 1000 */
 107 };
 108
 109 /* DRAM configuration (DMC0 and DMC1) */
 110 static struct dram_conf s5pv210_dram_conf[2];
 111
 112 enum perf_level {
 113         L0, L1, L2, L3, L4,
 114 };
 115
 116 enum s5pv210_mem_type {
 117         LPDDR   = 0x1,
 118         LPDDR2  = 0x2,
 119         DDR2    = 0x4,
 120 };
 121
 122 enum s5pv210_dmc_port {
 123         DMC0 = 0,
 124         DMC1,
 125 };
 126
 127 static struct cpufreq_frequency_table s5pv210_freq_table[] = {
 128         {0, L0, 1000*1000},
 129         {0, L1, 800*1000},
 130         {0, L2, 400*1000},
 131         {0, L3, 200*1000},
 132         {0, L4, 100*1000},
 133         {0, 0, CPUFREQ_TABLE_END},
 134 };
 135
 136 static struct regulator *arm_regulator;
 137 static struct regulator *int_regulator;
 138
 139 struct s5pv210_dvs_conf {
 140         int arm_volt;   /* uV */
 141         int int_volt;   /* uV */
 142 };
 143
 144 static const int arm_volt_max = 1350000;
 145 static const int int_volt_max = 1250000;
 146
 147 static struct s5pv210_dvs_conf dvs_conf[] = {
 148         [L0] = {
 149                 .arm_volt       = 1250000,
 150                 .int_volt       = 1100000,
 151         },
 152         [L1] = {
 153                 .arm_volt       = 1200000,
 154                 .int_volt       = 1100000,
 155         },
 156         [L2] = {
 157                 .arm_volt       = 1050000,
 158                 .int_volt       = 1100000,
 159         },
 160         [L3] = {
 161                 .arm_volt       = 950000,
 162                 .int_volt       = 1100000,
 163         },
 164         [L4] = {
 165                 .arm_volt       = 950000,
 166                 .int_volt       = 1000000,
 167         },
 168 };
 169
 170 static u32 clkdiv_val[5][11] = {
 171         /*
 172          * Clock divider value for following
 173          * { APLL, A2M, HCLK_MSYS, PCLK_MSYS,
 174          *   HCLK_DSYS, PCLK_DSYS, HCLK_PSYS, PCLK_PSYS,
 175          *   ONEDRAM, MFC, G3D }
 176          */
 177
 178         /* L0 : [1000/200/100][166/83][133/66][200/200] */
 179         {0, 4, 4, 1, 3, 1, 4, 1, 3, 0, 0},
 180
 181         /* L1 : [800/200/100][166/83][133/66][200/200] */
 182         {0, 3, 3, 1, 3, 1, 4, 1, 3, 0, 0},
 183
 184         /* L2 : [400/200/100][166/83][133/66][200/200] */
 185         {1, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
 186
 187         /* L3 : [200/200/100][166/83][133/66][200/200] */
 188         {3, 3, 1, 1, 3, 1, 4, 1, 3, 0, 0},
 189
 190         /* L4 : [100/100/100][83/83][66/66][100/100] */
 191         {7, 7, 0, 0, 7, 0, 9, 0, 7, 0, 0},
 192 };
 193
 194 /*
 195  * This function set DRAM refresh counter
 196  * accoriding to operating frequency of DRAM
 197  * ch: DMC port number 0 or 1
 198  * freq: Operating frequency of DRAM(KHz)
 199  */
 200 static void s5pv210_set_refresh(enum s5pv210_dmc_port ch, unsigned long freq)
 201 {
 202         unsigned long tmp, tmp1;
 203         void __iomem *reg = NULL;
 204
 205         if (ch == DMC0) {
 206                 reg = (dmc_base[0] + 0x30);
 207         } else if (ch == DMC1) {
 208                 reg = (dmc_base[1] + 0x30);
 209         } else {
 210                 pr_err("Cannot find DMC port\n");
 211                 return;
 212         }
 213
 214         /* Find current DRAM frequency */
 215         tmp = s5pv210_dram_conf[ch].freq;
 216
 217         tmp /= freq;
 218
 219         tmp1 = s5pv210_dram_conf[ch].refresh;
 220
 221         tmp1 /= tmp;
 222
 223         __raw_writel(tmp1, reg);
 224 }
 225
 226 static int s5pv210_target(struct cpufreq_policy *policy, unsigned int index)
 227 {
 228         unsigned long reg;
 229         unsigned int priv_index;
 230         unsigned int pll_changing = 0;
 231         unsigned int bus_speed_changing = 0;
 232         unsigned int old_freq, new_freq;
 233         int arm_volt, int_volt;
 234         int ret = 0;
 235
 236         mutex_lock(&set_freq_lock);
 237
 238         if (no_cpufreq_access) {
 239                 pr_err("Denied access to %s as it is disabled temporarily\n",
 240                        __func__);
 241                 ret = -EINVAL;
 242                 goto exit;
 243         }
 244
 245         old_freq = policy->cur;
 246         new_freq = s5pv210_freq_table[index].frequency;
 247
 248         /* Finding current running level index */
 249         if (cpufreq_frequency_table_target(policy, s5pv210_freq_table,
 250                                            old_freq, CPUFREQ_RELATION_H,
 251                                            &priv_index)) {
 252                 ret = -EINVAL;
 253                 goto exit;
 254         }
 255
 256         arm_volt = dvs_conf[index].arm_volt;
 257         int_volt = dvs_conf[index].int_volt;
 258
 259         if (new_freq > old_freq) {
 260                 ret = regulator_set_voltage(arm_regulator,
 261                                 arm_volt, arm_volt_max);
 262                 if (ret)
 263                         goto exit;
 264
 265                 ret = regulator_set_voltage(int_regulator,
 266                                 int_volt, int_volt_max);
 267                 if (ret)
 268                         goto exit;
 269         }
 270
 271         /* Check if there need to change PLL */
 272         if ((index == L0) || (priv_index == L0))
 273                 pll_changing = 1;
 274
 275         /* Check if there need to change System bus clock */
 276         if ((index == L4) || (priv_index == L4))
 277                 bus_speed_changing = 1;
 278
 279         if (bus_speed_changing) {
 280                 /*
 281                  * Reconfigure DRAM refresh counter value for minimum
 282                  * temporary clock while changing divider.
 283                  * expected clock is 83Mhz : 7.8usec/(1/83Mhz) = 0x287
 284                  */
 285                 if (pll_changing)
 286                         s5pv210_set_refresh(DMC1, 83000);
 287                 else
 288                         s5pv210_set_refresh(DMC1, 100000);
 289
 290                 s5pv210_set_refresh(DMC0, 83000);
 291         }
 292
 293         /*
 294          * APLL should be changed in this level
 295          * APLL -> MPLL(for stable transition) -> APLL
 296          * Some clock source's clock API are not prepared.
 297          * Do not use clock API in below code.
 298          */
 299         if (pll_changing) {
 300                 /*
 301                  * 1. Temporary Change divider for MFC and G3D
 302                  * SCLKA2M(200/1=200)->(200/4=50)Mhz
 303                  */
 304                 reg = __raw_readl(S5P_CLK_DIV2);
 305                 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 306                 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
 307                         (3 << S5P_CLKDIV2_MFC_SHIFT);
 308                 __raw_writel(reg, S5P_CLK_DIV2);
 309
 310                 /* For MFC, G3D dividing */
 311                 do {
 312                         reg = __raw_readl(S5P_CLKDIV_STAT0);
 313                 } while (reg & ((1 << 16) | (1 << 17)));
 314
 315                 /*
 316                  * 2. Change SCLKA2M(200Mhz)to SCLKMPLL in MFC_MUX, G3D MUX
 317                  * (200/4=50)->(667/4=166)Mhz
 318                  */
 319                 reg = __raw_readl(S5P_CLK_SRC2);
 320                 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 321                 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
 322                         (1 << S5P_CLKSRC2_MFC_SHIFT);
 323                 __raw_writel(reg, S5P_CLK_SRC2);
 324
 325                 do {
 326                         reg = __raw_readl(S5P_CLKMUX_STAT1);
 327                 } while (reg & ((1 << 7) | (1 << 3)));
 328
 329                 /*
 330                  * 3. DMC1 refresh count for 133Mhz if (index == L4) is
 331                  * true refresh counter is already programed in upper
 332                  * code. 0x287@83Mhz
 333                  */
 334                 if (!bus_speed_changing)
 335                         s5pv210_set_refresh(DMC1, 133000);
 336
 337                 /* 4. SCLKAPLL -> SCLKMPLL */
 338                 reg = __raw_readl(S5P_CLK_SRC0);
 339                 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 340                 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
 341                 __raw_writel(reg, S5P_CLK_SRC0);
 342
 343                 do {
 344                         reg = __raw_readl(S5P_CLKMUX_STAT0);
 345                 } while (reg & (0x1 << 18));
 346
 347         }
 348
 349         /* Change divider */
 350         reg = __raw_readl(S5P_CLK_DIV0);
 351
 352         reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
 353                 S5P_CLKDIV0_HCLK200_MASK | S5P_CLKDIV0_PCLK100_MASK |
 354                 S5P_CLKDIV0_HCLK166_MASK | S5P_CLKDIV0_PCLK83_MASK |
 355                 S5P_CLKDIV0_HCLK133_MASK | S5P_CLKDIV0_PCLK66_MASK);
 356
 357         reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
 358                 (clkdiv_val[index][1] << S5P_CLKDIV0_A2M_SHIFT) |
 359                 (clkdiv_val[index][2] << S5P_CLKDIV0_HCLK200_SHIFT) |
 360                 (clkdiv_val[index][3] << S5P_CLKDIV0_PCLK100_SHIFT) |
 361                 (clkdiv_val[index][4] << S5P_CLKDIV0_HCLK166_SHIFT) |
 362                 (clkdiv_val[index][5] << S5P_CLKDIV0_PCLK83_SHIFT) |
 363                 (clkdiv_val[index][6] << S5P_CLKDIV0_HCLK133_SHIFT) |
 364                 (clkdiv_val[index][7] << S5P_CLKDIV0_PCLK66_SHIFT));
 365
 366         __raw_writel(reg, S5P_CLK_DIV0);
 367
 368         do {
 369                 reg = __raw_readl(S5P_CLKDIV_STAT0);
 370         } while (reg & 0xff);
 371
 372         /* ARM MCS value changed */
 373         reg = __raw_readl(S5P_ARM_MCS_CON);
 374         reg &= ~0x3;
 375         if (index >= L3)
 376                 reg |= 0x3;
 377         else
 378                 reg |= 0x1;
 379
 380         __raw_writel(reg, S5P_ARM_MCS_CON);
 381
 382         if (pll_changing) {
 383                 /* 5. Set Lock time = 30us*24Mhz = 0x2cf */
 384                 __raw_writel(0x2cf, S5P_APLL_LOCK);
 385
 386                 /*
 387                  * 6. Turn on APLL
 388                  * 6-1. Set PMS values
 389                  * 6-2. Wait untile the PLL is locked
 390                  */
 391                 if (index == L0)
 392                         __raw_writel(APLL_VAL_1000, S5P_APLL_CON);
 393                 else
 394                         __raw_writel(APLL_VAL_800, S5P_APLL_CON);
 395
 396                 do {
 397                         reg = __raw_readl(S5P_APLL_CON);
 398                 } while (!(reg & (0x1 << 29)));
 399
 400                 /*
 401                  * 7. Change souce clock from SCLKMPLL(667Mhz)
 402                  * to SCLKA2M(200Mhz) in MFC_MUX and G3D MUX
 403                  * (667/4=166)->(200/4=50)Mhz
 404                  */
 405                 reg = __raw_readl(S5P_CLK_SRC2);
 406                 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
 407                 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
 408                         (0 << S5P_CLKSRC2_MFC_SHIFT);
 409                 __raw_writel(reg, S5P_CLK_SRC2);
 410
 411                 do {
 412                         reg = __raw_readl(S5P_CLKMUX_STAT1);
 413                 } while (reg & ((1 << 7) | (1 << 3)));
 414
 415                 /*
 416                  * 8. Change divider for MFC and G3D
 417                  * (200/4=50)->(200/1=200)Mhz
 418                  */
 419                 reg = __raw_readl(S5P_CLK_DIV2);
 420                 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
 421                 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
 422                         (clkdiv_val[index][9] << S5P_CLKDIV2_MFC_SHIFT);
 423                 __raw_writel(reg, S5P_CLK_DIV2);
 424
 425                 /* For MFC, G3D dividing */
 426                 do {
 427                         reg = __raw_readl(S5P_CLKDIV_STAT0);
 428                 } while (reg & ((1 << 16) | (1 << 17)));
 429
 430                 /* 9. Change MPLL to APLL in MSYS_MUX */
 431                 reg = __raw_readl(S5P_CLK_SRC0);
 432                 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
 433                 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
 434                 __raw_writel(reg, S5P_CLK_SRC0);
 435
 436                 do {
 437                         reg = __raw_readl(S5P_CLKMUX_STAT0);
 438                 } while (reg & (0x1 << 18));
 439
 440                 /*
 441                  * 10. DMC1 refresh counter
 442                  * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
 443                  * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
 444                  */
 445                 if (!bus_speed_changing)
 446                         s5pv210_set_refresh(DMC1, 200000);
 447         }
 448
 449         /*
 450          * L4 level need to change memory bus speed, hence onedram clock divier
 451          * and memory refresh parameter should be changed
 452          */
 453         if (bus_speed_changing) {
 454                 reg = __raw_readl(S5P_CLK_DIV6);
 455                 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
 456                 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
 457                 __raw_writel(reg, S5P_CLK_DIV6);
 458
 459                 do {
 460                         reg = __raw_readl(S5P_CLKDIV_STAT1);
 461                 } while (reg & (1 << 15));
 462
 463                 /* Reconfigure DRAM refresh counter value */
 464                 if (index != L4) {
 465                         /*
 466                          * DMC0 : 166Mhz
 467                          * DMC1 : 200Mhz
 468                          */
 469                         s5pv210_set_refresh(DMC0, 166000);
 470                         s5pv210_set_refresh(DMC1, 200000);
 471                 } else {
 472                         /*
 473                          * DMC0 : 83Mhz
 474                          * DMC1 : 100Mhz
 475                          */
 476                         s5pv210_set_refresh(DMC0, 83000);
 477                         s5pv210_set_refresh(DMC1, 100000);
 478                 }
 479         }
 480
 481         if (new_freq < old_freq) {
 482                 regulator_set_voltage(int_regulator,
 483                                 int_volt, int_volt_max);
 484
 485                 regulator_set_voltage(arm_regulator,
 486                                 arm_volt, arm_volt_max);
 487         }
 488
 489         printk(KERN_DEBUG "Perf changed[L%d]\n", index);
 490
 491 exit:
 492         mutex_unlock(&set_freq_lock);
 493         return ret;
 494 }
 495
 496 static int check_mem_type(void __iomem *dmc_reg)
 497 {
 498         unsigned long val;
 499
 500         val = __raw_readl(dmc_reg + 0x4);
 501         val = (val & (0xf << 8));
 502
 503         return val >> 8;
 504 }
 505
 506 static int s5pv210_cpu_init(struct cpufreq_policy *policy)
 507 {
 508         unsigned long mem_type;
 509         int ret;
 510
 511         policy->clk = clk_get(NULL, "armclk");
 512         if (IS_ERR(policy->clk))
 513                 return PTR_ERR(policy->clk);
 514
 515         dmc0_clk = clk_get(NULL, "sclk_dmc0");
 516         if (IS_ERR(dmc0_clk)) {
 517                 ret = PTR_ERR(dmc0_clk);
 518                 goto out_dmc0;
 519         }
 520
 521         dmc1_clk = clk_get(NULL, "hclk_msys");
 522         if (IS_ERR(dmc1_clk)) {
 523                 ret = PTR_ERR(dmc1_clk);
 524                 goto out_dmc1;
 525         }
 526
 527         if (policy->cpu != 0) {
 528                 ret = -EINVAL;
 529                 goto out_dmc1;
 530         }
 531
 532         /*
 533          * check_mem_type : This driver only support LPDDR & LPDDR2.
 534          * other memory type is not supported.
 535          */
 536         mem_type = check_mem_type(dmc_base[0]);
 537
 538         if ((mem_type != LPDDR) && (mem_type != LPDDR2)) {
 539                 pr_err("CPUFreq doesn't support this memory type\n");
 540                 ret = -EINVAL;
 541                 goto out_dmc1;
 542         }
 543
 544         /* Find current refresh counter and frequency each DMC */
 545         s5pv210_dram_conf[0].refresh = (__raw_readl(dmc_base[0] + 0x30) * 1000);
 546         s5pv210_dram_conf[0].freq = clk_get_rate(dmc0_clk);
 547
 548         s5pv210_dram_conf[1].refresh = (__raw_readl(dmc_base[1] + 0x30) * 1000);
 549         s5pv210_dram_conf[1].freq = clk_get_rate(dmc1_clk);
 550
 551         policy->suspend_freq = SLEEP_FREQ;
 552         return cpufreq_generic_init(policy, s5pv210_freq_table, 40000);
 553
 554 out_dmc1:
 555         clk_put(dmc0_clk);
 556 out_dmc0:
 557         clk_put(policy->clk);
 558         return ret;
 559 }
 560
 561 static int s5pv210_cpufreq_reboot_notifier_event(struct notifier_block *this,
 562                                                  unsigned long event, void *ptr)
 563 {
 564         int ret;
 565
 566         ret = cpufreq_driver_target(cpufreq_cpu_get(0), SLEEP_FREQ, 0);
 567         if (ret < 0)
 568                 return NOTIFY_BAD;
 569
 570         no_cpufreq_access = true;
 571         return NOTIFY_DONE;
 572 }
 573
 574 static struct cpufreq_driver s5pv210_driver = {
 575         .flags          = CPUFREQ_STICKY | CPUFREQ_NEED_INITIAL_FREQ_CHECK,
 576         .verify         = cpufreq_generic_frequency_table_verify,
 577         .target_index   = s5pv210_target,
 578         .get            = cpufreq_generic_get,
 579         .init           = s5pv210_cpu_init,
 580         .name           = "s5pv210",
 581         .suspend        = cpufreq_generic_suspend,
 582         .resume         = cpufreq_generic_suspend, /* We need to set SLEEP FREQ again */
 583 };
 584
 585 static struct notifier_block s5pv210_cpufreq_reboot_notifier = {
 586         .notifier_call = s5pv210_cpufreq_reboot_notifier_event,
 587 };
 588
 589 static int s5pv210_cpufreq_probe(struct platform_device *pdev)
 590 {
 591         struct device_node *np;
 592         int id;
 593
 594         /*
 595          * HACK: This is a temporary workaround to get access to clock
 596          * and DMC controller registers directly and remove static mappings
 597          * and dependencies on platform headers. It is necessary to enable
 598          * S5PV210 multi-platform support and will be removed together with
 599          * this whole driver as soon as S5PV210 gets migrated to use
 600          * cpufreq-dt driver.
 601          */
 602         np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
 603         if (!np) {
 604                 pr_err("%s: failed to find clock controller DT node\n",
 605                         __func__);
 606                 return -ENODEV;
 607         }
 608
 609         clk_base = of_iomap(np, 0);
 610         if (!clk_base) {
 611                 pr_err("%s: failed to map clock registers\n", __func__);
 612                 return -EFAULT;
 613         }
 614
 615         for_each_compatible_node(np, NULL, "samsung,s5pv210-dmc") {
 616                 id = of_alias_get_id(np, "dmc");
 617                 if (id < 0 || id >= ARRAY_SIZE(dmc_base)) {
 618                         pr_err("%s: failed to get alias of dmc node '%s'\n",
 619                                 __func__, np->name);
 620                         return id;
 621                 }
 622
 623                 dmc_base[id] = of_iomap(np, 0);
 624                 if (!dmc_base[id]) {
 625                         pr_err("%s: failed to map dmc%d registers\n",
 626                                 __func__, id);
 627                         return -EFAULT;
 628                 }
 629         }
 630
 631         for (id = 0; id < ARRAY_SIZE(dmc_base); ++id) {
 632                 if (!dmc_base[id]) {
 633                         pr_err("%s: failed to find dmc%d node\n", __func__, id);
 634                         return -ENODEV;
 635                 }
 636         }
 637
 638         arm_regulator = regulator_get(NULL, "vddarm");
 639         if (IS_ERR(arm_regulator)) {
 640                 pr_err("failed to get regulator vddarm\n");
 641                 return PTR_ERR(arm_regulator);
 642         }
 643
 644         int_regulator = regulator_get(NULL, "vddint");
 645         if (IS_ERR(int_regulator)) {
 646                 pr_err("failed to get regulator vddint\n");
 647                 regulator_put(arm_regulator);
 648                 return PTR_ERR(int_regulator);
 649         }
 650
 651         register_reboot_notifier(&s5pv210_cpufreq_reboot_notifier);
 652
 653         return cpufreq_register_driver(&s5pv210_driver);
 654 }
 655
 656 static struct platform_driver s5pv210_cpufreq_platdrv = {
 657         .driver = {
 658                 .name   = "s5pv210-cpufreq",
 659         },
 660         .probe = s5pv210_cpufreq_probe,
 661 };
 662 builtin_platform_driver(s5pv210_cpufreq_platdrv);