drivers/gpio/gpio-mxc.c

   1 /*
   2  * MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
   3  * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
   4  *
   5  * Based on code from Freescale,
   6  * Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License
  10  * as published by the Free Software Foundation; either version 2
  11  * of the License, or (at your option) any later version.
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
  20  */
  21
  22 #include <linux/err.h>
  23 #include <linux/init.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/irqchip/chained_irq.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/slab.h>
  31 #include <linux/gpio/driver.h>
  32 /* FIXME: for gpio_get_value() replace this with direct register read */
  33 #include <linux/gpio.h>
  34 #include <linux/of.h>
  35 #include <linux/of_device.h>
  36 #include <linux/module.h>
  37 #include <linux/bug.h>
  38
  39 enum mxc_gpio_hwtype {
  40         IMX1_GPIO,      /* runs on i.mx1 */
  41         IMX21_GPIO,     /* runs on i.mx21 and i.mx27 */
  42         IMX31_GPIO,     /* runs on i.mx31 */
  43         IMX35_GPIO,     /* runs on all other i.mx */
  44 };
  45
  46 /* device type dependent stuff */
  47 struct mxc_gpio_hwdata {
  48         unsigned dr_reg;
  49         unsigned gdir_reg;
  50         unsigned psr_reg;
  51         unsigned icr1_reg;
  52         unsigned icr2_reg;
  53         unsigned imr_reg;
  54         unsigned isr_reg;
  55         int edge_sel_reg;
  56         unsigned low_level;
  57         unsigned high_level;
  58         unsigned rise_edge;
  59         unsigned fall_edge;
  60 };
  61
  62 struct mxc_gpio_port {
  63         struct list_head node;
  64         void __iomem *base;
  65         int irq;
  66         int irq_high;
  67         struct irq_domain *domain;
  68         struct gpio_chip gc;
  69         u32 both_edges;
  70 };
  71
  72 static struct mxc_gpio_hwdata imx1_imx21_gpio_hwdata = {
  73         .dr_reg         = 0x1c,
  74         .gdir_reg       = 0x00,
  75         .psr_reg        = 0x24,
  76         .icr1_reg       = 0x28,
  77         .icr2_reg       = 0x2c,
  78         .imr_reg        = 0x30,
  79         .isr_reg        = 0x34,
  80         .edge_sel_reg   = -EINVAL,
  81         .low_level      = 0x03,
  82         .high_level     = 0x02,
  83         .rise_edge      = 0x00,
  84         .fall_edge      = 0x01,
  85 };
  86
  87 static struct mxc_gpio_hwdata imx31_gpio_hwdata = {
  88         .dr_reg         = 0x00,
  89         .gdir_reg       = 0x04,
  90         .psr_reg        = 0x08,
  91         .icr1_reg       = 0x0c,
  92         .icr2_reg       = 0x10,
  93         .imr_reg        = 0x14,
  94         .isr_reg        = 0x18,
  95         .edge_sel_reg   = -EINVAL,
  96         .low_level      = 0x00,
  97         .high_level     = 0x01,
  98         .rise_edge      = 0x02,
  99         .fall_edge      = 0x03,
 100 };
 101
 102 static struct mxc_gpio_hwdata imx35_gpio_hwdata = {
 103         .dr_reg         = 0x00,
 104         .gdir_reg       = 0x04,
 105         .psr_reg        = 0x08,
 106         .icr1_reg       = 0x0c,
 107         .icr2_reg       = 0x10,
 108         .imr_reg        = 0x14,
 109         .isr_reg        = 0x18,
 110         .edge_sel_reg   = 0x1c,
 111         .low_level      = 0x00,
 112         .high_level     = 0x01,
 113         .rise_edge      = 0x02,
 114         .fall_edge      = 0x03,
 115 };
 116
 117 static enum mxc_gpio_hwtype mxc_gpio_hwtype;
 118 static struct mxc_gpio_hwdata *mxc_gpio_hwdata;
 119
 120 #define GPIO_DR                 (mxc_gpio_hwdata->dr_reg)
 121 #define GPIO_GDIR               (mxc_gpio_hwdata->gdir_reg)
 122 #define GPIO_PSR                (mxc_gpio_hwdata->psr_reg)
 123 #define GPIO_ICR1               (mxc_gpio_hwdata->icr1_reg)
 124 #define GPIO_ICR2               (mxc_gpio_hwdata->icr2_reg)
 125 #define GPIO_IMR                (mxc_gpio_hwdata->imr_reg)
 126 #define GPIO_ISR                (mxc_gpio_hwdata->isr_reg)
 127 #define GPIO_EDGE_SEL           (mxc_gpio_hwdata->edge_sel_reg)
 128
 129 #define GPIO_INT_LOW_LEV        (mxc_gpio_hwdata->low_level)
 130 #define GPIO_INT_HIGH_LEV       (mxc_gpio_hwdata->high_level)
 131 #define GPIO_INT_RISE_EDGE      (mxc_gpio_hwdata->rise_edge)
 132 #define GPIO_INT_FALL_EDGE      (mxc_gpio_hwdata->fall_edge)
 133 #define GPIO_INT_BOTH_EDGES     0x4
 134
 135 static const struct platform_device_id mxc_gpio_devtype[] = {
 136         {
 137                 .name = "imx1-gpio",
 138                 .driver_data = IMX1_GPIO,
 139         }, {
 140                 .name = "imx21-gpio",
 141                 .driver_data = IMX21_GPIO,
 142         }, {
 143                 .name = "imx31-gpio",
 144                 .driver_data = IMX31_GPIO,
 145         }, {
 146                 .name = "imx35-gpio",
 147                 .driver_data = IMX35_GPIO,
 148         }, {
 149                 /* sentinel */
 150         }
 151 };
 152
 153 static const struct of_device_id mxc_gpio_dt_ids[] = {
 154         { .compatible = "fsl,imx1-gpio", .data = &mxc_gpio_devtype[IMX1_GPIO], },
 155         { .compatible = "fsl,imx21-gpio", .data = &mxc_gpio_devtype[IMX21_GPIO], },
 156         { .compatible = "fsl,imx31-gpio", .data = &mxc_gpio_devtype[IMX31_GPIO], },
 157         { .compatible = "fsl,imx35-gpio", .data = &mxc_gpio_devtype[IMX35_GPIO], },
 158         { /* sentinel */ }
 159 };
 160
 161 /*
 162  * MX2 has one interrupt *for all* gpio ports. The list is used
 163  * to save the references to all ports, so that mx2_gpio_irq_handler
 164  * can walk through all interrupt status registers.
 165  */
 166 static LIST_HEAD(mxc_gpio_ports);
 167
 168 /* Note: This driver assumes 32 GPIOs are handled in one register */
 169
 170 static int gpio_set_irq_type(struct irq_data *d, u32 type)
 171 {
 172         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 173         struct mxc_gpio_port *port = gc->private;
 174         u32 bit, val;
 175         u32 gpio_idx = d->hwirq;
 176         u32 gpio = port->gc.base + gpio_idx;
 177         int edge;
 178         void __iomem *reg = port->base;
 179
 180         port->both_edges &= ~(1 << gpio_idx);
 181         switch (type) {
 182         case IRQ_TYPE_EDGE_RISING:
 183                 edge = GPIO_INT_RISE_EDGE;
 184                 break;
 185         case IRQ_TYPE_EDGE_FALLING:
 186                 edge = GPIO_INT_FALL_EDGE;
 187                 break;
 188         case IRQ_TYPE_EDGE_BOTH:
 189                 if (GPIO_EDGE_SEL >= 0) {
 190                         edge = GPIO_INT_BOTH_EDGES;
 191                 } else {
 192                         val = gpio_get_value(gpio);
 193                         if (val) {
 194                                 edge = GPIO_INT_LOW_LEV;
 195                                 pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
 196                         } else {
 197                                 edge = GPIO_INT_HIGH_LEV;
 198                                 pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
 199                         }
 200                         port->both_edges |= 1 << gpio_idx;
 201                 }
 202                 break;
 203         case IRQ_TYPE_LEVEL_LOW:
 204                 edge = GPIO_INT_LOW_LEV;
 205                 break;
 206         case IRQ_TYPE_LEVEL_HIGH:
 207                 edge = GPIO_INT_HIGH_LEV;
 208                 break;
 209         default:
 210                 return -EINVAL;
 211         }
 212
 213         if (GPIO_EDGE_SEL >= 0) {
 214                 val = readl(port->base + GPIO_EDGE_SEL);
 215                 if (edge == GPIO_INT_BOTH_EDGES)
 216                         writel(val | (1 << gpio_idx),
 217                                 port->base + GPIO_EDGE_SEL);
 218                 else
 219                         writel(val & ~(1 << gpio_idx),
 220                                 port->base + GPIO_EDGE_SEL);
 221         }
 222
 223         if (edge != GPIO_INT_BOTH_EDGES) {
 224                 reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */
 225                 bit = gpio_idx & 0xf;
 226                 val = readl(reg) & ~(0x3 << (bit << 1));
 227                 writel(val | (edge << (bit << 1)), reg);
 228         }
 229
 230         writel(1 << gpio_idx, port->base + GPIO_ISR);
 231
 232         return 0;
 233 }
 234
 235 static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
 236 {
 237         void __iomem *reg = port->base;
 238         u32 bit, val;
 239         int edge;
 240
 241         reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
 242         bit = gpio & 0xf;
 243         val = readl(reg);
 244         edge = (val >> (bit << 1)) & 3;
 245         val &= ~(0x3 << (bit << 1));
 246         if (edge == GPIO_INT_HIGH_LEV) {
 247                 edge = GPIO_INT_LOW_LEV;
 248                 pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
 249         } else if (edge == GPIO_INT_LOW_LEV) {
 250                 edge = GPIO_INT_HIGH_LEV;
 251                 pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
 252         } else {
 253                 pr_err("mxc: invalid configuration for GPIO %d: %x\n",
 254                        gpio, edge);
 255                 return;
 256         }
 257         writel(val | (edge << (bit << 1)), reg);
 258 }
 259
 260 /* handle 32 interrupts in one status register */
 261 static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
 262 {
 263         while (irq_stat != 0) {
 264                 int irqoffset = fls(irq_stat) - 1;
 265
 266                 if (port->both_edges & (1 << irqoffset))
 267                         mxc_flip_edge(port, irqoffset);
 268
 269                 generic_handle_irq(irq_find_mapping(port->domain, irqoffset));
 270
 271                 irq_stat &= ~(1 << irqoffset);
 272         }
 273 }
 274
 275 /* MX1 and MX3 has one interrupt *per* gpio port */
 276 static void mx3_gpio_irq_handler(struct irq_desc *desc)
 277 {
 278         u32 irq_stat;
 279         struct mxc_gpio_port *port = irq_desc_get_handler_data(desc);
 280         struct irq_chip *chip = irq_desc_get_chip(desc);
 281
 282         chained_irq_enter(chip, desc);
 283
 284         irq_stat = readl(port->base + GPIO_ISR) & readl(port->base + GPIO_IMR);
 285
 286         mxc_gpio_irq_handler(port, irq_stat);
 287
 288         chained_irq_exit(chip, desc);
 289 }
 290
 291 /* MX2 has one interrupt *for all* gpio ports */
 292 static void mx2_gpio_irq_handler(struct irq_desc *desc)
 293 {
 294         u32 irq_msk, irq_stat;
 295         struct mxc_gpio_port *port;
 296         struct irq_chip *chip = irq_desc_get_chip(desc);
 297
 298         chained_irq_enter(chip, desc);
 299
 300         /* walk through all interrupt status registers */
 301         list_for_each_entry(port, &mxc_gpio_ports, node) {
 302                 irq_msk = readl(port->base + GPIO_IMR);
 303                 if (!irq_msk)
 304                         continue;
 305
 306                 irq_stat = readl(port->base + GPIO_ISR) & irq_msk;
 307                 if (irq_stat)
 308                         mxc_gpio_irq_handler(port, irq_stat);
 309         }
 310         chained_irq_exit(chip, desc);
 311 }
 312
 313 /*
 314  * Set interrupt number "irq" in the GPIO as a wake-up source.
 315  * While system is running, all registered GPIO interrupts need to have
 316  * wake-up enabled. When system is suspended, only selected GPIO interrupts
 317  * need to have wake-up enabled.
 318  * @param  irq          interrupt source number
 319  * @param  enable       enable as wake-up if equal to non-zero
 320  * @return       This function returns 0 on success.
 321  */
 322 static int gpio_set_wake_irq(struct irq_data *d, u32 enable)
 323 {
 324         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
 325         struct mxc_gpio_port *port = gc->private;
 326         u32 gpio_idx = d->hwirq;
 327
 328         if (enable) {
 329                 if (port->irq_high && (gpio_idx >= 16))
 330                         enable_irq_wake(port->irq_high);
 331                 else
 332                         enable_irq_wake(port->irq);
 333         } else {
 334                 if (port->irq_high && (gpio_idx >= 16))
 335                         disable_irq_wake(port->irq_high);
 336                 else
 337                         disable_irq_wake(port->irq);
 338         }
 339
 340         return 0;
 341 }
 342
 343 static int mxc_gpio_init_gc(struct mxc_gpio_port *port, int irq_base)
 344 {
 345         struct irq_chip_generic *gc;
 346         struct irq_chip_type *ct;
 347
 348         gc = irq_alloc_generic_chip("gpio-mxc", 1, irq_base,
 349                                     port->base, handle_level_irq);
 350         if (!gc)
 351                 return -ENOMEM;
 352         gc->private = port;
 353
 354         ct = gc->chip_types;
 355         ct->chip.irq_ack = irq_gc_ack_set_bit;
 356         ct->chip.irq_mask = irq_gc_mask_clr_bit;
 357         ct->chip.irq_unmask = irq_gc_mask_set_bit;
 358         ct->chip.irq_set_type = gpio_set_irq_type;
 359         ct->chip.irq_set_wake = gpio_set_wake_irq;
 360         ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND;
 361         ct->regs.ack = GPIO_ISR;
 362         ct->regs.mask = GPIO_IMR;
 363
 364         irq_setup_generic_chip(gc, IRQ_MSK(32), IRQ_GC_INIT_NESTED_LOCK,
 365                                IRQ_NOREQUEST, 0);
 366
 367         return 0;
 368 }
 369
 370 static void mxc_gpio_get_hw(struct platform_device *pdev)
 371 {
 372         const struct of_device_id *of_id =
 373                         of_match_device(mxc_gpio_dt_ids, &pdev->dev);
 374         enum mxc_gpio_hwtype hwtype;
 375
 376         if (of_id)
 377                 pdev->id_entry = of_id->data;
 378         hwtype = pdev->id_entry->driver_data;
 379
 380         if (mxc_gpio_hwtype) {
 381                 /*
 382                  * The driver works with a reasonable presupposition,
 383                  * that is all gpio ports must be the same type when
 384                  * running on one soc.
 385                  */
 386                 BUG_ON(mxc_gpio_hwtype != hwtype);
 387                 return;
 388         }
 389
 390         if (hwtype == IMX35_GPIO)
 391                 mxc_gpio_hwdata = &imx35_gpio_hwdata;
 392         else if (hwtype == IMX31_GPIO)
 393                 mxc_gpio_hwdata = &imx31_gpio_hwdata;
 394         else
 395                 mxc_gpio_hwdata = &imx1_imx21_gpio_hwdata;
 396
 397         mxc_gpio_hwtype = hwtype;
 398 }
 399
 400 static int mxc_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
 401 {
 402         struct mxc_gpio_port *port = gpiochip_get_data(gc);
 403
 404         return irq_find_mapping(port->domain, offset);
 405 }
 406
 407 static int mxc_gpio_probe(struct platform_device *pdev)
 408 {
 409         struct device_node *np = pdev->dev.of_node;
 410         struct mxc_gpio_port *port;
 411         struct resource *iores;
 412         int irq_base;
 413         int err;
 414
 415         mxc_gpio_get_hw(pdev);
 416
 417         port = devm_kzalloc(&pdev->dev, sizeof(*port), GFP_KERNEL);
 418         if (!port)
 419                 return -ENOMEM;
 420
 421         iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 422         port->base = devm_ioremap_resource(&pdev->dev, iores);
 423         if (IS_ERR(port->base))
 424                 return PTR_ERR(port->base);
 425
 426         port->irq_high = platform_get_irq(pdev, 1);
 427         port->irq = platform_get_irq(pdev, 0);
 428         if (port->irq < 0)
 429                 return port->irq;
 430
 431         /* disable the interrupt and clear the status */
 432         writel(0, port->base + GPIO_IMR);
 433         writel(~0, port->base + GPIO_ISR);
 434
 435         if (mxc_gpio_hwtype == IMX21_GPIO) {
 436                 /*
 437                  * Setup one handler for all GPIO interrupts. Actually setting
 438                  * the handler is needed only once, but doing it for every port
 439                  * is more robust and easier.
 440                  */
 441                 irq_set_chained_handler(port->irq, mx2_gpio_irq_handler);
 442         } else {
 443                 /* setup one handler for each entry */
 444                 irq_set_chained_handler_and_data(port->irq,
 445                                                  mx3_gpio_irq_handler, port);
 446                 if (port->irq_high > 0)
 447                         /* setup handler for GPIO 16 to 31 */
 448                         irq_set_chained_handler_and_data(port->irq_high,
 449                                                          mx3_gpio_irq_handler,
 450                                                          port);
 451         }
 452
 453         err = bgpio_init(&port->gc, &pdev->dev, 4,
 454                          port->base + GPIO_PSR,
 455                          port->base + GPIO_DR, NULL,
 456                          port->base + GPIO_GDIR, NULL,
 457                          BGPIOF_READ_OUTPUT_REG_SET);
 458         if (err)
 459                 goto out_bgio;
 460
 461         port->gc.to_irq = mxc_gpio_to_irq;
 462         port->gc.base = (pdev->id < 0) ? of_alias_get_id(np, "gpio") * 32 :
 463                                              pdev->id * 32;
 464
 465         err = devm_gpiochip_add_data(&pdev->dev, &port->gc, port);
 466         if (err)
 467                 goto out_bgio;
 468
 469         irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
 470         if (irq_base < 0) {
 471                 err = irq_base;
 472                 goto out_bgio;
 473         }
 474
 475         port->domain = irq_domain_add_legacy(np, 32, irq_base, 0,
 476                                              &irq_domain_simple_ops, NULL);
 477         if (!port->domain) {
 478                 err = -ENODEV;
 479                 goto out_irqdesc_free;
 480         }
 481
 482         /* gpio-mxc can be a generic irq chip */
 483         err = mxc_gpio_init_gc(port, irq_base);
 484         if (err < 0)
 485                 goto out_irqdomain_remove;
 486
 487         list_add_tail(&port->node, &mxc_gpio_ports);
 488
 489         return 0;
 490
 491 out_irqdomain_remove:
 492         irq_domain_remove(port->domain);
 493 out_irqdesc_free:
 494         irq_free_descs(irq_base, 32);
 495 out_bgio:
 496         dev_info(&pdev->dev, "%s failed with errno %d\n", __func__, err);
 497         return err;
 498 }
 499
 500 static struct platform_driver mxc_gpio_driver = {
 501         .driver         = {
 502                 .name   = "gpio-mxc",
 503                 .of_match_table = mxc_gpio_dt_ids,
 504         },
 505         .probe          = mxc_gpio_probe,
 506         .id_table       = mxc_gpio_devtype,
 507 };
 508
 509 static int __init gpio_mxc_init(void)
 510 {
 511         return platform_driver_register(&mxc_gpio_driver);
 512 }
 513 postcore_initcall(gpio_mxc_init);
 514
 515 MODULE_AUTHOR("Freescale Semiconductor, "
 516               "Daniel Mack <danielncaiaq.de>, "
 517               "Juergen Beisert <kernel@pengutronix.de>");
 518 MODULE_DESCRIPTION("Freescale MXC GPIO");
 519 MODULE_LICENSE("GPL");