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Merge branch 'r6040-next'
[linux/fpc-iii.git] / drivers / idle / intel_idle.c
blobc96649292b556f18647f1dc2a3fa075cfe176ae8
1 /*
2 * intel_idle.c - native hardware idle loop for modern Intel processors
3 *
4 * Copyright (c) 2013, Intel Corporation.
5 * Len Brown <len.brown@intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 */
20
21 /*
22 * intel_idle is a cpuidle driver that loads on specific Intel processors
23 * in lieu of the legacy ACPI processor_idle driver. The intent is to
24 * make Linux more efficient on these processors, as intel_idle knows
25 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
26 */
27
28 /*
29 * Design Assumptions
30 *
31 * All CPUs have same idle states as boot CPU
32 *
33 * Chipset BM_STS (bus master status) bit is a NOP
34 * for preventing entry into deep C-stats
35 */
36
37 /*
38 * Known limitations
39 *
40 * The driver currently initializes for_each_online_cpu() upon modprobe.
41 * It it unaware of subsequent processors hot-added to the system.
42 * This means that if you boot with maxcpus=n and later online
43 * processors above n, those processors will use C1 only.
44 *
45 * ACPI has a .suspend hack to turn off deep c-statees during suspend
46 * to avoid complications with the lapic timer workaround.
47 * Have not seen issues with suspend, but may need same workaround here.
48 *
49 * There is currently no kernel-based automatic probing/loading mechanism
50 * if the driver is built as a module.
51 */
52
53 /* un-comment DEBUG to enable pr_debug() statements */
54 #define DEBUG
55
56 #include <linux/kernel.h>
57 #include <linux/cpuidle.h>
58 #include <linux/tick.h>
59 #include <trace/events/power.h>
60 #include <linux/sched.h>
61 #include <linux/notifier.h>
62 #include <linux/cpu.h>
63 #include <linux/module.h>
64 #include <asm/cpu_device_id.h>
65 #include <asm/mwait.h>
66 #include <asm/msr.h>
67
68 #define INTEL_IDLE_VERSION "0.4.1"
69 #define PREFIX "intel_idle: "
70
71 static struct cpuidle_driver intel_idle_driver = {
72 .name = "intel_idle",
73 .owner = THIS_MODULE,
74 };
75 /* intel_idle.max_cstate=0 disables driver */
76 static int max_cstate = CPUIDLE_STATE_MAX - 1;
77
78 static unsigned int mwait_substates;
79
80 #define LAPIC_TIMER_ALWAYS_RELIABLE 0xFFFFFFFF
81 /* Reliable LAPIC Timer States, bit 1 for C1 etc. */
82 static unsigned int lapic_timer_reliable_states = (1 << 1); /* Default to only C1 */
83
84 struct idle_cpu {
85 struct cpuidle_state *state_table;
86
87 /*
88 * Hardware C-state auto-demotion may not always be optimal.
89 * Indicate which enable bits to clear here.
90 */
91 unsigned long auto_demotion_disable_flags;
92 bool byt_auto_demotion_disable_flag;
93 bool disable_promotion_to_c1e;
94 };
95
96 static const struct idle_cpu *icpu;
97 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
98 static int intel_idle(struct cpuidle_device *dev,
99 struct cpuidle_driver *drv, int index);
100 static void intel_idle_freeze(struct cpuidle_device *dev,
101 struct cpuidle_driver *drv, int index);
102 static int intel_idle_cpu_init(int cpu);
103
104 static struct cpuidle_state *cpuidle_state_table;
105
106 /*
107 * Set this flag for states where the HW flushes the TLB for us
108 * and so we don't need cross-calls to keep it consistent.
109 * If this flag is set, SW flushes the TLB, so even if the
110 * HW doesn't do the flushing, this flag is safe to use.
111 */
112 #define CPUIDLE_FLAG_TLB_FLUSHED 0x10000
113
114 /*
115 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
116 * the C-state (top nibble) and sub-state (bottom nibble)
117 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
118 *
119 * We store the hint at the top of our "flags" for each state.
120 */
121 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
122 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
123
124 /*
125 * States are indexed by the cstate number,
126 * which is also the index into the MWAIT hint array.
127 * Thus C0 is a dummy.
128 */
129 static struct cpuidle_state nehalem_cstates[] = {
130 {
131 .name = "C1-NHM",
132 .desc = "MWAIT 0x00",
133 .flags = MWAIT2flg(0x00),
134 .exit_latency = 3,
135 .target_residency = 6,
136 .enter = &intel_idle,
137 .enter_freeze = intel_idle_freeze, },
138 {
139 .name = "C1E-NHM",
140 .desc = "MWAIT 0x01",
141 .flags = MWAIT2flg(0x01),
142 .exit_latency = 10,
143 .target_residency = 20,
144 .enter = &intel_idle,
145 .enter_freeze = intel_idle_freeze, },
146 {
147 .name = "C3-NHM",
148 .desc = "MWAIT 0x10",
149 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
150 .exit_latency = 20,
151 .target_residency = 80,
152 .enter = &intel_idle,
153 .enter_freeze = intel_idle_freeze, },
154 {
155 .name = "C6-NHM",
156 .desc = "MWAIT 0x20",
157 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
158 .exit_latency = 200,
159 .target_residency = 800,
160 .enter = &intel_idle,
161 .enter_freeze = intel_idle_freeze, },
162 {
163 .enter = NULL }
164 };
165
166 static struct cpuidle_state snb_cstates[] = {
167 {
168 .name = "C1-SNB",
169 .desc = "MWAIT 0x00",
170 .flags = MWAIT2flg(0x00),
171 .exit_latency = 2,
172 .target_residency = 2,
173 .enter = &intel_idle,
174 .enter_freeze = intel_idle_freeze, },
175 {
176 .name = "C1E-SNB",
177 .desc = "MWAIT 0x01",
178 .flags = MWAIT2flg(0x01),
179 .exit_latency = 10,
180 .target_residency = 20,
181 .enter = &intel_idle,
182 .enter_freeze = intel_idle_freeze, },
183 {
184 .name = "C3-SNB",
185 .desc = "MWAIT 0x10",
186 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
187 .exit_latency = 80,
188 .target_residency = 211,
189 .enter = &intel_idle,
190 .enter_freeze = intel_idle_freeze, },
191 {
192 .name = "C6-SNB",
193 .desc = "MWAIT 0x20",
194 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
195 .exit_latency = 104,
196 .target_residency = 345,
197 .enter = &intel_idle,
198 .enter_freeze = intel_idle_freeze, },
199 {
200 .name = "C7-SNB",
201 .desc = "MWAIT 0x30",
202 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
203 .exit_latency = 109,
204 .target_residency = 345,
205 .enter = &intel_idle,
206 .enter_freeze = intel_idle_freeze, },
207 {
208 .enter = NULL }
209 };
210
211 static struct cpuidle_state byt_cstates[] = {
212 {
213 .name = "C1-BYT",
214 .desc = "MWAIT 0x00",
215 .flags = MWAIT2flg(0x00),
216 .exit_latency = 1,
217 .target_residency = 1,
218 .enter = &intel_idle,
219 .enter_freeze = intel_idle_freeze, },
220 {
221 .name = "C6N-BYT",
222 .desc = "MWAIT 0x58",
223 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
224 .exit_latency = 300,
225 .target_residency = 275,
226 .enter = &intel_idle,
227 .enter_freeze = intel_idle_freeze, },
228 {
229 .name = "C6S-BYT",
230 .desc = "MWAIT 0x52",
231 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
232 .exit_latency = 500,
233 .target_residency = 560,
234 .enter = &intel_idle,
235 .enter_freeze = intel_idle_freeze, },
236 {
237 .name = "C7-BYT",
238 .desc = "MWAIT 0x60",
239 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
240 .exit_latency = 1200,
241 .target_residency = 4000,
242 .enter = &intel_idle,
243 .enter_freeze = intel_idle_freeze, },
244 {
245 .name = "C7S-BYT",
246 .desc = "MWAIT 0x64",
247 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
248 .exit_latency = 10000,
249 .target_residency = 20000,
250 .enter = &intel_idle,
251 .enter_freeze = intel_idle_freeze, },
252 {
253 .enter = NULL }
254 };
255
256 static struct cpuidle_state cht_cstates[] = {
257 {
258 .name = "C1-CHT",
259 .desc = "MWAIT 0x00",
260 .flags = MWAIT2flg(0x00),
261 .exit_latency = 1,
262 .target_residency = 1,
263 .enter = &intel_idle,
264 .enter_freeze = intel_idle_freeze, },
265 {
266 .name = "C6N-CHT",
267 .desc = "MWAIT 0x58",
268 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
269 .exit_latency = 80,
270 .target_residency = 275,
271 .enter = &intel_idle,
272 .enter_freeze = intel_idle_freeze, },
273 {
274 .name = "C6S-CHT",
275 .desc = "MWAIT 0x52",
276 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
277 .exit_latency = 200,
278 .target_residency = 560,
279 .enter = &intel_idle,
280 .enter_freeze = intel_idle_freeze, },
281 {
282 .name = "C7-CHT",
283 .desc = "MWAIT 0x60",
284 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
285 .exit_latency = 1200,
286 .target_residency = 4000,
287 .enter = &intel_idle,
288 .enter_freeze = intel_idle_freeze, },
289 {
290 .name = "C7S-CHT",
291 .desc = "MWAIT 0x64",
292 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
293 .exit_latency = 10000,
294 .target_residency = 20000,
295 .enter = &intel_idle,
296 .enter_freeze = intel_idle_freeze, },
297 {
298 .enter = NULL }
299 };
300
301 static struct cpuidle_state ivb_cstates[] = {
302 {
303 .name = "C1-IVB",
304 .desc = "MWAIT 0x00",
305 .flags = MWAIT2flg(0x00),
306 .exit_latency = 1,
307 .target_residency = 1,
308 .enter = &intel_idle,
309 .enter_freeze = intel_idle_freeze, },
310 {
311 .name = "C1E-IVB",
312 .desc = "MWAIT 0x01",
313 .flags = MWAIT2flg(0x01),
314 .exit_latency = 10,
315 .target_residency = 20,
316 .enter = &intel_idle,
317 .enter_freeze = intel_idle_freeze, },
318 {
319 .name = "C3-IVB",
320 .desc = "MWAIT 0x10",
321 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
322 .exit_latency = 59,
323 .target_residency = 156,
324 .enter = &intel_idle,
325 .enter_freeze = intel_idle_freeze, },
326 {
327 .name = "C6-IVB",
328 .desc = "MWAIT 0x20",
329 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
330 .exit_latency = 80,
331 .target_residency = 300,
332 .enter = &intel_idle,
333 .enter_freeze = intel_idle_freeze, },
334 {
335 .name = "C7-IVB",
336 .desc = "MWAIT 0x30",
337 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
338 .exit_latency = 87,
339 .target_residency = 300,
340 .enter = &intel_idle,
341 .enter_freeze = intel_idle_freeze, },
342 {
343 .enter = NULL }
344 };
345
346 static struct cpuidle_state ivt_cstates[] = {
347 {
348 .name = "C1-IVT",
349 .desc = "MWAIT 0x00",
350 .flags = MWAIT2flg(0x00),
351 .exit_latency = 1,
352 .target_residency = 1,
353 .enter = &intel_idle,
354 .enter_freeze = intel_idle_freeze, },
355 {
356 .name = "C1E-IVT",
357 .desc = "MWAIT 0x01",
358 .flags = MWAIT2flg(0x01),
359 .exit_latency = 10,
360 .target_residency = 80,
361 .enter = &intel_idle,
362 .enter_freeze = intel_idle_freeze, },
363 {
364 .name = "C3-IVT",
365 .desc = "MWAIT 0x10",
366 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
367 .exit_latency = 59,
368 .target_residency = 156,
369 .enter = &intel_idle,
370 .enter_freeze = intel_idle_freeze, },
371 {
372 .name = "C6-IVT",
373 .desc = "MWAIT 0x20",
374 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
375 .exit_latency = 82,
376 .target_residency = 300,
377 .enter = &intel_idle,
378 .enter_freeze = intel_idle_freeze, },
379 {
380 .enter = NULL }
381 };
382
383 static struct cpuidle_state ivt_cstates_4s[] = {
384 {
385 .name = "C1-IVT-4S",
386 .desc = "MWAIT 0x00",
387 .flags = MWAIT2flg(0x00),
388 .exit_latency = 1,
389 .target_residency = 1,
390 .enter = &intel_idle,
391 .enter_freeze = intel_idle_freeze, },
392 {
393 .name = "C1E-IVT-4S",
394 .desc = "MWAIT 0x01",
395 .flags = MWAIT2flg(0x01),
396 .exit_latency = 10,
397 .target_residency = 250,
398 .enter = &intel_idle,
399 .enter_freeze = intel_idle_freeze, },
400 {
401 .name = "C3-IVT-4S",
402 .desc = "MWAIT 0x10",
403 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
404 .exit_latency = 59,
405 .target_residency = 300,
406 .enter = &intel_idle,
407 .enter_freeze = intel_idle_freeze, },
408 {
409 .name = "C6-IVT-4S",
410 .desc = "MWAIT 0x20",
411 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
412 .exit_latency = 84,
413 .target_residency = 400,
414 .enter = &intel_idle,
415 .enter_freeze = intel_idle_freeze, },
416 {
417 .enter = NULL }
418 };
419
420 static struct cpuidle_state ivt_cstates_8s[] = {
421 {
422 .name = "C1-IVT-8S",
423 .desc = "MWAIT 0x00",
424 .flags = MWAIT2flg(0x00),
425 .exit_latency = 1,
426 .target_residency = 1,
427 .enter = &intel_idle,
428 .enter_freeze = intel_idle_freeze, },
429 {
430 .name = "C1E-IVT-8S",
431 .desc = "MWAIT 0x01",
432 .flags = MWAIT2flg(0x01),
433 .exit_latency = 10,
434 .target_residency = 500,
435 .enter = &intel_idle,
436 .enter_freeze = intel_idle_freeze, },
437 {
438 .name = "C3-IVT-8S",
439 .desc = "MWAIT 0x10",
440 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
441 .exit_latency = 59,
442 .target_residency = 600,
443 .enter = &intel_idle,
444 .enter_freeze = intel_idle_freeze, },
445 {
446 .name = "C6-IVT-8S",
447 .desc = "MWAIT 0x20",
448 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
449 .exit_latency = 88,
450 .target_residency = 700,
451 .enter = &intel_idle,
452 .enter_freeze = intel_idle_freeze, },
453 {
454 .enter = NULL }
455 };
456
457 static struct cpuidle_state hsw_cstates[] = {
458 {
459 .name = "C1-HSW",
460 .desc = "MWAIT 0x00",
461 .flags = MWAIT2flg(0x00),
462 .exit_latency = 2,
463 .target_residency = 2,
464 .enter = &intel_idle,
465 .enter_freeze = intel_idle_freeze, },
466 {
467 .name = "C1E-HSW",
468 .desc = "MWAIT 0x01",
469 .flags = MWAIT2flg(0x01),
470 .exit_latency = 10,
471 .target_residency = 20,
472 .enter = &intel_idle,
473 .enter_freeze = intel_idle_freeze, },
474 {
475 .name = "C3-HSW",
476 .desc = "MWAIT 0x10",
477 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
478 .exit_latency = 33,
479 .target_residency = 100,
480 .enter = &intel_idle,
481 .enter_freeze = intel_idle_freeze, },
482 {
483 .name = "C6-HSW",
484 .desc = "MWAIT 0x20",
485 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
486 .exit_latency = 133,
487 .target_residency = 400,
488 .enter = &intel_idle,
489 .enter_freeze = intel_idle_freeze, },
490 {
491 .name = "C7s-HSW",
492 .desc = "MWAIT 0x32",
493 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
494 .exit_latency = 166,
495 .target_residency = 500,
496 .enter = &intel_idle,
497 .enter_freeze = intel_idle_freeze, },
498 {
499 .name = "C8-HSW",
500 .desc = "MWAIT 0x40",
501 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
502 .exit_latency = 300,
503 .target_residency = 900,
504 .enter = &intel_idle,
505 .enter_freeze = intel_idle_freeze, },
506 {
507 .name = "C9-HSW",
508 .desc = "MWAIT 0x50",
509 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
510 .exit_latency = 600,
511 .target_residency = 1800,
512 .enter = &intel_idle,
513 .enter_freeze = intel_idle_freeze, },
514 {
515 .name = "C10-HSW",
516 .desc = "MWAIT 0x60",
517 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
518 .exit_latency = 2600,
519 .target_residency = 7700,
520 .enter = &intel_idle,
521 .enter_freeze = intel_idle_freeze, },
522 {
523 .enter = NULL }
524 };
525 static struct cpuidle_state bdw_cstates[] = {
526 {
527 .name = "C1-BDW",
528 .desc = "MWAIT 0x00",
529 .flags = MWAIT2flg(0x00),
530 .exit_latency = 2,
531 .target_residency = 2,
532 .enter = &intel_idle,
533 .enter_freeze = intel_idle_freeze, },
534 {
535 .name = "C1E-BDW",
536 .desc = "MWAIT 0x01",
537 .flags = MWAIT2flg(0x01),
538 .exit_latency = 10,
539 .target_residency = 20,
540 .enter = &intel_idle,
541 .enter_freeze = intel_idle_freeze, },
542 {
543 .name = "C3-BDW",
544 .desc = "MWAIT 0x10",
545 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
546 .exit_latency = 40,
547 .target_residency = 100,
548 .enter = &intel_idle,
549 .enter_freeze = intel_idle_freeze, },
550 {
551 .name = "C6-BDW",
552 .desc = "MWAIT 0x20",
553 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
554 .exit_latency = 133,
555 .target_residency = 400,
556 .enter = &intel_idle,
557 .enter_freeze = intel_idle_freeze, },
558 {
559 .name = "C7s-BDW",
560 .desc = "MWAIT 0x32",
561 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
562 .exit_latency = 166,
563 .target_residency = 500,
564 .enter = &intel_idle,
565 .enter_freeze = intel_idle_freeze, },
566 {
567 .name = "C8-BDW",
568 .desc = "MWAIT 0x40",
569 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
570 .exit_latency = 300,
571 .target_residency = 900,
572 .enter = &intel_idle,
573 .enter_freeze = intel_idle_freeze, },
574 {
575 .name = "C9-BDW",
576 .desc = "MWAIT 0x50",
577 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
578 .exit_latency = 600,
579 .target_residency = 1800,
580 .enter = &intel_idle,
581 .enter_freeze = intel_idle_freeze, },
582 {
583 .name = "C10-BDW",
584 .desc = "MWAIT 0x60",
585 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
586 .exit_latency = 2600,
587 .target_residency = 7700,
588 .enter = &intel_idle,
589 .enter_freeze = intel_idle_freeze, },
590 {
591 .enter = NULL }
592 };
593
594 static struct cpuidle_state skl_cstates[] = {
595 {
596 .name = "C1-SKL",
597 .desc = "MWAIT 0x00",
598 .flags = MWAIT2flg(0x00),
599 .exit_latency = 2,
600 .target_residency = 2,
601 .enter = &intel_idle,
602 .enter_freeze = intel_idle_freeze, },
603 {
604 .name = "C1E-SKL",
605 .desc = "MWAIT 0x01",
606 .flags = MWAIT2flg(0x01),
607 .exit_latency = 10,
608 .target_residency = 20,
609 .enter = &intel_idle,
610 .enter_freeze = intel_idle_freeze, },
611 {
612 .name = "C3-SKL",
613 .desc = "MWAIT 0x10",
614 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
615 .exit_latency = 70,
616 .target_residency = 100,
617 .enter = &intel_idle,
618 .enter_freeze = intel_idle_freeze, },
619 {
620 .name = "C6-SKL",
621 .desc = "MWAIT 0x20",
622 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
623 .exit_latency = 85,
624 .target_residency = 200,
625 .enter = &intel_idle,
626 .enter_freeze = intel_idle_freeze, },
627 {
628 .name = "C7s-SKL",
629 .desc = "MWAIT 0x33",
630 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
631 .exit_latency = 124,
632 .target_residency = 800,
633 .enter = &intel_idle,
634 .enter_freeze = intel_idle_freeze, },
635 {
636 .name = "C8-SKL",
637 .desc = "MWAIT 0x40",
638 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
639 .exit_latency = 200,
640 .target_residency = 800,
641 .enter = &intel_idle,
642 .enter_freeze = intel_idle_freeze, },
643 {
644 .name = "C9-SKL",
645 .desc = "MWAIT 0x50",
646 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
647 .exit_latency = 480,
648 .target_residency = 5000,
649 .enter = &intel_idle,
650 .enter_freeze = intel_idle_freeze, },
651 {
652 .name = "C10-SKL",
653 .desc = "MWAIT 0x60",
654 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
655 .exit_latency = 890,
656 .target_residency = 5000,
657 .enter = &intel_idle,
658 .enter_freeze = intel_idle_freeze, },
659 {
660 .enter = NULL }
661 };
662
663 static struct cpuidle_state skx_cstates[] = {
664 {
665 .name = "C1-SKX",
666 .desc = "MWAIT 0x00",
667 .flags = MWAIT2flg(0x00),
668 .exit_latency = 2,
669 .target_residency = 2,
670 .enter = &intel_idle,
671 .enter_freeze = intel_idle_freeze, },
672 {
673 .name = "C1E-SKX",
674 .desc = "MWAIT 0x01",
675 .flags = MWAIT2flg(0x01),
676 .exit_latency = 10,
677 .target_residency = 20,
678 .enter = &intel_idle,
679 .enter_freeze = intel_idle_freeze, },
680 {
681 .name = "C6-SKX",
682 .desc = "MWAIT 0x20",
683 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
684 .exit_latency = 133,
685 .target_residency = 600,
686 .enter = &intel_idle,
687 .enter_freeze = intel_idle_freeze, },
688 {
689 .enter = NULL }
690 };
691
692 static struct cpuidle_state atom_cstates[] = {
693 {
694 .name = "C1E-ATM",
695 .desc = "MWAIT 0x00",
696 .flags = MWAIT2flg(0x00),
697 .exit_latency = 10,
698 .target_residency = 20,
699 .enter = &intel_idle,
700 .enter_freeze = intel_idle_freeze, },
701 {
702 .name = "C2-ATM",
703 .desc = "MWAIT 0x10",
704 .flags = MWAIT2flg(0x10),
705 .exit_latency = 20,
706 .target_residency = 80,
707 .enter = &intel_idle,
708 .enter_freeze = intel_idle_freeze, },
709 {
710 .name = "C4-ATM",
711 .desc = "MWAIT 0x30",
712 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
713 .exit_latency = 100,
714 .target_residency = 400,
715 .enter = &intel_idle,
716 .enter_freeze = intel_idle_freeze, },
717 {
718 .name = "C6-ATM",
719 .desc = "MWAIT 0x52",
720 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
721 .exit_latency = 140,
722 .target_residency = 560,
723 .enter = &intel_idle,
724 .enter_freeze = intel_idle_freeze, },
725 {
726 .enter = NULL }
727 };
728 static struct cpuidle_state avn_cstates[] = {
729 {
730 .name = "C1-AVN",
731 .desc = "MWAIT 0x00",
732 .flags = MWAIT2flg(0x00),
733 .exit_latency = 2,
734 .target_residency = 2,
735 .enter = &intel_idle,
736 .enter_freeze = intel_idle_freeze, },
737 {
738 .name = "C6-AVN",
739 .desc = "MWAIT 0x51",
740 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
741 .exit_latency = 15,
742 .target_residency = 45,
743 .enter = &intel_idle,
744 .enter_freeze = intel_idle_freeze, },
745 {
746 .enter = NULL }
747 };
748 static struct cpuidle_state knl_cstates[] = {
749 {
750 .name = "C1-KNL",
751 .desc = "MWAIT 0x00",
752 .flags = MWAIT2flg(0x00),
753 .exit_latency = 1,
754 .target_residency = 2,
755 .enter = &intel_idle,
756 .enter_freeze = intel_idle_freeze },
757 {
758 .name = "C6-KNL",
759 .desc = "MWAIT 0x10",
760 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
761 .exit_latency = 120,
762 .target_residency = 500,
763 .enter = &intel_idle,
764 .enter_freeze = intel_idle_freeze },
765 {
766 .enter = NULL }
767 };
768
769 static struct cpuidle_state bxt_cstates[] = {
770 {
771 .name = "C1-BXT",
772 .desc = "MWAIT 0x00",
773 .flags = MWAIT2flg(0x00),
774 .exit_latency = 2,
775 .target_residency = 2,
776 .enter = &intel_idle,
777 .enter_freeze = intel_idle_freeze, },
778 {
779 .name = "C1E-BXT",
780 .desc = "MWAIT 0x01",
781 .flags = MWAIT2flg(0x01),
782 .exit_latency = 10,
783 .target_residency = 20,
784 .enter = &intel_idle,
785 .enter_freeze = intel_idle_freeze, },
786 {
787 .name = "C6-BXT",
788 .desc = "MWAIT 0x20",
789 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
790 .exit_latency = 133,
791 .target_residency = 133,
792 .enter = &intel_idle,
793 .enter_freeze = intel_idle_freeze, },
794 {
795 .name = "C7s-BXT",
796 .desc = "MWAIT 0x31",
797 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
798 .exit_latency = 155,
799 .target_residency = 155,
800 .enter = &intel_idle,
801 .enter_freeze = intel_idle_freeze, },
802 {
803 .name = "C8-BXT",
804 .desc = "MWAIT 0x40",
805 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
806 .exit_latency = 1000,
807 .target_residency = 1000,
808 .enter = &intel_idle,
809 .enter_freeze = intel_idle_freeze, },
810 {
811 .name = "C9-BXT",
812 .desc = "MWAIT 0x50",
813 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
814 .exit_latency = 2000,
815 .target_residency = 2000,
816 .enter = &intel_idle,
817 .enter_freeze = intel_idle_freeze, },
818 {
819 .name = "C10-BXT",
820 .desc = "MWAIT 0x60",
821 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
822 .exit_latency = 10000,
823 .target_residency = 10000,
824 .enter = &intel_idle,
825 .enter_freeze = intel_idle_freeze, },
826 {
827 .enter = NULL }
828 };
829
830 /**
831 * intel_idle
832 * @dev: cpuidle_device
833 * @drv: cpuidle driver
834 * @index: index of cpuidle state
835 *
836 * Must be called under local_irq_disable().
837 */
838 static int intel_idle(struct cpuidle_device *dev,
839 struct cpuidle_driver *drv, int index)
840 {
841 unsigned long ecx = 1; /* break on interrupt flag */
842 struct cpuidle_state *state = &drv->states[index];
843 unsigned long eax = flg2MWAIT(state->flags);
844 unsigned int cstate;
845 int cpu = smp_processor_id();
846
847 cstate = (((eax) >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK) + 1;
848
849 /*
850 * leave_mm() to avoid costly and often unnecessary wakeups
851 * for flushing the user TLB's associated with the active mm.
852 */
853 if (state->flags & CPUIDLE_FLAG_TLB_FLUSHED)
854 leave_mm(cpu);
855
856 if (!(lapic_timer_reliable_states & (1 << (cstate))))
857 tick_broadcast_enter();
858
859 mwait_idle_with_hints(eax, ecx);
860
861 if (!(lapic_timer_reliable_states & (1 << (cstate))))
862 tick_broadcast_exit();
863
864 return index;
865 }
866
867 /**
868 * intel_idle_freeze - simplified "enter" callback routine for suspend-to-idle
869 * @dev: cpuidle_device
870 * @drv: cpuidle driver
871 * @index: state index
872 */
873 static void intel_idle_freeze(struct cpuidle_device *dev,
874 struct cpuidle_driver *drv, int index)
875 {
876 unsigned long ecx = 1; /* break on interrupt flag */
877 unsigned long eax = flg2MWAIT(drv->states[index].flags);
878
879 mwait_idle_with_hints(eax, ecx);
880 }
881
882 static void __setup_broadcast_timer(void *arg)
883 {
884 unsigned long on = (unsigned long)arg;
885
886 if (on)
887 tick_broadcast_enable();
888 else
889 tick_broadcast_disable();
890 }
891
892 static int cpu_hotplug_notify(struct notifier_block *n,
893 unsigned long action, void *hcpu)
894 {
895 int hotcpu = (unsigned long)hcpu;
896 struct cpuidle_device *dev;
897
898 switch (action & ~CPU_TASKS_FROZEN) {
899 case CPU_ONLINE:
900
901 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
902 smp_call_function_single(hotcpu, __setup_broadcast_timer,
903 (void *)true, 1);
904
905 /*
906 * Some systems can hotplug a cpu at runtime after
907 * the kernel has booted, we have to initialize the
908 * driver in this case
909 */
910 dev = per_cpu_ptr(intel_idle_cpuidle_devices, hotcpu);
911 if (dev->registered)
912 break;
913
914 if (intel_idle_cpu_init(hotcpu))
915 return NOTIFY_BAD;
916
917 break;
918 }
919 return NOTIFY_OK;
920 }
921
922 static struct notifier_block cpu_hotplug_notifier = {
923 .notifier_call = cpu_hotplug_notify,
924 };
925
926 static void auto_demotion_disable(void *dummy)
927 {
928 unsigned long long msr_bits;
929
930 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
931 msr_bits &= ~(icpu->auto_demotion_disable_flags);
932 wrmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr_bits);
933 }
934 static void c1e_promotion_disable(void *dummy)
935 {
936 unsigned long long msr_bits;
937
938 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
939 msr_bits &= ~0x2;
940 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
941 }
942
943 static const struct idle_cpu idle_cpu_nehalem = {
944 .state_table = nehalem_cstates,
945 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
946 .disable_promotion_to_c1e = true,
947 };
948
949 static const struct idle_cpu idle_cpu_atom = {
950 .state_table = atom_cstates,
951 };
952
953 static const struct idle_cpu idle_cpu_lincroft = {
954 .state_table = atom_cstates,
955 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
956 };
957
958 static const struct idle_cpu idle_cpu_snb = {
959 .state_table = snb_cstates,
960 .disable_promotion_to_c1e = true,
961 };
962
963 static const struct idle_cpu idle_cpu_byt = {
964 .state_table = byt_cstates,
965 .disable_promotion_to_c1e = true,
966 .byt_auto_demotion_disable_flag = true,
967 };
968
969 static const struct idle_cpu idle_cpu_cht = {
970 .state_table = cht_cstates,
971 .disable_promotion_to_c1e = true,
972 .byt_auto_demotion_disable_flag = true,
973 };
974
975 static const struct idle_cpu idle_cpu_ivb = {
976 .state_table = ivb_cstates,
977 .disable_promotion_to_c1e = true,
978 };
979
980 static const struct idle_cpu idle_cpu_ivt = {
981 .state_table = ivt_cstates,
982 .disable_promotion_to_c1e = true,
983 };
984
985 static const struct idle_cpu idle_cpu_hsw = {
986 .state_table = hsw_cstates,
987 .disable_promotion_to_c1e = true,
988 };
989
990 static const struct idle_cpu idle_cpu_bdw = {
991 .state_table = bdw_cstates,
992 .disable_promotion_to_c1e = true,
993 };
994
995 static const struct idle_cpu idle_cpu_skl = {
996 .state_table = skl_cstates,
997 .disable_promotion_to_c1e = true,
998 };
999
1000 static const struct idle_cpu idle_cpu_skx = {
1001 .state_table = skx_cstates,
1002 .disable_promotion_to_c1e = true,
1003 };
1004
1005 static const struct idle_cpu idle_cpu_avn = {
1006 .state_table = avn_cstates,
1007 .disable_promotion_to_c1e = true,
1008 };
1009
1010 static const struct idle_cpu idle_cpu_knl = {
1011 .state_table = knl_cstates,
1012 };
1013
1014 static const struct idle_cpu idle_cpu_bxt = {
1015 .state_table = bxt_cstates,
1016 .disable_promotion_to_c1e = true,
1017 };
1018
1019 #define ICPU(model, cpu) \
1020 { X86_VENDOR_INTEL, 6, model, X86_FEATURE_MWAIT, (unsigned long)&cpu }
1021
1022 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1023 ICPU(0x1a, idle_cpu_nehalem),
1024 ICPU(0x1e, idle_cpu_nehalem),
1025 ICPU(0x1f, idle_cpu_nehalem),
1026 ICPU(0x25, idle_cpu_nehalem),
1027 ICPU(0x2c, idle_cpu_nehalem),
1028 ICPU(0x2e, idle_cpu_nehalem),
1029 ICPU(0x1c, idle_cpu_atom),
1030 ICPU(0x26, idle_cpu_lincroft),
1031 ICPU(0x2f, idle_cpu_nehalem),
1032 ICPU(0x2a, idle_cpu_snb),
1033 ICPU(0x2d, idle_cpu_snb),
1034 ICPU(0x36, idle_cpu_atom),
1035 ICPU(0x37, idle_cpu_byt),
1036 ICPU(0x4c, idle_cpu_cht),
1037 ICPU(0x3a, idle_cpu_ivb),
1038 ICPU(0x3e, idle_cpu_ivt),
1039 ICPU(0x3c, idle_cpu_hsw),
1040 ICPU(0x3f, idle_cpu_hsw),
1041 ICPU(0x45, idle_cpu_hsw),
1042 ICPU(0x46, idle_cpu_hsw),
1043 ICPU(0x4d, idle_cpu_avn),
1044 ICPU(0x3d, idle_cpu_bdw),
1045 ICPU(0x47, idle_cpu_bdw),
1046 ICPU(0x4f, idle_cpu_bdw),
1047 ICPU(0x56, idle_cpu_bdw),
1048 ICPU(0x4e, idle_cpu_skl),
1049 ICPU(0x5e, idle_cpu_skl),
1050 ICPU(0x8e, idle_cpu_skl),
1051 ICPU(0x9e, idle_cpu_skl),
1052 ICPU(0x55, idle_cpu_skx),
1053 ICPU(0x57, idle_cpu_knl),
1054 ICPU(0x5c, idle_cpu_bxt),
1055 {}
1056 };
1057 MODULE_DEVICE_TABLE(x86cpu, intel_idle_ids);
1058
1059 /*
1060 * intel_idle_probe()
1061 */
1062 static int __init intel_idle_probe(void)
1063 {
1064 unsigned int eax, ebx, ecx;
1065 const struct x86_cpu_id *id;
1066
1067 if (max_cstate == 0) {
1068 pr_debug(PREFIX "disabled\n");
1069 return -EPERM;
1070 }
1071
1072 id = x86_match_cpu(intel_idle_ids);
1073 if (!id) {
1074 if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
1075 boot_cpu_data.x86 == 6)
1076 pr_debug(PREFIX "does not run on family %d model %d\n",
1077 boot_cpu_data.x86, boot_cpu_data.x86_model);
1078 return -ENODEV;
1079 }
1080
1081 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1082 return -ENODEV;
1083
1084 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1085
1086 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1087 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1088 !mwait_substates)
1089 return -ENODEV;
1090
1091 pr_debug(PREFIX "MWAIT substates: 0x%x\n", mwait_substates);
1092
1093 icpu = (const struct idle_cpu *)id->driver_data;
1094 cpuidle_state_table = icpu->state_table;
1095
1096 pr_debug(PREFIX "v" INTEL_IDLE_VERSION
1097 " model 0x%X\n", boot_cpu_data.x86_model);
1098
1099 return 0;
1100 }
1101
1102 /*
1103 * intel_idle_cpuidle_devices_uninit()
1104 * Unregisters the cpuidle devices.
1105 */
1106 static void intel_idle_cpuidle_devices_uninit(void)
1107 {
1108 int i;
1109 struct cpuidle_device *dev;
1110
1111 for_each_online_cpu(i) {
1112 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
1113 cpuidle_unregister_device(dev);
1114 }
1115 }
1116
1117 /*
1118 * ivt_idle_state_table_update(void)
1119 *
1120 * Tune IVT multi-socket targets
1121 * Assumption: num_sockets == (max_package_num + 1)
1122 */
1123 static void ivt_idle_state_table_update(void)
1124 {
1125 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1126 int cpu, package_num, num_sockets = 1;
1127
1128 for_each_online_cpu(cpu) {
1129 package_num = topology_physical_package_id(cpu);
1130 if (package_num + 1 > num_sockets) {
1131 num_sockets = package_num + 1;
1132
1133 if (num_sockets > 4) {
1134 cpuidle_state_table = ivt_cstates_8s;
1135 return;
1136 }
1137 }
1138 }
1139
1140 if (num_sockets > 2)
1141 cpuidle_state_table = ivt_cstates_4s;
1142
1143 /* else, 1 and 2 socket systems use default ivt_cstates */
1144 }
1145
1146 /*
1147 * Translate IRTL (Interrupt Response Time Limit) MSR to usec
1148 */
1149
1150 static unsigned int irtl_ns_units[] = {
1151 1, 32, 1024, 32768, 1048576, 33554432, 0, 0 };
1152
1153 static unsigned long long irtl_2_usec(unsigned long long irtl)
1154 {
1155 unsigned long long ns;
1156
1157 ns = irtl_ns_units[(irtl >> 10) & 0x3];
1158
1159 return div64_u64((irtl & 0x3FF) * ns, 1000);
1160 }
1161 /*
1162 * bxt_idle_state_table_update(void)
1163 *
1164 * On BXT, we trust the IRTL to show the definitive maximum latency
1165 * We use the same value for target_residency.
1166 */
1167 static void bxt_idle_state_table_update(void)
1168 {
1169 unsigned long long msr;
1170
1171 rdmsrl(MSR_PKGC6_IRTL, msr);
1172 if (msr) {
1173 unsigned int usec = irtl_2_usec(msr);
1174
1175 bxt_cstates[2].exit_latency = usec;
1176 bxt_cstates[2].target_residency = usec;
1177 }
1178
1179 rdmsrl(MSR_PKGC7_IRTL, msr);
1180 if (msr) {
1181 unsigned int usec = irtl_2_usec(msr);
1182
1183 bxt_cstates[3].exit_latency = usec;
1184 bxt_cstates[3].target_residency = usec;
1185 }
1186
1187 rdmsrl(MSR_PKGC8_IRTL, msr);
1188 if (msr) {
1189 unsigned int usec = irtl_2_usec(msr);
1190
1191 bxt_cstates[4].exit_latency = usec;
1192 bxt_cstates[4].target_residency = usec;
1193 }
1194
1195 rdmsrl(MSR_PKGC9_IRTL, msr);
1196 if (msr) {
1197 unsigned int usec = irtl_2_usec(msr);
1198
1199 bxt_cstates[5].exit_latency = usec;
1200 bxt_cstates[5].target_residency = usec;
1201 }
1202
1203 rdmsrl(MSR_PKGC10_IRTL, msr);
1204 if (msr) {
1205 unsigned int usec = irtl_2_usec(msr);
1206
1207 bxt_cstates[6].exit_latency = usec;
1208 bxt_cstates[6].target_residency = usec;
1209 }
1210
1211 }
1212 /*
1213 * sklh_idle_state_table_update(void)
1214 *
1215 * On SKL-H (model 0x5e) disable C8 and C9 if:
1216 * C10 is enabled and SGX disabled
1217 */
1218 static void sklh_idle_state_table_update(void)
1219 {
1220 unsigned long long msr;
1221 unsigned int eax, ebx, ecx, edx;
1222
1223
1224 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1225 if (max_cstate <= 7)
1226 return;
1227
1228 /* if PC10 not present in CPUID.MWAIT.EDX */
1229 if ((mwait_substates & (0xF << 28)) == 0)
1230 return;
1231
1232 rdmsrl(MSR_NHM_SNB_PKG_CST_CFG_CTL, msr);
1233
1234 /* PC10 is not enabled in PKG C-state limit */
1235 if ((msr & 0xF) != 8)
1236 return;
1237
1238 ecx = 0;
1239 cpuid(7, &eax, &ebx, &ecx, &edx);
1240
1241 /* if SGX is present */
1242 if (ebx & (1 << 2)) {
1243
1244 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
1245
1246 /* if SGX is enabled */
1247 if (msr & (1 << 18))
1248 return;
1249 }
1250
1251 skl_cstates[5].disabled = 1; /* C8-SKL */
1252 skl_cstates[6].disabled = 1; /* C9-SKL */
1253 }
1254 /*
1255 * intel_idle_state_table_update()
1256 *
1257 * Update the default state_table for this CPU-id
1258 */
1259
1260 static void intel_idle_state_table_update(void)
1261 {
1262 switch (boot_cpu_data.x86_model) {
1263
1264 case 0x3e: /* IVT */
1265 ivt_idle_state_table_update();
1266 break;
1267 case 0x5c: /* BXT */
1268 bxt_idle_state_table_update();
1269 break;
1270 case 0x5e: /* SKL-H */
1271 sklh_idle_state_table_update();
1272 break;
1273 }
1274 }
1275
1276 /*
1277 * intel_idle_cpuidle_driver_init()
1278 * allocate, initialize cpuidle_states
1279 */
1280 static void __init intel_idle_cpuidle_driver_init(void)
1281 {
1282 int cstate;
1283 struct cpuidle_driver *drv = &intel_idle_driver;
1284
1285 intel_idle_state_table_update();
1286
1287 drv->state_count = 1;
1288
1289 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1290 int num_substates, mwait_hint, mwait_cstate;
1291
1292 if ((cpuidle_state_table[cstate].enter == NULL) &&
1293 (cpuidle_state_table[cstate].enter_freeze == NULL))
1294 break;
1295
1296 if (cstate + 1 > max_cstate) {
1297 printk(PREFIX "max_cstate %d reached\n",
1298 max_cstate);
1299 break;
1300 }
1301
1302 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1303 mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint);
1304
1305 /* number of sub-states for this state in CPUID.MWAIT */
1306 num_substates = (mwait_substates >> ((mwait_cstate + 1) * 4))
1307 & MWAIT_SUBSTATE_MASK;
1308
1309 /* if NO sub-states for this state in CPUID, skip it */
1310 if (num_substates == 0)
1311 continue;
1312
1313 /* if state marked as disabled, skip it */
1314 if (cpuidle_state_table[cstate].disabled != 0) {
1315 pr_debug(PREFIX "state %s is disabled",
1316 cpuidle_state_table[cstate].name);
1317 continue;
1318 }
1319
1320
1321 if (((mwait_cstate + 1) > 2) &&
1322 !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1323 mark_tsc_unstable("TSC halts in idle"
1324 " states deeper than C2");
1325
1326 drv->states[drv->state_count] = /* structure copy */
1327 cpuidle_state_table[cstate];
1328
1329 drv->state_count += 1;
1330 }
1331
1332 if (icpu->byt_auto_demotion_disable_flag) {
1333 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1334 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1335 }
1336 }
1337
1338
1339 /*
1340 * intel_idle_cpu_init()
1341 * allocate, initialize, register cpuidle_devices
1342 * @cpu: cpu/core to initialize
1343 */
1344 static int intel_idle_cpu_init(int cpu)
1345 {
1346 struct cpuidle_device *dev;
1347
1348 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1349
1350 dev->cpu = cpu;
1351
1352 if (cpuidle_register_device(dev)) {
1353 pr_debug(PREFIX "cpuidle_register_device %d failed!\n", cpu);
1354 return -EIO;
1355 }
1356
1357 if (icpu->auto_demotion_disable_flags)
1358 smp_call_function_single(cpu, auto_demotion_disable, NULL, 1);
1359
1360 if (icpu->disable_promotion_to_c1e)
1361 smp_call_function_single(cpu, c1e_promotion_disable, NULL, 1);
1362
1363 return 0;
1364 }
1365
1366 static int __init intel_idle_init(void)
1367 {
1368 int retval, i;
1369
1370 /* Do not load intel_idle at all for now if idle= is passed */
1371 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1372 return -ENODEV;
1373
1374 retval = intel_idle_probe();
1375 if (retval)
1376 return retval;
1377
1378 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1379 if (intel_idle_cpuidle_devices == NULL)
1380 return -ENOMEM;
1381
1382 intel_idle_cpuidle_driver_init();
1383 retval = cpuidle_register_driver(&intel_idle_driver);
1384 if (retval) {
1385 struct cpuidle_driver *drv = cpuidle_get_driver();
1386 printk(KERN_DEBUG PREFIX "intel_idle yielding to %s",
1387 drv ? drv->name : "none");
1388 free_percpu(intel_idle_cpuidle_devices);
1389 return retval;
1390 }
1391
1392 cpu_notifier_register_begin();
1393
1394 for_each_online_cpu(i) {
1395 retval = intel_idle_cpu_init(i);
1396 if (retval) {
1397 intel_idle_cpuidle_devices_uninit();
1398 cpu_notifier_register_done();
1399 cpuidle_unregister_driver(&intel_idle_driver);
1400 free_percpu(intel_idle_cpuidle_devices);
1401 return retval;
1402 }
1403 }
1404 __register_cpu_notifier(&cpu_hotplug_notifier);
1405
1406 if (boot_cpu_has(X86_FEATURE_ARAT)) /* Always Reliable APIC Timer */
1407 lapic_timer_reliable_states = LAPIC_TIMER_ALWAYS_RELIABLE;
1408 else
1409 on_each_cpu(__setup_broadcast_timer, (void *)true, 1);
1410
1411 cpu_notifier_register_done();
1412
1413 pr_debug(PREFIX "lapic_timer_reliable_states 0x%x\n",
1414 lapic_timer_reliable_states);
1415
1416 return 0;
1417 }
1418
1419 static void __exit intel_idle_exit(void)
1420 {
1421 struct cpuidle_device *dev;
1422 int i;
1423
1424 cpu_notifier_register_begin();
1425
1426 if (lapic_timer_reliable_states != LAPIC_TIMER_ALWAYS_RELIABLE)
1427 on_each_cpu(__setup_broadcast_timer, (void *)false, 1);
1428 __unregister_cpu_notifier(&cpu_hotplug_notifier);
1429
1430 for_each_possible_cpu(i) {
1431 dev = per_cpu_ptr(intel_idle_cpuidle_devices, i);
1432 cpuidle_unregister_device(dev);
1433 }
1434
1435 cpu_notifier_register_done();
1436
1437 cpuidle_unregister_driver(&intel_idle_driver);
1438 free_percpu(intel_idle_cpuidle_devices);
1439 }
1440
1441 module_init(intel_idle_init);
1442 module_exit(intel_idle_exit);
1443
1444 module_param(max_cstate, int, 0444);
1445
1446 MODULE_AUTHOR("Len Brown <len.brown@intel.com>");
1447 MODULE_DESCRIPTION("Cpuidle driver for Intel Hardware v" INTEL_IDLE_VERSION);
1448 MODULE_LICENSE("GPL");
Linux with added FPC-III support