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Merge branch 'r6040-next'
[linux/fpc-iii.git] / drivers / pci / host / pci-tegra.c
blobc388468c202a75efd28bef26eaafb190690c5856
1 /*
2 * PCIe host controller driver for Tegra SoCs
3 *
4 * Copyright (c) 2010, CompuLab, Ltd.
5 * Author: Mike Rapoport <mike@compulab.co.il>
6 *
7 * Based on NVIDIA PCIe driver
8 * Copyright (c) 2008-2009, NVIDIA Corporation.
9 *
10 * Bits taken from arch/arm/mach-dove/pcie.c
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful, but WITHOUT
18 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
20 * more details.
21 *
22 * You should have received a copy of the GNU General Public License along
23 * with this program; if not, write to the Free Software Foundation, Inc.,
24 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
25 */
26
27 #include <linux/clk.h>
28 #include <linux/debugfs.h>
29 #include <linux/delay.h>
30 #include <linux/export.h>
31 #include <linux/interrupt.h>
32 #include <linux/irq.h>
33 #include <linux/irqdomain.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/msi.h>
37 #include <linux/of_address.h>
38 #include <linux/of_pci.h>
39 #include <linux/of_platform.h>
40 #include <linux/pci.h>
41 #include <linux/phy/phy.h>
42 #include <linux/platform_device.h>
43 #include <linux/reset.h>
44 #include <linux/sizes.h>
45 #include <linux/slab.h>
46 #include <linux/vmalloc.h>
47 #include <linux/regulator/consumer.h>
48
49 #include <soc/tegra/cpuidle.h>
50 #include <soc/tegra/pmc.h>
51
52 #include <asm/mach/irq.h>
53 #include <asm/mach/map.h>
54 #include <asm/mach/pci.h>
55
56 #define INT_PCI_MSI_NR (8 * 32)
57
58 /* register definitions */
59
60 #define AFI_AXI_BAR0_SZ 0x00
61 #define AFI_AXI_BAR1_SZ 0x04
62 #define AFI_AXI_BAR2_SZ 0x08
63 #define AFI_AXI_BAR3_SZ 0x0c
64 #define AFI_AXI_BAR4_SZ 0x10
65 #define AFI_AXI_BAR5_SZ 0x14
66
67 #define AFI_AXI_BAR0_START 0x18
68 #define AFI_AXI_BAR1_START 0x1c
69 #define AFI_AXI_BAR2_START 0x20
70 #define AFI_AXI_BAR3_START 0x24
71 #define AFI_AXI_BAR4_START 0x28
72 #define AFI_AXI_BAR5_START 0x2c
73
74 #define AFI_FPCI_BAR0 0x30
75 #define AFI_FPCI_BAR1 0x34
76 #define AFI_FPCI_BAR2 0x38
77 #define AFI_FPCI_BAR3 0x3c
78 #define AFI_FPCI_BAR4 0x40
79 #define AFI_FPCI_BAR5 0x44
80
81 #define AFI_CACHE_BAR0_SZ 0x48
82 #define AFI_CACHE_BAR0_ST 0x4c
83 #define AFI_CACHE_BAR1_SZ 0x50
84 #define AFI_CACHE_BAR1_ST 0x54
85
86 #define AFI_MSI_BAR_SZ 0x60
87 #define AFI_MSI_FPCI_BAR_ST 0x64
88 #define AFI_MSI_AXI_BAR_ST 0x68
89
90 #define AFI_MSI_VEC0 0x6c
91 #define AFI_MSI_VEC1 0x70
92 #define AFI_MSI_VEC2 0x74
93 #define AFI_MSI_VEC3 0x78
94 #define AFI_MSI_VEC4 0x7c
95 #define AFI_MSI_VEC5 0x80
96 #define AFI_MSI_VEC6 0x84
97 #define AFI_MSI_VEC7 0x88
98
99 #define AFI_MSI_EN_VEC0 0x8c
100 #define AFI_MSI_EN_VEC1 0x90
101 #define AFI_MSI_EN_VEC2 0x94
102 #define AFI_MSI_EN_VEC3 0x98
103 #define AFI_MSI_EN_VEC4 0x9c
104 #define AFI_MSI_EN_VEC5 0xa0
105 #define AFI_MSI_EN_VEC6 0xa4
106 #define AFI_MSI_EN_VEC7 0xa8
107
108 #define AFI_CONFIGURATION 0xac
109 #define AFI_CONFIGURATION_EN_FPCI (1 << 0)
110
111 #define AFI_FPCI_ERROR_MASKS 0xb0
112
113 #define AFI_INTR_MASK 0xb4
114 #define AFI_INTR_MASK_INT_MASK (1 << 0)
115 #define AFI_INTR_MASK_MSI_MASK (1 << 8)
116
117 #define AFI_INTR_CODE 0xb8
118 #define AFI_INTR_CODE_MASK 0xf
119 #define AFI_INTR_INI_SLAVE_ERROR 1
120 #define AFI_INTR_INI_DECODE_ERROR 2
121 #define AFI_INTR_TARGET_ABORT 3
122 #define AFI_INTR_MASTER_ABORT 4
123 #define AFI_INTR_INVALID_WRITE 5
124 #define AFI_INTR_LEGACY 6
125 #define AFI_INTR_FPCI_DECODE_ERROR 7
126 #define AFI_INTR_AXI_DECODE_ERROR 8
127 #define AFI_INTR_FPCI_TIMEOUT 9
128 #define AFI_INTR_PE_PRSNT_SENSE 10
129 #define AFI_INTR_PE_CLKREQ_SENSE 11
130 #define AFI_INTR_CLKCLAMP_SENSE 12
131 #define AFI_INTR_RDY4PD_SENSE 13
132 #define AFI_INTR_P2P_ERROR 14
133
134 #define AFI_INTR_SIGNATURE 0xbc
135 #define AFI_UPPER_FPCI_ADDRESS 0xc0
136 #define AFI_SM_INTR_ENABLE 0xc4
137 #define AFI_SM_INTR_INTA_ASSERT (1 << 0)
138 #define AFI_SM_INTR_INTB_ASSERT (1 << 1)
139 #define AFI_SM_INTR_INTC_ASSERT (1 << 2)
140 #define AFI_SM_INTR_INTD_ASSERT (1 << 3)
141 #define AFI_SM_INTR_INTA_DEASSERT (1 << 4)
142 #define AFI_SM_INTR_INTB_DEASSERT (1 << 5)
143 #define AFI_SM_INTR_INTC_DEASSERT (1 << 6)
144 #define AFI_SM_INTR_INTD_DEASSERT (1 << 7)
145
146 #define AFI_AFI_INTR_ENABLE 0xc8
147 #define AFI_INTR_EN_INI_SLVERR (1 << 0)
148 #define AFI_INTR_EN_INI_DECERR (1 << 1)
149 #define AFI_INTR_EN_TGT_SLVERR (1 << 2)
150 #define AFI_INTR_EN_TGT_DECERR (1 << 3)
151 #define AFI_INTR_EN_TGT_WRERR (1 << 4)
152 #define AFI_INTR_EN_DFPCI_DECERR (1 << 5)
153 #define AFI_INTR_EN_AXI_DECERR (1 << 6)
154 #define AFI_INTR_EN_FPCI_TIMEOUT (1 << 7)
155 #define AFI_INTR_EN_PRSNT_SENSE (1 << 8)
156
157 #define AFI_PCIE_CONFIG 0x0f8
158 #define AFI_PCIE_CONFIG_PCIE_DISABLE(x) (1 << ((x) + 1))
159 #define AFI_PCIE_CONFIG_PCIE_DISABLE_ALL 0xe
160 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK (0xf << 20)
161 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE (0x0 << 20)
162 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420 (0x0 << 20)
163 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1 (0x0 << 20)
164 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL (0x1 << 20)
165 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222 (0x1 << 20)
166 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1 (0x1 << 20)
167 #define AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411 (0x2 << 20)
168
169 #define AFI_FUSE 0x104
170 #define AFI_FUSE_PCIE_T0_GEN2_DIS (1 << 2)
171
172 #define AFI_PEX0_CTRL 0x110
173 #define AFI_PEX1_CTRL 0x118
174 #define AFI_PEX2_CTRL 0x128
175 #define AFI_PEX_CTRL_RST (1 << 0)
176 #define AFI_PEX_CTRL_CLKREQ_EN (1 << 1)
177 #define AFI_PEX_CTRL_REFCLK_EN (1 << 3)
178 #define AFI_PEX_CTRL_OVERRIDE_EN (1 << 4)
179
180 #define AFI_PLLE_CONTROL 0x160
181 #define AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL (1 << 9)
182 #define AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN (1 << 1)
183
184 #define AFI_PEXBIAS_CTRL_0 0x168
185
186 #define RP_VEND_XP 0x00000F00
187 #define RP_VEND_XP_DL_UP (1 << 30)
188
189 #define RP_PRIV_MISC 0x00000FE0
190 #define RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT (0xE << 0)
191 #define RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT (0xF << 0)
192
193 #define RP_LINK_CONTROL_STATUS 0x00000090
194 #define RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE 0x20000000
195 #define RP_LINK_CONTROL_STATUS_LINKSTAT_MASK 0x3fff0000
196
197 #define PADS_CTL_SEL 0x0000009C
198
199 #define PADS_CTL 0x000000A0
200 #define PADS_CTL_IDDQ_1L (1 << 0)
201 #define PADS_CTL_TX_DATA_EN_1L (1 << 6)
202 #define PADS_CTL_RX_DATA_EN_1L (1 << 10)
203
204 #define PADS_PLL_CTL_TEGRA20 0x000000B8
205 #define PADS_PLL_CTL_TEGRA30 0x000000B4
206 #define PADS_PLL_CTL_RST_B4SM (1 << 1)
207 #define PADS_PLL_CTL_LOCKDET (1 << 8)
208 #define PADS_PLL_CTL_REFCLK_MASK (0x3 << 16)
209 #define PADS_PLL_CTL_REFCLK_INTERNAL_CML (0 << 16)
210 #define PADS_PLL_CTL_REFCLK_INTERNAL_CMOS (1 << 16)
211 #define PADS_PLL_CTL_REFCLK_EXTERNAL (2 << 16)
212 #define PADS_PLL_CTL_TXCLKREF_MASK (0x1 << 20)
213 #define PADS_PLL_CTL_TXCLKREF_DIV10 (0 << 20)
214 #define PADS_PLL_CTL_TXCLKREF_DIV5 (1 << 20)
215 #define PADS_PLL_CTL_TXCLKREF_BUF_EN (1 << 22)
216
217 #define PADS_REFCLK_CFG0 0x000000C8
218 #define PADS_REFCLK_CFG1 0x000000CC
219 #define PADS_REFCLK_BIAS 0x000000D0
220
221 /*
222 * Fields in PADS_REFCLK_CFG*. Those registers form an array of 16-bit
223 * entries, one entry per PCIe port. These field definitions and desired
224 * values aren't in the TRM, but do come from NVIDIA.
225 */
226 #define PADS_REFCLK_CFG_TERM_SHIFT 2 /* 6:2 */
227 #define PADS_REFCLK_CFG_E_TERM_SHIFT 7
228 #define PADS_REFCLK_CFG_PREDI_SHIFT 8 /* 11:8 */
229 #define PADS_REFCLK_CFG_DRVI_SHIFT 12 /* 15:12 */
230
231 /* Default value provided by HW engineering is 0xfa5c */
232 #define PADS_REFCLK_CFG_VALUE \
233 ( \
234 (0x17 << PADS_REFCLK_CFG_TERM_SHIFT) | \
235 (0 << PADS_REFCLK_CFG_E_TERM_SHIFT) | \
236 (0xa << PADS_REFCLK_CFG_PREDI_SHIFT) | \
237 (0xf << PADS_REFCLK_CFG_DRVI_SHIFT) \
238 )
239
240 struct tegra_msi {
241 struct msi_controller chip;
242 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
243 struct irq_domain *domain;
244 unsigned long pages;
245 struct mutex lock;
246 int irq;
247 };
248
249 /* used to differentiate between Tegra SoC generations */
250 struct tegra_pcie_soc_data {
251 unsigned int num_ports;
252 unsigned int msi_base_shift;
253 u32 pads_pll_ctl;
254 u32 tx_ref_sel;
255 bool has_pex_clkreq_en;
256 bool has_pex_bias_ctrl;
257 bool has_intr_prsnt_sense;
258 bool has_cml_clk;
259 bool has_gen2;
260 };
261
262 static inline struct tegra_msi *to_tegra_msi(struct msi_controller *chip)
263 {
264 return container_of(chip, struct tegra_msi, chip);
265 }
266
267 struct tegra_pcie {
268 struct device *dev;
269
270 void __iomem *pads;
271 void __iomem *afi;
272 int irq;
273
274 struct list_head buses;
275 struct resource *cs;
276
277 struct resource all;
278 struct resource io;
279 struct resource pio;
280 struct resource mem;
281 struct resource prefetch;
282 struct resource busn;
283
284 struct {
285 resource_size_t mem;
286 resource_size_t io;
287 } offset;
288
289 struct clk *pex_clk;
290 struct clk *afi_clk;
291 struct clk *pll_e;
292 struct clk *cml_clk;
293
294 struct reset_control *pex_rst;
295 struct reset_control *afi_rst;
296 struct reset_control *pcie_xrst;
297
298 bool legacy_phy;
299 struct phy *phy;
300
301 struct tegra_msi msi;
302
303 struct list_head ports;
304 u32 xbar_config;
305
306 struct regulator_bulk_data *supplies;
307 unsigned int num_supplies;
308
309 const struct tegra_pcie_soc_data *soc_data;
310 struct dentry *debugfs;
311 };
312
313 struct tegra_pcie_port {
314 struct tegra_pcie *pcie;
315 struct device_node *np;
316 struct list_head list;
317 struct resource regs;
318 void __iomem *base;
319 unsigned int index;
320 unsigned int lanes;
321
322 struct phy **phys;
323 };
324
325 struct tegra_pcie_bus {
326 struct vm_struct *area;
327 struct list_head list;
328 unsigned int nr;
329 };
330
331 static inline struct tegra_pcie *sys_to_pcie(struct pci_sys_data *sys)
332 {
333 return sys->private_data;
334 }
335
336 static inline void afi_writel(struct tegra_pcie *pcie, u32 value,
337 unsigned long offset)
338 {
339 writel(value, pcie->afi + offset);
340 }
341
342 static inline u32 afi_readl(struct tegra_pcie *pcie, unsigned long offset)
343 {
344 return readl(pcie->afi + offset);
345 }
346
347 static inline void pads_writel(struct tegra_pcie *pcie, u32 value,
348 unsigned long offset)
349 {
350 writel(value, pcie->pads + offset);
351 }
352
353 static inline u32 pads_readl(struct tegra_pcie *pcie, unsigned long offset)
354 {
355 return readl(pcie->pads + offset);
356 }
357
358 /*
359 * The configuration space mapping on Tegra is somewhat similar to the ECAM
360 * defined by PCIe. However it deviates a bit in how the 4 bits for extended
361 * register accesses are mapped:
362 *
363 * [27:24] extended register number
364 * [23:16] bus number
365 * [15:11] device number
366 * [10: 8] function number
367 * [ 7: 0] register number
368 *
369 * Mapping the whole extended configuration space would require 256 MiB of
370 * virtual address space, only a small part of which will actually be used.
371 * To work around this, a 1 MiB of virtual addresses are allocated per bus
372 * when the bus is first accessed. When the physical range is mapped, the
373 * the bus number bits are hidden so that the extended register number bits
374 * appear as bits [19:16]. Therefore the virtual mapping looks like this:
375 *
376 * [19:16] extended register number
377 * [15:11] device number
378 * [10: 8] function number
379 * [ 7: 0] register number
380 *
381 * This is achieved by stitching together 16 chunks of 64 KiB of physical
382 * address space via the MMU.
383 */
384 static unsigned long tegra_pcie_conf_offset(unsigned int devfn, int where)
385 {
386 return ((where & 0xf00) << 8) | (PCI_SLOT(devfn) << 11) |
387 (PCI_FUNC(devfn) << 8) | (where & 0xfc);
388 }
389
390 static struct tegra_pcie_bus *tegra_pcie_bus_alloc(struct tegra_pcie *pcie,
391 unsigned int busnr)
392 {
393 pgprot_t prot = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY |
394 L_PTE_XN | L_PTE_MT_DEV_SHARED | L_PTE_SHARED);
395 phys_addr_t cs = pcie->cs->start;
396 struct tegra_pcie_bus *bus;
397 unsigned int i;
398 int err;
399
400 bus = kzalloc(sizeof(*bus), GFP_KERNEL);
401 if (!bus)
402 return ERR_PTR(-ENOMEM);
403
404 INIT_LIST_HEAD(&bus->list);
405 bus->nr = busnr;
406
407 /* allocate 1 MiB of virtual addresses */
408 bus->area = get_vm_area(SZ_1M, VM_IOREMAP);
409 if (!bus->area) {
410 err = -ENOMEM;
411 goto free;
412 }
413
414 /* map each of the 16 chunks of 64 KiB each */
415 for (i = 0; i < 16; i++) {
416 unsigned long virt = (unsigned long)bus->area->addr +
417 i * SZ_64K;
418 phys_addr_t phys = cs + i * SZ_16M + busnr * SZ_64K;
419
420 err = ioremap_page_range(virt, virt + SZ_64K, phys, prot);
421 if (err < 0) {
422 dev_err(pcie->dev, "ioremap_page_range() failed: %d\n",
423 err);
424 goto unmap;
425 }
426 }
427
428 return bus;
429
430 unmap:
431 vunmap(bus->area->addr);
432 free:
433 kfree(bus);
434 return ERR_PTR(err);
435 }
436
437 static int tegra_pcie_add_bus(struct pci_bus *bus)
438 {
439 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
440 struct tegra_pcie_bus *b;
441
442 b = tegra_pcie_bus_alloc(pcie, bus->number);
443 if (IS_ERR(b))
444 return PTR_ERR(b);
445
446 list_add_tail(&b->list, &pcie->buses);
447
448 return 0;
449 }
450
451 static void tegra_pcie_remove_bus(struct pci_bus *child)
452 {
453 struct tegra_pcie *pcie = sys_to_pcie(child->sysdata);
454 struct tegra_pcie_bus *bus, *tmp;
455
456 list_for_each_entry_safe(bus, tmp, &pcie->buses, list) {
457 if (bus->nr == child->number) {
458 vunmap(bus->area->addr);
459 list_del(&bus->list);
460 kfree(bus);
461 break;
462 }
463 }
464 }
465
466 static void __iomem *tegra_pcie_map_bus(struct pci_bus *bus,
467 unsigned int devfn,
468 int where)
469 {
470 struct tegra_pcie *pcie = sys_to_pcie(bus->sysdata);
471 void __iomem *addr = NULL;
472
473 if (bus->number == 0) {
474 unsigned int slot = PCI_SLOT(devfn);
475 struct tegra_pcie_port *port;
476
477 list_for_each_entry(port, &pcie->ports, list) {
478 if (port->index + 1 == slot) {
479 addr = port->base + (where & ~3);
480 break;
481 }
482 }
483 } else {
484 struct tegra_pcie_bus *b;
485
486 list_for_each_entry(b, &pcie->buses, list)
487 if (b->nr == bus->number)
488 addr = (void __iomem *)b->area->addr;
489
490 if (!addr) {
491 dev_err(pcie->dev,
492 "failed to map cfg. space for bus %u\n",
493 bus->number);
494 return NULL;
495 }
496
497 addr += tegra_pcie_conf_offset(devfn, where);
498 }
499
500 return addr;
501 }
502
503 static struct pci_ops tegra_pcie_ops = {
504 .add_bus = tegra_pcie_add_bus,
505 .remove_bus = tegra_pcie_remove_bus,
506 .map_bus = tegra_pcie_map_bus,
507 .read = pci_generic_config_read32,
508 .write = pci_generic_config_write32,
509 };
510
511 static unsigned long tegra_pcie_port_get_pex_ctrl(struct tegra_pcie_port *port)
512 {
513 unsigned long ret = 0;
514
515 switch (port->index) {
516 case 0:
517 ret = AFI_PEX0_CTRL;
518 break;
519
520 case 1:
521 ret = AFI_PEX1_CTRL;
522 break;
523
524 case 2:
525 ret = AFI_PEX2_CTRL;
526 break;
527 }
528
529 return ret;
530 }
531
532 static void tegra_pcie_port_reset(struct tegra_pcie_port *port)
533 {
534 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
535 unsigned long value;
536
537 /* pulse reset signal */
538 value = afi_readl(port->pcie, ctrl);
539 value &= ~AFI_PEX_CTRL_RST;
540 afi_writel(port->pcie, value, ctrl);
541
542 usleep_range(1000, 2000);
543
544 value = afi_readl(port->pcie, ctrl);
545 value |= AFI_PEX_CTRL_RST;
546 afi_writel(port->pcie, value, ctrl);
547 }
548
549 static void tegra_pcie_port_enable(struct tegra_pcie_port *port)
550 {
551 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
552 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
553 unsigned long value;
554
555 /* enable reference clock */
556 value = afi_readl(port->pcie, ctrl);
557 value |= AFI_PEX_CTRL_REFCLK_EN;
558
559 if (soc->has_pex_clkreq_en)
560 value |= AFI_PEX_CTRL_CLKREQ_EN;
561
562 value |= AFI_PEX_CTRL_OVERRIDE_EN;
563
564 afi_writel(port->pcie, value, ctrl);
565
566 tegra_pcie_port_reset(port);
567 }
568
569 static void tegra_pcie_port_disable(struct tegra_pcie_port *port)
570 {
571 const struct tegra_pcie_soc_data *soc = port->pcie->soc_data;
572 unsigned long ctrl = tegra_pcie_port_get_pex_ctrl(port);
573 unsigned long value;
574
575 /* assert port reset */
576 value = afi_readl(port->pcie, ctrl);
577 value &= ~AFI_PEX_CTRL_RST;
578 afi_writel(port->pcie, value, ctrl);
579
580 /* disable reference clock */
581 value = afi_readl(port->pcie, ctrl);
582
583 if (soc->has_pex_clkreq_en)
584 value &= ~AFI_PEX_CTRL_CLKREQ_EN;
585
586 value &= ~AFI_PEX_CTRL_REFCLK_EN;
587 afi_writel(port->pcie, value, ctrl);
588 }
589
590 static void tegra_pcie_port_free(struct tegra_pcie_port *port)
591 {
592 struct tegra_pcie *pcie = port->pcie;
593
594 devm_iounmap(pcie->dev, port->base);
595 devm_release_mem_region(pcie->dev, port->regs.start,
596 resource_size(&port->regs));
597 list_del(&port->list);
598 devm_kfree(pcie->dev, port);
599 }
600
601 /* Tegra PCIE root complex wrongly reports device class */
602 static void tegra_pcie_fixup_class(struct pci_dev *dev)
603 {
604 dev->class = PCI_CLASS_BRIDGE_PCI << 8;
605 }
606 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, tegra_pcie_fixup_class);
607 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, tegra_pcie_fixup_class);
608 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, tegra_pcie_fixup_class);
609 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, tegra_pcie_fixup_class);
610
611 /* Tegra PCIE requires relaxed ordering */
612 static void tegra_pcie_relax_enable(struct pci_dev *dev)
613 {
614 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_RELAX_EN);
615 }
616 DECLARE_PCI_FIXUP_FINAL(PCI_ANY_ID, PCI_ANY_ID, tegra_pcie_relax_enable);
617
618 static int tegra_pcie_setup(int nr, struct pci_sys_data *sys)
619 {
620 struct tegra_pcie *pcie = sys_to_pcie(sys);
621 int err;
622
623 sys->mem_offset = pcie->offset.mem;
624 sys->io_offset = pcie->offset.io;
625
626 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->io);
627 if (err < 0)
628 return err;
629
630 err = devm_request_resource(pcie->dev, &ioport_resource, &pcie->pio);
631 if (err < 0)
632 return err;
633
634 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->mem);
635 if (err < 0)
636 return err;
637
638 err = devm_request_resource(pcie->dev, &pcie->all, &pcie->prefetch);
639 if (err)
640 return err;
641
642 pci_add_resource_offset(&sys->resources, &pcie->pio, sys->io_offset);
643 pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
644 pci_add_resource_offset(&sys->resources, &pcie->prefetch,
645 sys->mem_offset);
646 pci_add_resource(&sys->resources, &pcie->busn);
647
648 pci_ioremap_io(pcie->pio.start, pcie->io.start);
649
650 return 1;
651 }
652
653 static int tegra_pcie_map_irq(const struct pci_dev *pdev, u8 slot, u8 pin)
654 {
655 struct tegra_pcie *pcie = sys_to_pcie(pdev->bus->sysdata);
656 int irq;
657
658 tegra_cpuidle_pcie_irqs_in_use();
659
660 irq = of_irq_parse_and_map_pci(pdev, slot, pin);
661 if (!irq)
662 irq = pcie->irq;
663
664 return irq;
665 }
666
667 static irqreturn_t tegra_pcie_isr(int irq, void *arg)
668 {
669 const char *err_msg[] = {
670 "Unknown",
671 "AXI slave error",
672 "AXI decode error",
673 "Target abort",
674 "Master abort",
675 "Invalid write",
676 "Legacy interrupt",
677 "Response decoding error",
678 "AXI response decoding error",
679 "Transaction timeout",
680 "Slot present pin change",
681 "Slot clock request change",
682 "TMS clock ramp change",
683 "TMS ready for power down",
684 "Peer2Peer error",
685 };
686 struct tegra_pcie *pcie = arg;
687 u32 code, signature;
688
689 code = afi_readl(pcie, AFI_INTR_CODE) & AFI_INTR_CODE_MASK;
690 signature = afi_readl(pcie, AFI_INTR_SIGNATURE);
691 afi_writel(pcie, 0, AFI_INTR_CODE);
692
693 if (code == AFI_INTR_LEGACY)
694 return IRQ_NONE;
695
696 if (code >= ARRAY_SIZE(err_msg))
697 code = 0;
698
699 /*
700 * do not pollute kernel log with master abort reports since they
701 * happen a lot during enumeration
702 */
703 if (code == AFI_INTR_MASTER_ABORT)
704 dev_dbg(pcie->dev, "%s, signature: %08x\n", err_msg[code],
705 signature);
706 else
707 dev_err(pcie->dev, "%s, signature: %08x\n", err_msg[code],
708 signature);
709
710 if (code == AFI_INTR_TARGET_ABORT || code == AFI_INTR_MASTER_ABORT ||
711 code == AFI_INTR_FPCI_DECODE_ERROR) {
712 u32 fpci = afi_readl(pcie, AFI_UPPER_FPCI_ADDRESS) & 0xff;
713 u64 address = (u64)fpci << 32 | (signature & 0xfffffffc);
714
715 if (code == AFI_INTR_MASTER_ABORT)
716 dev_dbg(pcie->dev, " FPCI address: %10llx\n", address);
717 else
718 dev_err(pcie->dev, " FPCI address: %10llx\n", address);
719 }
720
721 return IRQ_HANDLED;
722 }
723
724 /*
725 * FPCI map is as follows:
726 * - 0xfdfc000000: I/O space
727 * - 0xfdfe000000: type 0 configuration space
728 * - 0xfdff000000: type 1 configuration space
729 * - 0xfe00000000: type 0 extended configuration space
730 * - 0xfe10000000: type 1 extended configuration space
731 */
732 static void tegra_pcie_setup_translations(struct tegra_pcie *pcie)
733 {
734 u32 fpci_bar, size, axi_address;
735
736 /* Bar 0: type 1 extended configuration space */
737 fpci_bar = 0xfe100000;
738 size = resource_size(pcie->cs);
739 axi_address = pcie->cs->start;
740 afi_writel(pcie, axi_address, AFI_AXI_BAR0_START);
741 afi_writel(pcie, size >> 12, AFI_AXI_BAR0_SZ);
742 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR0);
743
744 /* Bar 1: downstream IO bar */
745 fpci_bar = 0xfdfc0000;
746 size = resource_size(&pcie->io);
747 axi_address = pcie->io.start;
748 afi_writel(pcie, axi_address, AFI_AXI_BAR1_START);
749 afi_writel(pcie, size >> 12, AFI_AXI_BAR1_SZ);
750 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR1);
751
752 /* Bar 2: prefetchable memory BAR */
753 fpci_bar = (((pcie->prefetch.start >> 12) & 0x0fffffff) << 4) | 0x1;
754 size = resource_size(&pcie->prefetch);
755 axi_address = pcie->prefetch.start;
756 afi_writel(pcie, axi_address, AFI_AXI_BAR2_START);
757 afi_writel(pcie, size >> 12, AFI_AXI_BAR2_SZ);
758 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR2);
759
760 /* Bar 3: non prefetchable memory BAR */
761 fpci_bar = (((pcie->mem.start >> 12) & 0x0fffffff) << 4) | 0x1;
762 size = resource_size(&pcie->mem);
763 axi_address = pcie->mem.start;
764 afi_writel(pcie, axi_address, AFI_AXI_BAR3_START);
765 afi_writel(pcie, size >> 12, AFI_AXI_BAR3_SZ);
766 afi_writel(pcie, fpci_bar, AFI_FPCI_BAR3);
767
768 /* NULL out the remaining BARs as they are not used */
769 afi_writel(pcie, 0, AFI_AXI_BAR4_START);
770 afi_writel(pcie, 0, AFI_AXI_BAR4_SZ);
771 afi_writel(pcie, 0, AFI_FPCI_BAR4);
772
773 afi_writel(pcie, 0, AFI_AXI_BAR5_START);
774 afi_writel(pcie, 0, AFI_AXI_BAR5_SZ);
775 afi_writel(pcie, 0, AFI_FPCI_BAR5);
776
777 /* map all upstream transactions as uncached */
778 afi_writel(pcie, 0, AFI_CACHE_BAR0_ST);
779 afi_writel(pcie, 0, AFI_CACHE_BAR0_SZ);
780 afi_writel(pcie, 0, AFI_CACHE_BAR1_ST);
781 afi_writel(pcie, 0, AFI_CACHE_BAR1_SZ);
782
783 /* MSI translations are setup only when needed */
784 afi_writel(pcie, 0, AFI_MSI_FPCI_BAR_ST);
785 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
786 afi_writel(pcie, 0, AFI_MSI_AXI_BAR_ST);
787 afi_writel(pcie, 0, AFI_MSI_BAR_SZ);
788 }
789
790 static int tegra_pcie_pll_wait(struct tegra_pcie *pcie, unsigned long timeout)
791 {
792 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
793 u32 value;
794
795 timeout = jiffies + msecs_to_jiffies(timeout);
796
797 while (time_before(jiffies, timeout)) {
798 value = pads_readl(pcie, soc->pads_pll_ctl);
799 if (value & PADS_PLL_CTL_LOCKDET)
800 return 0;
801 }
802
803 return -ETIMEDOUT;
804 }
805
806 static int tegra_pcie_phy_enable(struct tegra_pcie *pcie)
807 {
808 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
809 u32 value;
810 int err;
811
812 /* initialize internal PHY, enable up to 16 PCIE lanes */
813 pads_writel(pcie, 0x0, PADS_CTL_SEL);
814
815 /* override IDDQ to 1 on all 4 lanes */
816 value = pads_readl(pcie, PADS_CTL);
817 value |= PADS_CTL_IDDQ_1L;
818 pads_writel(pcie, value, PADS_CTL);
819
820 /*
821 * Set up PHY PLL inputs select PLLE output as refclock,
822 * set TX ref sel to div10 (not div5).
823 */
824 value = pads_readl(pcie, soc->pads_pll_ctl);
825 value &= ~(PADS_PLL_CTL_REFCLK_MASK | PADS_PLL_CTL_TXCLKREF_MASK);
826 value |= PADS_PLL_CTL_REFCLK_INTERNAL_CML | soc->tx_ref_sel;
827 pads_writel(pcie, value, soc->pads_pll_ctl);
828
829 /* reset PLL */
830 value = pads_readl(pcie, soc->pads_pll_ctl);
831 value &= ~PADS_PLL_CTL_RST_B4SM;
832 pads_writel(pcie, value, soc->pads_pll_ctl);
833
834 usleep_range(20, 100);
835
836 /* take PLL out of reset */
837 value = pads_readl(pcie, soc->pads_pll_ctl);
838 value |= PADS_PLL_CTL_RST_B4SM;
839 pads_writel(pcie, value, soc->pads_pll_ctl);
840
841 /* Configure the reference clock driver */
842 value = PADS_REFCLK_CFG_VALUE | (PADS_REFCLK_CFG_VALUE << 16);
843 pads_writel(pcie, value, PADS_REFCLK_CFG0);
844 if (soc->num_ports > 2)
845 pads_writel(pcie, PADS_REFCLK_CFG_VALUE, PADS_REFCLK_CFG1);
846
847 /* wait for the PLL to lock */
848 err = tegra_pcie_pll_wait(pcie, 500);
849 if (err < 0) {
850 dev_err(pcie->dev, "PLL failed to lock: %d\n", err);
851 return err;
852 }
853
854 /* turn off IDDQ override */
855 value = pads_readl(pcie, PADS_CTL);
856 value &= ~PADS_CTL_IDDQ_1L;
857 pads_writel(pcie, value, PADS_CTL);
858
859 /* enable TX/RX data */
860 value = pads_readl(pcie, PADS_CTL);
861 value |= PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L;
862 pads_writel(pcie, value, PADS_CTL);
863
864 return 0;
865 }
866
867 static int tegra_pcie_phy_disable(struct tegra_pcie *pcie)
868 {
869 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
870 u32 value;
871
872 /* disable TX/RX data */
873 value = pads_readl(pcie, PADS_CTL);
874 value &= ~(PADS_CTL_TX_DATA_EN_1L | PADS_CTL_RX_DATA_EN_1L);
875 pads_writel(pcie, value, PADS_CTL);
876
877 /* override IDDQ */
878 value = pads_readl(pcie, PADS_CTL);
879 value |= PADS_CTL_IDDQ_1L;
880 pads_writel(pcie, PADS_CTL, value);
881
882 /* reset PLL */
883 value = pads_readl(pcie, soc->pads_pll_ctl);
884 value &= ~PADS_PLL_CTL_RST_B4SM;
885 pads_writel(pcie, value, soc->pads_pll_ctl);
886
887 usleep_range(20, 100);
888
889 return 0;
890 }
891
892 static int tegra_pcie_port_phy_power_on(struct tegra_pcie_port *port)
893 {
894 struct device *dev = port->pcie->dev;
895 unsigned int i;
896 int err;
897
898 for (i = 0; i < port->lanes; i++) {
899 err = phy_power_on(port->phys[i]);
900 if (err < 0) {
901 dev_err(dev, "failed to power on PHY#%u: %d\n", i,
902 err);
903 return err;
904 }
905 }
906
907 return 0;
908 }
909
910 static int tegra_pcie_port_phy_power_off(struct tegra_pcie_port *port)
911 {
912 struct device *dev = port->pcie->dev;
913 unsigned int i;
914 int err;
915
916 for (i = 0; i < port->lanes; i++) {
917 err = phy_power_off(port->phys[i]);
918 if (err < 0) {
919 dev_err(dev, "failed to power off PHY#%u: %d\n", i,
920 err);
921 return err;
922 }
923 }
924
925 return 0;
926 }
927
928 static int tegra_pcie_phy_power_on(struct tegra_pcie *pcie)
929 {
930 struct tegra_pcie_port *port;
931 int err;
932
933 if (pcie->legacy_phy) {
934 if (pcie->phy)
935 err = phy_power_on(pcie->phy);
936 else
937 err = tegra_pcie_phy_enable(pcie);
938
939 if (err < 0)
940 dev_err(pcie->dev, "failed to power on PHY: %d\n", err);
941
942 return err;
943 }
944
945 list_for_each_entry(port, &pcie->ports, list) {
946 err = tegra_pcie_port_phy_power_on(port);
947 if (err < 0) {
948 dev_err(pcie->dev,
949 "failed to power on PCIe port %u PHY: %d\n",
950 port->index, err);
951 return err;
952 }
953 }
954
955 return 0;
956 }
957
958 static int tegra_pcie_phy_power_off(struct tegra_pcie *pcie)
959 {
960 struct tegra_pcie_port *port;
961 int err;
962
963 if (pcie->legacy_phy) {
964 if (pcie->phy)
965 err = phy_power_off(pcie->phy);
966 else
967 err = tegra_pcie_phy_disable(pcie);
968
969 if (err < 0)
970 dev_err(pcie->dev, "failed to power off PHY: %d\n",
971 err);
972
973 return err;
974 }
975
976 list_for_each_entry(port, &pcie->ports, list) {
977 err = tegra_pcie_port_phy_power_off(port);
978 if (err < 0) {
979 dev_err(pcie->dev,
980 "failed to power off PCIe port %u PHY: %d\n",
981 port->index, err);
982 return err;
983 }
984 }
985
986 return 0;
987 }
988
989 static int tegra_pcie_enable_controller(struct tegra_pcie *pcie)
990 {
991 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
992 struct tegra_pcie_port *port;
993 unsigned long value;
994 int err;
995
996 /* enable PLL power down */
997 if (pcie->phy) {
998 value = afi_readl(pcie, AFI_PLLE_CONTROL);
999 value &= ~AFI_PLLE_CONTROL_BYPASS_PADS2PLLE_CONTROL;
1000 value |= AFI_PLLE_CONTROL_PADS2PLLE_CONTROL_EN;
1001 afi_writel(pcie, value, AFI_PLLE_CONTROL);
1002 }
1003
1004 /* power down PCIe slot clock bias pad */
1005 if (soc->has_pex_bias_ctrl)
1006 afi_writel(pcie, 0, AFI_PEXBIAS_CTRL_0);
1007
1008 /* configure mode and disable all ports */
1009 value = afi_readl(pcie, AFI_PCIE_CONFIG);
1010 value &= ~AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_MASK;
1011 value |= AFI_PCIE_CONFIG_PCIE_DISABLE_ALL | pcie->xbar_config;
1012
1013 list_for_each_entry(port, &pcie->ports, list)
1014 value &= ~AFI_PCIE_CONFIG_PCIE_DISABLE(port->index);
1015
1016 afi_writel(pcie, value, AFI_PCIE_CONFIG);
1017
1018 if (soc->has_gen2) {
1019 value = afi_readl(pcie, AFI_FUSE);
1020 value &= ~AFI_FUSE_PCIE_T0_GEN2_DIS;
1021 afi_writel(pcie, value, AFI_FUSE);
1022 } else {
1023 value = afi_readl(pcie, AFI_FUSE);
1024 value |= AFI_FUSE_PCIE_T0_GEN2_DIS;
1025 afi_writel(pcie, value, AFI_FUSE);
1026 }
1027
1028 err = tegra_pcie_phy_power_on(pcie);
1029 if (err < 0) {
1030 dev_err(pcie->dev, "failed to power on PHY(s): %d\n", err);
1031 return err;
1032 }
1033
1034 /* take the PCIe interface module out of reset */
1035 reset_control_deassert(pcie->pcie_xrst);
1036
1037 /* finally enable PCIe */
1038 value = afi_readl(pcie, AFI_CONFIGURATION);
1039 value |= AFI_CONFIGURATION_EN_FPCI;
1040 afi_writel(pcie, value, AFI_CONFIGURATION);
1041
1042 value = AFI_INTR_EN_INI_SLVERR | AFI_INTR_EN_INI_DECERR |
1043 AFI_INTR_EN_TGT_SLVERR | AFI_INTR_EN_TGT_DECERR |
1044 AFI_INTR_EN_TGT_WRERR | AFI_INTR_EN_DFPCI_DECERR;
1045
1046 if (soc->has_intr_prsnt_sense)
1047 value |= AFI_INTR_EN_PRSNT_SENSE;
1048
1049 afi_writel(pcie, value, AFI_AFI_INTR_ENABLE);
1050 afi_writel(pcie, 0xffffffff, AFI_SM_INTR_ENABLE);
1051
1052 /* don't enable MSI for now, only when needed */
1053 afi_writel(pcie, AFI_INTR_MASK_INT_MASK, AFI_INTR_MASK);
1054
1055 /* disable all exceptions */
1056 afi_writel(pcie, 0, AFI_FPCI_ERROR_MASKS);
1057
1058 return 0;
1059 }
1060
1061 static void tegra_pcie_power_off(struct tegra_pcie *pcie)
1062 {
1063 int err;
1064
1065 /* TODO: disable and unprepare clocks? */
1066
1067 err = tegra_pcie_phy_power_off(pcie);
1068 if (err < 0)
1069 dev_err(pcie->dev, "failed to power off PHY(s): %d\n", err);
1070
1071 reset_control_assert(pcie->pcie_xrst);
1072 reset_control_assert(pcie->afi_rst);
1073 reset_control_assert(pcie->pex_rst);
1074
1075 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
1076
1077 err = regulator_bulk_disable(pcie->num_supplies, pcie->supplies);
1078 if (err < 0)
1079 dev_warn(pcie->dev, "failed to disable regulators: %d\n", err);
1080 }
1081
1082 static int tegra_pcie_power_on(struct tegra_pcie *pcie)
1083 {
1084 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1085 int err;
1086
1087 reset_control_assert(pcie->pcie_xrst);
1088 reset_control_assert(pcie->afi_rst);
1089 reset_control_assert(pcie->pex_rst);
1090
1091 tegra_powergate_power_off(TEGRA_POWERGATE_PCIE);
1092
1093 /* enable regulators */
1094 err = regulator_bulk_enable(pcie->num_supplies, pcie->supplies);
1095 if (err < 0)
1096 dev_err(pcie->dev, "failed to enable regulators: %d\n", err);
1097
1098 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_PCIE,
1099 pcie->pex_clk,
1100 pcie->pex_rst);
1101 if (err) {
1102 dev_err(pcie->dev, "powerup sequence failed: %d\n", err);
1103 return err;
1104 }
1105
1106 reset_control_deassert(pcie->afi_rst);
1107
1108 err = clk_prepare_enable(pcie->afi_clk);
1109 if (err < 0) {
1110 dev_err(pcie->dev, "failed to enable AFI clock: %d\n", err);
1111 return err;
1112 }
1113
1114 if (soc->has_cml_clk) {
1115 err = clk_prepare_enable(pcie->cml_clk);
1116 if (err < 0) {
1117 dev_err(pcie->dev, "failed to enable CML clock: %d\n",
1118 err);
1119 return err;
1120 }
1121 }
1122
1123 err = clk_prepare_enable(pcie->pll_e);
1124 if (err < 0) {
1125 dev_err(pcie->dev, "failed to enable PLLE clock: %d\n", err);
1126 return err;
1127 }
1128
1129 return 0;
1130 }
1131
1132 static int tegra_pcie_clocks_get(struct tegra_pcie *pcie)
1133 {
1134 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1135
1136 pcie->pex_clk = devm_clk_get(pcie->dev, "pex");
1137 if (IS_ERR(pcie->pex_clk))
1138 return PTR_ERR(pcie->pex_clk);
1139
1140 pcie->afi_clk = devm_clk_get(pcie->dev, "afi");
1141 if (IS_ERR(pcie->afi_clk))
1142 return PTR_ERR(pcie->afi_clk);
1143
1144 pcie->pll_e = devm_clk_get(pcie->dev, "pll_e");
1145 if (IS_ERR(pcie->pll_e))
1146 return PTR_ERR(pcie->pll_e);
1147
1148 if (soc->has_cml_clk) {
1149 pcie->cml_clk = devm_clk_get(pcie->dev, "cml");
1150 if (IS_ERR(pcie->cml_clk))
1151 return PTR_ERR(pcie->cml_clk);
1152 }
1153
1154 return 0;
1155 }
1156
1157 static int tegra_pcie_resets_get(struct tegra_pcie *pcie)
1158 {
1159 pcie->pex_rst = devm_reset_control_get(pcie->dev, "pex");
1160 if (IS_ERR(pcie->pex_rst))
1161 return PTR_ERR(pcie->pex_rst);
1162
1163 pcie->afi_rst = devm_reset_control_get(pcie->dev, "afi");
1164 if (IS_ERR(pcie->afi_rst))
1165 return PTR_ERR(pcie->afi_rst);
1166
1167 pcie->pcie_xrst = devm_reset_control_get(pcie->dev, "pcie_x");
1168 if (IS_ERR(pcie->pcie_xrst))
1169 return PTR_ERR(pcie->pcie_xrst);
1170
1171 return 0;
1172 }
1173
1174 static int tegra_pcie_phys_get_legacy(struct tegra_pcie *pcie)
1175 {
1176 int err;
1177
1178 pcie->phy = devm_phy_optional_get(pcie->dev, "pcie");
1179 if (IS_ERR(pcie->phy)) {
1180 err = PTR_ERR(pcie->phy);
1181 dev_err(pcie->dev, "failed to get PHY: %d\n", err);
1182 return err;
1183 }
1184
1185 err = phy_init(pcie->phy);
1186 if (err < 0) {
1187 dev_err(pcie->dev, "failed to initialize PHY: %d\n", err);
1188 return err;
1189 }
1190
1191 pcie->legacy_phy = true;
1192
1193 return 0;
1194 }
1195
1196 static struct phy *devm_of_phy_optional_get_index(struct device *dev,
1197 struct device_node *np,
1198 const char *consumer,
1199 unsigned int index)
1200 {
1201 struct phy *phy;
1202 char *name;
1203
1204 name = kasprintf(GFP_KERNEL, "%s-%u", consumer, index);
1205 if (!name)
1206 return ERR_PTR(-ENOMEM);
1207
1208 phy = devm_of_phy_get(dev, np, name);
1209 kfree(name);
1210
1211 if (IS_ERR(phy) && PTR_ERR(phy) == -ENODEV)
1212 phy = NULL;
1213
1214 return phy;
1215 }
1216
1217 static int tegra_pcie_port_get_phys(struct tegra_pcie_port *port)
1218 {
1219 struct device *dev = port->pcie->dev;
1220 struct phy *phy;
1221 unsigned int i;
1222 int err;
1223
1224 port->phys = devm_kcalloc(dev, sizeof(phy), port->lanes, GFP_KERNEL);
1225 if (!port->phys)
1226 return -ENOMEM;
1227
1228 for (i = 0; i < port->lanes; i++) {
1229 phy = devm_of_phy_optional_get_index(dev, port->np, "pcie", i);
1230 if (IS_ERR(phy)) {
1231 dev_err(dev, "failed to get PHY#%u: %ld\n", i,
1232 PTR_ERR(phy));
1233 return PTR_ERR(phy);
1234 }
1235
1236 err = phy_init(phy);
1237 if (err < 0) {
1238 dev_err(dev, "failed to initialize PHY#%u: %d\n", i,
1239 err);
1240 return err;
1241 }
1242
1243 port->phys[i] = phy;
1244 }
1245
1246 return 0;
1247 }
1248
1249 static int tegra_pcie_phys_get(struct tegra_pcie *pcie)
1250 {
1251 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1252 struct device_node *np = pcie->dev->of_node;
1253 struct tegra_pcie_port *port;
1254 int err;
1255
1256 if (!soc->has_gen2 || of_find_property(np, "phys", NULL) != NULL)
1257 return tegra_pcie_phys_get_legacy(pcie);
1258
1259 list_for_each_entry(port, &pcie->ports, list) {
1260 err = tegra_pcie_port_get_phys(port);
1261 if (err < 0)
1262 return err;
1263 }
1264
1265 return 0;
1266 }
1267
1268 static int tegra_pcie_get_resources(struct tegra_pcie *pcie)
1269 {
1270 struct platform_device *pdev = to_platform_device(pcie->dev);
1271 struct resource *pads, *afi, *res;
1272 int err;
1273
1274 err = tegra_pcie_clocks_get(pcie);
1275 if (err) {
1276 dev_err(&pdev->dev, "failed to get clocks: %d\n", err);
1277 return err;
1278 }
1279
1280 err = tegra_pcie_resets_get(pcie);
1281 if (err) {
1282 dev_err(&pdev->dev, "failed to get resets: %d\n", err);
1283 return err;
1284 }
1285
1286 err = tegra_pcie_phys_get(pcie);
1287 if (err < 0) {
1288 dev_err(&pdev->dev, "failed to get PHYs: %d\n", err);
1289 return err;
1290 }
1291
1292 err = tegra_pcie_power_on(pcie);
1293 if (err) {
1294 dev_err(&pdev->dev, "failed to power up: %d\n", err);
1295 return err;
1296 }
1297
1298 pads = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pads");
1299 pcie->pads = devm_ioremap_resource(&pdev->dev, pads);
1300 if (IS_ERR(pcie->pads)) {
1301 err = PTR_ERR(pcie->pads);
1302 goto poweroff;
1303 }
1304
1305 afi = platform_get_resource_byname(pdev, IORESOURCE_MEM, "afi");
1306 pcie->afi = devm_ioremap_resource(&pdev->dev, afi);
1307 if (IS_ERR(pcie->afi)) {
1308 err = PTR_ERR(pcie->afi);
1309 goto poweroff;
1310 }
1311
1312 /* request configuration space, but remap later, on demand */
1313 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cs");
1314 if (!res) {
1315 err = -EADDRNOTAVAIL;
1316 goto poweroff;
1317 }
1318
1319 pcie->cs = devm_request_mem_region(pcie->dev, res->start,
1320 resource_size(res), res->name);
1321 if (!pcie->cs) {
1322 err = -EADDRNOTAVAIL;
1323 goto poweroff;
1324 }
1325
1326 /* request interrupt */
1327 err = platform_get_irq_byname(pdev, "intr");
1328 if (err < 0) {
1329 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1330 goto poweroff;
1331 }
1332
1333 pcie->irq = err;
1334
1335 err = request_irq(pcie->irq, tegra_pcie_isr, IRQF_SHARED, "PCIE", pcie);
1336 if (err) {
1337 dev_err(&pdev->dev, "failed to register IRQ: %d\n", err);
1338 goto poweroff;
1339 }
1340
1341 return 0;
1342
1343 poweroff:
1344 tegra_pcie_power_off(pcie);
1345 return err;
1346 }
1347
1348 static int tegra_pcie_put_resources(struct tegra_pcie *pcie)
1349 {
1350 int err;
1351
1352 if (pcie->irq > 0)
1353 free_irq(pcie->irq, pcie);
1354
1355 tegra_pcie_power_off(pcie);
1356
1357 err = phy_exit(pcie->phy);
1358 if (err < 0)
1359 dev_err(pcie->dev, "failed to teardown PHY: %d\n", err);
1360
1361 return 0;
1362 }
1363
1364 static int tegra_msi_alloc(struct tegra_msi *chip)
1365 {
1366 int msi;
1367
1368 mutex_lock(&chip->lock);
1369
1370 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
1371 if (msi < INT_PCI_MSI_NR)
1372 set_bit(msi, chip->used);
1373 else
1374 msi = -ENOSPC;
1375
1376 mutex_unlock(&chip->lock);
1377
1378 return msi;
1379 }
1380
1381 static void tegra_msi_free(struct tegra_msi *chip, unsigned long irq)
1382 {
1383 struct device *dev = chip->chip.dev;
1384
1385 mutex_lock(&chip->lock);
1386
1387 if (!test_bit(irq, chip->used))
1388 dev_err(dev, "trying to free unused MSI#%lu\n", irq);
1389 else
1390 clear_bit(irq, chip->used);
1391
1392 mutex_unlock(&chip->lock);
1393 }
1394
1395 static irqreturn_t tegra_pcie_msi_irq(int irq, void *data)
1396 {
1397 struct tegra_pcie *pcie = data;
1398 struct tegra_msi *msi = &pcie->msi;
1399 unsigned int i, processed = 0;
1400
1401 for (i = 0; i < 8; i++) {
1402 unsigned long reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1403
1404 while (reg) {
1405 unsigned int offset = find_first_bit(&reg, 32);
1406 unsigned int index = i * 32 + offset;
1407 unsigned int irq;
1408
1409 /* clear the interrupt */
1410 afi_writel(pcie, 1 << offset, AFI_MSI_VEC0 + i * 4);
1411
1412 irq = irq_find_mapping(msi->domain, index);
1413 if (irq) {
1414 if (test_bit(index, msi->used))
1415 generic_handle_irq(irq);
1416 else
1417 dev_info(pcie->dev, "unhandled MSI\n");
1418 } else {
1419 /*
1420 * that's weird who triggered this?
1421 * just clear it
1422 */
1423 dev_info(pcie->dev, "unexpected MSI\n");
1424 }
1425
1426 /* see if there's any more pending in this vector */
1427 reg = afi_readl(pcie, AFI_MSI_VEC0 + i * 4);
1428
1429 processed++;
1430 }
1431 }
1432
1433 return processed > 0 ? IRQ_HANDLED : IRQ_NONE;
1434 }
1435
1436 static int tegra_msi_setup_irq(struct msi_controller *chip,
1437 struct pci_dev *pdev, struct msi_desc *desc)
1438 {
1439 struct tegra_msi *msi = to_tegra_msi(chip);
1440 struct msi_msg msg;
1441 unsigned int irq;
1442 int hwirq;
1443
1444 hwirq = tegra_msi_alloc(msi);
1445 if (hwirq < 0)
1446 return hwirq;
1447
1448 irq = irq_create_mapping(msi->domain, hwirq);
1449 if (!irq) {
1450 tegra_msi_free(msi, hwirq);
1451 return -EINVAL;
1452 }
1453
1454 irq_set_msi_desc(irq, desc);
1455
1456 msg.address_lo = virt_to_phys((void *)msi->pages);
1457 /* 32 bit address only */
1458 msg.address_hi = 0;
1459 msg.data = hwirq;
1460
1461 pci_write_msi_msg(irq, &msg);
1462
1463 return 0;
1464 }
1465
1466 static void tegra_msi_teardown_irq(struct msi_controller *chip,
1467 unsigned int irq)
1468 {
1469 struct tegra_msi *msi = to_tegra_msi(chip);
1470 struct irq_data *d = irq_get_irq_data(irq);
1471 irq_hw_number_t hwirq = irqd_to_hwirq(d);
1472
1473 irq_dispose_mapping(irq);
1474 tegra_msi_free(msi, hwirq);
1475 }
1476
1477 static struct irq_chip tegra_msi_irq_chip = {
1478 .name = "Tegra PCIe MSI",
1479 .irq_enable = pci_msi_unmask_irq,
1480 .irq_disable = pci_msi_mask_irq,
1481 .irq_mask = pci_msi_mask_irq,
1482 .irq_unmask = pci_msi_unmask_irq,
1483 };
1484
1485 static int tegra_msi_map(struct irq_domain *domain, unsigned int irq,
1486 irq_hw_number_t hwirq)
1487 {
1488 irq_set_chip_and_handler(irq, &tegra_msi_irq_chip, handle_simple_irq);
1489 irq_set_chip_data(irq, domain->host_data);
1490
1491 tegra_cpuidle_pcie_irqs_in_use();
1492
1493 return 0;
1494 }
1495
1496 static const struct irq_domain_ops msi_domain_ops = {
1497 .map = tegra_msi_map,
1498 };
1499
1500 static int tegra_pcie_enable_msi(struct tegra_pcie *pcie)
1501 {
1502 struct platform_device *pdev = to_platform_device(pcie->dev);
1503 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1504 struct tegra_msi *msi = &pcie->msi;
1505 unsigned long base;
1506 int err;
1507 u32 reg;
1508
1509 mutex_init(&msi->lock);
1510
1511 msi->chip.dev = pcie->dev;
1512 msi->chip.setup_irq = tegra_msi_setup_irq;
1513 msi->chip.teardown_irq = tegra_msi_teardown_irq;
1514
1515 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
1516 &msi_domain_ops, &msi->chip);
1517 if (!msi->domain) {
1518 dev_err(&pdev->dev, "failed to create IRQ domain\n");
1519 return -ENOMEM;
1520 }
1521
1522 err = platform_get_irq_byname(pdev, "msi");
1523 if (err < 0) {
1524 dev_err(&pdev->dev, "failed to get IRQ: %d\n", err);
1525 goto err;
1526 }
1527
1528 msi->irq = err;
1529
1530 err = request_irq(msi->irq, tegra_pcie_msi_irq, IRQF_NO_THREAD,
1531 tegra_msi_irq_chip.name, pcie);
1532 if (err < 0) {
1533 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1534 goto err;
1535 }
1536
1537 /* setup AFI/FPCI range */
1538 msi->pages = __get_free_pages(GFP_KERNEL, 0);
1539 base = virt_to_phys((void *)msi->pages);
1540
1541 afi_writel(pcie, base >> soc->msi_base_shift, AFI_MSI_FPCI_BAR_ST);
1542 afi_writel(pcie, base, AFI_MSI_AXI_BAR_ST);
1543 /* this register is in 4K increments */
1544 afi_writel(pcie, 1, AFI_MSI_BAR_SZ);
1545
1546 /* enable all MSI vectors */
1547 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC0);
1548 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC1);
1549 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC2);
1550 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC3);
1551 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC4);
1552 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC5);
1553 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC6);
1554 afi_writel(pcie, 0xffffffff, AFI_MSI_EN_VEC7);
1555
1556 /* and unmask the MSI interrupt */
1557 reg = afi_readl(pcie, AFI_INTR_MASK);
1558 reg |= AFI_INTR_MASK_MSI_MASK;
1559 afi_writel(pcie, reg, AFI_INTR_MASK);
1560
1561 return 0;
1562
1563 err:
1564 irq_domain_remove(msi->domain);
1565 return err;
1566 }
1567
1568 static int tegra_pcie_disable_msi(struct tegra_pcie *pcie)
1569 {
1570 struct tegra_msi *msi = &pcie->msi;
1571 unsigned int i, irq;
1572 u32 value;
1573
1574 /* mask the MSI interrupt */
1575 value = afi_readl(pcie, AFI_INTR_MASK);
1576 value &= ~AFI_INTR_MASK_MSI_MASK;
1577 afi_writel(pcie, value, AFI_INTR_MASK);
1578
1579 /* disable all MSI vectors */
1580 afi_writel(pcie, 0, AFI_MSI_EN_VEC0);
1581 afi_writel(pcie, 0, AFI_MSI_EN_VEC1);
1582 afi_writel(pcie, 0, AFI_MSI_EN_VEC2);
1583 afi_writel(pcie, 0, AFI_MSI_EN_VEC3);
1584 afi_writel(pcie, 0, AFI_MSI_EN_VEC4);
1585 afi_writel(pcie, 0, AFI_MSI_EN_VEC5);
1586 afi_writel(pcie, 0, AFI_MSI_EN_VEC6);
1587 afi_writel(pcie, 0, AFI_MSI_EN_VEC7);
1588
1589 free_pages(msi->pages, 0);
1590
1591 if (msi->irq > 0)
1592 free_irq(msi->irq, pcie);
1593
1594 for (i = 0; i < INT_PCI_MSI_NR; i++) {
1595 irq = irq_find_mapping(msi->domain, i);
1596 if (irq > 0)
1597 irq_dispose_mapping(irq);
1598 }
1599
1600 irq_domain_remove(msi->domain);
1601
1602 return 0;
1603 }
1604
1605 static int tegra_pcie_get_xbar_config(struct tegra_pcie *pcie, u32 lanes,
1606 u32 *xbar)
1607 {
1608 struct device_node *np = pcie->dev->of_node;
1609
1610 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1611 switch (lanes) {
1612 case 0x0000104:
1613 dev_info(pcie->dev, "4x1, 1x1 configuration\n");
1614 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X4_X1;
1615 return 0;
1616
1617 case 0x0000102:
1618 dev_info(pcie->dev, "2x1, 1x1 configuration\n");
1619 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_X2_X1;
1620 return 0;
1621 }
1622 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1623 switch (lanes) {
1624 case 0x00000204:
1625 dev_info(pcie->dev, "4x1, 2x1 configuration\n");
1626 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_420;
1627 return 0;
1628
1629 case 0x00020202:
1630 dev_info(pcie->dev, "2x3 configuration\n");
1631 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_222;
1632 return 0;
1633
1634 case 0x00010104:
1635 dev_info(pcie->dev, "4x1, 1x2 configuration\n");
1636 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_411;
1637 return 0;
1638 }
1639 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1640 switch (lanes) {
1641 case 0x00000004:
1642 dev_info(pcie->dev, "single-mode configuration\n");
1643 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_SINGLE;
1644 return 0;
1645
1646 case 0x00000202:
1647 dev_info(pcie->dev, "dual-mode configuration\n");
1648 *xbar = AFI_PCIE_CONFIG_SM2TMS0_XBAR_CONFIG_DUAL;
1649 return 0;
1650 }
1651 }
1652
1653 return -EINVAL;
1654 }
1655
1656 /*
1657 * Check whether a given set of supplies is available in a device tree node.
1658 * This is used to check whether the new or the legacy device tree bindings
1659 * should be used.
1660 */
1661 static bool of_regulator_bulk_available(struct device_node *np,
1662 struct regulator_bulk_data *supplies,
1663 unsigned int num_supplies)
1664 {
1665 char property[32];
1666 unsigned int i;
1667
1668 for (i = 0; i < num_supplies; i++) {
1669 snprintf(property, 32, "%s-supply", supplies[i].supply);
1670
1671 if (of_find_property(np, property, NULL) == NULL)
1672 return false;
1673 }
1674
1675 return true;
1676 }
1677
1678 /*
1679 * Old versions of the device tree binding for this device used a set of power
1680 * supplies that didn't match the hardware inputs. This happened to work for a
1681 * number of cases but is not future proof. However to preserve backwards-
1682 * compatibility with old device trees, this function will try to use the old
1683 * set of supplies.
1684 */
1685 static int tegra_pcie_get_legacy_regulators(struct tegra_pcie *pcie)
1686 {
1687 struct device_node *np = pcie->dev->of_node;
1688
1689 if (of_device_is_compatible(np, "nvidia,tegra30-pcie"))
1690 pcie->num_supplies = 3;
1691 else if (of_device_is_compatible(np, "nvidia,tegra20-pcie"))
1692 pcie->num_supplies = 2;
1693
1694 if (pcie->num_supplies == 0) {
1695 dev_err(pcie->dev, "device %s not supported in legacy mode\n",
1696 np->full_name);
1697 return -ENODEV;
1698 }
1699
1700 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1701 sizeof(*pcie->supplies),
1702 GFP_KERNEL);
1703 if (!pcie->supplies)
1704 return -ENOMEM;
1705
1706 pcie->supplies[0].supply = "pex-clk";
1707 pcie->supplies[1].supply = "vdd";
1708
1709 if (pcie->num_supplies > 2)
1710 pcie->supplies[2].supply = "avdd";
1711
1712 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
1713 pcie->supplies);
1714 }
1715
1716 /*
1717 * Obtains the list of regulators required for a particular generation of the
1718 * IP block.
1719 *
1720 * This would've been nice to do simply by providing static tables for use
1721 * with the regulator_bulk_*() API, but unfortunately Tegra30 is a bit quirky
1722 * in that it has two pairs or AVDD_PEX and VDD_PEX supplies (PEXA and PEXB)
1723 * and either seems to be optional depending on which ports are being used.
1724 */
1725 static int tegra_pcie_get_regulators(struct tegra_pcie *pcie, u32 lane_mask)
1726 {
1727 struct device_node *np = pcie->dev->of_node;
1728 unsigned int i = 0;
1729
1730 if (of_device_is_compatible(np, "nvidia,tegra124-pcie")) {
1731 pcie->num_supplies = 7;
1732
1733 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1734 sizeof(*pcie->supplies),
1735 GFP_KERNEL);
1736 if (!pcie->supplies)
1737 return -ENOMEM;
1738
1739 pcie->supplies[i++].supply = "avddio-pex";
1740 pcie->supplies[i++].supply = "dvddio-pex";
1741 pcie->supplies[i++].supply = "avdd-pex-pll";
1742 pcie->supplies[i++].supply = "hvdd-pex";
1743 pcie->supplies[i++].supply = "hvdd-pex-pll-e";
1744 pcie->supplies[i++].supply = "vddio-pex-ctl";
1745 pcie->supplies[i++].supply = "avdd-pll-erefe";
1746 } else if (of_device_is_compatible(np, "nvidia,tegra30-pcie")) {
1747 bool need_pexa = false, need_pexb = false;
1748
1749 /* VDD_PEXA and AVDD_PEXA supply lanes 0 to 3 */
1750 if (lane_mask & 0x0f)
1751 need_pexa = true;
1752
1753 /* VDD_PEXB and AVDD_PEXB supply lanes 4 to 5 */
1754 if (lane_mask & 0x30)
1755 need_pexb = true;
1756
1757 pcie->num_supplies = 4 + (need_pexa ? 2 : 0) +
1758 (need_pexb ? 2 : 0);
1759
1760 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1761 sizeof(*pcie->supplies),
1762 GFP_KERNEL);
1763 if (!pcie->supplies)
1764 return -ENOMEM;
1765
1766 pcie->supplies[i++].supply = "avdd-pex-pll";
1767 pcie->supplies[i++].supply = "hvdd-pex";
1768 pcie->supplies[i++].supply = "vddio-pex-ctl";
1769 pcie->supplies[i++].supply = "avdd-plle";
1770
1771 if (need_pexa) {
1772 pcie->supplies[i++].supply = "avdd-pexa";
1773 pcie->supplies[i++].supply = "vdd-pexa";
1774 }
1775
1776 if (need_pexb) {
1777 pcie->supplies[i++].supply = "avdd-pexb";
1778 pcie->supplies[i++].supply = "vdd-pexb";
1779 }
1780 } else if (of_device_is_compatible(np, "nvidia,tegra20-pcie")) {
1781 pcie->num_supplies = 5;
1782
1783 pcie->supplies = devm_kcalloc(pcie->dev, pcie->num_supplies,
1784 sizeof(*pcie->supplies),
1785 GFP_KERNEL);
1786 if (!pcie->supplies)
1787 return -ENOMEM;
1788
1789 pcie->supplies[0].supply = "avdd-pex";
1790 pcie->supplies[1].supply = "vdd-pex";
1791 pcie->supplies[2].supply = "avdd-pex-pll";
1792 pcie->supplies[3].supply = "avdd-plle";
1793 pcie->supplies[4].supply = "vddio-pex-clk";
1794 }
1795
1796 if (of_regulator_bulk_available(pcie->dev->of_node, pcie->supplies,
1797 pcie->num_supplies))
1798 return devm_regulator_bulk_get(pcie->dev, pcie->num_supplies,
1799 pcie->supplies);
1800
1801 /*
1802 * If not all regulators are available for this new scheme, assume
1803 * that the device tree complies with an older version of the device
1804 * tree binding.
1805 */
1806 dev_info(pcie->dev, "using legacy DT binding for power supplies\n");
1807
1808 devm_kfree(pcie->dev, pcie->supplies);
1809 pcie->num_supplies = 0;
1810
1811 return tegra_pcie_get_legacy_regulators(pcie);
1812 }
1813
1814 static int tegra_pcie_parse_dt(struct tegra_pcie *pcie)
1815 {
1816 const struct tegra_pcie_soc_data *soc = pcie->soc_data;
1817 struct device_node *np = pcie->dev->of_node, *port;
1818 struct of_pci_range_parser parser;
1819 struct of_pci_range range;
1820 u32 lanes = 0, mask = 0;
1821 unsigned int lane = 0;
1822 struct resource res;
1823 int err;
1824
1825 memset(&pcie->all, 0, sizeof(pcie->all));
1826 pcie->all.flags = IORESOURCE_MEM;
1827 pcie->all.name = np->full_name;
1828 pcie->all.start = ~0;
1829 pcie->all.end = 0;
1830
1831 if (of_pci_range_parser_init(&parser, np)) {
1832 dev_err(pcie->dev, "missing \"ranges\" property\n");
1833 return -EINVAL;
1834 }
1835
1836 for_each_of_pci_range(&parser, &range) {
1837 err = of_pci_range_to_resource(&range, np, &res);
1838 if (err < 0)
1839 return err;
1840
1841 switch (res.flags & IORESOURCE_TYPE_BITS) {
1842 case IORESOURCE_IO:
1843 /* Track the bus -> CPU I/O mapping offset. */
1844 pcie->offset.io = res.start - range.pci_addr;
1845
1846 memcpy(&pcie->pio, &res, sizeof(res));
1847 pcie->pio.name = np->full_name;
1848
1849 /*
1850 * The Tegra PCIe host bridge uses this to program the
1851 * mapping of the I/O space to the physical address,
1852 * so we override the .start and .end fields here that
1853 * of_pci_range_to_resource() converted to I/O space.
1854 * We also set the IORESOURCE_MEM type to clarify that
1855 * the resource is in the physical memory space.
1856 */
1857 pcie->io.start = range.cpu_addr;
1858 pcie->io.end = range.cpu_addr + range.size - 1;
1859 pcie->io.flags = IORESOURCE_MEM;
1860 pcie->io.name = "I/O";
1861
1862 memcpy(&res, &pcie->io, sizeof(res));
1863 break;
1864
1865 case IORESOURCE_MEM:
1866 /*
1867 * Track the bus -> CPU memory mapping offset. This
1868 * assumes that the prefetchable and non-prefetchable
1869 * regions will be the last of type IORESOURCE_MEM in
1870 * the ranges property.
1871 * */
1872 pcie->offset.mem = res.start - range.pci_addr;
1873
1874 if (res.flags & IORESOURCE_PREFETCH) {
1875 memcpy(&pcie->prefetch, &res, sizeof(res));
1876 pcie->prefetch.name = "prefetchable";
1877 } else {
1878 memcpy(&pcie->mem, &res, sizeof(res));
1879 pcie->mem.name = "non-prefetchable";
1880 }
1881 break;
1882 }
1883
1884 if (res.start <= pcie->all.start)
1885 pcie->all.start = res.start;
1886
1887 if (res.end >= pcie->all.end)
1888 pcie->all.end = res.end;
1889 }
1890
1891 err = devm_request_resource(pcie->dev, &iomem_resource, &pcie->all);
1892 if (err < 0)
1893 return err;
1894
1895 err = of_pci_parse_bus_range(np, &pcie->busn);
1896 if (err < 0) {
1897 dev_err(pcie->dev, "failed to parse ranges property: %d\n",
1898 err);
1899 pcie->busn.name = np->name;
1900 pcie->busn.start = 0;
1901 pcie->busn.end = 0xff;
1902 pcie->busn.flags = IORESOURCE_BUS;
1903 }
1904
1905 /* parse root ports */
1906 for_each_child_of_node(np, port) {
1907 struct tegra_pcie_port *rp;
1908 unsigned int index;
1909 u32 value;
1910
1911 err = of_pci_get_devfn(port);
1912 if (err < 0) {
1913 dev_err(pcie->dev, "failed to parse address: %d\n",
1914 err);
1915 return err;
1916 }
1917
1918 index = PCI_SLOT(err);
1919
1920 if (index < 1 || index > soc->num_ports) {
1921 dev_err(pcie->dev, "invalid port number: %d\n", index);
1922 return -EINVAL;
1923 }
1924
1925 index--;
1926
1927 err = of_property_read_u32(port, "nvidia,num-lanes", &value);
1928 if (err < 0) {
1929 dev_err(pcie->dev, "failed to parse # of lanes: %d\n",
1930 err);
1931 return err;
1932 }
1933
1934 if (value > 16) {
1935 dev_err(pcie->dev, "invalid # of lanes: %u\n", value);
1936 return -EINVAL;
1937 }
1938
1939 lanes |= value << (index << 3);
1940
1941 if (!of_device_is_available(port)) {
1942 lane += value;
1943 continue;
1944 }
1945
1946 mask |= ((1 << value) - 1) << lane;
1947 lane += value;
1948
1949 rp = devm_kzalloc(pcie->dev, sizeof(*rp), GFP_KERNEL);
1950 if (!rp)
1951 return -ENOMEM;
1952
1953 err = of_address_to_resource(port, 0, &rp->regs);
1954 if (err < 0) {
1955 dev_err(pcie->dev, "failed to parse address: %d\n",
1956 err);
1957 return err;
1958 }
1959
1960 INIT_LIST_HEAD(&rp->list);
1961 rp->index = index;
1962 rp->lanes = value;
1963 rp->pcie = pcie;
1964 rp->np = port;
1965
1966 rp->base = devm_ioremap_resource(pcie->dev, &rp->regs);
1967 if (IS_ERR(rp->base))
1968 return PTR_ERR(rp->base);
1969
1970 list_add_tail(&rp->list, &pcie->ports);
1971 }
1972
1973 err = tegra_pcie_get_xbar_config(pcie, lanes, &pcie->xbar_config);
1974 if (err < 0) {
1975 dev_err(pcie->dev, "invalid lane configuration\n");
1976 return err;
1977 }
1978
1979 err = tegra_pcie_get_regulators(pcie, mask);
1980 if (err < 0)
1981 return err;
1982
1983 return 0;
1984 }
1985
1986 /*
1987 * FIXME: If there are no PCIe cards attached, then calling this function
1988 * can result in the increase of the bootup time as there are big timeout
1989 * loops.
1990 */
1991 #define TEGRA_PCIE_LINKUP_TIMEOUT 200 /* up to 1.2 seconds */
1992 static bool tegra_pcie_port_check_link(struct tegra_pcie_port *port)
1993 {
1994 unsigned int retries = 3;
1995 unsigned long value;
1996
1997 /* override presence detection */
1998 value = readl(port->base + RP_PRIV_MISC);
1999 value &= ~RP_PRIV_MISC_PRSNT_MAP_EP_ABSNT;
2000 value |= RP_PRIV_MISC_PRSNT_MAP_EP_PRSNT;
2001 writel(value, port->base + RP_PRIV_MISC);
2002
2003 do {
2004 unsigned int timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
2005
2006 do {
2007 value = readl(port->base + RP_VEND_XP);
2008
2009 if (value & RP_VEND_XP_DL_UP)
2010 break;
2011
2012 usleep_range(1000, 2000);
2013 } while (--timeout);
2014
2015 if (!timeout) {
2016 dev_err(port->pcie->dev, "link %u down, retrying\n",
2017 port->index);
2018 goto retry;
2019 }
2020
2021 timeout = TEGRA_PCIE_LINKUP_TIMEOUT;
2022
2023 do {
2024 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2025
2026 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2027 return true;
2028
2029 usleep_range(1000, 2000);
2030 } while (--timeout);
2031
2032 retry:
2033 tegra_pcie_port_reset(port);
2034 } while (--retries);
2035
2036 return false;
2037 }
2038
2039 static int tegra_pcie_enable(struct tegra_pcie *pcie)
2040 {
2041 struct tegra_pcie_port *port, *tmp;
2042 struct hw_pci hw;
2043
2044 list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
2045 dev_info(pcie->dev, "probing port %u, using %u lanes\n",
2046 port->index, port->lanes);
2047
2048 tegra_pcie_port_enable(port);
2049
2050 if (tegra_pcie_port_check_link(port))
2051 continue;
2052
2053 dev_info(pcie->dev, "link %u down, ignoring\n", port->index);
2054
2055 tegra_pcie_port_disable(port);
2056 tegra_pcie_port_free(port);
2057 }
2058
2059 memset(&hw, 0, sizeof(hw));
2060
2061 #ifdef CONFIG_PCI_MSI
2062 hw.msi_ctrl = &pcie->msi.chip;
2063 #endif
2064
2065 hw.nr_controllers = 1;
2066 hw.private_data = (void **)&pcie;
2067 hw.setup = tegra_pcie_setup;
2068 hw.map_irq = tegra_pcie_map_irq;
2069 hw.ops = &tegra_pcie_ops;
2070
2071 pci_common_init_dev(pcie->dev, &hw);
2072
2073 return 0;
2074 }
2075
2076 static const struct tegra_pcie_soc_data tegra20_pcie_data = {
2077 .num_ports = 2,
2078 .msi_base_shift = 0,
2079 .pads_pll_ctl = PADS_PLL_CTL_TEGRA20,
2080 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_DIV10,
2081 .has_pex_clkreq_en = false,
2082 .has_pex_bias_ctrl = false,
2083 .has_intr_prsnt_sense = false,
2084 .has_cml_clk = false,
2085 .has_gen2 = false,
2086 };
2087
2088 static const struct tegra_pcie_soc_data tegra30_pcie_data = {
2089 .num_ports = 3,
2090 .msi_base_shift = 8,
2091 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2092 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2093 .has_pex_clkreq_en = true,
2094 .has_pex_bias_ctrl = true,
2095 .has_intr_prsnt_sense = true,
2096 .has_cml_clk = true,
2097 .has_gen2 = false,
2098 };
2099
2100 static const struct tegra_pcie_soc_data tegra124_pcie_data = {
2101 .num_ports = 2,
2102 .msi_base_shift = 8,
2103 .pads_pll_ctl = PADS_PLL_CTL_TEGRA30,
2104 .tx_ref_sel = PADS_PLL_CTL_TXCLKREF_BUF_EN,
2105 .has_pex_clkreq_en = true,
2106 .has_pex_bias_ctrl = true,
2107 .has_intr_prsnt_sense = true,
2108 .has_cml_clk = true,
2109 .has_gen2 = true,
2110 };
2111
2112 static const struct of_device_id tegra_pcie_of_match[] = {
2113 { .compatible = "nvidia,tegra124-pcie", .data = &tegra124_pcie_data },
2114 { .compatible = "nvidia,tegra30-pcie", .data = &tegra30_pcie_data },
2115 { .compatible = "nvidia,tegra20-pcie", .data = &tegra20_pcie_data },
2116 { },
2117 };
2118 MODULE_DEVICE_TABLE(of, tegra_pcie_of_match);
2119
2120 static void *tegra_pcie_ports_seq_start(struct seq_file *s, loff_t *pos)
2121 {
2122 struct tegra_pcie *pcie = s->private;
2123
2124 if (list_empty(&pcie->ports))
2125 return NULL;
2126
2127 seq_printf(s, "Index Status\n");
2128
2129 return seq_list_start(&pcie->ports, *pos);
2130 }
2131
2132 static void *tegra_pcie_ports_seq_next(struct seq_file *s, void *v, loff_t *pos)
2133 {
2134 struct tegra_pcie *pcie = s->private;
2135
2136 return seq_list_next(v, &pcie->ports, pos);
2137 }
2138
2139 static void tegra_pcie_ports_seq_stop(struct seq_file *s, void *v)
2140 {
2141 }
2142
2143 static int tegra_pcie_ports_seq_show(struct seq_file *s, void *v)
2144 {
2145 bool up = false, active = false;
2146 struct tegra_pcie_port *port;
2147 unsigned int value;
2148
2149 port = list_entry(v, struct tegra_pcie_port, list);
2150
2151 value = readl(port->base + RP_VEND_XP);
2152
2153 if (value & RP_VEND_XP_DL_UP)
2154 up = true;
2155
2156 value = readl(port->base + RP_LINK_CONTROL_STATUS);
2157
2158 if (value & RP_LINK_CONTROL_STATUS_DL_LINK_ACTIVE)
2159 active = true;
2160
2161 seq_printf(s, "%2u ", port->index);
2162
2163 if (up)
2164 seq_printf(s, "up");
2165
2166 if (active) {
2167 if (up)
2168 seq_printf(s, ", ");
2169
2170 seq_printf(s, "active");
2171 }
2172
2173 seq_printf(s, "\n");
2174 return 0;
2175 }
2176
2177 static const struct seq_operations tegra_pcie_ports_seq_ops = {
2178 .start = tegra_pcie_ports_seq_start,
2179 .next = tegra_pcie_ports_seq_next,
2180 .stop = tegra_pcie_ports_seq_stop,
2181 .show = tegra_pcie_ports_seq_show,
2182 };
2183
2184 static int tegra_pcie_ports_open(struct inode *inode, struct file *file)
2185 {
2186 struct tegra_pcie *pcie = inode->i_private;
2187 struct seq_file *s;
2188 int err;
2189
2190 err = seq_open(file, &tegra_pcie_ports_seq_ops);
2191 if (err)
2192 return err;
2193
2194 s = file->private_data;
2195 s->private = pcie;
2196
2197 return 0;
2198 }
2199
2200 static const struct file_operations tegra_pcie_ports_ops = {
2201 .owner = THIS_MODULE,
2202 .open = tegra_pcie_ports_open,
2203 .read = seq_read,
2204 .llseek = seq_lseek,
2205 .release = seq_release,
2206 };
2207
2208 static int tegra_pcie_debugfs_init(struct tegra_pcie *pcie)
2209 {
2210 struct dentry *file;
2211
2212 pcie->debugfs = debugfs_create_dir("pcie", NULL);
2213 if (!pcie->debugfs)
2214 return -ENOMEM;
2215
2216 file = debugfs_create_file("ports", S_IFREG | S_IRUGO, pcie->debugfs,
2217 pcie, &tegra_pcie_ports_ops);
2218 if (!file)
2219 goto remove;
2220
2221 return 0;
2222
2223 remove:
2224 debugfs_remove_recursive(pcie->debugfs);
2225 pcie->debugfs = NULL;
2226 return -ENOMEM;
2227 }
2228
2229 static int tegra_pcie_probe(struct platform_device *pdev)
2230 {
2231 const struct of_device_id *match;
2232 struct tegra_pcie *pcie;
2233 int err;
2234
2235 match = of_match_device(tegra_pcie_of_match, &pdev->dev);
2236 if (!match)
2237 return -ENODEV;
2238
2239 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
2240 if (!pcie)
2241 return -ENOMEM;
2242
2243 INIT_LIST_HEAD(&pcie->buses);
2244 INIT_LIST_HEAD(&pcie->ports);
2245 pcie->soc_data = match->data;
2246 pcie->dev = &pdev->dev;
2247
2248 err = tegra_pcie_parse_dt(pcie);
2249 if (err < 0)
2250 return err;
2251
2252 pcibios_min_mem = 0;
2253
2254 err = tegra_pcie_get_resources(pcie);
2255 if (err < 0) {
2256 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
2257 return err;
2258 }
2259
2260 err = tegra_pcie_enable_controller(pcie);
2261 if (err)
2262 goto put_resources;
2263
2264 /* setup the AFI address translations */
2265 tegra_pcie_setup_translations(pcie);
2266
2267 if (IS_ENABLED(CONFIG_PCI_MSI)) {
2268 err = tegra_pcie_enable_msi(pcie);
2269 if (err < 0) {
2270 dev_err(&pdev->dev,
2271 "failed to enable MSI support: %d\n",
2272 err);
2273 goto put_resources;
2274 }
2275 }
2276
2277 err = tegra_pcie_enable(pcie);
2278 if (err < 0) {
2279 dev_err(&pdev->dev, "failed to enable PCIe ports: %d\n", err);
2280 goto disable_msi;
2281 }
2282
2283 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
2284 err = tegra_pcie_debugfs_init(pcie);
2285 if (err < 0)
2286 dev_err(&pdev->dev, "failed to setup debugfs: %d\n",
2287 err);
2288 }
2289
2290 platform_set_drvdata(pdev, pcie);
2291 return 0;
2292
2293 disable_msi:
2294 if (IS_ENABLED(CONFIG_PCI_MSI))
2295 tegra_pcie_disable_msi(pcie);
2296 put_resources:
2297 tegra_pcie_put_resources(pcie);
2298 return err;
2299 }
2300
2301 static struct platform_driver tegra_pcie_driver = {
2302 .driver = {
2303 .name = "tegra-pcie",
2304 .of_match_table = tegra_pcie_of_match,
2305 .suppress_bind_attrs = true,
2306 },
2307 .probe = tegra_pcie_probe,
2308 };
2309 module_platform_driver(tegra_pcie_driver);
2310
2311 MODULE_AUTHOR("Thierry Reding <treding@nvidia.com>");
2312 MODULE_DESCRIPTION("NVIDIA Tegra PCIe driver");
2313 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support