drivers/pci/host/pci-thunder-pem.c

   1 /*
   2  * This program is free software; you can redistribute it and/or modify
   3  * it under the terms of the GNU General Public License version 2 as
   4  * published by the Free Software Foundation.
   5  *
   6  * This program is distributed in the hope that it will be useful,
   7  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   8  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
   9  * GNU General Public License for more details.
  10  *
  11  * You should have received a copy of the GNU General Public License
  12  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  13  *
  14  * Copyright (C) 2015 - 2016 Cavium, Inc.
  15  */
  16
  17 #include <linux/kernel.h>
  18 #include <linux/module.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_pci.h>
  21 #include <linux/platform_device.h>
  22
  23 #include "../ecam.h"
  24
  25 #define PEM_CFG_WR 0x28
  26 #define PEM_CFG_RD 0x30
  27
  28 struct thunder_pem_pci {
  29         u32             ea_entry[3];
  30         void __iomem    *pem_reg_base;
  31 };
  32
  33 static int thunder_pem_bridge_read(struct pci_bus *bus, unsigned int devfn,
  34                                    int where, int size, u32 *val)
  35 {
  36         u64 read_val;
  37         struct pci_config_window *cfg = bus->sysdata;
  38         struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
  39
  40         if (devfn != 0 || where >= 2048) {
  41                 *val = ~0;
  42                 return PCIBIOS_DEVICE_NOT_FOUND;
  43         }
  44
  45         /*
  46          * 32-bit accesses only.  Write the address to the low order
  47          * bits of PEM_CFG_RD, then trigger the read by reading back.
  48          * The config data lands in the upper 32-bits of PEM_CFG_RD.
  49          */
  50         read_val = where & ~3ull;
  51         writeq(read_val, pem_pci->pem_reg_base + PEM_CFG_RD);
  52         read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
  53         read_val >>= 32;
  54
  55         /*
  56          * The config space contains some garbage, fix it up.  Also
  57          * synthesize an EA capability for the BAR used by MSI-X.
  58          */
  59         switch (where & ~3) {
  60         case 0x40:
  61                 read_val &= 0xffff00ff;
  62                 read_val |= 0x00007000; /* Skip MSI CAP */
  63                 break;
  64         case 0x70: /* Express Cap */
  65                 /* PME interrupt on vector 2*/
  66                 read_val |= (2u << 25);
  67                 break;
  68         case 0xb0: /* MSI-X Cap */
  69                 /* TableSize=4, Next Cap is EA */
  70                 read_val &= 0xc00000ff;
  71                 read_val |= 0x0003bc00;
  72                 break;
  73         case 0xb4:
  74                 /* Table offset=0, BIR=0 */
  75                 read_val = 0x00000000;
  76                 break;
  77         case 0xb8:
  78                 /* BPA offset=0xf0000, BIR=0 */
  79                 read_val = 0x000f0000;
  80                 break;
  81         case 0xbc:
  82                 /* EA, 1 entry, no next Cap */
  83                 read_val = 0x00010014;
  84                 break;
  85         case 0xc0:
  86                 /* DW2 for type-1 */
  87                 read_val = 0x00000000;
  88                 break;
  89         case 0xc4:
  90                 /* Entry BEI=0, PP=0x00, SP=0xff, ES=3 */
  91                 read_val = 0x80ff0003;
  92                 break;
  93         case 0xc8:
  94                 read_val = pem_pci->ea_entry[0];
  95                 break;
  96         case 0xcc:
  97                 read_val = pem_pci->ea_entry[1];
  98                 break;
  99         case 0xd0:
 100                 read_val = pem_pci->ea_entry[2];
 101                 break;
 102         default:
 103                 break;
 104         }
 105         read_val >>= (8 * (where & 3));
 106         switch (size) {
 107         case 1:
 108                 read_val &= 0xff;
 109                 break;
 110         case 2:
 111                 read_val &= 0xffff;
 112                 break;
 113         default:
 114                 break;
 115         }
 116         *val = read_val;
 117         return PCIBIOS_SUCCESSFUL;
 118 }
 119
 120 static int thunder_pem_config_read(struct pci_bus *bus, unsigned int devfn,
 121                                    int where, int size, u32 *val)
 122 {
 123         struct pci_config_window *cfg = bus->sysdata;
 124
 125         if (bus->number < cfg->busr.start ||
 126             bus->number > cfg->busr.end)
 127                 return PCIBIOS_DEVICE_NOT_FOUND;
 128
 129         /*
 130          * The first device on the bus is the PEM PCIe bridge.
 131          * Special case its config access.
 132          */
 133         if (bus->number == cfg->busr.start)
 134                 return thunder_pem_bridge_read(bus, devfn, where, size, val);
 135
 136         return pci_generic_config_read(bus, devfn, where, size, val);
 137 }
 138
 139 /*
 140  * Some of the w1c_bits below also include read-only or non-writable
 141  * reserved bits, this makes the code simpler and is OK as the bits
 142  * are not affected by writing zeros to them.
 143  */
 144 static u32 thunder_pem_bridge_w1c_bits(u64 where_aligned)
 145 {
 146         u32 w1c_bits = 0;
 147
 148         switch (where_aligned) {
 149         case 0x04: /* Command/Status */
 150         case 0x1c: /* Base and I/O Limit/Secondary Status */
 151                 w1c_bits = 0xff000000;
 152                 break;
 153         case 0x44: /* Power Management Control and Status */
 154                 w1c_bits = 0xfffffe00;
 155                 break;
 156         case 0x78: /* Device Control/Device Status */
 157         case 0x80: /* Link Control/Link Status */
 158         case 0x88: /* Slot Control/Slot Status */
 159         case 0x90: /* Root Status */
 160         case 0xa0: /* Link Control 2 Registers/Link Status 2 */
 161                 w1c_bits = 0xffff0000;
 162                 break;
 163         case 0x104: /* Uncorrectable Error Status */
 164         case 0x110: /* Correctable Error Status */
 165         case 0x130: /* Error Status */
 166         case 0x160: /* Link Control 4 */
 167                 w1c_bits = 0xffffffff;
 168                 break;
 169         default:
 170                 break;
 171         }
 172         return w1c_bits;
 173 }
 174
 175 /* Some bits must be written to one so they appear to be read-only. */
 176 static u32 thunder_pem_bridge_w1_bits(u64 where_aligned)
 177 {
 178         u32 w1_bits;
 179
 180         switch (where_aligned) {
 181         case 0x1c: /* I/O Base / I/O Limit, Secondary Status */
 182                 /* Force 32-bit I/O addressing. */
 183                 w1_bits = 0x0101;
 184                 break;
 185         case 0x24: /* Prefetchable Memory Base / Prefetchable Memory Limit */
 186                 /* Force 64-bit addressing */
 187                 w1_bits = 0x00010001;
 188                 break;
 189         default:
 190                 w1_bits = 0;
 191                 break;
 192         }
 193         return w1_bits;
 194 }
 195
 196 static int thunder_pem_bridge_write(struct pci_bus *bus, unsigned int devfn,
 197                                     int where, int size, u32 val)
 198 {
 199         struct pci_config_window *cfg = bus->sysdata;
 200         struct thunder_pem_pci *pem_pci = (struct thunder_pem_pci *)cfg->priv;
 201         u64 write_val, read_val;
 202         u64 where_aligned = where & ~3ull;
 203         u32 mask = 0;
 204
 205
 206         if (devfn != 0 || where >= 2048)
 207                 return PCIBIOS_DEVICE_NOT_FOUND;
 208
 209         /*
 210          * 32-bit accesses only.  If the write is for a size smaller
 211          * than 32-bits, we must first read the 32-bit value and merge
 212          * in the desired bits and then write the whole 32-bits back
 213          * out.
 214          */
 215         switch (size) {
 216         case 1:
 217                 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
 218                 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
 219                 read_val >>= 32;
 220                 mask = ~(0xff << (8 * (where & 3)));
 221                 read_val &= mask;
 222                 val = (val & 0xff) << (8 * (where & 3));
 223                 val |= (u32)read_val;
 224                 break;
 225         case 2:
 226                 writeq(where_aligned, pem_pci->pem_reg_base + PEM_CFG_RD);
 227                 read_val = readq(pem_pci->pem_reg_base + PEM_CFG_RD);
 228                 read_val >>= 32;
 229                 mask = ~(0xffff << (8 * (where & 3)));
 230                 read_val &= mask;
 231                 val = (val & 0xffff) << (8 * (where & 3));
 232                 val |= (u32)read_val;
 233                 break;
 234         default:
 235                 break;
 236         }
 237
 238         /*
 239          * By expanding the write width to 32 bits, we may
 240          * inadvertently hit some W1C bits that were not intended to
 241          * be written.  Calculate the mask that must be applied to the
 242          * data to be written to avoid these cases.
 243          */
 244         if (mask) {
 245                 u32 w1c_bits = thunder_pem_bridge_w1c_bits(where);
 246
 247                 if (w1c_bits) {
 248                         mask &= w1c_bits;
 249                         val &= ~mask;
 250                 }
 251         }
 252
 253         /*
 254          * Some bits must be read-only with value of one.  Since the
 255          * access method allows these to be cleared if a zero is
 256          * written, force them to one before writing.
 257          */
 258         val |= thunder_pem_bridge_w1_bits(where_aligned);
 259
 260         /*
 261          * Low order bits are the config address, the high order 32
 262          * bits are the data to be written.
 263          */
 264         write_val = (((u64)val) << 32) | where_aligned;
 265         writeq(write_val, pem_pci->pem_reg_base + PEM_CFG_WR);
 266         return PCIBIOS_SUCCESSFUL;
 267 }
 268
 269 static int thunder_pem_config_write(struct pci_bus *bus, unsigned int devfn,
 270                                     int where, int size, u32 val)
 271 {
 272         struct pci_config_window *cfg = bus->sysdata;
 273
 274         if (bus->number < cfg->busr.start ||
 275             bus->number > cfg->busr.end)
 276                 return PCIBIOS_DEVICE_NOT_FOUND;
 277         /*
 278          * The first device on the bus is the PEM PCIe bridge.
 279          * Special case its config access.
 280          */
 281         if (bus->number == cfg->busr.start)
 282                 return thunder_pem_bridge_write(bus, devfn, where, size, val);
 283
 284
 285         return pci_generic_config_write(bus, devfn, where, size, val);
 286 }
 287
 288 static int thunder_pem_init(struct device *dev, struct pci_config_window *cfg)
 289 {
 290         resource_size_t bar4_start;
 291         struct resource *res_pem;
 292         struct thunder_pem_pci *pem_pci;
 293         struct platform_device *pdev;
 294
 295         /* Only OF support for now */
 296         if (!dev->of_node)
 297                 return -EINVAL;
 298
 299         pem_pci = devm_kzalloc(dev, sizeof(*pem_pci), GFP_KERNEL);
 300         if (!pem_pci)
 301                 return -ENOMEM;
 302
 303         pdev = to_platform_device(dev);
 304
 305         /*
 306          * The second register range is the PEM bridge to the PCIe
 307          * bus.  It has a different config access method than those
 308          * devices behind the bridge.
 309          */
 310         res_pem = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 311         if (!res_pem) {
 312                 dev_err(dev, "missing \"reg[1]\"property\n");
 313                 return -EINVAL;
 314         }
 315
 316         pem_pci->pem_reg_base = devm_ioremap(dev, res_pem->start, 0x10000);
 317         if (!pem_pci->pem_reg_base)
 318                 return -ENOMEM;
 319
 320         /*
 321          * The MSI-X BAR for the PEM and AER interrupts is located at
 322          * a fixed offset from the PEM register base.  Generate a
 323          * fragment of the synthesized Enhanced Allocation capability
 324          * structure here for the BAR.
 325          */
 326         bar4_start = res_pem->start + 0xf00000;
 327         pem_pci->ea_entry[0] = (u32)bar4_start | 2;
 328         pem_pci->ea_entry[1] = (u32)(res_pem->end - bar4_start) & ~3u;
 329         pem_pci->ea_entry[2] = (u32)(bar4_start >> 32);
 330
 331         cfg->priv = pem_pci;
 332         return 0;
 333 }
 334
 335 static struct pci_ecam_ops pci_thunder_pem_ops = {
 336         .bus_shift      = 24,
 337         .init           = thunder_pem_init,
 338         .pci_ops        = {
 339                 .map_bus        = pci_ecam_map_bus,
 340                 .read           = thunder_pem_config_read,
 341                 .write          = thunder_pem_config_write,
 342         }
 343 };
 344
 345 static const struct of_device_id thunder_pem_of_match[] = {
 346         { .compatible = "cavium,pci-host-thunder-pem" },
 347         { },
 348 };
 349 MODULE_DEVICE_TABLE(of, thunder_pem_of_match);
 350
 351 static int thunder_pem_probe(struct platform_device *pdev)
 352 {
 353         return pci_host_common_probe(pdev, &pci_thunder_pem_ops);
 354 }
 355
 356 static struct platform_driver thunder_pem_driver = {
 357         .driver = {
 358                 .name = KBUILD_MODNAME,
 359                 .of_match_table = thunder_pem_of_match,
 360         },
 361         .probe = thunder_pem_probe,
 362 };
 363 module_platform_driver(thunder_pem_driver);
 364
 365 MODULE_DESCRIPTION("Thunder PEM PCIe host driver");
 366 MODULE_LICENSE("GPL v2");