?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge branch 'r6040-next'
[linux/fpc-iii.git] / drivers / pci / probe.c
blob8e3ef720997dfba2858c4dae77b2a0651f678c2d
1 /*
2 * probe.c - PCI detection and setup code
3 */
4
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
8 #include <linux/pci.h>
9 #include <linux/of_device.h>
10 #include <linux/of_pci.h>
11 #include <linux/pci_hotplug.h>
12 #include <linux/slab.h>
13 #include <linux/module.h>
14 #include <linux/cpumask.h>
15 #include <linux/pci-aspm.h>
16 #include <linux/aer.h>
17 #include <linux/acpi.h>
18 #include <linux/irqdomain.h>
19 #include "pci.h"
20
21 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
22 #define CARDBUS_RESERVE_BUSNR 3
23
24 static struct resource busn_resource = {
25 .name = "PCI busn",
26 .start = 0,
27 .end = 255,
28 .flags = IORESOURCE_BUS,
29 };
30
31 /* Ugh. Need to stop exporting this to modules. */
32 LIST_HEAD(pci_root_buses);
33 EXPORT_SYMBOL(pci_root_buses);
34
35 static LIST_HEAD(pci_domain_busn_res_list);
36
37 struct pci_domain_busn_res {
38 struct list_head list;
39 struct resource res;
40 int domain_nr;
41 };
42
43 static struct resource *get_pci_domain_busn_res(int domain_nr)
44 {
45 struct pci_domain_busn_res *r;
46
47 list_for_each_entry(r, &pci_domain_busn_res_list, list)
48 if (r->domain_nr == domain_nr)
49 return &r->res;
50
51 r = kzalloc(sizeof(*r), GFP_KERNEL);
52 if (!r)
53 return NULL;
54
55 r->domain_nr = domain_nr;
56 r->res.start = 0;
57 r->res.end = 0xff;
58 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
59
60 list_add_tail(&r->list, &pci_domain_busn_res_list);
61
62 return &r->res;
63 }
64
65 static int find_anything(struct device *dev, void *data)
66 {
67 return 1;
68 }
69
70 /*
71 * Some device drivers need know if pci is initiated.
72 * Basically, we think pci is not initiated when there
73 * is no device to be found on the pci_bus_type.
74 */
75 int no_pci_devices(void)
76 {
77 struct device *dev;
78 int no_devices;
79
80 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
81 no_devices = (dev == NULL);
82 put_device(dev);
83 return no_devices;
84 }
85 EXPORT_SYMBOL(no_pci_devices);
86
87 /*
88 * PCI Bus Class
89 */
90 static void release_pcibus_dev(struct device *dev)
91 {
92 struct pci_bus *pci_bus = to_pci_bus(dev);
93
94 put_device(pci_bus->bridge);
95 pci_bus_remove_resources(pci_bus);
96 pci_release_bus_of_node(pci_bus);
97 kfree(pci_bus);
98 }
99
100 static struct class pcibus_class = {
101 .name = "pci_bus",
102 .dev_release = &release_pcibus_dev,
103 .dev_groups = pcibus_groups,
104 };
105
106 static int __init pcibus_class_init(void)
107 {
108 return class_register(&pcibus_class);
109 }
110 postcore_initcall(pcibus_class_init);
111
112 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
113 {
114 u64 size = mask & maxbase; /* Find the significant bits */
115 if (!size)
116 return 0;
117
118 /* Get the lowest of them to find the decode size, and
119 from that the extent. */
120 size = (size & ~(size-1)) - 1;
121
122 /* base == maxbase can be valid only if the BAR has
123 already been programmed with all 1s. */
124 if (base == maxbase && ((base | size) & mask) != mask)
125 return 0;
126
127 return size;
128 }
129
130 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131 {
132 u32 mem_type;
133 unsigned long flags;
134
135 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
136 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
137 flags |= IORESOURCE_IO;
138 return flags;
139 }
140
141 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
142 flags |= IORESOURCE_MEM;
143 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
144 flags |= IORESOURCE_PREFETCH;
145
146 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
147 switch (mem_type) {
148 case PCI_BASE_ADDRESS_MEM_TYPE_32:
149 break;
150 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
151 /* 1M mem BAR treated as 32-bit BAR */
152 break;
153 case PCI_BASE_ADDRESS_MEM_TYPE_64:
154 flags |= IORESOURCE_MEM_64;
155 break;
156 default:
157 /* mem unknown type treated as 32-bit BAR */
158 break;
159 }
160 return flags;
161 }
162
163 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
164
165 /**
166 * pci_read_base - read a PCI BAR
167 * @dev: the PCI device
168 * @type: type of the BAR
169 * @res: resource buffer to be filled in
170 * @pos: BAR position in the config space
171 *
172 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
173 */
174 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
175 struct resource *res, unsigned int pos)
176 {
177 u32 l, sz, mask;
178 u64 l64, sz64, mask64;
179 u16 orig_cmd;
180 struct pci_bus_region region, inverted_region;
181
182 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
183
184 /* No printks while decoding is disabled! */
185 if (!dev->mmio_always_on) {
186 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
187 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
188 pci_write_config_word(dev, PCI_COMMAND,
189 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
190 }
191 }
192
193 res->name = pci_name(dev);
194
195 pci_read_config_dword(dev, pos, &l);
196 pci_write_config_dword(dev, pos, l | mask);
197 pci_read_config_dword(dev, pos, &sz);
198 pci_write_config_dword(dev, pos, l);
199
200 /*
201 * All bits set in sz means the device isn't working properly.
202 * If the BAR isn't implemented, all bits must be 0. If it's a
203 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
204 * 1 must be clear.
205 */
206 if (sz == 0xffffffff)
207 sz = 0;
208
209 /*
210 * I don't know how l can have all bits set. Copied from old code.
211 * Maybe it fixes a bug on some ancient platform.
212 */
213 if (l == 0xffffffff)
214 l = 0;
215
216 if (type == pci_bar_unknown) {
217 res->flags = decode_bar(dev, l);
218 res->flags |= IORESOURCE_SIZEALIGN;
219 if (res->flags & IORESOURCE_IO) {
220 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
222 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
223 } else {
224 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
225 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
226 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
227 }
228 } else {
229 res->flags |= (l & IORESOURCE_ROM_ENABLE);
230 l64 = l & PCI_ROM_ADDRESS_MASK;
231 sz64 = sz & PCI_ROM_ADDRESS_MASK;
232 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
233 }
234
235 if (res->flags & IORESOURCE_MEM_64) {
236 pci_read_config_dword(dev, pos + 4, &l);
237 pci_write_config_dword(dev, pos + 4, ~0);
238 pci_read_config_dword(dev, pos + 4, &sz);
239 pci_write_config_dword(dev, pos + 4, l);
240
241 l64 |= ((u64)l << 32);
242 sz64 |= ((u64)sz << 32);
243 mask64 |= ((u64)~0 << 32);
244 }
245
246 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
247 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
248
249 if (!sz64)
250 goto fail;
251
252 sz64 = pci_size(l64, sz64, mask64);
253 if (!sz64) {
254 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
255 pos);
256 goto fail;
257 }
258
259 if (res->flags & IORESOURCE_MEM_64) {
260 if ((sizeof(pci_bus_addr_t) < 8 || sizeof(resource_size_t) < 8)
261 && sz64 > 0x100000000ULL) {
262 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
263 res->start = 0;
264 res->end = 0;
265 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
266 pos, (unsigned long long)sz64);
267 goto out;
268 }
269
270 if ((sizeof(pci_bus_addr_t) < 8) && l) {
271 /* Above 32-bit boundary; try to reallocate */
272 res->flags |= IORESOURCE_UNSET;
273 res->start = 0;
274 res->end = sz64;
275 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
276 pos, (unsigned long long)l64);
277 goto out;
278 }
279 }
280
281 region.start = l64;
282 region.end = l64 + sz64;
283
284 pcibios_bus_to_resource(dev->bus, res, &region);
285 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
286
287 /*
288 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
289 * the corresponding resource address (the physical address used by
290 * the CPU. Converting that resource address back to a bus address
291 * should yield the original BAR value:
292 *
293 * resource_to_bus(bus_to_resource(A)) == A
294 *
295 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
296 * be claimed by the device.
297 */
298 if (inverted_region.start != region.start) {
299 res->flags |= IORESOURCE_UNSET;
300 res->start = 0;
301 res->end = region.end - region.start;
302 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
303 pos, (unsigned long long)region.start);
304 }
305
306 goto out;
307
308
309 fail:
310 res->flags = 0;
311 out:
312 if (res->flags)
313 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
314
315 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
316 }
317
318 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
319 {
320 unsigned int pos, reg;
321
322 if (dev->non_compliant_bars)
323 return;
324
325 for (pos = 0; pos < howmany; pos++) {
326 struct resource *res = &dev->resource[pos];
327 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
328 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
329 }
330
331 if (rom) {
332 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
333 dev->rom_base_reg = rom;
334 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
335 IORESOURCE_READONLY | IORESOURCE_SIZEALIGN;
336 __pci_read_base(dev, pci_bar_mem32, res, rom);
337 }
338 }
339
340 static void pci_read_bridge_io(struct pci_bus *child)
341 {
342 struct pci_dev *dev = child->self;
343 u8 io_base_lo, io_limit_lo;
344 unsigned long io_mask, io_granularity, base, limit;
345 struct pci_bus_region region;
346 struct resource *res;
347
348 io_mask = PCI_IO_RANGE_MASK;
349 io_granularity = 0x1000;
350 if (dev->io_window_1k) {
351 /* Support 1K I/O space granularity */
352 io_mask = PCI_IO_1K_RANGE_MASK;
353 io_granularity = 0x400;
354 }
355
356 res = child->resource[0];
357 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
358 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
359 base = (io_base_lo & io_mask) << 8;
360 limit = (io_limit_lo & io_mask) << 8;
361
362 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
363 u16 io_base_hi, io_limit_hi;
364
365 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
366 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
367 base |= ((unsigned long) io_base_hi << 16);
368 limit |= ((unsigned long) io_limit_hi << 16);
369 }
370
371 if (base <= limit) {
372 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
373 region.start = base;
374 region.end = limit + io_granularity - 1;
375 pcibios_bus_to_resource(dev->bus, res, &region);
376 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
377 }
378 }
379
380 static void pci_read_bridge_mmio(struct pci_bus *child)
381 {
382 struct pci_dev *dev = child->self;
383 u16 mem_base_lo, mem_limit_lo;
384 unsigned long base, limit;
385 struct pci_bus_region region;
386 struct resource *res;
387
388 res = child->resource[1];
389 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
390 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
391 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
392 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
393 if (base <= limit) {
394 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
395 region.start = base;
396 region.end = limit + 0xfffff;
397 pcibios_bus_to_resource(dev->bus, res, &region);
398 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
399 }
400 }
401
402 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
403 {
404 struct pci_dev *dev = child->self;
405 u16 mem_base_lo, mem_limit_lo;
406 u64 base64, limit64;
407 pci_bus_addr_t base, limit;
408 struct pci_bus_region region;
409 struct resource *res;
410
411 res = child->resource[2];
412 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
413 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
414 base64 = (mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
415 limit64 = (mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
416
417 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
418 u32 mem_base_hi, mem_limit_hi;
419
420 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
421 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
422
423 /*
424 * Some bridges set the base > limit by default, and some
425 * (broken) BIOSes do not initialize them. If we find
426 * this, just assume they are not being used.
427 */
428 if (mem_base_hi <= mem_limit_hi) {
429 base64 |= (u64) mem_base_hi << 32;
430 limit64 |= (u64) mem_limit_hi << 32;
431 }
432 }
433
434 base = (pci_bus_addr_t) base64;
435 limit = (pci_bus_addr_t) limit64;
436
437 if (base != base64) {
438 dev_err(&dev->dev, "can't handle bridge window above 4GB (bus address %#010llx)\n",
439 (unsigned long long) base64);
440 return;
441 }
442
443 if (base <= limit) {
444 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
445 IORESOURCE_MEM | IORESOURCE_PREFETCH;
446 if (res->flags & PCI_PREF_RANGE_TYPE_64)
447 res->flags |= IORESOURCE_MEM_64;
448 region.start = base;
449 region.end = limit + 0xfffff;
450 pcibios_bus_to_resource(dev->bus, res, &region);
451 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
452 }
453 }
454
455 void pci_read_bridge_bases(struct pci_bus *child)
456 {
457 struct pci_dev *dev = child->self;
458 struct resource *res;
459 int i;
460
461 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
462 return;
463
464 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
465 &child->busn_res,
466 dev->transparent ? " (subtractive decode)" : "");
467
468 pci_bus_remove_resources(child);
469 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
470 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
471
472 pci_read_bridge_io(child);
473 pci_read_bridge_mmio(child);
474 pci_read_bridge_mmio_pref(child);
475
476 if (dev->transparent) {
477 pci_bus_for_each_resource(child->parent, res, i) {
478 if (res && res->flags) {
479 pci_bus_add_resource(child, res,
480 PCI_SUBTRACTIVE_DECODE);
481 dev_printk(KERN_DEBUG, &dev->dev,
482 " bridge window %pR (subtractive decode)\n",
483 res);
484 }
485 }
486 }
487 }
488
489 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
490 {
491 struct pci_bus *b;
492
493 b = kzalloc(sizeof(*b), GFP_KERNEL);
494 if (!b)
495 return NULL;
496
497 INIT_LIST_HEAD(&b->node);
498 INIT_LIST_HEAD(&b->children);
499 INIT_LIST_HEAD(&b->devices);
500 INIT_LIST_HEAD(&b->slots);
501 INIT_LIST_HEAD(&b->resources);
502 b->max_bus_speed = PCI_SPEED_UNKNOWN;
503 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
504 #ifdef CONFIG_PCI_DOMAINS_GENERIC
505 if (parent)
506 b->domain_nr = parent->domain_nr;
507 #endif
508 return b;
509 }
510
511 static void pci_release_host_bridge_dev(struct device *dev)
512 {
513 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
514
515 if (bridge->release_fn)
516 bridge->release_fn(bridge);
517
518 pci_free_resource_list(&bridge->windows);
519
520 kfree(bridge);
521 }
522
523 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
524 {
525 struct pci_host_bridge *bridge;
526
527 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
528 if (!bridge)
529 return NULL;
530
531 INIT_LIST_HEAD(&bridge->windows);
532 bridge->bus = b;
533 return bridge;
534 }
535
536 static const unsigned char pcix_bus_speed[] = {
537 PCI_SPEED_UNKNOWN, /* 0 */
538 PCI_SPEED_66MHz_PCIX, /* 1 */
539 PCI_SPEED_100MHz_PCIX, /* 2 */
540 PCI_SPEED_133MHz_PCIX, /* 3 */
541 PCI_SPEED_UNKNOWN, /* 4 */
542 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
543 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
544 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
545 PCI_SPEED_UNKNOWN, /* 8 */
546 PCI_SPEED_66MHz_PCIX_266, /* 9 */
547 PCI_SPEED_100MHz_PCIX_266, /* A */
548 PCI_SPEED_133MHz_PCIX_266, /* B */
549 PCI_SPEED_UNKNOWN, /* C */
550 PCI_SPEED_66MHz_PCIX_533, /* D */
551 PCI_SPEED_100MHz_PCIX_533, /* E */
552 PCI_SPEED_133MHz_PCIX_533 /* F */
553 };
554
555 const unsigned char pcie_link_speed[] = {
556 PCI_SPEED_UNKNOWN, /* 0 */
557 PCIE_SPEED_2_5GT, /* 1 */
558 PCIE_SPEED_5_0GT, /* 2 */
559 PCIE_SPEED_8_0GT, /* 3 */
560 PCI_SPEED_UNKNOWN, /* 4 */
561 PCI_SPEED_UNKNOWN, /* 5 */
562 PCI_SPEED_UNKNOWN, /* 6 */
563 PCI_SPEED_UNKNOWN, /* 7 */
564 PCI_SPEED_UNKNOWN, /* 8 */
565 PCI_SPEED_UNKNOWN, /* 9 */
566 PCI_SPEED_UNKNOWN, /* A */
567 PCI_SPEED_UNKNOWN, /* B */
568 PCI_SPEED_UNKNOWN, /* C */
569 PCI_SPEED_UNKNOWN, /* D */
570 PCI_SPEED_UNKNOWN, /* E */
571 PCI_SPEED_UNKNOWN /* F */
572 };
573
574 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
575 {
576 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
577 }
578 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
579
580 static unsigned char agp_speeds[] = {
581 AGP_UNKNOWN,
582 AGP_1X,
583 AGP_2X,
584 AGP_4X,
585 AGP_8X
586 };
587
588 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
589 {
590 int index = 0;
591
592 if (agpstat & 4)
593 index = 3;
594 else if (agpstat & 2)
595 index = 2;
596 else if (agpstat & 1)
597 index = 1;
598 else
599 goto out;
600
601 if (agp3) {
602 index += 2;
603 if (index == 5)
604 index = 0;
605 }
606
607 out:
608 return agp_speeds[index];
609 }
610
611 static void pci_set_bus_speed(struct pci_bus *bus)
612 {
613 struct pci_dev *bridge = bus->self;
614 int pos;
615
616 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
617 if (!pos)
618 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
619 if (pos) {
620 u32 agpstat, agpcmd;
621
622 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
623 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
624
625 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
626 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
627 }
628
629 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
630 if (pos) {
631 u16 status;
632 enum pci_bus_speed max;
633
634 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
635 &status);
636
637 if (status & PCI_X_SSTATUS_533MHZ) {
638 max = PCI_SPEED_133MHz_PCIX_533;
639 } else if (status & PCI_X_SSTATUS_266MHZ) {
640 max = PCI_SPEED_133MHz_PCIX_266;
641 } else if (status & PCI_X_SSTATUS_133MHZ) {
642 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
643 max = PCI_SPEED_133MHz_PCIX_ECC;
644 else
645 max = PCI_SPEED_133MHz_PCIX;
646 } else {
647 max = PCI_SPEED_66MHz_PCIX;
648 }
649
650 bus->max_bus_speed = max;
651 bus->cur_bus_speed = pcix_bus_speed[
652 (status & PCI_X_SSTATUS_FREQ) >> 6];
653
654 return;
655 }
656
657 if (pci_is_pcie(bridge)) {
658 u32 linkcap;
659 u16 linksta;
660
661 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
662 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
663
664 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
665 pcie_update_link_speed(bus, linksta);
666 }
667 }
668
669 static struct irq_domain *pci_host_bridge_msi_domain(struct pci_bus *bus)
670 {
671 struct irq_domain *d;
672
673 /*
674 * Any firmware interface that can resolve the msi_domain
675 * should be called from here.
676 */
677 d = pci_host_bridge_of_msi_domain(bus);
678 if (!d)
679 d = pci_host_bridge_acpi_msi_domain(bus);
680
681 #ifdef CONFIG_PCI_MSI_IRQ_DOMAIN
682 /*
683 * If no IRQ domain was found via the OF tree, try looking it up
684 * directly through the fwnode_handle.
685 */
686 if (!d) {
687 struct fwnode_handle *fwnode = pci_root_bus_fwnode(bus);
688
689 if (fwnode)
690 d = irq_find_matching_fwnode(fwnode,
691 DOMAIN_BUS_PCI_MSI);
692 }
693 #endif
694
695 return d;
696 }
697
698 static void pci_set_bus_msi_domain(struct pci_bus *bus)
699 {
700 struct irq_domain *d;
701 struct pci_bus *b;
702
703 /*
704 * The bus can be a root bus, a subordinate bus, or a virtual bus
705 * created by an SR-IOV device. Walk up to the first bridge device
706 * found or derive the domain from the host bridge.
707 */
708 for (b = bus, d = NULL; !d && !pci_is_root_bus(b); b = b->parent) {
709 if (b->self)
710 d = dev_get_msi_domain(&b->self->dev);
711 }
712
713 if (!d)
714 d = pci_host_bridge_msi_domain(b);
715
716 dev_set_msi_domain(&bus->dev, d);
717 }
718
719 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
720 struct pci_dev *bridge, int busnr)
721 {
722 struct pci_bus *child;
723 int i;
724 int ret;
725
726 /*
727 * Allocate a new bus, and inherit stuff from the parent..
728 */
729 child = pci_alloc_bus(parent);
730 if (!child)
731 return NULL;
732
733 child->parent = parent;
734 child->ops = parent->ops;
735 child->msi = parent->msi;
736 child->sysdata = parent->sysdata;
737 child->bus_flags = parent->bus_flags;
738
739 /* initialize some portions of the bus device, but don't register it
740 * now as the parent is not properly set up yet.
741 */
742 child->dev.class = &pcibus_class;
743 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
744
745 /*
746 * Set up the primary, secondary and subordinate
747 * bus numbers.
748 */
749 child->number = child->busn_res.start = busnr;
750 child->primary = parent->busn_res.start;
751 child->busn_res.end = 0xff;
752
753 if (!bridge) {
754 child->dev.parent = parent->bridge;
755 goto add_dev;
756 }
757
758 child->self = bridge;
759 child->bridge = get_device(&bridge->dev);
760 child->dev.parent = child->bridge;
761 pci_set_bus_of_node(child);
762 pci_set_bus_speed(child);
763
764 /* Set up default resource pointers and names.. */
765 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
766 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
767 child->resource[i]->name = child->name;
768 }
769 bridge->subordinate = child;
770
771 add_dev:
772 pci_set_bus_msi_domain(child);
773 ret = device_register(&child->dev);
774 WARN_ON(ret < 0);
775
776 pcibios_add_bus(child);
777
778 if (child->ops->add_bus) {
779 ret = child->ops->add_bus(child);
780 if (WARN_ON(ret < 0))
781 dev_err(&child->dev, "failed to add bus: %d\n", ret);
782 }
783
784 /* Create legacy_io and legacy_mem files for this bus */
785 pci_create_legacy_files(child);
786
787 return child;
788 }
789
790 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
791 int busnr)
792 {
793 struct pci_bus *child;
794
795 child = pci_alloc_child_bus(parent, dev, busnr);
796 if (child) {
797 down_write(&pci_bus_sem);
798 list_add_tail(&child->node, &parent->children);
799 up_write(&pci_bus_sem);
800 }
801 return child;
802 }
803 EXPORT_SYMBOL(pci_add_new_bus);
804
805 static void pci_enable_crs(struct pci_dev *pdev)
806 {
807 u16 root_cap = 0;
808
809 /* Enable CRS Software Visibility if supported */
810 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
811 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
812 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
813 PCI_EXP_RTCTL_CRSSVE);
814 }
815
816 /*
817 * If it's a bridge, configure it and scan the bus behind it.
818 * For CardBus bridges, we don't scan behind as the devices will
819 * be handled by the bridge driver itself.
820 *
821 * We need to process bridges in two passes -- first we scan those
822 * already configured by the BIOS and after we are done with all of
823 * them, we proceed to assigning numbers to the remaining buses in
824 * order to avoid overlaps between old and new bus numbers.
825 */
826 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
827 {
828 struct pci_bus *child;
829 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
830 u32 buses, i, j = 0;
831 u16 bctl;
832 u8 primary, secondary, subordinate;
833 int broken = 0;
834
835 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
836 primary = buses & 0xFF;
837 secondary = (buses >> 8) & 0xFF;
838 subordinate = (buses >> 16) & 0xFF;
839
840 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
841 secondary, subordinate, pass);
842
843 if (!primary && (primary != bus->number) && secondary && subordinate) {
844 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
845 primary = bus->number;
846 }
847
848 /* Check if setup is sensible at all */
849 if (!pass &&
850 (primary != bus->number || secondary <= bus->number ||
851 secondary > subordinate)) {
852 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
853 secondary, subordinate);
854 broken = 1;
855 }
856
857 /* Disable MasterAbortMode during probing to avoid reporting
858 of bus errors (in some architectures) */
859 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
860 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
861 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
862
863 pci_enable_crs(dev);
864
865 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
866 !is_cardbus && !broken) {
867 unsigned int cmax;
868 /*
869 * Bus already configured by firmware, process it in the first
870 * pass and just note the configuration.
871 */
872 if (pass)
873 goto out;
874
875 /*
876 * The bus might already exist for two reasons: Either we are
877 * rescanning the bus or the bus is reachable through more than
878 * one bridge. The second case can happen with the i450NX
879 * chipset.
880 */
881 child = pci_find_bus(pci_domain_nr(bus), secondary);
882 if (!child) {
883 child = pci_add_new_bus(bus, dev, secondary);
884 if (!child)
885 goto out;
886 child->primary = primary;
887 pci_bus_insert_busn_res(child, secondary, subordinate);
888 child->bridge_ctl = bctl;
889 }
890
891 cmax = pci_scan_child_bus(child);
892 if (cmax > subordinate)
893 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
894 subordinate, cmax);
895 /* subordinate should equal child->busn_res.end */
896 if (subordinate > max)
897 max = subordinate;
898 } else {
899 /*
900 * We need to assign a number to this bus which we always
901 * do in the second pass.
902 */
903 if (!pass) {
904 if (pcibios_assign_all_busses() || broken || is_cardbus)
905 /* Temporarily disable forwarding of the
906 configuration cycles on all bridges in
907 this bus segment to avoid possible
908 conflicts in the second pass between two
909 bridges programmed with overlapping
910 bus ranges. */
911 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
912 buses & ~0xffffff);
913 goto out;
914 }
915
916 /* Clear errors */
917 pci_write_config_word(dev, PCI_STATUS, 0xffff);
918
919 /* Prevent assigning a bus number that already exists.
920 * This can happen when a bridge is hot-plugged, so in
921 * this case we only re-scan this bus. */
922 child = pci_find_bus(pci_domain_nr(bus), max+1);
923 if (!child) {
924 child = pci_add_new_bus(bus, dev, max+1);
925 if (!child)
926 goto out;
927 pci_bus_insert_busn_res(child, max+1, 0xff);
928 }
929 max++;
930 buses = (buses & 0xff000000)
931 | ((unsigned int)(child->primary) << 0)
932 | ((unsigned int)(child->busn_res.start) << 8)
933 | ((unsigned int)(child->busn_res.end) << 16);
934
935 /*
936 * yenta.c forces a secondary latency timer of 176.
937 * Copy that behaviour here.
938 */
939 if (is_cardbus) {
940 buses &= ~0xff000000;
941 buses |= CARDBUS_LATENCY_TIMER << 24;
942 }
943
944 /*
945 * We need to blast all three values with a single write.
946 */
947 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
948
949 if (!is_cardbus) {
950 child->bridge_ctl = bctl;
951 max = pci_scan_child_bus(child);
952 } else {
953 /*
954 * For CardBus bridges, we leave 4 bus numbers
955 * as cards with a PCI-to-PCI bridge can be
956 * inserted later.
957 */
958 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
959 struct pci_bus *parent = bus;
960 if (pci_find_bus(pci_domain_nr(bus),
961 max+i+1))
962 break;
963 while (parent->parent) {
964 if ((!pcibios_assign_all_busses()) &&
965 (parent->busn_res.end > max) &&
966 (parent->busn_res.end <= max+i)) {
967 j = 1;
968 }
969 parent = parent->parent;
970 }
971 if (j) {
972 /*
973 * Often, there are two cardbus bridges
974 * -- try to leave one valid bus number
975 * for each one.
976 */
977 i /= 2;
978 break;
979 }
980 }
981 max += i;
982 }
983 /*
984 * Set the subordinate bus number to its real value.
985 */
986 pci_bus_update_busn_res_end(child, max);
987 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
988 }
989
990 sprintf(child->name,
991 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
992 pci_domain_nr(bus), child->number);
993
994 /* Has only triggered on CardBus, fixup is in yenta_socket */
995 while (bus->parent) {
996 if ((child->busn_res.end > bus->busn_res.end) ||
997 (child->number > bus->busn_res.end) ||
998 (child->number < bus->number) ||
999 (child->busn_res.end < bus->number)) {
1000 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
1001 &child->busn_res,
1002 (bus->number > child->busn_res.end &&
1003 bus->busn_res.end < child->number) ?
1004 "wholly" : "partially",
1005 bus->self->transparent ? " transparent" : "",
1006 dev_name(&bus->dev),
1007 &bus->busn_res);
1008 }
1009 bus = bus->parent;
1010 }
1011
1012 out:
1013 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
1014
1015 return max;
1016 }
1017 EXPORT_SYMBOL(pci_scan_bridge);
1018
1019 /*
1020 * Read interrupt line and base address registers.
1021 * The architecture-dependent code can tweak these, of course.
1022 */
1023 static void pci_read_irq(struct pci_dev *dev)
1024 {
1025 unsigned char irq;
1026
1027 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
1028 dev->pin = irq;
1029 if (irq)
1030 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
1031 dev->irq = irq;
1032 }
1033
1034 void set_pcie_port_type(struct pci_dev *pdev)
1035 {
1036 int pos;
1037 u16 reg16;
1038 int type;
1039 struct pci_dev *parent;
1040
1041 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
1042 if (!pos)
1043 return;
1044 pdev->pcie_cap = pos;
1045 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
1046 pdev->pcie_flags_reg = reg16;
1047 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
1048 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
1049
1050 /*
1051 * A Root Port is always the upstream end of a Link. No PCIe
1052 * component has two Links. Two Links are connected by a Switch
1053 * that has a Port on each Link and internal logic to connect the
1054 * two Ports.
1055 */
1056 type = pci_pcie_type(pdev);
1057 if (type == PCI_EXP_TYPE_ROOT_PORT)
1058 pdev->has_secondary_link = 1;
1059 else if (type == PCI_EXP_TYPE_UPSTREAM ||
1060 type == PCI_EXP_TYPE_DOWNSTREAM) {
1061 parent = pci_upstream_bridge(pdev);
1062
1063 /*
1064 * Usually there's an upstream device (Root Port or Switch
1065 * Downstream Port), but we can't assume one exists.
1066 */
1067 if (parent && !parent->has_secondary_link)
1068 pdev->has_secondary_link = 1;
1069 }
1070 }
1071
1072 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
1073 {
1074 u32 reg32;
1075
1076 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, &reg32);
1077 if (reg32 & PCI_EXP_SLTCAP_HPC)
1078 pdev->is_hotplug_bridge = 1;
1079 }
1080
1081 /**
1082 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
1083 * @dev: PCI device
1084 *
1085 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
1086 * when forwarding a type1 configuration request the bridge must check that
1087 * the extended register address field is zero. The bridge is not permitted
1088 * to forward the transactions and must handle it as an Unsupported Request.
1089 * Some bridges do not follow this rule and simply drop the extended register
1090 * bits, resulting in the standard config space being aliased, every 256
1091 * bytes across the entire configuration space. Test for this condition by
1092 * comparing the first dword of each potential alias to the vendor/device ID.
1093 * Known offenders:
1094 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1095 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1096 */
1097 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1098 {
1099 #ifdef CONFIG_PCI_QUIRKS
1100 int pos;
1101 u32 header, tmp;
1102
1103 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1104
1105 for (pos = PCI_CFG_SPACE_SIZE;
1106 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1107 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1108 || header != tmp)
1109 return false;
1110 }
1111
1112 return true;
1113 #else
1114 return false;
1115 #endif
1116 }
1117
1118 /**
1119 * pci_cfg_space_size - get the configuration space size of the PCI device.
1120 * @dev: PCI device
1121 *
1122 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1123 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1124 * access it. Maybe we don't have a way to generate extended config space
1125 * accesses, or the device is behind a reverse Express bridge. So we try
1126 * reading the dword at 0x100 which must either be 0 or a valid extended
1127 * capability header.
1128 */
1129 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1130 {
1131 u32 status;
1132 int pos = PCI_CFG_SPACE_SIZE;
1133
1134 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1135 return PCI_CFG_SPACE_SIZE;
1136 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1137 return PCI_CFG_SPACE_SIZE;
1138
1139 return PCI_CFG_SPACE_EXP_SIZE;
1140 }
1141
1142 int pci_cfg_space_size(struct pci_dev *dev)
1143 {
1144 int pos;
1145 u32 status;
1146 u16 class;
1147
1148 class = dev->class >> 8;
1149 if (class == PCI_CLASS_BRIDGE_HOST)
1150 return pci_cfg_space_size_ext(dev);
1151
1152 if (pci_is_pcie(dev))
1153 return pci_cfg_space_size_ext(dev);
1154
1155 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1156 if (!pos)
1157 return PCI_CFG_SPACE_SIZE;
1158
1159 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1160 if (status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ))
1161 return pci_cfg_space_size_ext(dev);
1162
1163 return PCI_CFG_SPACE_SIZE;
1164 }
1165
1166 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1167
1168 static void pci_msi_setup_pci_dev(struct pci_dev *dev)
1169 {
1170 /*
1171 * Disable the MSI hardware to avoid screaming interrupts
1172 * during boot. This is the power on reset default so
1173 * usually this should be a noop.
1174 */
1175 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1176 if (dev->msi_cap)
1177 pci_msi_set_enable(dev, 0);
1178
1179 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1180 if (dev->msix_cap)
1181 pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_ENABLE, 0);
1182 }
1183
1184 /**
1185 * pci_setup_device - fill in class and map information of a device
1186 * @dev: the device structure to fill
1187 *
1188 * Initialize the device structure with information about the device's
1189 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1190 * Called at initialisation of the PCI subsystem and by CardBus services.
1191 * Returns 0 on success and negative if unknown type of device (not normal,
1192 * bridge or CardBus).
1193 */
1194 int pci_setup_device(struct pci_dev *dev)
1195 {
1196 u32 class;
1197 u16 cmd;
1198 u8 hdr_type;
1199 int pos = 0;
1200 struct pci_bus_region region;
1201 struct resource *res;
1202
1203 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1204 return -EIO;
1205
1206 dev->sysdata = dev->bus->sysdata;
1207 dev->dev.parent = dev->bus->bridge;
1208 dev->dev.bus = &pci_bus_type;
1209 dev->hdr_type = hdr_type & 0x7f;
1210 dev->multifunction = !!(hdr_type & 0x80);
1211 dev->error_state = pci_channel_io_normal;
1212 set_pcie_port_type(dev);
1213
1214 pci_dev_assign_slot(dev);
1215 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1216 set this higher, assuming the system even supports it. */
1217 dev->dma_mask = 0xffffffff;
1218
1219 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1220 dev->bus->number, PCI_SLOT(dev->devfn),
1221 PCI_FUNC(dev->devfn));
1222
1223 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1224 dev->revision = class & 0xff;
1225 dev->class = class >> 8; /* upper 3 bytes */
1226
1227 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1228 dev->vendor, dev->device, dev->hdr_type, dev->class);
1229
1230 /* need to have dev->class ready */
1231 dev->cfg_size = pci_cfg_space_size(dev);
1232
1233 /* "Unknown power state" */
1234 dev->current_state = PCI_UNKNOWN;
1235
1236 /* Early fixups, before probing the BARs */
1237 pci_fixup_device(pci_fixup_early, dev);
1238 /* device class may be changed after fixup */
1239 class = dev->class >> 8;
1240
1241 if (dev->non_compliant_bars) {
1242 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1243 if (cmd & (PCI_COMMAND_IO | PCI_COMMAND_MEMORY)) {
1244 dev_info(&dev->dev, "device has non-compliant BARs; disabling IO/MEM decoding\n");
1245 cmd &= ~PCI_COMMAND_IO;
1246 cmd &= ~PCI_COMMAND_MEMORY;
1247 pci_write_config_word(dev, PCI_COMMAND, cmd);
1248 }
1249 }
1250
1251 switch (dev->hdr_type) { /* header type */
1252 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1253 if (class == PCI_CLASS_BRIDGE_PCI)
1254 goto bad;
1255 pci_read_irq(dev);
1256 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1257 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1258 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1259
1260 /*
1261 * Do the ugly legacy mode stuff here rather than broken chip
1262 * quirk code. Legacy mode ATA controllers have fixed
1263 * addresses. These are not always echoed in BAR0-3, and
1264 * BAR0-3 in a few cases contain junk!
1265 */
1266 if (class == PCI_CLASS_STORAGE_IDE) {
1267 u8 progif;
1268 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1269 if ((progif & 1) == 0) {
1270 region.start = 0x1F0;
1271 region.end = 0x1F7;
1272 res = &dev->resource[0];
1273 res->flags = LEGACY_IO_RESOURCE;
1274 pcibios_bus_to_resource(dev->bus, res, &region);
1275 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1276 res);
1277 region.start = 0x3F6;
1278 region.end = 0x3F6;
1279 res = &dev->resource[1];
1280 res->flags = LEGACY_IO_RESOURCE;
1281 pcibios_bus_to_resource(dev->bus, res, &region);
1282 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1283 res);
1284 }
1285 if ((progif & 4) == 0) {
1286 region.start = 0x170;
1287 region.end = 0x177;
1288 res = &dev->resource[2];
1289 res->flags = LEGACY_IO_RESOURCE;
1290 pcibios_bus_to_resource(dev->bus, res, &region);
1291 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1292 res);
1293 region.start = 0x376;
1294 region.end = 0x376;
1295 res = &dev->resource[3];
1296 res->flags = LEGACY_IO_RESOURCE;
1297 pcibios_bus_to_resource(dev->bus, res, &region);
1298 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1299 res);
1300 }
1301 }
1302 break;
1303
1304 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1305 if (class != PCI_CLASS_BRIDGE_PCI)
1306 goto bad;
1307 /* The PCI-to-PCI bridge spec requires that subtractive
1308 decoding (i.e. transparent) bridge must have programming
1309 interface code of 0x01. */
1310 pci_read_irq(dev);
1311 dev->transparent = ((dev->class & 0xff) == 1);
1312 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1313 set_pcie_hotplug_bridge(dev);
1314 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1315 if (pos) {
1316 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1317 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1318 }
1319 break;
1320
1321 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1322 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1323 goto bad;
1324 pci_read_irq(dev);
1325 pci_read_bases(dev, 1, 0);
1326 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1327 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1328 break;
1329
1330 default: /* unknown header */
1331 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1332 dev->hdr_type);
1333 return -EIO;
1334
1335 bad:
1336 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1337 dev->class, dev->hdr_type);
1338 dev->class = PCI_CLASS_NOT_DEFINED << 8;
1339 }
1340
1341 /* We found a fine healthy device, go go go... */
1342 return 0;
1343 }
1344
1345 static void pci_configure_mps(struct pci_dev *dev)
1346 {
1347 struct pci_dev *bridge = pci_upstream_bridge(dev);
1348 int mps, p_mps, rc;
1349
1350 if (!pci_is_pcie(dev) || !bridge || !pci_is_pcie(bridge))
1351 return;
1352
1353 mps = pcie_get_mps(dev);
1354 p_mps = pcie_get_mps(bridge);
1355
1356 if (mps == p_mps)
1357 return;
1358
1359 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1360 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1361 mps, pci_name(bridge), p_mps);
1362 return;
1363 }
1364
1365 /*
1366 * Fancier MPS configuration is done later by
1367 * pcie_bus_configure_settings()
1368 */
1369 if (pcie_bus_config != PCIE_BUS_DEFAULT)
1370 return;
1371
1372 rc = pcie_set_mps(dev, p_mps);
1373 if (rc) {
1374 dev_warn(&dev->dev, "can't set Max Payload Size to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1375 p_mps);
1376 return;
1377 }
1378
1379 dev_info(&dev->dev, "Max Payload Size set to %d (was %d, max %d)\n",
1380 p_mps, mps, 128 << dev->pcie_mpss);
1381 }
1382
1383 static struct hpp_type0 pci_default_type0 = {
1384 .revision = 1,
1385 .cache_line_size = 8,
1386 .latency_timer = 0x40,
1387 .enable_serr = 0,
1388 .enable_perr = 0,
1389 };
1390
1391 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1392 {
1393 u16 pci_cmd, pci_bctl;
1394
1395 if (!hpp)
1396 hpp = &pci_default_type0;
1397
1398 if (hpp->revision > 1) {
1399 dev_warn(&dev->dev,
1400 "PCI settings rev %d not supported; using defaults\n",
1401 hpp->revision);
1402 hpp = &pci_default_type0;
1403 }
1404
1405 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1406 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1407 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1408 if (hpp->enable_serr)
1409 pci_cmd |= PCI_COMMAND_SERR;
1410 if (hpp->enable_perr)
1411 pci_cmd |= PCI_COMMAND_PARITY;
1412 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1413
1414 /* Program bridge control value */
1415 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1416 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1417 hpp->latency_timer);
1418 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1419 if (hpp->enable_serr)
1420 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1421 if (hpp->enable_perr)
1422 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1423 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1424 }
1425 }
1426
1427 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1428 {
1429 if (hpp)
1430 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1431 }
1432
1433 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1434 {
1435 int pos;
1436 u32 reg32;
1437
1438 if (!hpp)
1439 return;
1440
1441 if (hpp->revision > 1) {
1442 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1443 hpp->revision);
1444 return;
1445 }
1446
1447 /*
1448 * Don't allow _HPX to change MPS or MRRS settings. We manage
1449 * those to make sure they're consistent with the rest of the
1450 * platform.
1451 */
1452 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1453 PCI_EXP_DEVCTL_READRQ;
1454 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1455 PCI_EXP_DEVCTL_READRQ);
1456
1457 /* Initialize Device Control Register */
1458 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1459 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1460
1461 /* Initialize Link Control Register */
1462 if (pcie_cap_has_lnkctl(dev))
1463 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1464 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1465
1466 /* Find Advanced Error Reporting Enhanced Capability */
1467 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1468 if (!pos)
1469 return;
1470
1471 /* Initialize Uncorrectable Error Mask Register */
1472 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, &reg32);
1473 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1474 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1475
1476 /* Initialize Uncorrectable Error Severity Register */
1477 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, &reg32);
1478 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1479 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1480
1481 /* Initialize Correctable Error Mask Register */
1482 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, &reg32);
1483 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1484 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1485
1486 /* Initialize Advanced Error Capabilities and Control Register */
1487 pci_read_config_dword(dev, pos + PCI_ERR_CAP, &reg32);
1488 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1489 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1490
1491 /*
1492 * FIXME: The following two registers are not supported yet.
1493 *
1494 * o Secondary Uncorrectable Error Severity Register
1495 * o Secondary Uncorrectable Error Mask Register
1496 */
1497 }
1498
1499 static void pci_configure_device(struct pci_dev *dev)
1500 {
1501 struct hotplug_params hpp;
1502 int ret;
1503
1504 pci_configure_mps(dev);
1505
1506 memset(&hpp, 0, sizeof(hpp));
1507 ret = pci_get_hp_params(dev, &hpp);
1508 if (ret)
1509 return;
1510
1511 program_hpp_type2(dev, hpp.t2);
1512 program_hpp_type1(dev, hpp.t1);
1513 program_hpp_type0(dev, hpp.t0);
1514 }
1515
1516 static void pci_release_capabilities(struct pci_dev *dev)
1517 {
1518 pci_vpd_release(dev);
1519 pci_iov_release(dev);
1520 pci_free_cap_save_buffers(dev);
1521 }
1522
1523 /**
1524 * pci_release_dev - free a pci device structure when all users of it are finished.
1525 * @dev: device that's been disconnected
1526 *
1527 * Will be called only by the device core when all users of this pci device are
1528 * done.
1529 */
1530 static void pci_release_dev(struct device *dev)
1531 {
1532 struct pci_dev *pci_dev;
1533
1534 pci_dev = to_pci_dev(dev);
1535 pci_release_capabilities(pci_dev);
1536 pci_release_of_node(pci_dev);
1537 pcibios_release_device(pci_dev);
1538 pci_bus_put(pci_dev->bus);
1539 kfree(pci_dev->driver_override);
1540 kfree(pci_dev->dma_alias_mask);
1541 kfree(pci_dev);
1542 }
1543
1544 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1545 {
1546 struct pci_dev *dev;
1547
1548 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1549 if (!dev)
1550 return NULL;
1551
1552 INIT_LIST_HEAD(&dev->bus_list);
1553 dev->dev.type = &pci_dev_type;
1554 dev->bus = pci_bus_get(bus);
1555
1556 return dev;
1557 }
1558 EXPORT_SYMBOL(pci_alloc_dev);
1559
1560 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1561 int crs_timeout)
1562 {
1563 int delay = 1;
1564
1565 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1566 return false;
1567
1568 /* some broken boards return 0 or ~0 if a slot is empty: */
1569 if (*l == 0xffffffff || *l == 0x00000000 ||
1570 *l == 0x0000ffff || *l == 0xffff0000)
1571 return false;
1572
1573 /*
1574 * Configuration Request Retry Status. Some root ports return the
1575 * actual device ID instead of the synthetic ID (0xFFFF) required
1576 * by the PCIe spec. Ignore the device ID and only check for
1577 * (vendor id == 1).
1578 */
1579 while ((*l & 0xffff) == 0x0001) {
1580 if (!crs_timeout)
1581 return false;
1582
1583 msleep(delay);
1584 delay *= 2;
1585 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1586 return false;
1587 /* Card hasn't responded in 60 seconds? Must be stuck. */
1588 if (delay > crs_timeout) {
1589 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1590 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1591 PCI_FUNC(devfn));
1592 return false;
1593 }
1594 }
1595
1596 return true;
1597 }
1598 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1599
1600 /*
1601 * Read the config data for a PCI device, sanity-check it
1602 * and fill in the dev structure...
1603 */
1604 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1605 {
1606 struct pci_dev *dev;
1607 u32 l;
1608
1609 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1610 return NULL;
1611
1612 dev = pci_alloc_dev(bus);
1613 if (!dev)
1614 return NULL;
1615
1616 dev->devfn = devfn;
1617 dev->vendor = l & 0xffff;
1618 dev->device = (l >> 16) & 0xffff;
1619
1620 pci_set_of_node(dev);
1621
1622 if (pci_setup_device(dev)) {
1623 pci_bus_put(dev->bus);
1624 kfree(dev);
1625 return NULL;
1626 }
1627
1628 return dev;
1629 }
1630
1631 static void pci_init_capabilities(struct pci_dev *dev)
1632 {
1633 /* Enhanced Allocation */
1634 pci_ea_init(dev);
1635
1636 /* Setup MSI caps & disable MSI/MSI-X interrupts */
1637 pci_msi_setup_pci_dev(dev);
1638
1639 /* Buffers for saving PCIe and PCI-X capabilities */
1640 pci_allocate_cap_save_buffers(dev);
1641
1642 /* Power Management */
1643 pci_pm_init(dev);
1644
1645 /* Vital Product Data */
1646 pci_vpd_init(dev);
1647
1648 /* Alternative Routing-ID Forwarding */
1649 pci_configure_ari(dev);
1650
1651 /* Single Root I/O Virtualization */
1652 pci_iov_init(dev);
1653
1654 /* Address Translation Services */
1655 pci_ats_init(dev);
1656
1657 /* Enable ACS P2P upstream forwarding */
1658 pci_enable_acs(dev);
1659
1660 pci_cleanup_aer_error_status_regs(dev);
1661 }
1662
1663 /*
1664 * This is the equivalent of pci_host_bridge_msi_domain that acts on
1665 * devices. Firmware interfaces that can select the MSI domain on a
1666 * per-device basis should be called from here.
1667 */
1668 static struct irq_domain *pci_dev_msi_domain(struct pci_dev *dev)
1669 {
1670 struct irq_domain *d;
1671
1672 /*
1673 * If a domain has been set through the pcibios_add_device
1674 * callback, then this is the one (platform code knows best).
1675 */
1676 d = dev_get_msi_domain(&dev->dev);
1677 if (d)
1678 return d;
1679
1680 /*
1681 * Let's see if we have a firmware interface able to provide
1682 * the domain.
1683 */
1684 d = pci_msi_get_device_domain(dev);
1685 if (d)
1686 return d;
1687
1688 return NULL;
1689 }
1690
1691 static void pci_set_msi_domain(struct pci_dev *dev)
1692 {
1693 struct irq_domain *d;
1694
1695 /*
1696 * If the platform or firmware interfaces cannot supply a
1697 * device-specific MSI domain, then inherit the default domain
1698 * from the host bridge itself.
1699 */
1700 d = pci_dev_msi_domain(dev);
1701 if (!d)
1702 d = dev_get_msi_domain(&dev->bus->dev);
1703
1704 dev_set_msi_domain(&dev->dev, d);
1705 }
1706
1707 /**
1708 * pci_dma_configure - Setup DMA configuration
1709 * @dev: ptr to pci_dev struct of the PCI device
1710 *
1711 * Function to update PCI devices's DMA configuration using the same
1712 * info from the OF node or ACPI node of host bridge's parent (if any).
1713 */
1714 static void pci_dma_configure(struct pci_dev *dev)
1715 {
1716 struct device *bridge = pci_get_host_bridge_device(dev);
1717
1718 if (IS_ENABLED(CONFIG_OF) &&
1719 bridge->parent && bridge->parent->of_node) {
1720 of_dma_configure(&dev->dev, bridge->parent->of_node);
1721 } else if (has_acpi_companion(bridge)) {
1722 struct acpi_device *adev = to_acpi_device_node(bridge->fwnode);
1723 enum dev_dma_attr attr = acpi_get_dma_attr(adev);
1724
1725 if (attr == DEV_DMA_NOT_SUPPORTED)
1726 dev_warn(&dev->dev, "DMA not supported.\n");
1727 else
1728 arch_setup_dma_ops(&dev->dev, 0, 0, NULL,
1729 attr == DEV_DMA_COHERENT);
1730 }
1731
1732 pci_put_host_bridge_device(bridge);
1733 }
1734
1735 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1736 {
1737 int ret;
1738
1739 pci_configure_device(dev);
1740
1741 device_initialize(&dev->dev);
1742 dev->dev.release = pci_release_dev;
1743
1744 set_dev_node(&dev->dev, pcibus_to_node(bus));
1745 dev->dev.dma_mask = &dev->dma_mask;
1746 dev->dev.dma_parms = &dev->dma_parms;
1747 dev->dev.coherent_dma_mask = 0xffffffffull;
1748 pci_dma_configure(dev);
1749
1750 pci_set_dma_max_seg_size(dev, 65536);
1751 pci_set_dma_seg_boundary(dev, 0xffffffff);
1752
1753 /* Fix up broken headers */
1754 pci_fixup_device(pci_fixup_header, dev);
1755
1756 /* moved out from quirk header fixup code */
1757 pci_reassigndev_resource_alignment(dev);
1758
1759 /* Clear the state_saved flag. */
1760 dev->state_saved = false;
1761
1762 /* Initialize various capabilities */
1763 pci_init_capabilities(dev);
1764
1765 /*
1766 * Add the device to our list of discovered devices
1767 * and the bus list for fixup functions, etc.
1768 */
1769 down_write(&pci_bus_sem);
1770 list_add_tail(&dev->bus_list, &bus->devices);
1771 up_write(&pci_bus_sem);
1772
1773 ret = pcibios_add_device(dev);
1774 WARN_ON(ret < 0);
1775
1776 /* Setup MSI irq domain */
1777 pci_set_msi_domain(dev);
1778
1779 /* Notifier could use PCI capabilities */
1780 dev->match_driver = false;
1781 ret = device_add(&dev->dev);
1782 WARN_ON(ret < 0);
1783 }
1784
1785 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1786 {
1787 struct pci_dev *dev;
1788
1789 dev = pci_get_slot(bus, devfn);
1790 if (dev) {
1791 pci_dev_put(dev);
1792 return dev;
1793 }
1794
1795 dev = pci_scan_device(bus, devfn);
1796 if (!dev)
1797 return NULL;
1798
1799 pci_device_add(dev, bus);
1800
1801 return dev;
1802 }
1803 EXPORT_SYMBOL(pci_scan_single_device);
1804
1805 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1806 {
1807 int pos;
1808 u16 cap = 0;
1809 unsigned next_fn;
1810
1811 if (pci_ari_enabled(bus)) {
1812 if (!dev)
1813 return 0;
1814 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1815 if (!pos)
1816 return 0;
1817
1818 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1819 next_fn = PCI_ARI_CAP_NFN(cap);
1820 if (next_fn <= fn)
1821 return 0; /* protect against malformed list */
1822
1823 return next_fn;
1824 }
1825
1826 /* dev may be NULL for non-contiguous multifunction devices */
1827 if (!dev || dev->multifunction)
1828 return (fn + 1) % 8;
1829
1830 return 0;
1831 }
1832
1833 static int only_one_child(struct pci_bus *bus)
1834 {
1835 struct pci_dev *parent = bus->self;
1836
1837 if (!parent || !pci_is_pcie(parent))
1838 return 0;
1839 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1840 return 1;
1841
1842 /*
1843 * PCIe downstream ports are bridges that normally lead to only a
1844 * device 0, but if PCI_SCAN_ALL_PCIE_DEVS is set, scan all
1845 * possible devices, not just device 0. See PCIe spec r3.0,
1846 * sec 7.3.1.
1847 */
1848 if (parent->has_secondary_link &&
1849 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1850 return 1;
1851 return 0;
1852 }
1853
1854 /**
1855 * pci_scan_slot - scan a PCI slot on a bus for devices.
1856 * @bus: PCI bus to scan
1857 * @devfn: slot number to scan (must have zero function.)
1858 *
1859 * Scan a PCI slot on the specified PCI bus for devices, adding
1860 * discovered devices to the @bus->devices list. New devices
1861 * will not have is_added set.
1862 *
1863 * Returns the number of new devices found.
1864 */
1865 int pci_scan_slot(struct pci_bus *bus, int devfn)
1866 {
1867 unsigned fn, nr = 0;
1868 struct pci_dev *dev;
1869
1870 if (only_one_child(bus) && (devfn > 0))
1871 return 0; /* Already scanned the entire slot */
1872
1873 dev = pci_scan_single_device(bus, devfn);
1874 if (!dev)
1875 return 0;
1876 if (!dev->is_added)
1877 nr++;
1878
1879 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1880 dev = pci_scan_single_device(bus, devfn + fn);
1881 if (dev) {
1882 if (!dev->is_added)
1883 nr++;
1884 dev->multifunction = 1;
1885 }
1886 }
1887
1888 /* only one slot has pcie device */
1889 if (bus->self && nr)
1890 pcie_aspm_init_link_state(bus->self);
1891
1892 return nr;
1893 }
1894 EXPORT_SYMBOL(pci_scan_slot);
1895
1896 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1897 {
1898 u8 *smpss = data;
1899
1900 if (!pci_is_pcie(dev))
1901 return 0;
1902
1903 /*
1904 * We don't have a way to change MPS settings on devices that have
1905 * drivers attached. A hot-added device might support only the minimum
1906 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1907 * where devices may be hot-added, we limit the fabric MPS to 128 so
1908 * hot-added devices will work correctly.
1909 *
1910 * However, if we hot-add a device to a slot directly below a Root
1911 * Port, it's impossible for there to be other existing devices below
1912 * the port. We don't limit the MPS in this case because we can
1913 * reconfigure MPS on both the Root Port and the hot-added device,
1914 * and there are no other devices involved.
1915 *
1916 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1917 */
1918 if (dev->is_hotplug_bridge &&
1919 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1920 *smpss = 0;
1921
1922 if (*smpss > dev->pcie_mpss)
1923 *smpss = dev->pcie_mpss;
1924
1925 return 0;
1926 }
1927
1928 static void pcie_write_mps(struct pci_dev *dev, int mps)
1929 {
1930 int rc;
1931
1932 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1933 mps = 128 << dev->pcie_mpss;
1934
1935 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1936 dev->bus->self)
1937 /* For "Performance", the assumption is made that
1938 * downstream communication will never be larger than
1939 * the MRRS. So, the MPS only needs to be configured
1940 * for the upstream communication. This being the case,
1941 * walk from the top down and set the MPS of the child
1942 * to that of the parent bus.
1943 *
1944 * Configure the device MPS with the smaller of the
1945 * device MPSS or the bridge MPS (which is assumed to be
1946 * properly configured at this point to the largest
1947 * allowable MPS based on its parent bus).
1948 */
1949 mps = min(mps, pcie_get_mps(dev->bus->self));
1950 }
1951
1952 rc = pcie_set_mps(dev, mps);
1953 if (rc)
1954 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1955 }
1956
1957 static void pcie_write_mrrs(struct pci_dev *dev)
1958 {
1959 int rc, mrrs;
1960
1961 /* In the "safe" case, do not configure the MRRS. There appear to be
1962 * issues with setting MRRS to 0 on a number of devices.
1963 */
1964 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1965 return;
1966
1967 /* For Max performance, the MRRS must be set to the largest supported
1968 * value. However, it cannot be configured larger than the MPS the
1969 * device or the bus can support. This should already be properly
1970 * configured by a prior call to pcie_write_mps.
1971 */
1972 mrrs = pcie_get_mps(dev);
1973
1974 /* MRRS is a R/W register. Invalid values can be written, but a
1975 * subsequent read will verify if the value is acceptable or not.
1976 * If the MRRS value provided is not acceptable (e.g., too large),
1977 * shrink the value until it is acceptable to the HW.
1978 */
1979 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1980 rc = pcie_set_readrq(dev, mrrs);
1981 if (!rc)
1982 break;
1983
1984 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1985 mrrs /= 2;
1986 }
1987
1988 if (mrrs < 128)
1989 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1990 }
1991
1992 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1993 {
1994 int mps, orig_mps;
1995
1996 if (!pci_is_pcie(dev))
1997 return 0;
1998
1999 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2000 pcie_bus_config == PCIE_BUS_DEFAULT)
2001 return 0;
2002
2003 mps = 128 << *(u8 *)data;
2004 orig_mps = pcie_get_mps(dev);
2005
2006 pcie_write_mps(dev, mps);
2007 pcie_write_mrrs(dev);
2008
2009 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
2010 pcie_get_mps(dev), 128 << dev->pcie_mpss,
2011 orig_mps, pcie_get_readrq(dev));
2012
2013 return 0;
2014 }
2015
2016 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
2017 * parents then children fashion. If this changes, then this code will not
2018 * work as designed.
2019 */
2020 void pcie_bus_configure_settings(struct pci_bus *bus)
2021 {
2022 u8 smpss = 0;
2023
2024 if (!bus->self)
2025 return;
2026
2027 if (!pci_is_pcie(bus->self))
2028 return;
2029
2030 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
2031 * to be aware of the MPS of the destination. To work around this,
2032 * simply force the MPS of the entire system to the smallest possible.
2033 */
2034 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
2035 smpss = 0;
2036
2037 if (pcie_bus_config == PCIE_BUS_SAFE) {
2038 smpss = bus->self->pcie_mpss;
2039
2040 pcie_find_smpss(bus->self, &smpss);
2041 pci_walk_bus(bus, pcie_find_smpss, &smpss);
2042 }
2043
2044 pcie_bus_configure_set(bus->self, &smpss);
2045 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
2046 }
2047 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
2048
2049 unsigned int pci_scan_child_bus(struct pci_bus *bus)
2050 {
2051 unsigned int devfn, pass, max = bus->busn_res.start;
2052 struct pci_dev *dev;
2053
2054 dev_dbg(&bus->dev, "scanning bus\n");
2055
2056 /* Go find them, Rover! */
2057 for (devfn = 0; devfn < 0x100; devfn += 8)
2058 pci_scan_slot(bus, devfn);
2059
2060 /* Reserve buses for SR-IOV capability. */
2061 max += pci_iov_bus_range(bus);
2062
2063 /*
2064 * After performing arch-dependent fixup of the bus, look behind
2065 * all PCI-to-PCI bridges on this bus.
2066 */
2067 if (!bus->is_added) {
2068 dev_dbg(&bus->dev, "fixups for bus\n");
2069 pcibios_fixup_bus(bus);
2070 bus->is_added = 1;
2071 }
2072
2073 for (pass = 0; pass < 2; pass++)
2074 list_for_each_entry(dev, &bus->devices, bus_list) {
2075 if (pci_is_bridge(dev))
2076 max = pci_scan_bridge(bus, dev, max, pass);
2077 }
2078
2079 /*
2080 * We've scanned the bus and so we know all about what's on
2081 * the other side of any bridges that may be on this bus plus
2082 * any devices.
2083 *
2084 * Return how far we've got finding sub-buses.
2085 */
2086 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
2087 return max;
2088 }
2089 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
2090
2091 /**
2092 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
2093 * @bridge: Host bridge to set up.
2094 *
2095 * Default empty implementation. Replace with an architecture-specific setup
2096 * routine, if necessary.
2097 */
2098 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
2099 {
2100 return 0;
2101 }
2102
2103 void __weak pcibios_add_bus(struct pci_bus *bus)
2104 {
2105 }
2106
2107 void __weak pcibios_remove_bus(struct pci_bus *bus)
2108 {
2109 }
2110
2111 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
2112 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2113 {
2114 int error;
2115 struct pci_host_bridge *bridge;
2116 struct pci_bus *b, *b2;
2117 struct resource_entry *window, *n;
2118 struct resource *res;
2119 resource_size_t offset;
2120 char bus_addr[64];
2121 char *fmt;
2122
2123 b = pci_alloc_bus(NULL);
2124 if (!b)
2125 return NULL;
2126
2127 b->sysdata = sysdata;
2128 b->ops = ops;
2129 b->number = b->busn_res.start = bus;
2130 pci_bus_assign_domain_nr(b, parent);
2131 b2 = pci_find_bus(pci_domain_nr(b), bus);
2132 if (b2) {
2133 /* If we already got to this bus through a different bridge, ignore it */
2134 dev_dbg(&b2->dev, "bus already known\n");
2135 goto err_out;
2136 }
2137
2138 bridge = pci_alloc_host_bridge(b);
2139 if (!bridge)
2140 goto err_out;
2141
2142 bridge->dev.parent = parent;
2143 bridge->dev.release = pci_release_host_bridge_dev;
2144 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
2145 error = pcibios_root_bridge_prepare(bridge);
2146 if (error) {
2147 kfree(bridge);
2148 goto err_out;
2149 }
2150
2151 error = device_register(&bridge->dev);
2152 if (error) {
2153 put_device(&bridge->dev);
2154 goto err_out;
2155 }
2156 b->bridge = get_device(&bridge->dev);
2157 device_enable_async_suspend(b->bridge);
2158 pci_set_bus_of_node(b);
2159 pci_set_bus_msi_domain(b);
2160
2161 if (!parent)
2162 set_dev_node(b->bridge, pcibus_to_node(b));
2163
2164 b->dev.class = &pcibus_class;
2165 b->dev.parent = b->bridge;
2166 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
2167 error = device_register(&b->dev);
2168 if (error)
2169 goto class_dev_reg_err;
2170
2171 pcibios_add_bus(b);
2172
2173 /* Create legacy_io and legacy_mem files for this bus */
2174 pci_create_legacy_files(b);
2175
2176 if (parent)
2177 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
2178 else
2179 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
2180
2181 /* Add initial resources to the bus */
2182 resource_list_for_each_entry_safe(window, n, resources) {
2183 list_move_tail(&window->node, &bridge->windows);
2184 res = window->res;
2185 offset = window->offset;
2186 if (res->flags & IORESOURCE_BUS)
2187 pci_bus_insert_busn_res(b, bus, res->end);
2188 else
2189 pci_bus_add_resource(b, res, 0);
2190 if (offset) {
2191 if (resource_type(res) == IORESOURCE_IO)
2192 fmt = " (bus address [%#06llx-%#06llx])";
2193 else
2194 fmt = " (bus address [%#010llx-%#010llx])";
2195 snprintf(bus_addr, sizeof(bus_addr), fmt,
2196 (unsigned long long) (res->start - offset),
2197 (unsigned long long) (res->end - offset));
2198 } else
2199 bus_addr[0] = '\0';
2200 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
2201 }
2202
2203 down_write(&pci_bus_sem);
2204 list_add_tail(&b->node, &pci_root_buses);
2205 up_write(&pci_bus_sem);
2206
2207 return b;
2208
2209 class_dev_reg_err:
2210 put_device(&bridge->dev);
2211 device_unregister(&bridge->dev);
2212 err_out:
2213 kfree(b);
2214 return NULL;
2215 }
2216 EXPORT_SYMBOL_GPL(pci_create_root_bus);
2217
2218 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
2219 {
2220 struct resource *res = &b->busn_res;
2221 struct resource *parent_res, *conflict;
2222
2223 res->start = bus;
2224 res->end = bus_max;
2225 res->flags = IORESOURCE_BUS;
2226
2227 if (!pci_is_root_bus(b))
2228 parent_res = &b->parent->busn_res;
2229 else {
2230 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2231 res->flags |= IORESOURCE_PCI_FIXED;
2232 }
2233
2234 conflict = request_resource_conflict(parent_res, res);
2235
2236 if (conflict)
2237 dev_printk(KERN_DEBUG, &b->dev,
2238 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2239 res, pci_is_root_bus(b) ? "domain " : "",
2240 parent_res, conflict->name, conflict);
2241
2242 return conflict == NULL;
2243 }
2244
2245 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2246 {
2247 struct resource *res = &b->busn_res;
2248 struct resource old_res = *res;
2249 resource_size_t size;
2250 int ret;
2251
2252 if (res->start > bus_max)
2253 return -EINVAL;
2254
2255 size = bus_max - res->start + 1;
2256 ret = adjust_resource(res, res->start, size);
2257 dev_printk(KERN_DEBUG, &b->dev,
2258 "busn_res: %pR end %s updated to %02x\n",
2259 &old_res, ret ? "can not be" : "is", bus_max);
2260
2261 if (!ret && !res->parent)
2262 pci_bus_insert_busn_res(b, res->start, res->end);
2263
2264 return ret;
2265 }
2266
2267 void pci_bus_release_busn_res(struct pci_bus *b)
2268 {
2269 struct resource *res = &b->busn_res;
2270 int ret;
2271
2272 if (!res->flags || !res->parent)
2273 return;
2274
2275 ret = release_resource(res);
2276 dev_printk(KERN_DEBUG, &b->dev,
2277 "busn_res: %pR %s released\n",
2278 res, ret ? "can not be" : "is");
2279 }
2280
2281 struct pci_bus *pci_scan_root_bus_msi(struct device *parent, int bus,
2282 struct pci_ops *ops, void *sysdata,
2283 struct list_head *resources, struct msi_controller *msi)
2284 {
2285 struct resource_entry *window;
2286 bool found = false;
2287 struct pci_bus *b;
2288 int max;
2289
2290 resource_list_for_each_entry(window, resources)
2291 if (window->res->flags & IORESOURCE_BUS) {
2292 found = true;
2293 break;
2294 }
2295
2296 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2297 if (!b)
2298 return NULL;
2299
2300 b->msi = msi;
2301
2302 if (!found) {
2303 dev_info(&b->dev,
2304 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2305 bus);
2306 pci_bus_insert_busn_res(b, bus, 255);
2307 }
2308
2309 max = pci_scan_child_bus(b);
2310
2311 if (!found)
2312 pci_bus_update_busn_res_end(b, max);
2313
2314 return b;
2315 }
2316
2317 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2318 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2319 {
2320 return pci_scan_root_bus_msi(parent, bus, ops, sysdata, resources,
2321 NULL);
2322 }
2323 EXPORT_SYMBOL(pci_scan_root_bus);
2324
2325 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2326 void *sysdata)
2327 {
2328 LIST_HEAD(resources);
2329 struct pci_bus *b;
2330
2331 pci_add_resource(&resources, &ioport_resource);
2332 pci_add_resource(&resources, &iomem_resource);
2333 pci_add_resource(&resources, &busn_resource);
2334 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2335 if (b) {
2336 pci_scan_child_bus(b);
2337 } else {
2338 pci_free_resource_list(&resources);
2339 }
2340 return b;
2341 }
2342 EXPORT_SYMBOL(pci_scan_bus);
2343
2344 /**
2345 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2346 * @bridge: PCI bridge for the bus to scan
2347 *
2348 * Scan a PCI bus and child buses for new devices, add them,
2349 * and enable them, resizing bridge mmio/io resource if necessary
2350 * and possible. The caller must ensure the child devices are already
2351 * removed for resizing to occur.
2352 *
2353 * Returns the max number of subordinate bus discovered.
2354 */
2355 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2356 {
2357 unsigned int max;
2358 struct pci_bus *bus = bridge->subordinate;
2359
2360 max = pci_scan_child_bus(bus);
2361
2362 pci_assign_unassigned_bridge_resources(bridge);
2363
2364 pci_bus_add_devices(bus);
2365
2366 return max;
2367 }
2368
2369 /**
2370 * pci_rescan_bus - scan a PCI bus for devices.
2371 * @bus: PCI bus to scan
2372 *
2373 * Scan a PCI bus and child buses for new devices, adds them,
2374 * and enables them.
2375 *
2376 * Returns the max number of subordinate bus discovered.
2377 */
2378 unsigned int pci_rescan_bus(struct pci_bus *bus)
2379 {
2380 unsigned int max;
2381
2382 max = pci_scan_child_bus(bus);
2383 pci_assign_unassigned_bus_resources(bus);
2384 pci_bus_add_devices(bus);
2385
2386 return max;
2387 }
2388 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2389
2390 /*
2391 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2392 * routines should always be executed under this mutex.
2393 */
2394 static DEFINE_MUTEX(pci_rescan_remove_lock);
2395
2396 void pci_lock_rescan_remove(void)
2397 {
2398 mutex_lock(&pci_rescan_remove_lock);
2399 }
2400 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2401
2402 void pci_unlock_rescan_remove(void)
2403 {
2404 mutex_unlock(&pci_rescan_remove_lock);
2405 }
2406 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2407
2408 static int __init pci_sort_bf_cmp(const struct device *d_a,
2409 const struct device *d_b)
2410 {
2411 const struct pci_dev *a = to_pci_dev(d_a);
2412 const struct pci_dev *b = to_pci_dev(d_b);
2413
2414 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2415 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2416
2417 if (a->bus->number < b->bus->number) return -1;
2418 else if (a->bus->number > b->bus->number) return 1;
2419
2420 if (a->devfn < b->devfn) return -1;
2421 else if (a->devfn > b->devfn) return 1;
2422
2423 return 0;
2424 }
2425
2426 void __init pci_sort_breadthfirst(void)
2427 {
2428 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);
2429 }
Linux with added FPC-III support