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Merge branch 'r6040-next'
[linux/fpc-iii.git] / drivers / pinctrl / sh-pfc / pfc-r8a7795.c
blob44632b1a5c978cb39ed9138149ca60c3b4455926
1 /*
2 * R-Car Gen3 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2015 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11 #include <linux/kernel.h>
12
13 #include "core.h"
14 #include "sh_pfc.h"
15
16 #define CPU_ALL_PORT(fn, sfx) \
17 PORT_GP_CFG_16(0, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
18 PORT_GP_CFG_28(1, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
19 PORT_GP_CFG_15(2, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
20 PORT_GP_CFG_16(3, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
21 PORT_GP_CFG_18(4, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
22 PORT_GP_CFG_26(5, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
23 PORT_GP_CFG_32(6, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH), \
24 PORT_GP_CFG_4(7, fn, sfx, SH_PFC_PIN_CFG_DRIVE_STRENGTH)
25 /*
26 * F_() : just information
27 * FM() : macro for FN_xxx / xxx_MARK
28 */
29
30 /* GPSR0 */
31 #define GPSR0_15 F_(D15, IP7_11_8)
32 #define GPSR0_14 F_(D14, IP7_7_4)
33 #define GPSR0_13 F_(D13, IP7_3_0)
34 #define GPSR0_12 F_(D12, IP6_31_28)
35 #define GPSR0_11 F_(D11, IP6_27_24)
36 #define GPSR0_10 F_(D10, IP6_23_20)
37 #define GPSR0_9 F_(D9, IP6_19_16)
38 #define GPSR0_8 F_(D8, IP6_15_12)
39 #define GPSR0_7 F_(D7, IP6_11_8)
40 #define GPSR0_6 F_(D6, IP6_7_4)
41 #define GPSR0_5 F_(D5, IP6_3_0)
42 #define GPSR0_4 F_(D4, IP5_31_28)
43 #define GPSR0_3 F_(D3, IP5_27_24)
44 #define GPSR0_2 F_(D2, IP5_23_20)
45 #define GPSR0_1 F_(D1, IP5_19_16)
46 #define GPSR0_0 F_(D0, IP5_15_12)
47
48 /* GPSR1 */
49 #define GPSR1_27 F_(EX_WAIT0_A, IP5_11_8)
50 #define GPSR1_26 F_(WE1_N, IP5_7_4)
51 #define GPSR1_25 F_(WE0_N, IP5_3_0)
52 #define GPSR1_24 F_(RD_WR_N, IP4_31_28)
53 #define GPSR1_23 F_(RD_N, IP4_27_24)
54 #define GPSR1_22 F_(BS_N, IP4_23_20)
55 #define GPSR1_21 F_(CS1_N_A26, IP4_19_16)
56 #define GPSR1_20 F_(CS0_N, IP4_15_12)
57 #define GPSR1_19 F_(A19, IP4_11_8)
58 #define GPSR1_18 F_(A18, IP4_7_4)
59 #define GPSR1_17 F_(A17, IP4_3_0)
60 #define GPSR1_16 F_(A16, IP3_31_28)
61 #define GPSR1_15 F_(A15, IP3_27_24)
62 #define GPSR1_14 F_(A14, IP3_23_20)
63 #define GPSR1_13 F_(A13, IP3_19_16)
64 #define GPSR1_12 F_(A12, IP3_15_12)
65 #define GPSR1_11 F_(A11, IP3_11_8)
66 #define GPSR1_10 F_(A10, IP3_7_4)
67 #define GPSR1_9 F_(A9, IP3_3_0)
68 #define GPSR1_8 F_(A8, IP2_31_28)
69 #define GPSR1_7 F_(A7, IP2_27_24)
70 #define GPSR1_6 F_(A6, IP2_23_20)
71 #define GPSR1_5 F_(A5, IP2_19_16)
72 #define GPSR1_4 F_(A4, IP2_15_12)
73 #define GPSR1_3 F_(A3, IP2_11_8)
74 #define GPSR1_2 F_(A2, IP2_7_4)
75 #define GPSR1_1 F_(A1, IP2_3_0)
76 #define GPSR1_0 F_(A0, IP1_31_28)
77
78 /* GPSR2 */
79 #define GPSR2_14 F_(AVB_AVTP_CAPTURE_A, IP0_23_20)
80 #define GPSR2_13 F_(AVB_AVTP_MATCH_A, IP0_19_16)
81 #define GPSR2_12 F_(AVB_LINK, IP0_15_12)
82 #define GPSR2_11 F_(AVB_PHY_INT, IP0_11_8)
83 #define GPSR2_10 F_(AVB_MAGIC, IP0_7_4)
84 #define GPSR2_9 F_(AVB_MDC, IP0_3_0)
85 #define GPSR2_8 F_(PWM2_A, IP1_27_24)
86 #define GPSR2_7 F_(PWM1_A, IP1_23_20)
87 #define GPSR2_6 F_(PWM0, IP1_19_16)
88 #define GPSR2_5 F_(IRQ5, IP1_15_12)
89 #define GPSR2_4 F_(IRQ4, IP1_11_8)
90 #define GPSR2_3 F_(IRQ3, IP1_7_4)
91 #define GPSR2_2 F_(IRQ2, IP1_3_0)
92 #define GPSR2_1 F_(IRQ1, IP0_31_28)
93 #define GPSR2_0 F_(IRQ0, IP0_27_24)
94
95 /* GPSR3 */
96 #define GPSR3_15 F_(SD1_WP, IP10_23_20)
97 #define GPSR3_14 F_(SD1_CD, IP10_19_16)
98 #define GPSR3_13 F_(SD0_WP, IP10_15_12)
99 #define GPSR3_12 F_(SD0_CD, IP10_11_8)
100 #define GPSR3_11 F_(SD1_DAT3, IP8_31_28)
101 #define GPSR3_10 F_(SD1_DAT2, IP8_27_24)
102 #define GPSR3_9 F_(SD1_DAT1, IP8_23_20)
103 #define GPSR3_8 F_(SD1_DAT0, IP8_19_16)
104 #define GPSR3_7 F_(SD1_CMD, IP8_15_12)
105 #define GPSR3_6 F_(SD1_CLK, IP8_11_8)
106 #define GPSR3_5 F_(SD0_DAT3, IP8_7_4)
107 #define GPSR3_4 F_(SD0_DAT2, IP8_3_0)
108 #define GPSR3_3 F_(SD0_DAT1, IP7_31_28)
109 #define GPSR3_2 F_(SD0_DAT0, IP7_27_24)
110 #define GPSR3_1 F_(SD0_CMD, IP7_23_20)
111 #define GPSR3_0 F_(SD0_CLK, IP7_19_16)
112
113 /* GPSR4 */
114 #define GPSR4_17 FM(SD3_DS)
115 #define GPSR4_16 F_(SD3_DAT7, IP10_7_4)
116 #define GPSR4_15 F_(SD3_DAT6, IP10_3_0)
117 #define GPSR4_14 F_(SD3_DAT5, IP9_31_28)
118 #define GPSR4_13 F_(SD3_DAT4, IP9_27_24)
119 #define GPSR4_12 FM(SD3_DAT3)
120 #define GPSR4_11 FM(SD3_DAT2)
121 #define GPSR4_10 FM(SD3_DAT1)
122 #define GPSR4_9 FM(SD3_DAT0)
123 #define GPSR4_8 FM(SD3_CMD)
124 #define GPSR4_7 FM(SD3_CLK)
125 #define GPSR4_6 F_(SD2_DS, IP9_23_20)
126 #define GPSR4_5 F_(SD2_DAT3, IP9_19_16)
127 #define GPSR4_4 F_(SD2_DAT2, IP9_15_12)
128 #define GPSR4_3 F_(SD2_DAT1, IP9_11_8)
129 #define GPSR4_2 F_(SD2_DAT0, IP9_7_4)
130 #define GPSR4_1 FM(SD2_CMD)
131 #define GPSR4_0 F_(SD2_CLK, IP9_3_0)
132
133 /* GPSR5 */
134 #define GPSR5_25 F_(MLB_DAT, IP13_19_16)
135 #define GPSR5_24 F_(MLB_SIG, IP13_15_12)
136 #define GPSR5_23 F_(MLB_CLK, IP13_11_8)
137 #define GPSR5_22 FM(MSIOF0_RXD)
138 #define GPSR5_21 F_(MSIOF0_SS2, IP13_7_4)
139 #define GPSR5_20 FM(MSIOF0_TXD)
140 #define GPSR5_19 F_(MSIOF0_SS1, IP13_3_0)
141 #define GPSR5_18 F_(MSIOF0_SYNC, IP12_31_28)
142 #define GPSR5_17 FM(MSIOF0_SCK)
143 #define GPSR5_16 F_(HRTS0_N, IP12_27_24)
144 #define GPSR5_15 F_(HCTS0_N, IP12_23_20)
145 #define GPSR5_14 F_(HTX0, IP12_19_16)
146 #define GPSR5_13 F_(HRX0, IP12_15_12)
147 #define GPSR5_12 F_(HSCK0, IP12_11_8)
148 #define GPSR5_11 F_(RX2_A, IP12_7_4)
149 #define GPSR5_10 F_(TX2_A, IP12_3_0)
150 #define GPSR5_9 F_(SCK2, IP11_31_28)
151 #define GPSR5_8 F_(RTS1_N_TANS, IP11_27_24)
152 #define GPSR5_7 F_(CTS1_N, IP11_23_20)
153 #define GPSR5_6 F_(TX1_A, IP11_19_16)
154 #define GPSR5_5 F_(RX1_A, IP11_15_12)
155 #define GPSR5_4 F_(RTS0_N_TANS, IP11_11_8)
156 #define GPSR5_3 F_(CTS0_N, IP11_7_4)
157 #define GPSR5_2 F_(TX0, IP11_3_0)
158 #define GPSR5_1 F_(RX0, IP10_31_28)
159 #define GPSR5_0 F_(SCK0, IP10_27_24)
160
161 /* GPSR6 */
162 #define GPSR6_31 F_(USB31_OVC, IP17_7_4)
163 #define GPSR6_30 F_(USB31_PWEN, IP17_3_0)
164 #define GPSR6_29 F_(USB30_OVC, IP16_31_28)
165 #define GPSR6_28 F_(USB30_PWEN, IP16_27_24)
166 #define GPSR6_27 F_(USB1_OVC, IP16_23_20)
167 #define GPSR6_26 F_(USB1_PWEN, IP16_19_16)
168 #define GPSR6_25 F_(USB0_OVC, IP16_15_12)
169 #define GPSR6_24 F_(USB0_PWEN, IP16_11_8)
170 #define GPSR6_23 F_(AUDIO_CLKB_B, IP16_7_4)
171 #define GPSR6_22 F_(AUDIO_CLKA_A, IP16_3_0)
172 #define GPSR6_21 F_(SSI_SDATA9_A, IP15_31_28)
173 #define GPSR6_20 F_(SSI_SDATA8, IP15_27_24)
174 #define GPSR6_19 F_(SSI_SDATA7, IP15_23_20)
175 #define GPSR6_18 F_(SSI_WS78, IP15_19_16)
176 #define GPSR6_17 F_(SSI_SCK78, IP15_15_12)
177 #define GPSR6_16 F_(SSI_SDATA6, IP15_11_8)
178 #define GPSR6_15 F_(SSI_WS6, IP15_7_4)
179 #define GPSR6_14 F_(SSI_SCK6, IP15_3_0)
180 #define GPSR6_13 FM(SSI_SDATA5)
181 #define GPSR6_12 FM(SSI_WS5)
182 #define GPSR6_11 FM(SSI_SCK5)
183 #define GPSR6_10 F_(SSI_SDATA4, IP14_31_28)
184 #define GPSR6_9 F_(SSI_WS4, IP14_27_24)
185 #define GPSR6_8 F_(SSI_SCK4, IP14_23_20)
186 #define GPSR6_7 F_(SSI_SDATA3, IP14_19_16)
187 #define GPSR6_6 F_(SSI_WS34, IP14_15_12)
188 #define GPSR6_5 F_(SSI_SCK34, IP14_11_8)
189 #define GPSR6_4 F_(SSI_SDATA2_A, IP14_7_4)
190 #define GPSR6_3 F_(SSI_SDATA1_A, IP14_3_0)
191 #define GPSR6_2 F_(SSI_SDATA0, IP13_31_28)
192 #define GPSR6_1 F_(SSI_WS01239, IP13_27_24)
193 #define GPSR6_0 F_(SSI_SCK01239, IP13_23_20)
194
195 /* GPSR7 */
196 #define GPSR7_3 FM(HDMI1_CEC)
197 #define GPSR7_2 FM(HDMI0_CEC)
198 #define GPSR7_1 FM(AVS2)
199 #define GPSR7_0 FM(AVS1)
200
201
202 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
203 #define IP0_3_0 FM(AVB_MDC) F_(0, 0) FM(MSIOF2_SS2_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
204 #define IP0_7_4 FM(AVB_MAGIC) F_(0, 0) FM(MSIOF2_SS1_C) FM(SCK4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
205 #define IP0_11_8 FM(AVB_PHY_INT) F_(0, 0) FM(MSIOF2_SYNC_C) FM(RX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
206 #define IP0_15_12 FM(AVB_LINK) F_(0, 0) FM(MSIOF2_SCK_C) FM(TX4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
207 #define IP0_19_16 FM(AVB_AVTP_MATCH_A) F_(0, 0) FM(MSIOF2_RXD_C) FM(CTS4_N_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
208 #define IP0_23_20 FM(AVB_AVTP_CAPTURE_A) F_(0, 0) FM(MSIOF2_TXD_C) FM(RTS4_N_TANS_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
209 #define IP0_27_24 FM(IRQ0) FM(QPOLB) F_(0, 0) FM(DU_CDE) FM(VI4_DATA0_B) FM(CAN0_TX_B) FM(CANFD0_TX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
210 #define IP0_31_28 FM(IRQ1) FM(QPOLA) F_(0, 0) FM(DU_DISP) FM(VI4_DATA1_B) FM(CAN0_RX_B) FM(CANFD0_RX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
211 #define IP1_3_0 FM(IRQ2) FM(QCPV_QDE) F_(0, 0) FM(DU_EXODDF_DU_ODDF_DISP_CDE) FM(VI4_DATA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
212 #define IP1_7_4 FM(IRQ3) FM(QSTVB_QVE) FM(A25) FM(DU_DOTCLKOUT1) FM(VI4_DATA3_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
213 #define IP1_11_8 FM(IRQ4) FM(QSTH_QHS) FM(A24) FM(DU_EXHSYNC_DU_HSYNC) FM(VI4_DATA4_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
214 #define IP1_15_12 FM(IRQ5) FM(QSTB_QHE) FM(A23) FM(DU_EXVSYNC_DU_VSYNC) FM(VI4_DATA5_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(PWM6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
215 #define IP1_19_16 FM(PWM0) FM(AVB_AVTP_PPS)FM(A22) F_(0, 0) FM(VI4_DATA6_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IECLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
216 #define IP1_23_20 FM(PWM1_A) F_(0, 0) FM(A21) FM(HRX3_D) FM(VI4_DATA7_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IERX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
217 #define IP1_27_24 FM(PWM2_A) F_(0, 0) FM(A20) FM(HTX3_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(IETX_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
218 #define IP1_31_28 FM(A0) FM(LCDOUT16) FM(MSIOF3_SYNC_B) F_(0, 0) FM(VI4_DATA8) F_(0, 0) FM(DU_DB0) F_(0, 0) F_(0, 0) FM(PWM3_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
219 #define IP2_3_0 FM(A1) FM(LCDOUT17) FM(MSIOF3_TXD_B) F_(0, 0) FM(VI4_DATA9) F_(0, 0) FM(DU_DB1) F_(0, 0) F_(0, 0) FM(PWM4_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
220 #define IP2_7_4 FM(A2) FM(LCDOUT18) FM(MSIOF3_SCK_B) F_(0, 0) FM(VI4_DATA10) F_(0, 0) FM(DU_DB2) F_(0, 0) F_(0, 0) FM(PWM5_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
221 #define IP2_11_8 FM(A3) FM(LCDOUT19) FM(MSIOF3_RXD_B) F_(0, 0) FM(VI4_DATA11) F_(0, 0) FM(DU_DB3) F_(0, 0) F_(0, 0) FM(PWM6_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
222
223 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
224 #define IP2_15_12 FM(A4) FM(LCDOUT20) FM(MSIOF3_SS1_B) F_(0, 0) FM(VI4_DATA12) FM(VI5_DATA12) FM(DU_DB4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
225 #define IP2_19_16 FM(A5) FM(LCDOUT21) FM(MSIOF3_SS2_B) FM(SCK4_B) FM(VI4_DATA13) FM(VI5_DATA13) FM(DU_DB5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
226 #define IP2_23_20 FM(A6) FM(LCDOUT22) FM(MSIOF2_SS1_A) FM(RX4_B) FM(VI4_DATA14) FM(VI5_DATA14) FM(DU_DB6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
227 #define IP2_27_24 FM(A7) FM(LCDOUT23) FM(MSIOF2_SS2_A) FM(TX4_B) FM(VI4_DATA15) FM(VI5_DATA15) FM(DU_DB7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
228 #define IP2_31_28 FM(A8) FM(RX3_B) FM(MSIOF2_SYNC_A) FM(HRX4_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA6_A) FM(AVB_AVTP_MATCH_B) FM(PWM1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
229 #define IP3_3_0 FM(A9) F_(0, 0) FM(MSIOF2_SCK_A) FM(CTS4_N_B) F_(0, 0) FM(VI5_VSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
230 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_TANS_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
231 #define IP3_11_8 FM(A11) FM(TX3_B) FM(MSIOF2_TXD_A) FM(HTX4_B) FM(HSCK4) FM(VI5_FIELD) F_(0, 0) FM(SCL6_A) FM(AVB_AVTP_CAPTURE_B) FM(PWM2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
232 #define IP3_15_12 FM(A12) FM(LCDOUT12) FM(MSIOF3_SCK_C) F_(0, 0) FM(HRX4_A) FM(VI5_DATA8) FM(DU_DG4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
233 #define IP3_19_16 FM(A13) FM(LCDOUT13) FM(MSIOF3_SYNC_C) F_(0, 0) FM(HTX4_A) FM(VI5_DATA9) FM(DU_DG5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
234 #define IP3_23_20 FM(A14) FM(LCDOUT14) FM(MSIOF3_RXD_C) F_(0, 0) FM(HCTS4_N) FM(VI5_DATA10) FM(DU_DG6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
235 #define IP3_27_24 FM(A15) FM(LCDOUT15) FM(MSIOF3_TXD_C) F_(0, 0) FM(HRTS4_N) FM(VI5_DATA11) FM(DU_DG7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
236 #define IP3_31_28 FM(A16) FM(LCDOUT8) F_(0, 0) F_(0, 0) FM(VI4_FIELD) F_(0, 0) FM(DU_DG0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
237 #define IP4_3_0 FM(A17) FM(LCDOUT9) F_(0, 0) F_(0, 0) FM(VI4_VSYNC_N) F_(0, 0) FM(DU_DG1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
238 #define IP4_7_4 FM(A18) FM(LCDOUT10) F_(0, 0) F_(0, 0) FM(VI4_HSYNC_N) F_(0, 0) FM(DU_DG2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
239 #define IP4_11_8 FM(A19) FM(LCDOUT11) F_(0, 0) F_(0, 0) FM(VI4_CLKENB) F_(0, 0) FM(DU_DG3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
240 #define IP4_15_12 FM(CS0_N) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLKENB) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
241 #define IP4_19_16 FM(CS1_N_A26) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(VI5_CLK) F_(0, 0) FM(EX_WAIT0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
242 #define IP4_23_20 FM(BS_N) FM(QSTVA_QVS) FM(MSIOF3_SCK_D) FM(SCK3) FM(HSCK3) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN1_TX) FM(CANFD1_TX) FM(IETX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
243 #define IP4_27_24 FM(RD_N) F_(0, 0) FM(MSIOF3_SYNC_D) FM(RX3_A) FM(HRX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_TX_A) FM(CANFD0_TX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
244 #define IP4_31_28 FM(RD_WR_N) F_(0, 0) FM(MSIOF3_RXD_D) FM(TX3_A) FM(HTX3_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(CAN0_RX_A) FM(CANFD0_RX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
245 #define IP5_3_0 FM(WE0_N) F_(0, 0) FM(MSIOF3_TXD_D) FM(CTS3_N) FM(HCTS3_N) F_(0, 0) F_(0, 0) FM(SCL6_B) FM(CAN_CLK) F_(0, 0) FM(IECLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
246 #define IP5_7_4 FM(WE1_N) F_(0, 0) FM(MSIOF3_SS1_D) FM(RTS3_N_TANS) FM(HRTS3_N) F_(0, 0) F_(0, 0) FM(SDA6_B) FM(CAN1_RX) FM(CANFD1_RX) FM(IERX_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
247 #define IP5_11_8 FM(EX_WAIT0_A) FM(QCLK) F_(0, 0) F_(0, 0) FM(VI4_CLK) F_(0, 0) FM(DU_DOTCLKOUT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
248 #define IP5_15_12 FM(D0) FM(MSIOF2_SS1_B)FM(MSIOF3_SCK_A) F_(0, 0) FM(VI4_DATA16) FM(VI5_DATA0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
249 #define IP5_19_16 FM(D1) FM(MSIOF2_SS2_B)FM(MSIOF3_SYNC_A) F_(0, 0) FM(VI4_DATA17) FM(VI5_DATA1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
250 #define IP5_23_20 FM(D2) F_(0, 0) FM(MSIOF3_RXD_A) F_(0, 0) FM(VI4_DATA18) FM(VI5_DATA2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
251 #define IP5_27_24 FM(D3) F_(0, 0) FM(MSIOF3_TXD_A) F_(0, 0) FM(VI4_DATA19) FM(VI5_DATA3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
252 #define IP5_31_28 FM(D4) FM(MSIOF2_SCK_B)F_(0, 0) F_(0, 0) FM(VI4_DATA20) FM(VI5_DATA4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
253 #define IP6_3_0 FM(D5) FM(MSIOF2_SYNC_B)F_(0, 0) F_(0, 0) FM(VI4_DATA21) FM(VI5_DATA5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
254 #define IP6_7_4 FM(D6) FM(MSIOF2_RXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA22) FM(VI5_DATA6) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
255 #define IP6_11_8 FM(D7) FM(MSIOF2_TXD_B)F_(0, 0) F_(0, 0) FM(VI4_DATA23) FM(VI5_DATA7) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
256 #define IP6_15_12 FM(D8) FM(LCDOUT0) FM(MSIOF2_SCK_D) FM(SCK4_C) FM(VI4_DATA0_A) F_(0, 0) FM(DU_DR0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
257 #define IP6_19_16 FM(D9) FM(LCDOUT1) FM(MSIOF2_SYNC_D) F_(0, 0) FM(VI4_DATA1_A) F_(0, 0) FM(DU_DR1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
258 #define IP6_23_20 FM(D10) FM(LCDOUT2) FM(MSIOF2_RXD_D) FM(HRX3_B) FM(VI4_DATA2_A) FM(CTS4_N_C) FM(DU_DR2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
259 #define IP6_27_24 FM(D11) FM(LCDOUT3) FM(MSIOF2_TXD_D) FM(HTX3_B) FM(VI4_DATA3_A) FM(RTS4_N_TANS_C)FM(DU_DR3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
260 #define IP6_31_28 FM(D12) FM(LCDOUT4) FM(MSIOF2_SS1_D) FM(RX4_C) FM(VI4_DATA4_A) F_(0, 0) FM(DU_DR4) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
261 #define IP7_3_0 FM(D13) FM(LCDOUT5) FM(MSIOF2_SS2_D) FM(TX4_C) FM(VI4_DATA5_A) F_(0, 0) FM(DU_DR5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
262 #define IP7_7_4 FM(D14) FM(LCDOUT6) FM(MSIOF3_SS1_A) FM(HRX3_C) FM(VI4_DATA6_A) F_(0, 0) FM(DU_DR6) FM(SCL6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
263 #define IP7_11_8 FM(D15) FM(LCDOUT7) FM(MSIOF3_SS2_A) FM(HTX3_C) FM(VI4_DATA7_A) F_(0, 0) FM(DU_DR7) FM(SDA6_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
264 #define IP7_15_12 FM(FSCLKST) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
265 #define IP7_19_16 FM(SD0_CLK) F_(0, 0) FM(MSIOF1_SCK_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
266
267 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
268 #define IP7_23_20 FM(SD0_CMD) F_(0, 0) FM(MSIOF1_SYNC_E) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
269 #define IP7_27_24 FM(SD0_DAT0) F_(0, 0) FM(MSIOF1_RXD_E) F_(0, 0) F_(0, 0) FM(TS_SCK0_B) FM(STP_ISCLK_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
270 #define IP7_31_28 FM(SD0_DAT1) F_(0, 0) FM(MSIOF1_TXD_E) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_B)FM(STP_ISSYNC_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
271 #define IP8_3_0 FM(SD0_DAT2) F_(0, 0) FM(MSIOF1_SS1_E) F_(0, 0) F_(0, 0) FM(TS_SDAT0_B) FM(STP_ISD_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
272 #define IP8_7_4 FM(SD0_DAT3) F_(0, 0) FM(MSIOF1_SS2_E) F_(0, 0) F_(0, 0) FM(TS_SDEN0_B) FM(STP_ISEN_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
273 #define IP8_11_8 FM(SD1_CLK) F_(0, 0) FM(MSIOF1_SCK_G) F_(0, 0) F_(0, 0) FM(SIM0_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
274 #define IP8_15_12 FM(SD1_CMD) F_(0, 0) FM(MSIOF1_SYNC_G) F_(0, 0) F_(0, 0) FM(SIM0_D_A) FM(STP_IVCXO27_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
275 #define IP8_19_16 FM(SD1_DAT0) FM(SD2_DAT4) FM(MSIOF1_RXD_G) F_(0, 0) F_(0, 0) FM(TS_SCK1_B) FM(STP_ISCLK_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
276 #define IP8_23_20 FM(SD1_DAT1) FM(SD2_DAT5) FM(MSIOF1_TXD_G) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_B)FM(STP_ISSYNC_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
277 #define IP8_27_24 FM(SD1_DAT2) FM(SD2_DAT6) FM(MSIOF1_SS1_G) F_(0, 0) F_(0, 0) FM(TS_SDAT1_B) FM(STP_ISD_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
278 #define IP8_31_28 FM(SD1_DAT3) FM(SD2_DAT7) FM(MSIOF1_SS2_G) F_(0, 0) F_(0, 0) FM(TS_SDEN1_B) FM(STP_ISEN_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
279 #define IP9_3_0 FM(SD2_CLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
280 #define IP9_7_4 FM(SD2_DAT0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
281 #define IP9_11_8 FM(SD2_DAT1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
282 #define IP9_15_12 FM(SD2_DAT2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
283 #define IP9_19_16 FM(SD2_DAT3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
284 #define IP9_23_20 FM(SD2_DS) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
285 #define IP9_27_24 FM(SD3_DAT4) FM(SD2_CD_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
286 #define IP9_31_28 FM(SD3_DAT5) FM(SD2_WP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
287 #define IP10_3_0 FM(SD3_DAT6) FM(SD3_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
288 #define IP10_7_4 FM(SD3_DAT7) FM(SD3_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
289 #define IP10_11_8 FM(SD0_CD) F_(0, 0) F_(0, 0) F_(0, 0) FM(SCL2_B) FM(SIM0_RST_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
290 #define IP10_15_12 FM(SD0_WP) F_(0, 0) F_(0, 0) F_(0, 0) FM(SDA2_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
291 #define IP10_19_16 FM(SD1_CD) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
292 #define IP10_23_20 FM(SD1_WP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SIM0_D_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
293 #define IP10_27_24 FM(SCK0) FM(HSCK1_B) FM(MSIOF1_SS2_B) FM(AUDIO_CLKC_B) FM(SDA2_A) FM(SIM0_RST_B) FM(STP_OPWM_0_C) FM(RIF0_CLK_B) F_(0, 0) FM(ADICHS2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
294 #define IP10_31_28 FM(RX0) FM(HRX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SCK0_C) FM(STP_ISCLK_0_C) FM(RIF0_D0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
295 #define IP11_3_0 FM(TX0) FM(HTX1_B) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_C)FM(STP_ISSYNC_0_C) FM(RIF0_D1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
296 #define IP11_7_4 FM(CTS0_N) FM(HCTS1_N_B) FM(MSIOF1_SYNC_B) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_C)FM(STP_ISSYNC_1_C) FM(RIF1_SYNC_B) FM(AUDIO_CLKOUT_C) FM(ADICS_SAMP) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
297 #define IP11_11_8 FM(RTS0_N_TANS) FM(HRTS1_N_B) FM(MSIOF1_SS1_B) FM(AUDIO_CLKA_B) FM(SCL2_A) F_(0, 0) FM(STP_IVCXO27_1_C) FM(RIF0_SYNC_B) F_(0, 0) FM(ADICHS1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
298 #define IP11_15_12 FM(RX1_A) FM(HRX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDAT0_C) FM(STP_ISD_0_C) FM(RIF1_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
299 #define IP11_19_16 FM(TX1_A) FM(HTX1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(TS_SDEN0_C) FM(STP_ISEN_0_C) FM(RIF1_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
300 #define IP11_23_20 FM(CTS1_N) FM(HCTS1_N_A) FM(MSIOF1_RXD_B) F_(0, 0) F_(0, 0) FM(TS_SDEN1_C) FM(STP_ISEN_1_C) FM(RIF1_D0_B) F_(0, 0) FM(ADIDATA) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
301 #define IP11_27_24 FM(RTS1_N_TANS) FM(HRTS1_N_A) FM(MSIOF1_TXD_B) F_(0, 0) F_(0, 0) FM(TS_SDAT1_C) FM(STP_ISD_1_C) FM(RIF1_D1_B) F_(0, 0) FM(ADICHS0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
302 #define IP11_31_28 FM(SCK2) FM(SCIF_CLK_B) FM(MSIOF1_SCK_B) F_(0, 0) F_(0, 0) FM(TS_SCK1_C) FM(STP_ISCLK_1_C) FM(RIF1_CLK_B) F_(0, 0) FM(ADICLK) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
303 #define IP12_3_0 FM(TX2_A) F_(0, 0) F_(0, 0) FM(SD2_CD_B) FM(SCL1_A) F_(0, 0) FM(FMCLK_A) FM(RIF1_D1_C) F_(0, 0) FM(FSO_CFE_0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
304 #define IP12_7_4 FM(RX2_A) F_(0, 0) F_(0, 0) FM(SD2_WP_B) FM(SDA1_A) F_(0, 0) FM(FMIN_A) FM(RIF1_SYNC_C) F_(0, 0) FM(FSO_CFE_1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
305 #define IP12_11_8 FM(HSCK0) F_(0, 0) FM(MSIOF1_SCK_D) FM(AUDIO_CLKB_A) FM(SSI_SDATA1_B)FM(TS_SCK0_D) FM(STP_ISCLK_0_D) FM(RIF0_CLK_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
306 #define IP12_15_12 FM(HRX0) F_(0, 0) FM(MSIOF1_RXD_D) F_(0, 0) FM(SSI_SDATA2_B)FM(TS_SDEN0_D) FM(STP_ISEN_0_D) FM(RIF0_D0_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
307 #define IP12_19_16 FM(HTX0) F_(0, 0) FM(MSIOF1_TXD_D) F_(0, 0) FM(SSI_SDATA9_B)FM(TS_SDAT0_D) FM(STP_ISD_0_D) FM(RIF0_D1_C) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
308 #define IP12_23_20 FM(HCTS0_N) FM(RX2_B) FM(MSIOF1_SYNC_D) F_(0, 0) FM(SSI_SCK9_A) FM(TS_SPSYNC0_D)FM(STP_ISSYNC_0_D) FM(RIF0_SYNC_C) FM(AUDIO_CLKOUT1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
309 #define IP12_27_24 FM(HRTS0_N) FM(TX2_B) FM(MSIOF1_SS1_D) F_(0, 0) FM(SSI_WS9_A) F_(0, 0) FM(STP_IVCXO27_0_D) FM(BPFCLK_A) FM(AUDIO_CLKOUT2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
310
311 /* IPSRx */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */ /* 8 */ /* 9 */ /* A */ /* B */ /* C - F */
312 #define IP12_31_28 FM(MSIOF0_SYNC) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
313 #define IP13_3_0 FM(MSIOF0_SS1) FM(RX5) F_(0, 0) FM(AUDIO_CLKA_C) FM(SSI_SCK2_A) F_(0, 0) FM(STP_IVCXO27_0_C) F_(0, 0) FM(AUDIO_CLKOUT3_A) F_(0, 0) FM(TCLK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
314 #define IP13_7_4 FM(MSIOF0_SS2) FM(TX5) FM(MSIOF1_SS2_D) FM(AUDIO_CLKC_A) FM(SSI_WS2_A) F_(0, 0) FM(STP_OPWM_0_D) F_(0, 0) FM(AUDIO_CLKOUT_D) F_(0, 0) FM(SPEEDIN_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
315 #define IP13_11_8 FM(MLB_CLK) F_(0, 0) FM(MSIOF1_SCK_F) F_(0, 0) FM(SCL1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
316 #define IP13_15_12 FM(MLB_SIG) FM(RX1_B) FM(MSIOF1_SYNC_F) F_(0, 0) FM(SDA1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
317 #define IP13_19_16 FM(MLB_DAT) FM(TX1_B) FM(MSIOF1_RXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
318 #define IP13_23_20 FM(SSI_SCK01239) F_(0, 0) FM(MSIOF1_TXD_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
319 #define IP13_27_24 FM(SSI_WS01239) F_(0, 0) FM(MSIOF1_SS1_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
320 #define IP13_31_28 FM(SSI_SDATA0) F_(0, 0) FM(MSIOF1_SS2_F) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
321 #define IP14_3_0 FM(SSI_SDATA1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
322 #define IP14_7_4 FM(SSI_SDATA2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(SSI_SCK1_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
323 #define IP14_11_8 FM(SSI_SCK34) F_(0, 0) FM(MSIOF1_SS1_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_OPWM_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
324 #define IP14_15_12 FM(SSI_WS34) FM(HCTS2_N_A) FM(MSIOF1_SS2_A) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
325 #define IP14_19_16 FM(SSI_SDATA3) FM(HRTS2_N_A) FM(MSIOF1_TXD_A) F_(0, 0) F_(0, 0) FM(TS_SCK0_A) FM(STP_ISCLK_0_A) FM(RIF0_D1_A) FM(RIF2_D0_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
326 #define IP14_23_20 FM(SSI_SCK4) FM(HRX2_A) FM(MSIOF1_SCK_A) F_(0, 0) F_(0, 0) FM(TS_SDAT0_A) FM(STP_ISD_0_A) FM(RIF0_CLK_A) FM(RIF2_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
327 #define IP14_27_24 FM(SSI_WS4) FM(HTX2_A) FM(MSIOF1_SYNC_A) F_(0, 0) F_(0, 0) FM(TS_SDEN0_A) FM(STP_ISEN_0_A) FM(RIF0_SYNC_A) FM(RIF2_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
328 #define IP14_31_28 FM(SSI_SDATA4) FM(HSCK2_A) FM(MSIOF1_RXD_A) F_(0, 0) F_(0, 0) FM(TS_SPSYNC0_A)FM(STP_ISSYNC_0_A) FM(RIF0_D0_A) FM(RIF2_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
329 #define IP15_3_0 FM(SSI_SCK6) FM(USB2_PWEN) F_(0, 0) FM(SIM0_RST_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
330 #define IP15_7_4 FM(SSI_WS6) FM(USB2_OVC) F_(0, 0) FM(SIM0_D_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
331 #define IP15_11_8 FM(SSI_SDATA6) F_(0, 0) F_(0, 0) FM(SIM0_CLK_D) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(SATA_DEVSLP_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
332 #define IP15_15_12 FM(SSI_SCK78) FM(HRX2_B) FM(MSIOF1_SCK_C) F_(0, 0) F_(0, 0) FM(TS_SCK1_A) FM(STP_ISCLK_1_A) FM(RIF1_CLK_A) FM(RIF3_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
333 #define IP15_19_16 FM(SSI_WS78) FM(HTX2_B) FM(MSIOF1_SYNC_C) F_(0, 0) F_(0, 0) FM(TS_SDAT1_A) FM(STP_ISD_1_A) FM(RIF1_SYNC_A) FM(RIF3_SYNC_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
334 #define IP15_23_20 FM(SSI_SDATA7) FM(HCTS2_N_B) FM(MSIOF1_RXD_C) F_(0, 0) F_(0, 0) FM(TS_SDEN1_A) FM(STP_ISEN_1_A) FM(RIF1_D0_A) FM(RIF3_D0_A) F_(0, 0) FM(TCLK2_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
335 #define IP15_27_24 FM(SSI_SDATA8) FM(HRTS2_N_B) FM(MSIOF1_TXD_C) F_(0, 0) F_(0, 0) FM(TS_SPSYNC1_A)FM(STP_ISSYNC_1_A) FM(RIF1_D1_A) FM(RIF3_D1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
336 #define IP15_31_28 FM(SSI_SDATA9_A) FM(HSCK2_B) FM(MSIOF1_SS1_C) FM(HSCK1_A) FM(SSI_WS1_B) FM(SCK1) FM(STP_IVCXO27_1_A) FM(SCK5) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
337 #define IP16_3_0 FM(AUDIO_CLKA_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(CC5_OSCOUT) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
338 #define IP16_7_4 FM(AUDIO_CLKB_B) FM(SCIF_CLK_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) FM(STP_IVCXO27_1_D) FM(REMOCON_A) F_(0, 0) F_(0, 0) FM(TCLK1_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
339 #define IP16_11_8 FM(USB0_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_RST_C) F_(0, 0) FM(TS_SCK1_D) FM(STP_ISCLK_1_D) FM(BPFCLK_B) FM(RIF3_CLK_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
340 #define IP16_15_12 FM(USB0_OVC) F_(0, 0) F_(0, 0) FM(SIM0_D_C) F_(0, 0) FM(TS_SDAT1_D) FM(STP_ISD_1_D) F_(0, 0) FM(RIF3_SYNC_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
341 #define IP16_19_16 FM(USB1_PWEN) F_(0, 0) F_(0, 0) FM(SIM0_CLK_C) FM(SSI_SCK1_A) FM(TS_SCK0_E) FM(STP_ISCLK_0_E) FM(FMCLK_B) FM(RIF2_CLK_B) F_(0, 0) FM(SPEEDIN_A) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
342 #define IP16_23_20 FM(USB1_OVC) F_(0, 0) FM(MSIOF1_SS2_C) F_(0, 0) FM(SSI_WS1_A) FM(TS_SDAT0_E) FM(STP_ISD_0_E) FM(FMIN_B) FM(RIF2_SYNC_B) F_(0, 0) FM(REMOCON_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
343 #define IP16_27_24 FM(USB30_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT_B) FM(SSI_SCK2_B) FM(TS_SDEN1_D) FM(STP_ISEN_1_D) FM(STP_OPWM_0_E)FM(RIF3_D0_B) F_(0, 0) FM(TCLK2_B) FM(TPU0TO0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
344 #define IP16_31_28 FM(USB30_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT1_B) FM(SSI_WS2_B) FM(TS_SPSYNC1_D)FM(STP_ISSYNC_1_D) FM(STP_IVCXO27_0_E)FM(RIF3_D1_B) F_(0, 0) FM(FSO_TOE_B) FM(TPU0TO1) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
345 #define IP17_3_0 FM(USB31_PWEN) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT2_B) FM(SSI_SCK9_B) FM(TS_SDEN0_E) FM(STP_ISEN_0_E) F_(0, 0) FM(RIF2_D0_B) F_(0, 0) F_(0, 0) FM(TPU0TO2) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
346 #define IP17_7_4 FM(USB31_OVC) F_(0, 0) F_(0, 0) FM(AUDIO_CLKOUT3_B) FM(SSI_WS9_B) FM(TS_SPSYNC0_E)FM(STP_ISSYNC_0_E) F_(0, 0) FM(RIF2_D1_B) F_(0, 0) F_(0, 0) FM(TPU0TO3) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)
347
348 #define PINMUX_GPSR \
349 \
350 GPSR6_31 \
351 GPSR6_30 \
352 GPSR6_29 \
353 GPSR6_28 \
354 GPSR1_27 GPSR6_27 \
355 GPSR1_26 GPSR6_26 \
356 GPSR1_25 GPSR5_25 GPSR6_25 \
357 GPSR1_24 GPSR5_24 GPSR6_24 \
358 GPSR1_23 GPSR5_23 GPSR6_23 \
359 GPSR1_22 GPSR5_22 GPSR6_22 \
360 GPSR1_21 GPSR5_21 GPSR6_21 \
361 GPSR1_20 GPSR5_20 GPSR6_20 \
362 GPSR1_19 GPSR5_19 GPSR6_19 \
363 GPSR1_18 GPSR5_18 GPSR6_18 \
364 GPSR1_17 GPSR4_17 GPSR5_17 GPSR6_17 \
365 GPSR1_16 GPSR4_16 GPSR5_16 GPSR6_16 \
366 GPSR0_15 GPSR1_15 GPSR3_15 GPSR4_15 GPSR5_15 GPSR6_15 \
367 GPSR0_14 GPSR1_14 GPSR2_14 GPSR3_14 GPSR4_14 GPSR5_14 GPSR6_14 \
368 GPSR0_13 GPSR1_13 GPSR2_13 GPSR3_13 GPSR4_13 GPSR5_13 GPSR6_13 \
369 GPSR0_12 GPSR1_12 GPSR2_12 GPSR3_12 GPSR4_12 GPSR5_12 GPSR6_12 \
370 GPSR0_11 GPSR1_11 GPSR2_11 GPSR3_11 GPSR4_11 GPSR5_11 GPSR6_11 \
371 GPSR0_10 GPSR1_10 GPSR2_10 GPSR3_10 GPSR4_10 GPSR5_10 GPSR6_10 \
372 GPSR0_9 GPSR1_9 GPSR2_9 GPSR3_9 GPSR4_9 GPSR5_9 GPSR6_9 \
373 GPSR0_8 GPSR1_8 GPSR2_8 GPSR3_8 GPSR4_8 GPSR5_8 GPSR6_8 \
374 GPSR0_7 GPSR1_7 GPSR2_7 GPSR3_7 GPSR4_7 GPSR5_7 GPSR6_7 \
375 GPSR0_6 GPSR1_6 GPSR2_6 GPSR3_6 GPSR4_6 GPSR5_6 GPSR6_6 \
376 GPSR0_5 GPSR1_5 GPSR2_5 GPSR3_5 GPSR4_5 GPSR5_5 GPSR6_5 \
377 GPSR0_4 GPSR1_4 GPSR2_4 GPSR3_4 GPSR4_4 GPSR5_4 GPSR6_4 \
378 GPSR0_3 GPSR1_3 GPSR2_3 GPSR3_3 GPSR4_3 GPSR5_3 GPSR6_3 GPSR7_3 \
379 GPSR0_2 GPSR1_2 GPSR2_2 GPSR3_2 GPSR4_2 GPSR5_2 GPSR6_2 GPSR7_2 \
380 GPSR0_1 GPSR1_1 GPSR2_1 GPSR3_1 GPSR4_1 GPSR5_1 GPSR6_1 GPSR7_1 \
381 GPSR0_0 GPSR1_0 GPSR2_0 GPSR3_0 GPSR4_0 GPSR5_0 GPSR6_0 GPSR7_0
382
383 #define PINMUX_IPSR \
384 \
385 FM(IP0_3_0) IP0_3_0 FM(IP1_3_0) IP1_3_0 FM(IP2_3_0) IP2_3_0 FM(IP3_3_0) IP3_3_0 \
386 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
387 FM(IP0_11_8) IP0_11_8 FM(IP1_11_8) IP1_11_8 FM(IP2_11_8) IP2_11_8 FM(IP3_11_8) IP3_11_8 \
388 FM(IP0_15_12) IP0_15_12 FM(IP1_15_12) IP1_15_12 FM(IP2_15_12) IP2_15_12 FM(IP3_15_12) IP3_15_12 \
389 FM(IP0_19_16) IP0_19_16 FM(IP1_19_16) IP1_19_16 FM(IP2_19_16) IP2_19_16 FM(IP3_19_16) IP3_19_16 \
390 FM(IP0_23_20) IP0_23_20 FM(IP1_23_20) IP1_23_20 FM(IP2_23_20) IP2_23_20 FM(IP3_23_20) IP3_23_20 \
391 FM(IP0_27_24) IP0_27_24 FM(IP1_27_24) IP1_27_24 FM(IP2_27_24) IP2_27_24 FM(IP3_27_24) IP3_27_24 \
392 FM(IP0_31_28) IP0_31_28 FM(IP1_31_28) IP1_31_28 FM(IP2_31_28) IP2_31_28 FM(IP3_31_28) IP3_31_28 \
393 \
394 FM(IP4_3_0) IP4_3_0 FM(IP5_3_0) IP5_3_0 FM(IP6_3_0) IP6_3_0 FM(IP7_3_0) IP7_3_0 \
395 FM(IP4_7_4) IP4_7_4 FM(IP5_7_4) IP5_7_4 FM(IP6_7_4) IP6_7_4 FM(IP7_7_4) IP7_7_4 \
396 FM(IP4_11_8) IP4_11_8 FM(IP5_11_8) IP5_11_8 FM(IP6_11_8) IP6_11_8 FM(IP7_11_8) IP7_11_8 \
397 FM(IP4_15_12) IP4_15_12 FM(IP5_15_12) IP5_15_12 FM(IP6_15_12) IP6_15_12 FM(IP7_15_12) IP7_15_12 \
398 FM(IP4_19_16) IP4_19_16 FM(IP5_19_16) IP5_19_16 FM(IP6_19_16) IP6_19_16 FM(IP7_19_16) IP7_19_16 \
399 FM(IP4_23_20) IP4_23_20 FM(IP5_23_20) IP5_23_20 FM(IP6_23_20) IP6_23_20 FM(IP7_23_20) IP7_23_20 \
400 FM(IP4_27_24) IP4_27_24 FM(IP5_27_24) IP5_27_24 FM(IP6_27_24) IP6_27_24 FM(IP7_27_24) IP7_27_24 \
401 FM(IP4_31_28) IP4_31_28 FM(IP5_31_28) IP5_31_28 FM(IP6_31_28) IP6_31_28 FM(IP7_31_28) IP7_31_28 \
402 \
403 FM(IP8_3_0) IP8_3_0 FM(IP9_3_0) IP9_3_0 FM(IP10_3_0) IP10_3_0 FM(IP11_3_0) IP11_3_0 \
404 FM(IP8_7_4) IP8_7_4 FM(IP9_7_4) IP9_7_4 FM(IP10_7_4) IP10_7_4 FM(IP11_7_4) IP11_7_4 \
405 FM(IP8_11_8) IP8_11_8 FM(IP9_11_8) IP9_11_8 FM(IP10_11_8) IP10_11_8 FM(IP11_11_8) IP11_11_8 \
406 FM(IP8_15_12) IP8_15_12 FM(IP9_15_12) IP9_15_12 FM(IP10_15_12) IP10_15_12 FM(IP11_15_12) IP11_15_12 \
407 FM(IP8_19_16) IP8_19_16 FM(IP9_19_16) IP9_19_16 FM(IP10_19_16) IP10_19_16 FM(IP11_19_16) IP11_19_16 \
408 FM(IP8_23_20) IP8_23_20 FM(IP9_23_20) IP9_23_20 FM(IP10_23_20) IP10_23_20 FM(IP11_23_20) IP11_23_20 \
409 FM(IP8_27_24) IP8_27_24 FM(IP9_27_24) IP9_27_24 FM(IP10_27_24) IP10_27_24 FM(IP11_27_24) IP11_27_24 \
410 FM(IP8_31_28) IP8_31_28 FM(IP9_31_28) IP9_31_28 FM(IP10_31_28) IP10_31_28 FM(IP11_31_28) IP11_31_28 \
411 \
412 FM(IP12_3_0) IP12_3_0 FM(IP13_3_0) IP13_3_0 FM(IP14_3_0) IP14_3_0 FM(IP15_3_0) IP15_3_0 \
413 FM(IP12_7_4) IP12_7_4 FM(IP13_7_4) IP13_7_4 FM(IP14_7_4) IP14_7_4 FM(IP15_7_4) IP15_7_4 \
414 FM(IP12_11_8) IP12_11_8 FM(IP13_11_8) IP13_11_8 FM(IP14_11_8) IP14_11_8 FM(IP15_11_8) IP15_11_8 \
415 FM(IP12_15_12) IP12_15_12 FM(IP13_15_12) IP13_15_12 FM(IP14_15_12) IP14_15_12 FM(IP15_15_12) IP15_15_12 \
416 FM(IP12_19_16) IP12_19_16 FM(IP13_19_16) IP13_19_16 FM(IP14_19_16) IP14_19_16 FM(IP15_19_16) IP15_19_16 \
417 FM(IP12_23_20) IP12_23_20 FM(IP13_23_20) IP13_23_20 FM(IP14_23_20) IP14_23_20 FM(IP15_23_20) IP15_23_20 \
418 FM(IP12_27_24) IP12_27_24 FM(IP13_27_24) IP13_27_24 FM(IP14_27_24) IP14_27_24 FM(IP15_27_24) IP15_27_24 \
419 FM(IP12_31_28) IP12_31_28 FM(IP13_31_28) IP13_31_28 FM(IP14_31_28) IP14_31_28 FM(IP15_31_28) IP15_31_28 \
420 \
421 FM(IP16_3_0) IP16_3_0 FM(IP17_3_0) IP17_3_0 \
422 FM(IP16_7_4) IP16_7_4 FM(IP17_7_4) IP17_7_4 \
423 FM(IP16_11_8) IP16_11_8 \
424 FM(IP16_15_12) IP16_15_12 \
425 FM(IP16_19_16) IP16_19_16 \
426 FM(IP16_23_20) IP16_23_20 \
427 FM(IP16_27_24) IP16_27_24 \
428 FM(IP16_31_28) IP16_31_28
429
430 /* MOD_SEL0 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
431 #define MOD_SEL0_30_29 FM(SEL_MSIOF3_0) FM(SEL_MSIOF3_1) FM(SEL_MSIOF3_2) FM(SEL_MSIOF3_3)
432 #define MOD_SEL0_28_27 FM(SEL_MSIOF2_0) FM(SEL_MSIOF2_1) FM(SEL_MSIOF2_2) FM(SEL_MSIOF2_3)
433 #define MOD_SEL0_26_25_24 FM(SEL_MSIOF1_0) FM(SEL_MSIOF1_1) FM(SEL_MSIOF1_2) FM(SEL_MSIOF1_3) FM(SEL_MSIOF1_4) FM(SEL_MSIOF1_5) FM(SEL_MSIOF1_6) F_(0, 0)
434 #define MOD_SEL0_23 FM(SEL_LBSC_0) FM(SEL_LBSC_1)
435 #define MOD_SEL0_22 FM(SEL_IEBUS_0) FM(SEL_IEBUS_1)
436 #define MOD_SEL0_21_20 FM(SEL_I2C6_0) FM(SEL_I2C6_1) FM(SEL_I2C6_2) F_(0, 0)
437 #define MOD_SEL0_19 FM(SEL_I2C2_0) FM(SEL_I2C2_1)
438 #define MOD_SEL0_18 FM(SEL_I2C1_0) FM(SEL_I2C1_1)
439 #define MOD_SEL0_17 FM(SEL_HSCIF4_0) FM(SEL_HSCIF4_1)
440 #define MOD_SEL0_16_15 FM(SEL_HSCIF3_0) FM(SEL_HSCIF3_1) FM(SEL_HSCIF3_2) FM(SEL_HSCIF3_3)
441 #define MOD_SEL0_14 FM(SEL_HSCIF2_0) FM(SEL_HSCIF2_1)
442 #define MOD_SEL0_13 FM(SEL_HSCIF1_0) FM(SEL_HSCIF1_1)
443 #define MOD_SEL0_12 FM(SEL_FSO_0) FM(SEL_FSO_1)
444 #define MOD_SEL0_11 FM(SEL_FM_0) FM(SEL_FM_1)
445 #define MOD_SEL0_10 FM(SEL_ETHERAVB_0) FM(SEL_ETHERAVB_1)
446 #define MOD_SEL0_9 FM(SEL_DRIF3_0) FM(SEL_DRIF3_1)
447 #define MOD_SEL0_8 FM(SEL_DRIF2_0) FM(SEL_DRIF2_1)
448 #define MOD_SEL0_7_6 FM(SEL_DRIF1_0) FM(SEL_DRIF1_1) FM(SEL_DRIF1_2) F_(0, 0)
449 #define MOD_SEL0_5_4 FM(SEL_DRIF0_0) FM(SEL_DRIF0_1) FM(SEL_DRIF0_2) F_(0, 0)
450 #define MOD_SEL0_3 FM(SEL_CANFD0_0) FM(SEL_CANFD0_1)
451 #define MOD_SEL0_2_1 FM(SEL_ADG_0) FM(SEL_ADG_1) FM(SEL_ADG_2) FM(SEL_ADG_3)
452
453 /* MOD_SEL1 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */ /* 4 */ /* 5 */ /* 6 */ /* 7 */
454 #define MOD_SEL1_31_30 FM(SEL_TSIF1_0) FM(SEL_TSIF1_1) FM(SEL_TSIF1_2) FM(SEL_TSIF1_3)
455 #define MOD_SEL1_29_28_27 FM(SEL_TSIF0_0) FM(SEL_TSIF0_1) FM(SEL_TSIF0_2) FM(SEL_TSIF0_3) FM(SEL_TSIF0_4) F_(0, 0) F_(0, 0) F_(0, 0)
456 #define MOD_SEL1_26 FM(SEL_TIMER_TMU_0) FM(SEL_TIMER_TMU_1)
457 #define MOD_SEL1_25_24 FM(SEL_SSP1_1_0) FM(SEL_SSP1_1_1) FM(SEL_SSP1_1_2) FM(SEL_SSP1_1_3)
458 #define MOD_SEL1_23_22_21 FM(SEL_SSP1_0_0) FM(SEL_SSP1_0_1) FM(SEL_SSP1_0_2) FM(SEL_SSP1_0_3) FM(SEL_SSP1_0_4) F_(0, 0) F_(0, 0) F_(0, 0)
459 #define MOD_SEL1_20 FM(SEL_SSI_0) FM(SEL_SSI_1)
460 #define MOD_SEL1_19 FM(SEL_SPEED_PULSE_0) FM(SEL_SPEED_PULSE_1)
461 #define MOD_SEL1_18_17 FM(SEL_SIMCARD_0) FM(SEL_SIMCARD_1) FM(SEL_SIMCARD_2) FM(SEL_SIMCARD_3)
462 #define MOD_SEL1_16 FM(SEL_SDHI2_0) FM(SEL_SDHI2_1)
463 #define MOD_SEL1_15_14 FM(SEL_SCIF4_0) FM(SEL_SCIF4_1) FM(SEL_SCIF4_2) F_(0, 0)
464 #define MOD_SEL1_13 FM(SEL_SCIF3_0) FM(SEL_SCIF3_1)
465 #define MOD_SEL1_12 FM(SEL_SCIF2_0) FM(SEL_SCIF2_1)
466 #define MOD_SEL1_11 FM(SEL_SCIF1_0) FM(SEL_SCIF1_1)
467 #define MOD_SEL1_10 FM(SEL_SATA_0) FM(SEL_SATA_1)
468 #define MOD_SEL1_9 FM(SEL_REMOCON_0) FM(SEL_REMOCON_1)
469 #define MOD_SEL1_6 FM(SEL_RCAN0_0) FM(SEL_RCAN0_1)
470 #define MOD_SEL1_5 FM(SEL_PWM6_0) FM(SEL_PWM6_1)
471 #define MOD_SEL1_4 FM(SEL_PWM5_0) FM(SEL_PWM5_1)
472 #define MOD_SEL1_3 FM(SEL_PWM4_0) FM(SEL_PWM4_1)
473 #define MOD_SEL1_2 FM(SEL_PWM3_0) FM(SEL_PWM3_1)
474 #define MOD_SEL1_1 FM(SEL_PWM2_0) FM(SEL_PWM2_1)
475 #define MOD_SEL1_0 FM(SEL_PWM1_0) FM(SEL_PWM1_1)
476
477 /* MOD_SEL2 */ /* 0 */ /* 1 */ /* 2 */ /* 3 */
478 #define MOD_SEL2_31 FM(I2C_SEL_5_0) FM(I2C_SEL_5_1)
479 #define MOD_SEL2_30 FM(I2C_SEL_3_0) FM(I2C_SEL_3_1)
480 #define MOD_SEL2_29 FM(I2C_SEL_0_0) FM(I2C_SEL_0_1)
481 #define MOD_SEL2_0 FM(SEL_VIN4_0) FM(SEL_VIN4_1)
482
483 #define PINMUX_MOD_SELS\
484 \
485 MOD_SEL1_31_30 MOD_SEL2_31 \
486 MOD_SEL0_30_29 MOD_SEL2_30 \
487 MOD_SEL1_29_28_27 MOD_SEL2_29 \
488 MOD_SEL0_28_27 \
489 \
490 MOD_SEL0_26_25_24 MOD_SEL1_26 \
491 MOD_SEL1_25_24 \
492 \
493 MOD_SEL0_23 MOD_SEL1_23_22_21 \
494 MOD_SEL0_22 \
495 MOD_SEL0_21_20 \
496 MOD_SEL1_20 \
497 MOD_SEL0_19 MOD_SEL1_19 \
498 MOD_SEL0_18 MOD_SEL1_18_17 \
499 MOD_SEL0_17 \
500 MOD_SEL0_16_15 MOD_SEL1_16 \
501 MOD_SEL1_15_14 \
502 MOD_SEL0_14 \
503 MOD_SEL0_13 MOD_SEL1_13 \
504 MOD_SEL0_12 MOD_SEL1_12 \
505 MOD_SEL0_11 MOD_SEL1_11 \
506 MOD_SEL0_10 MOD_SEL1_10 \
507 MOD_SEL0_9 MOD_SEL1_9 \
508 MOD_SEL0_8 \
509 MOD_SEL0_7_6 \
510 MOD_SEL1_6 \
511 MOD_SEL0_5_4 MOD_SEL1_5 \
512 MOD_SEL1_4 \
513 MOD_SEL0_3 MOD_SEL1_3 \
514 MOD_SEL0_2_1 MOD_SEL1_2 \
515 MOD_SEL1_1 \
516 MOD_SEL1_0 MOD_SEL2_0
517
518
519 enum {
520 PINMUX_RESERVED = 0,
521
522 PINMUX_DATA_BEGIN,
523 GP_ALL(DATA),
524 PINMUX_DATA_END,
525
526 #define F_(x, y)
527 #define FM(x) FN_##x,
528 PINMUX_FUNCTION_BEGIN,
529 GP_ALL(FN),
530 PINMUX_GPSR
531 PINMUX_IPSR
532 PINMUX_MOD_SELS
533 PINMUX_FUNCTION_END,
534 #undef F_
535 #undef FM
536
537 #define F_(x, y)
538 #define FM(x) x##_MARK,
539 PINMUX_MARK_BEGIN,
540 PINMUX_GPSR
541 PINMUX_IPSR
542 PINMUX_MOD_SELS
543 PINMUX_MARK_END,
544 #undef F_
545 #undef FM
546 };
547
548 static const u16 pinmux_data[] = {
549 PINMUX_DATA_GP_ALL(),
550
551 PINMUX_SINGLE(AVS1),
552 PINMUX_SINGLE(AVS2),
553 PINMUX_SINGLE(HDMI0_CEC),
554 PINMUX_SINGLE(HDMI1_CEC),
555 PINMUX_SINGLE(MSIOF0_RXD),
556 PINMUX_SINGLE(MSIOF0_SCK),
557 PINMUX_SINGLE(MSIOF0_TXD),
558 PINMUX_SINGLE(SD2_CMD),
559 PINMUX_SINGLE(SD3_CLK),
560 PINMUX_SINGLE(SD3_CMD),
561 PINMUX_SINGLE(SD3_DAT0),
562 PINMUX_SINGLE(SD3_DAT1),
563 PINMUX_SINGLE(SD3_DAT2),
564 PINMUX_SINGLE(SD3_DAT3),
565 PINMUX_SINGLE(SD3_DS),
566 PINMUX_SINGLE(SSI_SCK5),
567 PINMUX_SINGLE(SSI_SDATA5),
568 PINMUX_SINGLE(SSI_WS5),
569
570 /* IPSR0 */
571 PINMUX_IPSR_GPSR(IP0_3_0, AVB_MDC),
572 PINMUX_IPSR_MSEL(IP0_3_0, MSIOF2_SS2_C, SEL_MSIOF2_2),
573
574 PINMUX_IPSR_GPSR(IP0_7_4, AVB_MAGIC),
575 PINMUX_IPSR_MSEL(IP0_7_4, MSIOF2_SS1_C, SEL_MSIOF2_2),
576 PINMUX_IPSR_MSEL(IP0_7_4, SCK4_A, SEL_SCIF4_0),
577
578 PINMUX_IPSR_GPSR(IP0_11_8, AVB_PHY_INT),
579 PINMUX_IPSR_MSEL(IP0_11_8, MSIOF2_SYNC_C, SEL_MSIOF2_2),
580 PINMUX_IPSR_MSEL(IP0_11_8, RX4_A, SEL_SCIF4_0),
581
582 PINMUX_IPSR_GPSR(IP0_15_12, AVB_LINK),
583 PINMUX_IPSR_MSEL(IP0_15_12, MSIOF2_SCK_C, SEL_MSIOF2_2),
584 PINMUX_IPSR_MSEL(IP0_15_12, TX4_A, SEL_SCIF4_0),
585
586 PINMUX_IPSR_MSEL(IP0_19_16, AVB_AVTP_MATCH_A, SEL_ETHERAVB_0),
587 PINMUX_IPSR_MSEL(IP0_19_16, MSIOF2_RXD_C, SEL_MSIOF2_2),
588 PINMUX_IPSR_MSEL(IP0_19_16, CTS4_N_A, SEL_SCIF4_0),
589
590 PINMUX_IPSR_MSEL(IP0_23_20, AVB_AVTP_CAPTURE_A, SEL_ETHERAVB_0),
591 PINMUX_IPSR_MSEL(IP0_23_20, MSIOF2_TXD_C, SEL_MSIOF2_2),
592 PINMUX_IPSR_MSEL(IP0_23_20, RTS4_N_TANS_A, SEL_SCIF4_0),
593
594 PINMUX_IPSR_GPSR(IP0_27_24, IRQ0),
595 PINMUX_IPSR_GPSR(IP0_27_24, QPOLB),
596 PINMUX_IPSR_GPSR(IP0_27_24, DU_CDE),
597 PINMUX_IPSR_MSEL(IP0_27_24, VI4_DATA0_B, SEL_VIN4_1),
598 PINMUX_IPSR_MSEL(IP0_27_24, CAN0_TX_B, SEL_RCAN0_1),
599 PINMUX_IPSR_MSEL(IP0_27_24, CANFD0_TX_B, SEL_CANFD0_1),
600
601 PINMUX_IPSR_GPSR(IP0_31_28, IRQ1),
602 PINMUX_IPSR_GPSR(IP0_31_28, QPOLA),
603 PINMUX_IPSR_GPSR(IP0_31_28, DU_DISP),
604 PINMUX_IPSR_MSEL(IP0_31_28, VI4_DATA1_B, SEL_VIN4_1),
605 PINMUX_IPSR_MSEL(IP0_31_28, CAN0_RX_B, SEL_RCAN0_1),
606 PINMUX_IPSR_MSEL(IP0_31_28, CANFD0_RX_B, SEL_CANFD0_1),
607
608 /* IPSR1 */
609 PINMUX_IPSR_GPSR(IP1_3_0, IRQ2),
610 PINMUX_IPSR_GPSR(IP1_3_0, QCPV_QDE),
611 PINMUX_IPSR_GPSR(IP1_3_0, DU_EXODDF_DU_ODDF_DISP_CDE),
612 PINMUX_IPSR_MSEL(IP1_3_0, VI4_DATA2_B, SEL_VIN4_1),
613 PINMUX_IPSR_MSEL(IP1_3_0, PWM3_B, SEL_PWM3_1),
614
615 PINMUX_IPSR_GPSR(IP1_7_4, IRQ3),
616 PINMUX_IPSR_GPSR(IP1_7_4, QSTVB_QVE),
617 PINMUX_IPSR_GPSR(IP1_7_4, A25),
618 PINMUX_IPSR_GPSR(IP1_7_4, DU_DOTCLKOUT1),
619 PINMUX_IPSR_MSEL(IP1_7_4, VI4_DATA3_B, SEL_VIN4_1),
620 PINMUX_IPSR_MSEL(IP1_7_4, PWM4_B, SEL_PWM4_1),
621
622 PINMUX_IPSR_GPSR(IP1_11_8, IRQ4),
623 PINMUX_IPSR_GPSR(IP1_11_8, QSTH_QHS),
624 PINMUX_IPSR_GPSR(IP1_11_8, A24),
625 PINMUX_IPSR_GPSR(IP1_11_8, DU_EXHSYNC_DU_HSYNC),
626 PINMUX_IPSR_MSEL(IP1_11_8, VI4_DATA4_B, SEL_VIN4_1),
627 PINMUX_IPSR_MSEL(IP1_11_8, PWM5_B, SEL_PWM5_1),
628
629 PINMUX_IPSR_GPSR(IP1_15_12, IRQ5),
630 PINMUX_IPSR_GPSR(IP1_15_12, QSTB_QHE),
631 PINMUX_IPSR_GPSR(IP1_15_12, A23),
632 PINMUX_IPSR_GPSR(IP1_15_12, DU_EXVSYNC_DU_VSYNC),
633 PINMUX_IPSR_MSEL(IP1_15_12, VI4_DATA5_B, SEL_VIN4_1),
634 PINMUX_IPSR_MSEL(IP1_15_12, PWM6_B, SEL_PWM6_1),
635
636 PINMUX_IPSR_GPSR(IP1_19_16, PWM0),
637 PINMUX_IPSR_GPSR(IP1_19_16, AVB_AVTP_PPS),
638 PINMUX_IPSR_GPSR(IP1_19_16, A22),
639 PINMUX_IPSR_MSEL(IP1_19_16, VI4_DATA6_B, SEL_VIN4_1),
640 PINMUX_IPSR_MSEL(IP1_19_16, IECLK_B, SEL_IEBUS_1),
641
642 PINMUX_IPSR_MSEL(IP1_23_20, PWM1_A, SEL_PWM1_0),
643 PINMUX_IPSR_GPSR(IP1_23_20, A21),
644 PINMUX_IPSR_MSEL(IP1_23_20, HRX3_D, SEL_HSCIF3_3),
645 PINMUX_IPSR_MSEL(IP1_23_20, VI4_DATA7_B, SEL_VIN4_1),
646 PINMUX_IPSR_MSEL(IP1_23_20, IERX_B, SEL_IEBUS_1),
647
648 PINMUX_IPSR_MSEL(IP1_27_24, PWM2_A, SEL_PWM2_0),
649 PINMUX_IPSR_GPSR(IP1_27_24, A20),
650 PINMUX_IPSR_MSEL(IP1_27_24, HTX3_D, SEL_HSCIF3_3),
651 PINMUX_IPSR_MSEL(IP1_27_24, IETX_B, SEL_IEBUS_1),
652
653 PINMUX_IPSR_GPSR(IP1_31_28, A0),
654 PINMUX_IPSR_GPSR(IP1_31_28, LCDOUT16),
655 PINMUX_IPSR_MSEL(IP1_31_28, MSIOF3_SYNC_B, SEL_MSIOF3_1),
656 PINMUX_IPSR_GPSR(IP1_31_28, VI4_DATA8),
657 PINMUX_IPSR_GPSR(IP1_31_28, DU_DB0),
658 PINMUX_IPSR_MSEL(IP1_31_28, PWM3_A, SEL_PWM3_0),
659
660 /* IPSR2 */
661 PINMUX_IPSR_GPSR(IP2_3_0, A1),
662 PINMUX_IPSR_GPSR(IP2_3_0, LCDOUT17),
663 PINMUX_IPSR_MSEL(IP2_3_0, MSIOF3_TXD_B, SEL_MSIOF3_1),
664 PINMUX_IPSR_GPSR(IP2_3_0, VI4_DATA9),
665 PINMUX_IPSR_GPSR(IP2_3_0, DU_DB1),
666 PINMUX_IPSR_MSEL(IP2_3_0, PWM4_A, SEL_PWM4_0),
667
668 PINMUX_IPSR_GPSR(IP2_7_4, A2),
669 PINMUX_IPSR_GPSR(IP2_7_4, LCDOUT18),
670 PINMUX_IPSR_MSEL(IP2_7_4, MSIOF3_SCK_B, SEL_MSIOF3_1),
671 PINMUX_IPSR_GPSR(IP2_7_4, VI4_DATA10),
672 PINMUX_IPSR_GPSR(IP2_7_4, DU_DB2),
673 PINMUX_IPSR_MSEL(IP2_7_4, PWM5_A, SEL_PWM5_0),
674
675 PINMUX_IPSR_GPSR(IP2_11_8, A3),
676 PINMUX_IPSR_GPSR(IP2_11_8, LCDOUT19),
677 PINMUX_IPSR_MSEL(IP2_11_8, MSIOF3_RXD_B, SEL_MSIOF3_1),
678 PINMUX_IPSR_GPSR(IP2_11_8, VI4_DATA11),
679 PINMUX_IPSR_GPSR(IP2_11_8, DU_DB3),
680 PINMUX_IPSR_MSEL(IP2_11_8, PWM6_A, SEL_PWM6_0),
681
682 PINMUX_IPSR_GPSR(IP2_15_12, A4),
683 PINMUX_IPSR_GPSR(IP2_15_12, LCDOUT20),
684 PINMUX_IPSR_MSEL(IP2_15_12, MSIOF3_SS1_B, SEL_MSIOF3_1),
685 PINMUX_IPSR_GPSR(IP2_15_12, VI4_DATA12),
686 PINMUX_IPSR_GPSR(IP2_15_12, VI5_DATA12),
687 PINMUX_IPSR_GPSR(IP2_15_12, DU_DB4),
688
689 PINMUX_IPSR_GPSR(IP2_19_16, A5),
690 PINMUX_IPSR_GPSR(IP2_19_16, LCDOUT21),
691 PINMUX_IPSR_MSEL(IP2_19_16, MSIOF3_SS2_B, SEL_MSIOF3_1),
692 PINMUX_IPSR_MSEL(IP2_19_16, SCK4_B, SEL_SCIF4_1),
693 PINMUX_IPSR_GPSR(IP2_19_16, VI4_DATA13),
694 PINMUX_IPSR_GPSR(IP2_19_16, VI5_DATA13),
695 PINMUX_IPSR_GPSR(IP2_19_16, DU_DB5),
696
697 PINMUX_IPSR_GPSR(IP2_23_20, A6),
698 PINMUX_IPSR_GPSR(IP2_23_20, LCDOUT22),
699 PINMUX_IPSR_MSEL(IP2_23_20, MSIOF2_SS1_A, SEL_MSIOF2_0),
700 PINMUX_IPSR_MSEL(IP2_23_20, RX4_B, SEL_SCIF4_1),
701 PINMUX_IPSR_GPSR(IP2_23_20, VI4_DATA14),
702 PINMUX_IPSR_GPSR(IP2_23_20, VI5_DATA14),
703 PINMUX_IPSR_GPSR(IP2_23_20, DU_DB6),
704
705 PINMUX_IPSR_GPSR(IP2_27_24, A7),
706 PINMUX_IPSR_GPSR(IP2_27_24, LCDOUT23),
707 PINMUX_IPSR_MSEL(IP2_27_24, MSIOF2_SS2_A, SEL_MSIOF2_0),
708 PINMUX_IPSR_MSEL(IP2_27_24, TX4_B, SEL_SCIF4_1),
709 PINMUX_IPSR_GPSR(IP2_27_24, VI4_DATA15),
710 PINMUX_IPSR_GPSR(IP2_27_24, VI5_DATA15),
711 PINMUX_IPSR_GPSR(IP2_27_24, DU_DB7),
712
713 PINMUX_IPSR_GPSR(IP2_31_28, A8),
714 PINMUX_IPSR_MSEL(IP2_31_28, RX3_B, SEL_SCIF3_1),
715 PINMUX_IPSR_MSEL(IP2_31_28, MSIOF2_SYNC_A, SEL_MSIOF2_0),
716 PINMUX_IPSR_MSEL(IP2_31_28, HRX4_B, SEL_HSCIF4_1),
717 PINMUX_IPSR_MSEL(IP2_31_28, SDA6_A, SEL_I2C6_0),
718 PINMUX_IPSR_MSEL(IP2_31_28, AVB_AVTP_MATCH_B, SEL_ETHERAVB_1),
719 PINMUX_IPSR_MSEL(IP2_31_28, PWM1_B, SEL_PWM1_1),
720
721 /* IPSR3 */
722 PINMUX_IPSR_GPSR(IP3_3_0, A9),
723 PINMUX_IPSR_MSEL(IP3_3_0, MSIOF2_SCK_A, SEL_MSIOF2_0),
724 PINMUX_IPSR_MSEL(IP3_3_0, CTS4_N_B, SEL_SCIF4_1),
725 PINMUX_IPSR_GPSR(IP3_3_0, VI5_VSYNC_N),
726
727 PINMUX_IPSR_GPSR(IP3_7_4, A10),
728 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
729 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_TANS_B, SEL_SCIF4_1),
730 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
731
732 PINMUX_IPSR_GPSR(IP3_11_8, A11),
733 PINMUX_IPSR_MSEL(IP3_11_8, TX3_B, SEL_SCIF3_1),
734 PINMUX_IPSR_MSEL(IP3_11_8, MSIOF2_TXD_A, SEL_MSIOF2_0),
735 PINMUX_IPSR_MSEL(IP3_11_8, HTX4_B, SEL_HSCIF4_1),
736 PINMUX_IPSR_GPSR(IP3_11_8, HSCK4),
737 PINMUX_IPSR_GPSR(IP3_11_8, VI5_FIELD),
738 PINMUX_IPSR_MSEL(IP3_11_8, SCL6_A, SEL_I2C6_0),
739 PINMUX_IPSR_MSEL(IP3_11_8, AVB_AVTP_CAPTURE_B, SEL_ETHERAVB_1),
740 PINMUX_IPSR_MSEL(IP3_11_8, PWM2_B, SEL_PWM2_1),
741
742 PINMUX_IPSR_GPSR(IP3_15_12, A12),
743 PINMUX_IPSR_GPSR(IP3_15_12, LCDOUT12),
744 PINMUX_IPSR_MSEL(IP3_15_12, MSIOF3_SCK_C, SEL_MSIOF3_2),
745 PINMUX_IPSR_MSEL(IP3_15_12, HRX4_A, SEL_HSCIF4_0),
746 PINMUX_IPSR_GPSR(IP3_15_12, VI5_DATA8),
747 PINMUX_IPSR_GPSR(IP3_15_12, DU_DG4),
748
749 PINMUX_IPSR_GPSR(IP3_19_16, A13),
750 PINMUX_IPSR_GPSR(IP3_19_16, LCDOUT13),
751 PINMUX_IPSR_MSEL(IP3_19_16, MSIOF3_SYNC_C, SEL_MSIOF3_2),
752 PINMUX_IPSR_MSEL(IP3_19_16, HTX4_A, SEL_HSCIF4_0),
753 PINMUX_IPSR_GPSR(IP3_19_16, VI5_DATA9),
754 PINMUX_IPSR_GPSR(IP3_19_16, DU_DG5),
755
756 PINMUX_IPSR_GPSR(IP3_23_20, A14),
757 PINMUX_IPSR_GPSR(IP3_23_20, LCDOUT14),
758 PINMUX_IPSR_MSEL(IP3_23_20, MSIOF3_RXD_C, SEL_MSIOF3_2),
759 PINMUX_IPSR_GPSR(IP3_23_20, HCTS4_N),
760 PINMUX_IPSR_GPSR(IP3_23_20, VI5_DATA10),
761 PINMUX_IPSR_GPSR(IP3_23_20, DU_DG6),
762
763 PINMUX_IPSR_GPSR(IP3_27_24, A15),
764 PINMUX_IPSR_GPSR(IP3_27_24, LCDOUT15),
765 PINMUX_IPSR_MSEL(IP3_27_24, MSIOF3_TXD_C, SEL_MSIOF3_2),
766 PINMUX_IPSR_GPSR(IP3_27_24, HRTS4_N),
767 PINMUX_IPSR_GPSR(IP3_27_24, VI5_DATA11),
768 PINMUX_IPSR_GPSR(IP3_27_24, DU_DG7),
769
770 PINMUX_IPSR_GPSR(IP3_31_28, A16),
771 PINMUX_IPSR_GPSR(IP3_31_28, LCDOUT8),
772 PINMUX_IPSR_GPSR(IP3_31_28, VI4_FIELD),
773 PINMUX_IPSR_GPSR(IP3_31_28, DU_DG0),
774
775 /* IPSR4 */
776 PINMUX_IPSR_GPSR(IP4_3_0, A17),
777 PINMUX_IPSR_GPSR(IP4_3_0, LCDOUT9),
778 PINMUX_IPSR_GPSR(IP4_3_0, VI4_VSYNC_N),
779 PINMUX_IPSR_GPSR(IP4_3_0, DU_DG1),
780
781 PINMUX_IPSR_GPSR(IP4_7_4, A18),
782 PINMUX_IPSR_GPSR(IP4_7_4, LCDOUT10),
783 PINMUX_IPSR_GPSR(IP4_7_4, VI4_HSYNC_N),
784 PINMUX_IPSR_GPSR(IP4_7_4, DU_DG2),
785
786 PINMUX_IPSR_GPSR(IP4_11_8, A19),
787 PINMUX_IPSR_GPSR(IP4_11_8, LCDOUT11),
788 PINMUX_IPSR_GPSR(IP4_11_8, VI4_CLKENB),
789 PINMUX_IPSR_GPSR(IP4_11_8, DU_DG3),
790
791 PINMUX_IPSR_GPSR(IP4_15_12, CS0_N),
792 PINMUX_IPSR_GPSR(IP4_15_12, VI5_CLKENB),
793
794 PINMUX_IPSR_GPSR(IP4_19_16, CS1_N_A26),
795 PINMUX_IPSR_GPSR(IP4_19_16, VI5_CLK),
796 PINMUX_IPSR_MSEL(IP4_19_16, EX_WAIT0_B, SEL_LBSC_1),
797
798 PINMUX_IPSR_GPSR(IP4_23_20, BS_N),
799 PINMUX_IPSR_GPSR(IP4_23_20, QSTVA_QVS),
800 PINMUX_IPSR_MSEL(IP4_23_20, MSIOF3_SCK_D, SEL_MSIOF3_3),
801 PINMUX_IPSR_GPSR(IP4_23_20, SCK3),
802 PINMUX_IPSR_GPSR(IP4_23_20, HSCK3),
803 PINMUX_IPSR_GPSR(IP4_23_20, CAN1_TX),
804 PINMUX_IPSR_GPSR(IP4_23_20, CANFD1_TX),
805 PINMUX_IPSR_MSEL(IP4_23_20, IETX_A, SEL_IEBUS_0),
806
807 PINMUX_IPSR_GPSR(IP4_27_24, RD_N),
808 PINMUX_IPSR_MSEL(IP4_27_24, MSIOF3_SYNC_D, SEL_MSIOF3_3),
809 PINMUX_IPSR_MSEL(IP4_27_24, RX3_A, SEL_SCIF3_0),
810 PINMUX_IPSR_MSEL(IP4_27_24, HRX3_A, SEL_HSCIF3_0),
811 PINMUX_IPSR_MSEL(IP4_27_24, CAN0_TX_A, SEL_RCAN0_0),
812 PINMUX_IPSR_MSEL(IP4_27_24, CANFD0_TX_A, SEL_CANFD0_0),
813
814 PINMUX_IPSR_GPSR(IP4_31_28, RD_WR_N),
815 PINMUX_IPSR_MSEL(IP4_31_28, MSIOF3_RXD_D, SEL_MSIOF3_3),
816 PINMUX_IPSR_MSEL(IP4_31_28, TX3_A, SEL_SCIF3_0),
817 PINMUX_IPSR_MSEL(IP4_31_28, HTX3_A, SEL_HSCIF3_0),
818 PINMUX_IPSR_MSEL(IP4_31_28, CAN0_RX_A, SEL_RCAN0_0),
819 PINMUX_IPSR_MSEL(IP4_31_28, CANFD0_RX_A, SEL_CANFD0_0),
820
821 /* IPSR5 */
822 PINMUX_IPSR_GPSR(IP5_3_0, WE0_N),
823 PINMUX_IPSR_MSEL(IP5_3_0, MSIOF3_TXD_D, SEL_MSIOF3_3),
824 PINMUX_IPSR_GPSR(IP5_3_0, CTS3_N),
825 PINMUX_IPSR_GPSR(IP5_3_0, HCTS3_N),
826 PINMUX_IPSR_MSEL(IP5_3_0, SCL6_B, SEL_I2C6_1),
827 PINMUX_IPSR_GPSR(IP5_3_0, CAN_CLK),
828 PINMUX_IPSR_MSEL(IP5_3_0, IECLK_A, SEL_IEBUS_0),
829
830 PINMUX_IPSR_GPSR(IP5_7_4, WE1_N),
831 PINMUX_IPSR_MSEL(IP5_7_4, MSIOF3_SS1_D, SEL_MSIOF3_3),
832 PINMUX_IPSR_GPSR(IP5_7_4, RTS3_N_TANS),
833 PINMUX_IPSR_GPSR(IP5_7_4, HRTS3_N),
834 PINMUX_IPSR_MSEL(IP5_7_4, SDA6_B, SEL_I2C6_1),
835 PINMUX_IPSR_GPSR(IP5_7_4, CAN1_RX),
836 PINMUX_IPSR_GPSR(IP5_7_4, CANFD1_RX),
837 PINMUX_IPSR_MSEL(IP5_7_4, IERX_A, SEL_IEBUS_0),
838
839 PINMUX_IPSR_MSEL(IP5_11_8, EX_WAIT0_A, SEL_LBSC_0),
840 PINMUX_IPSR_GPSR(IP5_11_8, QCLK),
841 PINMUX_IPSR_GPSR(IP5_11_8, VI4_CLK),
842 PINMUX_IPSR_GPSR(IP5_11_8, DU_DOTCLKOUT0),
843
844 PINMUX_IPSR_GPSR(IP5_15_12, D0),
845 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF2_SS1_B, SEL_MSIOF2_1),
846 PINMUX_IPSR_MSEL(IP5_15_12, MSIOF3_SCK_A, SEL_MSIOF3_0),
847 PINMUX_IPSR_GPSR(IP5_15_12, VI4_DATA16),
848 PINMUX_IPSR_GPSR(IP5_15_12, VI5_DATA0),
849
850 PINMUX_IPSR_GPSR(IP5_19_16, D1),
851 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF2_SS2_B, SEL_MSIOF2_1),
852 PINMUX_IPSR_MSEL(IP5_19_16, MSIOF3_SYNC_A, SEL_MSIOF3_0),
853 PINMUX_IPSR_GPSR(IP5_19_16, VI4_DATA17),
854 PINMUX_IPSR_GPSR(IP5_19_16, VI5_DATA1),
855
856 PINMUX_IPSR_GPSR(IP5_23_20, D2),
857 PINMUX_IPSR_MSEL(IP5_23_20, MSIOF3_RXD_A, SEL_MSIOF3_0),
858 PINMUX_IPSR_GPSR(IP5_23_20, VI4_DATA18),
859 PINMUX_IPSR_GPSR(IP5_23_20, VI5_DATA2),
860
861 PINMUX_IPSR_GPSR(IP5_27_24, D3),
862 PINMUX_IPSR_MSEL(IP5_27_24, MSIOF3_TXD_A, SEL_MSIOF3_0),
863 PINMUX_IPSR_GPSR(IP5_27_24, VI4_DATA19),
864 PINMUX_IPSR_GPSR(IP5_27_24, VI5_DATA3),
865
866 PINMUX_IPSR_GPSR(IP5_31_28, D4),
867 PINMUX_IPSR_MSEL(IP5_31_28, MSIOF2_SCK_B, SEL_MSIOF2_1),
868 PINMUX_IPSR_GPSR(IP5_31_28, VI4_DATA20),
869 PINMUX_IPSR_GPSR(IP5_31_28, VI5_DATA4),
870
871 /* IPSR6 */
872 PINMUX_IPSR_GPSR(IP6_3_0, D5),
873 PINMUX_IPSR_MSEL(IP6_3_0, MSIOF2_SYNC_B, SEL_MSIOF2_1),
874 PINMUX_IPSR_GPSR(IP6_3_0, VI4_DATA21),
875 PINMUX_IPSR_GPSR(IP6_3_0, VI5_DATA5),
876
877 PINMUX_IPSR_GPSR(IP6_7_4, D6),
878 PINMUX_IPSR_MSEL(IP6_7_4, MSIOF2_RXD_B, SEL_MSIOF2_1),
879 PINMUX_IPSR_GPSR(IP6_7_4, VI4_DATA22),
880 PINMUX_IPSR_GPSR(IP6_7_4, VI5_DATA6),
881
882 PINMUX_IPSR_GPSR(IP6_11_8, D7),
883 PINMUX_IPSR_MSEL(IP6_11_8, MSIOF2_TXD_B, SEL_MSIOF2_1),
884 PINMUX_IPSR_GPSR(IP6_11_8, VI4_DATA23),
885 PINMUX_IPSR_GPSR(IP6_11_8, VI5_DATA7),
886
887 PINMUX_IPSR_GPSR(IP6_15_12, D8),
888 PINMUX_IPSR_GPSR(IP6_15_12, LCDOUT0),
889 PINMUX_IPSR_MSEL(IP6_15_12, MSIOF2_SCK_D, SEL_MSIOF2_3),
890 PINMUX_IPSR_MSEL(IP6_15_12, SCK4_C, SEL_SCIF4_2),
891 PINMUX_IPSR_MSEL(IP6_15_12, VI4_DATA0_A, SEL_VIN4_0),
892 PINMUX_IPSR_GPSR(IP6_15_12, DU_DR0),
893
894 PINMUX_IPSR_GPSR(IP6_19_16, D9),
895 PINMUX_IPSR_GPSR(IP6_19_16, LCDOUT1),
896 PINMUX_IPSR_MSEL(IP6_19_16, MSIOF2_SYNC_D, SEL_MSIOF2_3),
897 PINMUX_IPSR_MSEL(IP6_19_16, VI4_DATA1_A, SEL_VIN4_0),
898 PINMUX_IPSR_GPSR(IP6_19_16, DU_DR1),
899
900 PINMUX_IPSR_GPSR(IP6_23_20, D10),
901 PINMUX_IPSR_GPSR(IP6_23_20, LCDOUT2),
902 PINMUX_IPSR_MSEL(IP6_23_20, MSIOF2_RXD_D, SEL_MSIOF2_3),
903 PINMUX_IPSR_MSEL(IP6_23_20, HRX3_B, SEL_HSCIF3_1),
904 PINMUX_IPSR_MSEL(IP6_23_20, VI4_DATA2_A, SEL_VIN4_0),
905 PINMUX_IPSR_MSEL(IP6_23_20, CTS4_N_C, SEL_SCIF4_2),
906 PINMUX_IPSR_GPSR(IP6_23_20, DU_DR2),
907
908 PINMUX_IPSR_GPSR(IP6_27_24, D11),
909 PINMUX_IPSR_GPSR(IP6_27_24, LCDOUT3),
910 PINMUX_IPSR_MSEL(IP6_27_24, MSIOF2_TXD_D, SEL_MSIOF2_3),
911 PINMUX_IPSR_MSEL(IP6_27_24, HTX3_B, SEL_HSCIF3_1),
912 PINMUX_IPSR_MSEL(IP6_27_24, VI4_DATA3_A, SEL_VIN4_0),
913 PINMUX_IPSR_MSEL(IP6_27_24, RTS4_N_TANS_C, SEL_SCIF4_2),
914 PINMUX_IPSR_GPSR(IP6_27_24, DU_DR3),
915
916 PINMUX_IPSR_GPSR(IP6_31_28, D12),
917 PINMUX_IPSR_GPSR(IP6_31_28, LCDOUT4),
918 PINMUX_IPSR_MSEL(IP6_31_28, MSIOF2_SS1_D, SEL_MSIOF2_3),
919 PINMUX_IPSR_MSEL(IP6_31_28, RX4_C, SEL_SCIF4_2),
920 PINMUX_IPSR_MSEL(IP6_31_28, VI4_DATA4_A, SEL_VIN4_0),
921 PINMUX_IPSR_GPSR(IP6_31_28, DU_DR4),
922
923 /* IPSR7 */
924 PINMUX_IPSR_GPSR(IP7_3_0, D13),
925 PINMUX_IPSR_GPSR(IP7_3_0, LCDOUT5),
926 PINMUX_IPSR_MSEL(IP7_3_0, MSIOF2_SS2_D, SEL_MSIOF2_3),
927 PINMUX_IPSR_MSEL(IP7_3_0, TX4_C, SEL_SCIF4_2),
928 PINMUX_IPSR_MSEL(IP7_3_0, VI4_DATA5_A, SEL_VIN4_0),
929 PINMUX_IPSR_GPSR(IP7_3_0, DU_DR5),
930
931 PINMUX_IPSR_GPSR(IP7_7_4, D14),
932 PINMUX_IPSR_GPSR(IP7_7_4, LCDOUT6),
933 PINMUX_IPSR_MSEL(IP7_7_4, MSIOF3_SS1_A, SEL_MSIOF3_0),
934 PINMUX_IPSR_MSEL(IP7_7_4, HRX3_C, SEL_HSCIF3_2),
935 PINMUX_IPSR_MSEL(IP7_7_4, VI4_DATA6_A, SEL_VIN4_0),
936 PINMUX_IPSR_GPSR(IP7_7_4, DU_DR6),
937 PINMUX_IPSR_MSEL(IP7_7_4, SCL6_C, SEL_I2C6_2),
938
939 PINMUX_IPSR_GPSR(IP7_11_8, D15),
940 PINMUX_IPSR_GPSR(IP7_11_8, LCDOUT7),
941 PINMUX_IPSR_MSEL(IP7_11_8, MSIOF3_SS2_A, SEL_MSIOF3_0),
942 PINMUX_IPSR_MSEL(IP7_11_8, HTX3_C, SEL_HSCIF3_2),
943 PINMUX_IPSR_MSEL(IP7_11_8, VI4_DATA7_A, SEL_VIN4_0),
944 PINMUX_IPSR_GPSR(IP7_11_8, DU_DR7),
945 PINMUX_IPSR_MSEL(IP7_11_8, SDA6_C, SEL_I2C6_2),
946
947 PINMUX_IPSR_GPSR(IP7_15_12, FSCLKST),
948
949 PINMUX_IPSR_GPSR(IP7_19_16, SD0_CLK),
950 PINMUX_IPSR_MSEL(IP7_19_16, MSIOF1_SCK_E, SEL_MSIOF1_4),
951 PINMUX_IPSR_MSEL(IP7_19_16, STP_OPWM_0_B, SEL_SSP1_0_1),
952
953 PINMUX_IPSR_GPSR(IP7_23_20, SD0_CMD),
954 PINMUX_IPSR_MSEL(IP7_23_20, MSIOF1_SYNC_E, SEL_MSIOF1_4),
955 PINMUX_IPSR_MSEL(IP7_23_20, STP_IVCXO27_0_B, SEL_SSP1_0_1),
956
957 PINMUX_IPSR_GPSR(IP7_27_24, SD0_DAT0),
958 PINMUX_IPSR_MSEL(IP7_27_24, MSIOF1_RXD_E, SEL_MSIOF1_4),
959 PINMUX_IPSR_MSEL(IP7_27_24, TS_SCK0_B, SEL_TSIF0_1),
960 PINMUX_IPSR_MSEL(IP7_27_24, STP_ISCLK_0_B, SEL_SSP1_0_1),
961
962 PINMUX_IPSR_GPSR(IP7_31_28, SD0_DAT1),
963 PINMUX_IPSR_MSEL(IP7_31_28, MSIOF1_TXD_E, SEL_MSIOF1_4),
964 PINMUX_IPSR_MSEL(IP7_31_28, TS_SPSYNC0_B, SEL_TSIF0_1),
965 PINMUX_IPSR_MSEL(IP7_31_28, STP_ISSYNC_0_B, SEL_SSP1_0_1),
966
967 /* IPSR8 */
968 PINMUX_IPSR_GPSR(IP8_3_0, SD0_DAT2),
969 PINMUX_IPSR_MSEL(IP8_3_0, MSIOF1_SS1_E, SEL_MSIOF1_4),
970 PINMUX_IPSR_MSEL(IP8_3_0, TS_SDAT0_B, SEL_TSIF0_1),
971 PINMUX_IPSR_MSEL(IP8_3_0, STP_ISD_0_B, SEL_SSP1_0_1),
972
973 PINMUX_IPSR_GPSR(IP8_7_4, SD0_DAT3),
974 PINMUX_IPSR_MSEL(IP8_7_4, MSIOF1_SS2_E, SEL_MSIOF1_4),
975 PINMUX_IPSR_MSEL(IP8_7_4, TS_SDEN0_B, SEL_TSIF0_1),
976 PINMUX_IPSR_MSEL(IP8_7_4, STP_ISEN_0_B, SEL_SSP1_0_1),
977
978 PINMUX_IPSR_GPSR(IP8_11_8, SD1_CLK),
979 PINMUX_IPSR_MSEL(IP8_11_8, MSIOF1_SCK_G, SEL_MSIOF1_6),
980 PINMUX_IPSR_MSEL(IP8_11_8, SIM0_CLK_A, SEL_SIMCARD_0),
981
982 PINMUX_IPSR_GPSR(IP8_15_12, SD1_CMD),
983 PINMUX_IPSR_MSEL(IP8_15_12, MSIOF1_SYNC_G, SEL_MSIOF1_6),
984 PINMUX_IPSR_MSEL(IP8_15_12, SIM0_D_A, SEL_SIMCARD_0),
985 PINMUX_IPSR_MSEL(IP8_15_12, STP_IVCXO27_1_B, SEL_SSP1_1_1),
986
987 PINMUX_IPSR_GPSR(IP8_19_16, SD1_DAT0),
988 PINMUX_IPSR_GPSR(IP8_19_16, SD2_DAT4),
989 PINMUX_IPSR_MSEL(IP8_19_16, MSIOF1_RXD_G, SEL_MSIOF1_6),
990 PINMUX_IPSR_MSEL(IP8_19_16, TS_SCK1_B, SEL_TSIF1_1),
991 PINMUX_IPSR_MSEL(IP8_19_16, STP_ISCLK_1_B, SEL_SSP1_1_1),
992
993 PINMUX_IPSR_GPSR(IP8_23_20, SD1_DAT1),
994 PINMUX_IPSR_GPSR(IP8_23_20, SD2_DAT5),
995 PINMUX_IPSR_MSEL(IP8_23_20, MSIOF1_TXD_G, SEL_MSIOF1_6),
996 PINMUX_IPSR_MSEL(IP8_23_20, TS_SPSYNC1_B, SEL_TSIF1_1),
997 PINMUX_IPSR_MSEL(IP8_23_20, STP_ISSYNC_1_B, SEL_SSP1_1_1),
998
999 PINMUX_IPSR_GPSR(IP8_27_24, SD1_DAT2),
1000 PINMUX_IPSR_GPSR(IP8_27_24, SD2_DAT6),
1001 PINMUX_IPSR_MSEL(IP8_27_24, MSIOF1_SS1_G, SEL_MSIOF1_6),
1002 PINMUX_IPSR_MSEL(IP8_27_24, TS_SDAT1_B, SEL_TSIF1_1),
1003 PINMUX_IPSR_MSEL(IP8_27_24, STP_ISD_1_B, SEL_SSP1_1_1),
1004
1005 PINMUX_IPSR_GPSR(IP8_31_28, SD1_DAT3),
1006 PINMUX_IPSR_GPSR(IP8_31_28, SD2_DAT7),
1007 PINMUX_IPSR_MSEL(IP8_31_28, MSIOF1_SS2_G, SEL_MSIOF1_6),
1008 PINMUX_IPSR_MSEL(IP8_31_28, TS_SDEN1_B, SEL_TSIF1_1),
1009 PINMUX_IPSR_MSEL(IP8_31_28, STP_ISEN_1_B, SEL_SSP1_1_1),
1010
1011 /* IPSR9 */
1012 PINMUX_IPSR_GPSR(IP9_3_0, SD2_CLK),
1013
1014 PINMUX_IPSR_GPSR(IP9_7_4, SD2_DAT0),
1015
1016 PINMUX_IPSR_GPSR(IP9_11_8, SD2_DAT1),
1017
1018 PINMUX_IPSR_GPSR(IP9_15_12, SD2_DAT2),
1019
1020 PINMUX_IPSR_GPSR(IP9_19_16, SD2_DAT3),
1021
1022 PINMUX_IPSR_GPSR(IP9_23_20, SD2_DS),
1023 PINMUX_IPSR_MSEL(IP9_23_20, SATA_DEVSLP_B, SEL_SATA_1),
1024
1025 PINMUX_IPSR_GPSR(IP9_27_24, SD3_DAT4),
1026 PINMUX_IPSR_MSEL(IP9_27_24, SD2_CD_A, SEL_SDHI2_0),
1027
1028 PINMUX_IPSR_GPSR(IP9_31_28, SD3_DAT5),
1029 PINMUX_IPSR_MSEL(IP9_31_28, SD2_WP_A, SEL_SDHI2_0),
1030
1031 /* IPSR10 */
1032 PINMUX_IPSR_GPSR(IP10_3_0, SD3_DAT6),
1033 PINMUX_IPSR_GPSR(IP10_3_0, SD3_CD),
1034
1035 PINMUX_IPSR_GPSR(IP10_7_4, SD3_DAT7),
1036 PINMUX_IPSR_GPSR(IP10_7_4, SD3_WP),
1037
1038 PINMUX_IPSR_GPSR(IP10_11_8, SD0_CD),
1039 PINMUX_IPSR_MSEL(IP10_11_8, SCL2_B, SEL_I2C2_1),
1040 PINMUX_IPSR_MSEL(IP10_11_8, SIM0_RST_A, SEL_SIMCARD_0),
1041
1042 PINMUX_IPSR_GPSR(IP10_15_12, SD0_WP),
1043 PINMUX_IPSR_MSEL(IP10_15_12, SDA2_B, SEL_I2C2_1),
1044
1045 PINMUX_IPSR_GPSR(IP10_19_16, SD1_CD),
1046 PINMUX_IPSR_MSEL(IP10_19_16, SIM0_CLK_B, SEL_SIMCARD_1),
1047
1048 PINMUX_IPSR_GPSR(IP10_23_20, SD1_WP),
1049 PINMUX_IPSR_MSEL(IP10_23_20, SIM0_D_B, SEL_SIMCARD_1),
1050
1051 PINMUX_IPSR_GPSR(IP10_27_24, SCK0),
1052 PINMUX_IPSR_MSEL(IP10_27_24, HSCK1_B, SEL_HSCIF1_1),
1053 PINMUX_IPSR_MSEL(IP10_27_24, MSIOF1_SS2_B, SEL_MSIOF1_1),
1054 PINMUX_IPSR_MSEL(IP10_27_24, AUDIO_CLKC_B, SEL_ADG_1),
1055 PINMUX_IPSR_MSEL(IP10_27_24, SDA2_A, SEL_I2C2_0),
1056 PINMUX_IPSR_MSEL(IP10_27_24, SIM0_RST_B, SEL_SIMCARD_1),
1057 PINMUX_IPSR_MSEL(IP10_27_24, STP_OPWM_0_C, SEL_SSP1_0_2),
1058 PINMUX_IPSR_MSEL(IP10_27_24, RIF0_CLK_B, SEL_DRIF0_1),
1059 PINMUX_IPSR_GPSR(IP10_27_24, ADICHS2),
1060
1061 PINMUX_IPSR_GPSR(IP10_31_28, RX0),
1062 PINMUX_IPSR_MSEL(IP10_31_28, HRX1_B, SEL_HSCIF1_1),
1063 PINMUX_IPSR_MSEL(IP10_31_28, TS_SCK0_C, SEL_TSIF0_2),
1064 PINMUX_IPSR_MSEL(IP10_31_28, STP_ISCLK_0_C, SEL_SSP1_0_2),
1065 PINMUX_IPSR_MSEL(IP10_31_28, RIF0_D0_B, SEL_DRIF0_1),
1066
1067 /* IPSR11 */
1068 PINMUX_IPSR_GPSR(IP11_3_0, TX0),
1069 PINMUX_IPSR_MSEL(IP11_3_0, HTX1_B, SEL_HSCIF1_1),
1070 PINMUX_IPSR_MSEL(IP11_3_0, TS_SPSYNC0_C, SEL_TSIF0_2),
1071 PINMUX_IPSR_MSEL(IP11_3_0, STP_ISSYNC_0_C, SEL_SSP1_0_2),
1072 PINMUX_IPSR_MSEL(IP11_3_0, RIF0_D1_B, SEL_DRIF0_1),
1073
1074 PINMUX_IPSR_GPSR(IP11_7_4, CTS0_N),
1075 PINMUX_IPSR_MSEL(IP11_7_4, HCTS1_N_B, SEL_HSCIF1_1),
1076 PINMUX_IPSR_MSEL(IP11_7_4, MSIOF1_SYNC_B, SEL_MSIOF1_1),
1077 PINMUX_IPSR_MSEL(IP11_7_4, TS_SPSYNC1_C, SEL_TSIF1_2),
1078 PINMUX_IPSR_MSEL(IP11_7_4, STP_ISSYNC_1_C, SEL_SSP1_1_2),
1079 PINMUX_IPSR_MSEL(IP11_7_4, RIF1_SYNC_B, SEL_DRIF1_1),
1080 PINMUX_IPSR_MSEL(IP11_7_4, AUDIO_CLKOUT_C, SEL_ADG_2),
1081 PINMUX_IPSR_GPSR(IP11_7_4, ADICS_SAMP),
1082
1083 PINMUX_IPSR_GPSR(IP11_11_8, RTS0_N_TANS),
1084 PINMUX_IPSR_MSEL(IP11_11_8, HRTS1_N_B, SEL_HSCIF1_1),
1085 PINMUX_IPSR_MSEL(IP11_11_8, MSIOF1_SS1_B, SEL_MSIOF1_1),
1086 PINMUX_IPSR_MSEL(IP11_11_8, AUDIO_CLKA_B, SEL_ADG_1),
1087 PINMUX_IPSR_MSEL(IP11_11_8, SCL2_A, SEL_I2C2_0),
1088 PINMUX_IPSR_MSEL(IP11_11_8, STP_IVCXO27_1_C, SEL_SSP1_1_2),
1089 PINMUX_IPSR_MSEL(IP11_11_8, RIF0_SYNC_B, SEL_DRIF0_1),
1090 PINMUX_IPSR_GPSR(IP11_11_8, ADICHS1),
1091
1092 PINMUX_IPSR_MSEL(IP11_15_12, RX1_A, SEL_SCIF1_0),
1093 PINMUX_IPSR_MSEL(IP11_15_12, HRX1_A, SEL_HSCIF1_0),
1094 PINMUX_IPSR_MSEL(IP11_15_12, TS_SDAT0_C, SEL_TSIF0_2),
1095 PINMUX_IPSR_MSEL(IP11_15_12, STP_ISD_0_C, SEL_SSP1_0_2),
1096 PINMUX_IPSR_MSEL(IP11_15_12, RIF1_CLK_C, SEL_DRIF1_2),
1097
1098 PINMUX_IPSR_MSEL(IP11_19_16, TX1_A, SEL_SCIF1_0),
1099 PINMUX_IPSR_MSEL(IP11_19_16, HTX1_A, SEL_HSCIF1_0),
1100 PINMUX_IPSR_MSEL(IP11_19_16, TS_SDEN0_C, SEL_TSIF0_2),
1101 PINMUX_IPSR_MSEL(IP11_19_16, STP_ISEN_0_C, SEL_SSP1_0_2),
1102 PINMUX_IPSR_MSEL(IP11_19_16, RIF1_D0_C, SEL_DRIF1_2),
1103
1104 PINMUX_IPSR_GPSR(IP11_23_20, CTS1_N),
1105 PINMUX_IPSR_MSEL(IP11_23_20, HCTS1_N_A, SEL_HSCIF1_0),
1106 PINMUX_IPSR_MSEL(IP11_23_20, MSIOF1_RXD_B, SEL_MSIOF1_1),
1107 PINMUX_IPSR_MSEL(IP11_23_20, TS_SDEN1_C, SEL_TSIF1_2),
1108 PINMUX_IPSR_MSEL(IP11_23_20, STP_ISEN_1_C, SEL_SSP1_1_2),
1109 PINMUX_IPSR_MSEL(IP11_23_20, RIF1_D0_B, SEL_DRIF1_1),
1110 PINMUX_IPSR_GPSR(IP11_23_20, ADIDATA),
1111
1112 PINMUX_IPSR_GPSR(IP11_27_24, RTS1_N_TANS),
1113 PINMUX_IPSR_MSEL(IP11_27_24, HRTS1_N_A, SEL_HSCIF1_0),
1114 PINMUX_IPSR_MSEL(IP11_27_24, MSIOF1_TXD_B, SEL_MSIOF1_1),
1115 PINMUX_IPSR_MSEL(IP11_27_24, TS_SDAT1_C, SEL_TSIF1_2),
1116 PINMUX_IPSR_MSEL(IP11_27_24, STP_ISD_1_C, SEL_SSP1_1_2),
1117 PINMUX_IPSR_MSEL(IP11_27_24, RIF1_D1_B, SEL_DRIF1_1),
1118 PINMUX_IPSR_GPSR(IP11_27_24, ADICHS0),
1119
1120 PINMUX_IPSR_GPSR(IP11_31_28, SCK2),
1121 PINMUX_IPSR_MSEL(IP11_31_28, SCIF_CLK_B, SEL_SCIF1_1),
1122 PINMUX_IPSR_MSEL(IP11_31_28, MSIOF1_SCK_B, SEL_MSIOF1_1),
1123 PINMUX_IPSR_MSEL(IP11_31_28, TS_SCK1_C, SEL_TSIF1_2),
1124 PINMUX_IPSR_MSEL(IP11_31_28, STP_ISCLK_1_C, SEL_SSP1_1_2),
1125 PINMUX_IPSR_MSEL(IP11_31_28, RIF1_CLK_B, SEL_DRIF1_1),
1126 PINMUX_IPSR_GPSR(IP11_31_28, ADICLK),
1127
1128 /* IPSR12 */
1129 PINMUX_IPSR_MSEL(IP12_3_0, TX2_A, SEL_SCIF2_0),
1130 PINMUX_IPSR_MSEL(IP12_3_0, SD2_CD_B, SEL_SDHI2_1),
1131 PINMUX_IPSR_MSEL(IP12_3_0, SCL1_A, SEL_I2C1_0),
1132 PINMUX_IPSR_MSEL(IP12_3_0, FMCLK_A, SEL_FM_0),
1133 PINMUX_IPSR_MSEL(IP12_3_0, RIF1_D1_C, SEL_DRIF1_2),
1134 PINMUX_IPSR_MSEL(IP12_3_0, FSO_CFE_0_B, SEL_FSO_1),
1135
1136 PINMUX_IPSR_MSEL(IP12_7_4, RX2_A, SEL_SCIF2_0),
1137 PINMUX_IPSR_MSEL(IP12_7_4, SD2_WP_B, SEL_SDHI2_1),
1138 PINMUX_IPSR_MSEL(IP12_7_4, SDA1_A, SEL_I2C1_0),
1139 PINMUX_IPSR_MSEL(IP12_7_4, FMIN_A, SEL_FM_0),
1140 PINMUX_IPSR_MSEL(IP12_7_4, RIF1_SYNC_C, SEL_DRIF1_2),
1141 PINMUX_IPSR_MSEL(IP12_7_4, FSO_CFE_1_B, SEL_FSO_1),
1142
1143 PINMUX_IPSR_GPSR(IP12_11_8, HSCK0),
1144 PINMUX_IPSR_MSEL(IP12_11_8, MSIOF1_SCK_D, SEL_MSIOF1_3),
1145 PINMUX_IPSR_MSEL(IP12_11_8, AUDIO_CLKB_A, SEL_ADG_0),
1146 PINMUX_IPSR_MSEL(IP12_11_8, SSI_SDATA1_B, SEL_SSI_1),
1147 PINMUX_IPSR_MSEL(IP12_11_8, TS_SCK0_D, SEL_TSIF0_3),
1148 PINMUX_IPSR_MSEL(IP12_11_8, STP_ISCLK_0_D, SEL_SSP1_0_3),
1149 PINMUX_IPSR_MSEL(IP12_11_8, RIF0_CLK_C, SEL_DRIF0_2),
1150
1151 PINMUX_IPSR_GPSR(IP12_15_12, HRX0),
1152 PINMUX_IPSR_MSEL(IP12_15_12, MSIOF1_RXD_D, SEL_MSIOF1_3),
1153 PINMUX_IPSR_MSEL(IP12_15_12, SSI_SDATA2_B, SEL_SSI_1),
1154 PINMUX_IPSR_MSEL(IP12_15_12, TS_SDEN0_D, SEL_TSIF0_3),
1155 PINMUX_IPSR_MSEL(IP12_15_12, STP_ISEN_0_D, SEL_SSP1_0_3),
1156 PINMUX_IPSR_MSEL(IP12_15_12, RIF0_D0_C, SEL_DRIF0_2),
1157
1158 PINMUX_IPSR_GPSR(IP12_19_16, HTX0),
1159 PINMUX_IPSR_MSEL(IP12_19_16, MSIOF1_TXD_D, SEL_MSIOF1_3),
1160 PINMUX_IPSR_MSEL(IP12_19_16, SSI_SDATA9_B, SEL_SSI_1),
1161 PINMUX_IPSR_MSEL(IP12_19_16, TS_SDAT0_D, SEL_TSIF0_3),
1162 PINMUX_IPSR_MSEL(IP12_19_16, STP_ISD_0_D, SEL_SSP1_0_3),
1163 PINMUX_IPSR_MSEL(IP12_19_16, RIF0_D1_C, SEL_DRIF0_2),
1164
1165 PINMUX_IPSR_GPSR(IP12_23_20, HCTS0_N),
1166 PINMUX_IPSR_MSEL(IP12_23_20, RX2_B, SEL_SCIF2_1),
1167 PINMUX_IPSR_MSEL(IP12_23_20, MSIOF1_SYNC_D, SEL_MSIOF1_3),
1168 PINMUX_IPSR_MSEL(IP12_23_20, SSI_SCK9_A, SEL_SSI_0),
1169 PINMUX_IPSR_MSEL(IP12_23_20, TS_SPSYNC0_D, SEL_TSIF0_3),
1170 PINMUX_IPSR_MSEL(IP12_23_20, STP_ISSYNC_0_D, SEL_SSP1_0_3),
1171 PINMUX_IPSR_MSEL(IP12_23_20, RIF0_SYNC_C, SEL_DRIF0_2),
1172 PINMUX_IPSR_MSEL(IP12_23_20, AUDIO_CLKOUT1_A, SEL_ADG_0),
1173
1174 PINMUX_IPSR_GPSR(IP12_27_24, HRTS0_N),
1175 PINMUX_IPSR_MSEL(IP12_27_24, TX2_B, SEL_SCIF2_1),
1176 PINMUX_IPSR_MSEL(IP12_27_24, MSIOF1_SS1_D, SEL_MSIOF1_3),
1177 PINMUX_IPSR_MSEL(IP12_27_24, SSI_WS9_A, SEL_SSI_0),
1178 PINMUX_IPSR_MSEL(IP12_27_24, STP_IVCXO27_0_D, SEL_SSP1_0_3),
1179 PINMUX_IPSR_MSEL(IP12_27_24, BPFCLK_A, SEL_FM_0),
1180 PINMUX_IPSR_MSEL(IP12_27_24, AUDIO_CLKOUT2_A, SEL_ADG_0),
1181
1182 PINMUX_IPSR_GPSR(IP12_31_28, MSIOF0_SYNC),
1183 PINMUX_IPSR_MSEL(IP12_31_28, AUDIO_CLKOUT_A, SEL_ADG_0),
1184
1185 /* IPSR13 */
1186 PINMUX_IPSR_GPSR(IP13_3_0, MSIOF0_SS1),
1187 PINMUX_IPSR_GPSR(IP13_3_0, RX5),
1188 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKA_C, SEL_ADG_2),
1189 PINMUX_IPSR_MSEL(IP13_3_0, SSI_SCK2_A, SEL_SSI_0),
1190 PINMUX_IPSR_MSEL(IP13_3_0, STP_IVCXO27_0_C, SEL_SSP1_0_2),
1191 PINMUX_IPSR_MSEL(IP13_3_0, AUDIO_CLKOUT3_A, SEL_ADG_0),
1192 PINMUX_IPSR_MSEL(IP13_3_0, TCLK1_B, SEL_TIMER_TMU_1),
1193
1194 PINMUX_IPSR_GPSR(IP13_7_4, MSIOF0_SS2),
1195 PINMUX_IPSR_GPSR(IP13_7_4, TX5),
1196 PINMUX_IPSR_MSEL(IP13_7_4, MSIOF1_SS2_D, SEL_MSIOF1_3),
1197 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKC_A, SEL_ADG_0),
1198 PINMUX_IPSR_MSEL(IP13_7_4, SSI_WS2_A, SEL_SSI_0),
1199 PINMUX_IPSR_MSEL(IP13_7_4, STP_OPWM_0_D, SEL_SSP1_0_3),
1200 PINMUX_IPSR_MSEL(IP13_7_4, AUDIO_CLKOUT_D, SEL_ADG_3),
1201 PINMUX_IPSR_MSEL(IP13_7_4, SPEEDIN_B, SEL_SPEED_PULSE_1),
1202
1203 PINMUX_IPSR_GPSR(IP13_11_8, MLB_CLK),
1204 PINMUX_IPSR_MSEL(IP13_11_8, MSIOF1_SCK_F, SEL_MSIOF1_5),
1205 PINMUX_IPSR_MSEL(IP13_11_8, SCL1_B, SEL_I2C1_1),
1206
1207 PINMUX_IPSR_GPSR(IP13_15_12, MLB_SIG),
1208 PINMUX_IPSR_MSEL(IP13_15_12, RX1_B, SEL_SCIF1_1),
1209 PINMUX_IPSR_MSEL(IP13_15_12, MSIOF1_SYNC_F, SEL_MSIOF1_5),
1210 PINMUX_IPSR_MSEL(IP13_15_12, SDA1_B, SEL_I2C1_1),
1211
1212 PINMUX_IPSR_GPSR(IP13_19_16, MLB_DAT),
1213 PINMUX_IPSR_MSEL(IP13_19_16, TX1_B, SEL_SCIF1_1),
1214 PINMUX_IPSR_MSEL(IP13_19_16, MSIOF1_RXD_F, SEL_MSIOF1_5),
1215
1216 PINMUX_IPSR_GPSR(IP13_23_20, SSI_SCK01239),
1217 PINMUX_IPSR_MSEL(IP13_23_20, MSIOF1_TXD_F, SEL_MSIOF1_5),
1218
1219 PINMUX_IPSR_GPSR(IP13_27_24, SSI_WS01239),
1220 PINMUX_IPSR_MSEL(IP13_27_24, MSIOF1_SS1_F, SEL_MSIOF1_5),
1221
1222 PINMUX_IPSR_GPSR(IP13_31_28, SSI_SDATA0),
1223 PINMUX_IPSR_MSEL(IP13_31_28, MSIOF1_SS2_F, SEL_MSIOF1_5),
1224
1225 /* IPSR14 */
1226 PINMUX_IPSR_MSEL(IP14_3_0, SSI_SDATA1_A, SEL_SSI_0),
1227
1228 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SDATA2_A, SEL_SSI_0),
1229 PINMUX_IPSR_MSEL(IP14_7_4, SSI_SCK1_B, SEL_SSI_1),
1230
1231 PINMUX_IPSR_GPSR(IP14_11_8, SSI_SCK34),
1232 PINMUX_IPSR_MSEL(IP14_11_8, MSIOF1_SS1_A, SEL_MSIOF1_0),
1233 PINMUX_IPSR_MSEL(IP14_11_8, STP_OPWM_0_A, SEL_SSP1_0_0),
1234
1235 PINMUX_IPSR_GPSR(IP14_15_12, SSI_WS34),
1236 PINMUX_IPSR_MSEL(IP14_15_12, HCTS2_N_A, SEL_HSCIF2_0),
1237 PINMUX_IPSR_MSEL(IP14_15_12, MSIOF1_SS2_A, SEL_MSIOF1_0),
1238 PINMUX_IPSR_MSEL(IP14_15_12, STP_IVCXO27_0_A, SEL_SSP1_0_0),
1239
1240 PINMUX_IPSR_GPSR(IP14_19_16, SSI_SDATA3),
1241 PINMUX_IPSR_MSEL(IP14_19_16, HRTS2_N_A, SEL_HSCIF2_0),
1242 PINMUX_IPSR_MSEL(IP14_19_16, MSIOF1_TXD_A, SEL_MSIOF1_0),
1243 PINMUX_IPSR_MSEL(IP14_19_16, TS_SCK0_A, SEL_TSIF0_0),
1244 PINMUX_IPSR_MSEL(IP14_19_16, STP_ISCLK_0_A, SEL_SSP1_0_0),
1245 PINMUX_IPSR_MSEL(IP14_19_16, RIF0_D1_A, SEL_DRIF0_0),
1246 PINMUX_IPSR_MSEL(IP14_19_16, RIF2_D0_A, SEL_DRIF2_0),
1247
1248 PINMUX_IPSR_GPSR(IP14_23_20, SSI_SCK4),
1249 PINMUX_IPSR_MSEL(IP14_23_20, HRX2_A, SEL_HSCIF2_0),
1250 PINMUX_IPSR_MSEL(IP14_23_20, MSIOF1_SCK_A, SEL_MSIOF1_0),
1251 PINMUX_IPSR_MSEL(IP14_23_20, TS_SDAT0_A, SEL_TSIF0_0),
1252 PINMUX_IPSR_MSEL(IP14_23_20, STP_ISD_0_A, SEL_SSP1_0_0),
1253 PINMUX_IPSR_MSEL(IP14_23_20, RIF0_CLK_A, SEL_DRIF0_0),
1254 PINMUX_IPSR_MSEL(IP14_23_20, RIF2_CLK_A, SEL_DRIF2_0),
1255
1256 PINMUX_IPSR_GPSR(IP14_27_24, SSI_WS4),
1257 PINMUX_IPSR_MSEL(IP14_27_24, HTX2_A, SEL_HSCIF2_0),
1258 PINMUX_IPSR_MSEL(IP14_27_24, MSIOF1_SYNC_A, SEL_MSIOF1_0),
1259 PINMUX_IPSR_MSEL(IP14_27_24, TS_SDEN0_A, SEL_TSIF0_0),
1260 PINMUX_IPSR_MSEL(IP14_27_24, STP_ISEN_0_A, SEL_SSP1_0_0),
1261 PINMUX_IPSR_MSEL(IP14_27_24, RIF0_SYNC_A, SEL_DRIF0_0),
1262 PINMUX_IPSR_MSEL(IP14_27_24, RIF2_SYNC_A, SEL_DRIF2_0),
1263
1264 PINMUX_IPSR_GPSR(IP14_31_28, SSI_SDATA4),
1265 PINMUX_IPSR_MSEL(IP14_31_28, HSCK2_A, SEL_HSCIF2_0),
1266 PINMUX_IPSR_MSEL(IP14_31_28, MSIOF1_RXD_A, SEL_MSIOF1_0),
1267 PINMUX_IPSR_MSEL(IP14_31_28, TS_SPSYNC0_A, SEL_TSIF0_0),
1268 PINMUX_IPSR_MSEL(IP14_31_28, STP_ISSYNC_0_A, SEL_SSP1_0_0),
1269 PINMUX_IPSR_MSEL(IP14_31_28, RIF0_D0_A, SEL_DRIF0_0),
1270 PINMUX_IPSR_MSEL(IP14_31_28, RIF2_D1_A, SEL_DRIF2_0),
1271
1272 /* IPSR15 */
1273 PINMUX_IPSR_GPSR(IP15_3_0, SSI_SCK6),
1274 PINMUX_IPSR_GPSR(IP15_3_0, USB2_PWEN),
1275 PINMUX_IPSR_MSEL(IP15_3_0, SIM0_RST_D, SEL_SIMCARD_3),
1276
1277 PINMUX_IPSR_GPSR(IP15_7_4, SSI_WS6),
1278 PINMUX_IPSR_GPSR(IP15_7_4, USB2_OVC),
1279 PINMUX_IPSR_MSEL(IP15_7_4, SIM0_D_D, SEL_SIMCARD_3),
1280
1281 PINMUX_IPSR_GPSR(IP15_11_8, SSI_SDATA6),
1282 PINMUX_IPSR_MSEL(IP15_11_8, SIM0_CLK_D, SEL_SIMCARD_3),
1283 PINMUX_IPSR_MSEL(IP15_11_8, SATA_DEVSLP_A, SEL_SATA_0),
1284
1285 PINMUX_IPSR_GPSR(IP15_15_12, SSI_SCK78),
1286 PINMUX_IPSR_MSEL(IP15_15_12, HRX2_B, SEL_HSCIF2_1),
1287 PINMUX_IPSR_MSEL(IP15_15_12, MSIOF1_SCK_C, SEL_MSIOF1_2),
1288 PINMUX_IPSR_MSEL(IP15_15_12, TS_SCK1_A, SEL_TSIF1_0),
1289 PINMUX_IPSR_MSEL(IP15_15_12, STP_ISCLK_1_A, SEL_SSP1_1_0),
1290 PINMUX_IPSR_MSEL(IP15_15_12, RIF1_CLK_A, SEL_DRIF1_0),
1291 PINMUX_IPSR_MSEL(IP15_15_12, RIF3_CLK_A, SEL_DRIF3_0),
1292
1293 PINMUX_IPSR_GPSR(IP15_19_16, SSI_WS78),
1294 PINMUX_IPSR_MSEL(IP15_19_16, HTX2_B, SEL_HSCIF2_1),
1295 PINMUX_IPSR_MSEL(IP15_19_16, MSIOF1_SYNC_C, SEL_MSIOF1_2),
1296 PINMUX_IPSR_MSEL(IP15_19_16, TS_SDAT1_A, SEL_TSIF1_0),
1297 PINMUX_IPSR_MSEL(IP15_19_16, STP_ISD_1_A, SEL_SSP1_1_0),
1298 PINMUX_IPSR_MSEL(IP15_19_16, RIF1_SYNC_A, SEL_DRIF1_0),
1299 PINMUX_IPSR_MSEL(IP15_19_16, RIF3_SYNC_A, SEL_DRIF3_0),
1300
1301 PINMUX_IPSR_GPSR(IP15_23_20, SSI_SDATA7),
1302 PINMUX_IPSR_MSEL(IP15_23_20, HCTS2_N_B, SEL_HSCIF2_1),
1303 PINMUX_IPSR_MSEL(IP15_23_20, MSIOF1_RXD_C, SEL_MSIOF1_2),
1304 PINMUX_IPSR_MSEL(IP15_23_20, TS_SDEN1_A, SEL_TSIF1_0),
1305 PINMUX_IPSR_MSEL(IP15_23_20, STP_ISEN_1_A, SEL_SSP1_1_0),
1306 PINMUX_IPSR_MSEL(IP15_23_20, RIF1_D0_A, SEL_DRIF1_0),
1307 PINMUX_IPSR_MSEL(IP15_23_20, RIF3_D0_A, SEL_DRIF3_0),
1308 PINMUX_IPSR_MSEL(IP15_23_20, TCLK2_A, SEL_TIMER_TMU_0),
1309
1310 PINMUX_IPSR_GPSR(IP15_27_24, SSI_SDATA8),
1311 PINMUX_IPSR_MSEL(IP15_27_24, HRTS2_N_B, SEL_HSCIF2_1),
1312 PINMUX_IPSR_MSEL(IP15_27_24, MSIOF1_TXD_C, SEL_MSIOF1_2),
1313 PINMUX_IPSR_MSEL(IP15_27_24, TS_SPSYNC1_A, SEL_TSIF1_0),
1314 PINMUX_IPSR_MSEL(IP15_27_24, STP_ISSYNC_1_A, SEL_SSP1_1_0),
1315 PINMUX_IPSR_MSEL(IP15_27_24, RIF1_D1_A, SEL_DRIF1_0),
1316 PINMUX_IPSR_MSEL(IP15_27_24, RIF3_D1_A, SEL_DRIF3_0),
1317
1318 PINMUX_IPSR_MSEL(IP15_31_28, SSI_SDATA9_A, SEL_SSI_0),
1319 PINMUX_IPSR_MSEL(IP15_31_28, HSCK2_B, SEL_HSCIF2_1),
1320 PINMUX_IPSR_MSEL(IP15_31_28, MSIOF1_SS1_C, SEL_MSIOF1_2),
1321 PINMUX_IPSR_MSEL(IP15_31_28, HSCK1_A, SEL_HSCIF1_0),
1322 PINMUX_IPSR_MSEL(IP15_31_28, SSI_WS1_B, SEL_SSI_1),
1323 PINMUX_IPSR_GPSR(IP15_31_28, SCK1),
1324 PINMUX_IPSR_MSEL(IP15_31_28, STP_IVCXO27_1_A, SEL_SSP1_1_0),
1325 PINMUX_IPSR_GPSR(IP15_31_28, SCK5),
1326
1327 /* IPSR16 */
1328 PINMUX_IPSR_MSEL(IP16_3_0, AUDIO_CLKA_A, SEL_ADG_0),
1329 PINMUX_IPSR_GPSR(IP16_3_0, CC5_OSCOUT),
1330
1331 PINMUX_IPSR_MSEL(IP16_7_4, AUDIO_CLKB_B, SEL_ADG_1),
1332 PINMUX_IPSR_MSEL(IP16_7_4, SCIF_CLK_A, SEL_SCIF1_0),
1333 PINMUX_IPSR_MSEL(IP16_7_4, STP_IVCXO27_1_D, SEL_SSP1_1_3),
1334 PINMUX_IPSR_MSEL(IP16_7_4, REMOCON_A, SEL_REMOCON_0),
1335 PINMUX_IPSR_MSEL(IP16_7_4, TCLK1_A, SEL_TIMER_TMU_0),
1336
1337 PINMUX_IPSR_GPSR(IP16_11_8, USB0_PWEN),
1338 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_RST_C, SEL_SIMCARD_2),
1339 PINMUX_IPSR_MSEL(IP16_11_8, TS_SCK1_D, SEL_TSIF1_3),
1340 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISCLK_1_D, SEL_SSP1_1_3),
1341 PINMUX_IPSR_MSEL(IP16_11_8, BPFCLK_B, SEL_FM_1),
1342 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_CLK_B, SEL_DRIF3_1),
1343
1344 PINMUX_IPSR_GPSR(IP16_15_12, USB0_OVC),
1345 PINMUX_IPSR_MSEL(IP16_11_8, SIM0_D_C, SEL_SIMCARD_2),
1346 PINMUX_IPSR_MSEL(IP16_11_8, TS_SDAT1_D, SEL_TSIF1_3),
1347 PINMUX_IPSR_MSEL(IP16_11_8, STP_ISD_1_D, SEL_SSP1_1_3),
1348 PINMUX_IPSR_MSEL(IP16_11_8, RIF3_SYNC_B, SEL_DRIF3_1),
1349
1350 PINMUX_IPSR_GPSR(IP16_19_16, USB1_PWEN),
1351 PINMUX_IPSR_MSEL(IP16_19_16, SIM0_CLK_C, SEL_SIMCARD_2),
1352 PINMUX_IPSR_MSEL(IP16_19_16, SSI_SCK1_A, SEL_SSI_0),
1353 PINMUX_IPSR_MSEL(IP16_19_16, TS_SCK0_E, SEL_TSIF0_4),
1354 PINMUX_IPSR_MSEL(IP16_19_16, STP_ISCLK_0_E, SEL_SSP1_0_4),
1355 PINMUX_IPSR_MSEL(IP16_19_16, FMCLK_B, SEL_FM_1),
1356 PINMUX_IPSR_MSEL(IP16_19_16, RIF2_CLK_B, SEL_DRIF2_1),
1357 PINMUX_IPSR_MSEL(IP16_19_16, SPEEDIN_A, SEL_SPEED_PULSE_0),
1358
1359 PINMUX_IPSR_GPSR(IP16_23_20, USB1_OVC),
1360 PINMUX_IPSR_MSEL(IP16_23_20, MSIOF1_SS2_C, SEL_MSIOF1_2),
1361 PINMUX_IPSR_MSEL(IP16_23_20, SSI_WS1_A, SEL_SSI_0),
1362 PINMUX_IPSR_MSEL(IP16_23_20, TS_SDAT0_E, SEL_TSIF0_4),
1363 PINMUX_IPSR_MSEL(IP16_23_20, STP_ISD_0_E, SEL_SSP1_0_4),
1364 PINMUX_IPSR_MSEL(IP16_23_20, FMIN_B, SEL_FM_1),
1365 PINMUX_IPSR_MSEL(IP16_23_20, RIF2_SYNC_B, SEL_DRIF2_1),
1366 PINMUX_IPSR_MSEL(IP16_23_20, REMOCON_B, SEL_REMOCON_1),
1367
1368 PINMUX_IPSR_GPSR(IP16_27_24, USB30_PWEN),
1369 PINMUX_IPSR_MSEL(IP16_27_24, AUDIO_CLKOUT_B, SEL_ADG_1),
1370 PINMUX_IPSR_MSEL(IP16_27_24, SSI_SCK2_B, SEL_SSI_1),
1371 PINMUX_IPSR_MSEL(IP16_27_24, TS_SDEN1_D, SEL_TSIF1_3),
1372 PINMUX_IPSR_MSEL(IP16_27_24, STP_ISEN_1_D, SEL_SSP1_1_2),
1373 PINMUX_IPSR_MSEL(IP16_27_24, STP_OPWM_0_E, SEL_SSP1_0_4),
1374 PINMUX_IPSR_MSEL(IP16_27_24, RIF3_D0_B, SEL_DRIF3_1),
1375 PINMUX_IPSR_MSEL(IP16_27_24, TCLK2_B, SEL_TIMER_TMU_1),
1376 PINMUX_IPSR_GPSR(IP16_27_24, TPU0TO0),
1377
1378 PINMUX_IPSR_GPSR(IP16_31_28, USB30_OVC),
1379 PINMUX_IPSR_MSEL(IP16_31_28, AUDIO_CLKOUT1_B, SEL_ADG_1),
1380 PINMUX_IPSR_MSEL(IP16_31_28, SSI_WS2_B, SEL_SSI_1),
1381 PINMUX_IPSR_MSEL(IP16_31_28, TS_SPSYNC1_D, SEL_TSIF1_3),
1382 PINMUX_IPSR_MSEL(IP16_31_28, STP_ISSYNC_1_D, SEL_SSP1_1_3),
1383 PINMUX_IPSR_MSEL(IP16_31_28, STP_IVCXO27_0_E, SEL_SSP1_0_4),
1384 PINMUX_IPSR_MSEL(IP16_31_28, RIF3_D1_B, SEL_DRIF3_1),
1385 PINMUX_IPSR_MSEL(IP16_31_28, FSO_TOE_B, SEL_FSO_1),
1386 PINMUX_IPSR_GPSR(IP16_31_28, TPU0TO1),
1387
1388 /* IPSR17 */
1389 PINMUX_IPSR_GPSR(IP17_3_0, USB31_PWEN),
1390 PINMUX_IPSR_MSEL(IP17_3_0, AUDIO_CLKOUT2_B, SEL_ADG_1),
1391 PINMUX_IPSR_MSEL(IP17_3_0, SSI_SCK9_B, SEL_SSI_1),
1392 PINMUX_IPSR_MSEL(IP17_3_0, TS_SDEN0_E, SEL_TSIF0_4),
1393 PINMUX_IPSR_MSEL(IP17_3_0, STP_ISEN_0_E, SEL_SSP1_0_4),
1394 PINMUX_IPSR_MSEL(IP17_3_0, RIF2_D0_B, SEL_DRIF2_1),
1395 PINMUX_IPSR_GPSR(IP17_3_0, TPU0TO2),
1396
1397 PINMUX_IPSR_GPSR(IP17_7_4, USB31_OVC),
1398 PINMUX_IPSR_MSEL(IP17_7_4, AUDIO_CLKOUT3_B, SEL_ADG_1),
1399 PINMUX_IPSR_MSEL(IP17_7_4, SSI_WS9_B, SEL_SSI_1),
1400 PINMUX_IPSR_MSEL(IP17_7_4, TS_SPSYNC0_E, SEL_TSIF0_4),
1401 PINMUX_IPSR_MSEL(IP17_7_4, STP_ISSYNC_0_E, SEL_SSP1_0_4),
1402 PINMUX_IPSR_MSEL(IP17_7_4, RIF2_D1_B, SEL_DRIF2_1),
1403 PINMUX_IPSR_GPSR(IP17_7_4, TPU0TO3),
1404
1405 /* I2C */
1406 PINMUX_IPSR_NOGP(0, I2C_SEL_0_1),
1407 PINMUX_IPSR_NOGP(0, I2C_SEL_3_1),
1408 PINMUX_IPSR_NOGP(0, I2C_SEL_5_1),
1409 };
1410
1411 static const struct sh_pfc_pin pinmux_pins[] = {
1412 PINMUX_GPIO_GP_ALL(),
1413 };
1414
1415 /* - AUDIO CLOCK ------------------------------------------------------------ */
1416 static const unsigned int audio_clk_a_a_pins[] = {
1417 /* CLK A */
1418 RCAR_GP_PIN(6, 22),
1419 };
1420 static const unsigned int audio_clk_a_a_mux[] = {
1421 AUDIO_CLKA_A_MARK,
1422 };
1423 static const unsigned int audio_clk_a_b_pins[] = {
1424 /* CLK A */
1425 RCAR_GP_PIN(5, 4),
1426 };
1427 static const unsigned int audio_clk_a_b_mux[] = {
1428 AUDIO_CLKA_B_MARK,
1429 };
1430 static const unsigned int audio_clk_a_c_pins[] = {
1431 /* CLK A */
1432 RCAR_GP_PIN(5, 19),
1433 };
1434 static const unsigned int audio_clk_a_c_mux[] = {
1435 AUDIO_CLKA_C_MARK,
1436 };
1437 static const unsigned int audio_clk_b_a_pins[] = {
1438 /* CLK B */
1439 RCAR_GP_PIN(5, 12),
1440 };
1441 static const unsigned int audio_clk_b_a_mux[] = {
1442 AUDIO_CLKB_A_MARK,
1443 };
1444 static const unsigned int audio_clk_b_b_pins[] = {
1445 /* CLK B */
1446 RCAR_GP_PIN(6, 23),
1447 };
1448 static const unsigned int audio_clk_b_b_mux[] = {
1449 AUDIO_CLKB_B_MARK,
1450 };
1451 static const unsigned int audio_clk_c_a_pins[] = {
1452 /* CLK C */
1453 RCAR_GP_PIN(5, 21),
1454 };
1455 static const unsigned int audio_clk_c_a_mux[] = {
1456 AUDIO_CLKC_A_MARK,
1457 };
1458 static const unsigned int audio_clk_c_b_pins[] = {
1459 /* CLK C */
1460 RCAR_GP_PIN(5, 0),
1461 };
1462 static const unsigned int audio_clk_c_b_mux[] = {
1463 AUDIO_CLKC_B_MARK,
1464 };
1465 static const unsigned int audio_clkout_a_pins[] = {
1466 /* CLKOUT */
1467 RCAR_GP_PIN(5, 18),
1468 };
1469 static const unsigned int audio_clkout_a_mux[] = {
1470 AUDIO_CLKOUT_A_MARK,
1471 };
1472 static const unsigned int audio_clkout_b_pins[] = {
1473 /* CLKOUT */
1474 RCAR_GP_PIN(6, 28),
1475 };
1476 static const unsigned int audio_clkout_b_mux[] = {
1477 AUDIO_CLKOUT_B_MARK,
1478 };
1479 static const unsigned int audio_clkout_c_pins[] = {
1480 /* CLKOUT */
1481 RCAR_GP_PIN(5, 3),
1482 };
1483 static const unsigned int audio_clkout_c_mux[] = {
1484 AUDIO_CLKOUT_C_MARK,
1485 };
1486 static const unsigned int audio_clkout_d_pins[] = {
1487 /* CLKOUT */
1488 RCAR_GP_PIN(5, 21),
1489 };
1490 static const unsigned int audio_clkout_d_mux[] = {
1491 AUDIO_CLKOUT_D_MARK,
1492 };
1493 static const unsigned int audio_clkout1_a_pins[] = {
1494 /* CLKOUT1 */
1495 RCAR_GP_PIN(5, 15),
1496 };
1497 static const unsigned int audio_clkout1_a_mux[] = {
1498 AUDIO_CLKOUT1_A_MARK,
1499 };
1500 static const unsigned int audio_clkout1_b_pins[] = {
1501 /* CLKOUT1 */
1502 RCAR_GP_PIN(6, 29),
1503 };
1504 static const unsigned int audio_clkout1_b_mux[] = {
1505 AUDIO_CLKOUT1_B_MARK,
1506 };
1507 static const unsigned int audio_clkout2_a_pins[] = {
1508 /* CLKOUT2 */
1509 RCAR_GP_PIN(5, 16),
1510 };
1511 static const unsigned int audio_clkout2_a_mux[] = {
1512 AUDIO_CLKOUT2_A_MARK,
1513 };
1514 static const unsigned int audio_clkout2_b_pins[] = {
1515 /* CLKOUT2 */
1516 RCAR_GP_PIN(6, 30),
1517 };
1518 static const unsigned int audio_clkout2_b_mux[] = {
1519 AUDIO_CLKOUT2_B_MARK,
1520 };
1521
1522 static const unsigned int audio_clkout3_a_pins[] = {
1523 /* CLKOUT3 */
1524 RCAR_GP_PIN(5, 19),
1525 };
1526 static const unsigned int audio_clkout3_a_mux[] = {
1527 AUDIO_CLKOUT3_A_MARK,
1528 };
1529 static const unsigned int audio_clkout3_b_pins[] = {
1530 /* CLKOUT3 */
1531 RCAR_GP_PIN(6, 31),
1532 };
1533 static const unsigned int audio_clkout3_b_mux[] = {
1534 AUDIO_CLKOUT3_B_MARK,
1535 };
1536
1537 /* - EtherAVB --------------------------------------------------------------- */
1538 static const unsigned int avb_link_pins[] = {
1539 /* AVB_LINK */
1540 RCAR_GP_PIN(2, 12),
1541 };
1542 static const unsigned int avb_link_mux[] = {
1543 AVB_LINK_MARK,
1544 };
1545 static const unsigned int avb_magic_pins[] = {
1546 /* AVB_MAGIC_ */
1547 RCAR_GP_PIN(2, 10),
1548 };
1549 static const unsigned int avb_magic_mux[] = {
1550 AVB_MAGIC_MARK,
1551 };
1552 static const unsigned int avb_phy_int_pins[] = {
1553 /* AVB_PHY_INT */
1554 RCAR_GP_PIN(2, 11),
1555 };
1556 static const unsigned int avb_phy_int_mux[] = {
1557 AVB_PHY_INT_MARK,
1558 };
1559 static const unsigned int avb_mdc_pins[] = {
1560 /* AVB_MDC */
1561 RCAR_GP_PIN(2, 9),
1562 };
1563 static const unsigned int avb_mdc_mux[] = {
1564 AVB_MDC_MARK,
1565 };
1566 static const unsigned int avb_avtp_pps_pins[] = {
1567 /* AVB_AVTP_PPS */
1568 RCAR_GP_PIN(2, 6),
1569 };
1570 static const unsigned int avb_avtp_pps_mux[] = {
1571 AVB_AVTP_PPS_MARK,
1572 };
1573 static const unsigned int avb_avtp_match_a_pins[] = {
1574 /* AVB_AVTP_MATCH_A */
1575 RCAR_GP_PIN(2, 13),
1576 };
1577 static const unsigned int avb_avtp_match_a_mux[] = {
1578 AVB_AVTP_MATCH_A_MARK,
1579 };
1580 static const unsigned int avb_avtp_capture_a_pins[] = {
1581 /* AVB_AVTP_CAPTURE_A */
1582 RCAR_GP_PIN(2, 14),
1583 };
1584 static const unsigned int avb_avtp_capture_a_mux[] = {
1585 AVB_AVTP_CAPTURE_A_MARK,
1586 };
1587 static const unsigned int avb_avtp_match_b_pins[] = {
1588 /* AVB_AVTP_MATCH_B */
1589 RCAR_GP_PIN(1, 8),
1590 };
1591 static const unsigned int avb_avtp_match_b_mux[] = {
1592 AVB_AVTP_MATCH_B_MARK,
1593 };
1594 static const unsigned int avb_avtp_capture_b_pins[] = {
1595 /* AVB_AVTP_CAPTURE_B */
1596 RCAR_GP_PIN(1, 11),
1597 };
1598 static const unsigned int avb_avtp_capture_b_mux[] = {
1599 AVB_AVTP_CAPTURE_B_MARK,
1600 };
1601
1602 /* - CAN ------------------------------------------------------------------ */
1603 static const unsigned int can0_data_a_pins[] = {
1604 /* TX, RX */
1605 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1606 };
1607 static const unsigned int can0_data_a_mux[] = {
1608 CAN0_TX_A_MARK, CAN0_RX_A_MARK,
1609 };
1610 static const unsigned int can0_data_b_pins[] = {
1611 /* TX, RX */
1612 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1613 };
1614 static const unsigned int can0_data_b_mux[] = {
1615 CAN0_TX_B_MARK, CAN0_RX_B_MARK,
1616 };
1617 static const unsigned int can1_data_pins[] = {
1618 /* TX, RX */
1619 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1620 };
1621 static const unsigned int can1_data_mux[] = {
1622 CAN1_TX_MARK, CAN1_RX_MARK,
1623 };
1624
1625 /* - CAN Clock -------------------------------------------------------------- */
1626 static const unsigned int can_clk_pins[] = {
1627 /* CLK */
1628 RCAR_GP_PIN(1, 25),
1629 };
1630 static const unsigned int can_clk_mux[] = {
1631 CAN_CLK_MARK,
1632 };
1633
1634 /* - CAN FD --------------------------------------------------------------- */
1635 static const unsigned int canfd0_data_a_pins[] = {
1636 /* TX, RX */
1637 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1638 };
1639 static const unsigned int canfd0_data_a_mux[] = {
1640 CANFD0_TX_A_MARK, CANFD0_RX_A_MARK,
1641 };
1642 static const unsigned int canfd0_data_b_pins[] = {
1643 /* TX, RX */
1644 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1645 };
1646 static const unsigned int canfd0_data_b_mux[] = {
1647 CANFD0_TX_B_MARK, CANFD0_RX_B_MARK,
1648 };
1649 static const unsigned int canfd1_data_pins[] = {
1650 /* TX, RX */
1651 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 26),
1652 };
1653 static const unsigned int canfd1_data_mux[] = {
1654 CANFD1_TX_MARK, CANFD1_RX_MARK,
1655 };
1656
1657 /* - HSCIF0 ----------------------------------------------------------------- */
1658 static const unsigned int hscif0_data_pins[] = {
1659 /* RX, TX */
1660 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1661 };
1662 static const unsigned int hscif0_data_mux[] = {
1663 HRX0_MARK, HTX0_MARK,
1664 };
1665 static const unsigned int hscif0_clk_pins[] = {
1666 /* SCK */
1667 RCAR_GP_PIN(5, 12),
1668 };
1669 static const unsigned int hscif0_clk_mux[] = {
1670 HSCK0_MARK,
1671 };
1672 static const unsigned int hscif0_ctrl_pins[] = {
1673 /* RTS, CTS */
1674 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1675 };
1676 static const unsigned int hscif0_ctrl_mux[] = {
1677 HRTS0_N_MARK, HCTS0_N_MARK,
1678 };
1679 /* - HSCIF1 ----------------------------------------------------------------- */
1680 static const unsigned int hscif1_data_a_pins[] = {
1681 /* RX, TX */
1682 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
1683 };
1684 static const unsigned int hscif1_data_a_mux[] = {
1685 HRX1_A_MARK, HTX1_A_MARK,
1686 };
1687 static const unsigned int hscif1_clk_a_pins[] = {
1688 /* SCK */
1689 RCAR_GP_PIN(6, 21),
1690 };
1691 static const unsigned int hscif1_clk_a_mux[] = {
1692 HSCK1_A_MARK,
1693 };
1694 static const unsigned int hscif1_ctrl_a_pins[] = {
1695 /* RTS, CTS */
1696 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
1697 };
1698 static const unsigned int hscif1_ctrl_a_mux[] = {
1699 HRTS1_N_A_MARK, HCTS1_N_A_MARK,
1700 };
1701
1702 static const unsigned int hscif1_data_b_pins[] = {
1703 /* RX, TX */
1704 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
1705 };
1706 static const unsigned int hscif1_data_b_mux[] = {
1707 HRX1_B_MARK, HTX1_B_MARK,
1708 };
1709 static const unsigned int hscif1_clk_b_pins[] = {
1710 /* SCK */
1711 RCAR_GP_PIN(5, 0),
1712 };
1713 static const unsigned int hscif1_clk_b_mux[] = {
1714 HSCK1_B_MARK,
1715 };
1716 static const unsigned int hscif1_ctrl_b_pins[] = {
1717 /* RTS, CTS */
1718 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
1719 };
1720 static const unsigned int hscif1_ctrl_b_mux[] = {
1721 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1722 };
1723 /* - HSCIF2 ----------------------------------------------------------------- */
1724 static const unsigned int hscif2_data_a_pins[] = {
1725 /* RX, TX */
1726 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
1727 };
1728 static const unsigned int hscif2_data_a_mux[] = {
1729 HRX2_A_MARK, HTX2_A_MARK,
1730 };
1731 static const unsigned int hscif2_clk_a_pins[] = {
1732 /* SCK */
1733 RCAR_GP_PIN(6, 10),
1734 };
1735 static const unsigned int hscif2_clk_a_mux[] = {
1736 HSCK2_A_MARK,
1737 };
1738 static const unsigned int hscif2_ctrl_a_pins[] = {
1739 /* RTS, CTS */
1740 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
1741 };
1742 static const unsigned int hscif2_ctrl_a_mux[] = {
1743 HRTS2_N_A_MARK, HCTS2_N_A_MARK,
1744 };
1745
1746 static const unsigned int hscif2_data_b_pins[] = {
1747 /* RX, TX */
1748 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
1749 };
1750 static const unsigned int hscif2_data_b_mux[] = {
1751 HRX2_B_MARK, HTX2_B_MARK,
1752 };
1753 static const unsigned int hscif2_clk_b_pins[] = {
1754 /* SCK */
1755 RCAR_GP_PIN(6, 21),
1756 };
1757 static const unsigned int hscif2_clk_b_mux[] = {
1758 HSCK1_B_MARK,
1759 };
1760 static const unsigned int hscif2_ctrl_b_pins[] = {
1761 /* RTS, CTS */
1762 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 19),
1763 };
1764 static const unsigned int hscif2_ctrl_b_mux[] = {
1765 HRTS2_N_B_MARK, HCTS2_N_B_MARK,
1766 };
1767 /* - HSCIF3 ----------------------------------------------------------------- */
1768 static const unsigned int hscif3_data_a_pins[] = {
1769 /* RX, TX */
1770 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
1771 };
1772 static const unsigned int hscif3_data_a_mux[] = {
1773 HRX3_A_MARK, HTX3_A_MARK,
1774 };
1775 static const unsigned int hscif3_clk_pins[] = {
1776 /* SCK */
1777 RCAR_GP_PIN(1, 22),
1778 };
1779 static const unsigned int hscif3_clk_mux[] = {
1780 HSCK3_MARK,
1781 };
1782 static const unsigned int hscif3_ctrl_pins[] = {
1783 /* RTS, CTS */
1784 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1785 };
1786 static const unsigned int hscif3_ctrl_mux[] = {
1787 HRTS3_N_MARK, HCTS3_N_MARK,
1788 };
1789
1790 static const unsigned int hscif3_data_b_pins[] = {
1791 /* RX, TX */
1792 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
1793 };
1794 static const unsigned int hscif3_data_b_mux[] = {
1795 HRX3_B_MARK, HTX3_B_MARK,
1796 };
1797 static const unsigned int hscif3_data_c_pins[] = {
1798 /* RX, TX */
1799 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1800 };
1801 static const unsigned int hscif3_data_c_mux[] = {
1802 HRX3_C_MARK, HTX3_C_MARK,
1803 };
1804 static const unsigned int hscif3_data_d_pins[] = {
1805 /* RX, TX */
1806 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
1807 };
1808 static const unsigned int hscif3_data_d_mux[] = {
1809 HRX3_D_MARK, HTX3_D_MARK,
1810 };
1811 /* - HSCIF4 ----------------------------------------------------------------- */
1812 static const unsigned int hscif4_data_a_pins[] = {
1813 /* RX, TX */
1814 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
1815 };
1816 static const unsigned int hscif4_data_a_mux[] = {
1817 HRX4_A_MARK, HTX4_A_MARK,
1818 };
1819 static const unsigned int hscif4_clk_pins[] = {
1820 /* SCK */
1821 RCAR_GP_PIN(1, 11),
1822 };
1823 static const unsigned int hscif4_clk_mux[] = {
1824 HSCK4_MARK,
1825 };
1826 static const unsigned int hscif4_ctrl_pins[] = {
1827 /* RTS, CTS */
1828 RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
1829 };
1830 static const unsigned int hscif4_ctrl_mux[] = {
1831 HRTS4_N_MARK, HCTS3_N_MARK,
1832 };
1833
1834 static const unsigned int hscif4_data_b_pins[] = {
1835 /* RX, TX */
1836 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1837 };
1838 static const unsigned int hscif4_data_b_mux[] = {
1839 HRX4_B_MARK, HTX4_B_MARK,
1840 };
1841
1842 /* - I2C -------------------------------------------------------------------- */
1843 static const unsigned int i2c1_a_pins[] = {
1844 /* SDA, SCL */
1845 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
1846 };
1847 static const unsigned int i2c1_a_mux[] = {
1848 SDA1_A_MARK, SCL1_A_MARK,
1849 };
1850 static const unsigned int i2c1_b_pins[] = {
1851 /* SDA, SCL */
1852 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
1853 };
1854 static const unsigned int i2c1_b_mux[] = {
1855 SDA1_B_MARK, SCL1_B_MARK,
1856 };
1857 static const unsigned int i2c2_a_pins[] = {
1858 /* SDA, SCL */
1859 RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 4),
1860 };
1861 static const unsigned int i2c2_a_mux[] = {
1862 SDA2_A_MARK, SCL2_A_MARK,
1863 };
1864 static const unsigned int i2c2_b_pins[] = {
1865 /* SDA, SCL */
1866 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
1867 };
1868 static const unsigned int i2c2_b_mux[] = {
1869 SDA2_B_MARK, SCL2_B_MARK,
1870 };
1871 static const unsigned int i2c6_a_pins[] = {
1872 /* SDA, SCL */
1873 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
1874 };
1875 static const unsigned int i2c6_a_mux[] = {
1876 SDA6_A_MARK, SCL6_A_MARK,
1877 };
1878 static const unsigned int i2c6_b_pins[] = {
1879 /* SDA, SCL */
1880 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
1881 };
1882 static const unsigned int i2c6_b_mux[] = {
1883 SDA6_B_MARK, SCL6_B_MARK,
1884 };
1885 static const unsigned int i2c6_c_pins[] = {
1886 /* SDA, SCL */
1887 RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 14),
1888 };
1889 static const unsigned int i2c6_c_mux[] = {
1890 SDA6_C_MARK, SCL6_C_MARK,
1891 };
1892
1893 /* - INTC-EX ---------------------------------------------------------------- */
1894 static const unsigned int intc_ex_irq0_pins[] = {
1895 /* IRQ0 */
1896 RCAR_GP_PIN(2, 0),
1897 };
1898 static const unsigned int intc_ex_irq0_mux[] = {
1899 IRQ0_MARK,
1900 };
1901 static const unsigned int intc_ex_irq1_pins[] = {
1902 /* IRQ1 */
1903 RCAR_GP_PIN(2, 1),
1904 };
1905 static const unsigned int intc_ex_irq1_mux[] = {
1906 IRQ1_MARK,
1907 };
1908 static const unsigned int intc_ex_irq2_pins[] = {
1909 /* IRQ2 */
1910 RCAR_GP_PIN(2, 2),
1911 };
1912 static const unsigned int intc_ex_irq2_mux[] = {
1913 IRQ2_MARK,
1914 };
1915 static const unsigned int intc_ex_irq3_pins[] = {
1916 /* IRQ3 */
1917 RCAR_GP_PIN(2, 3),
1918 };
1919 static const unsigned int intc_ex_irq3_mux[] = {
1920 IRQ3_MARK,
1921 };
1922 static const unsigned int intc_ex_irq4_pins[] = {
1923 /* IRQ4 */
1924 RCAR_GP_PIN(2, 4),
1925 };
1926 static const unsigned int intc_ex_irq4_mux[] = {
1927 IRQ4_MARK,
1928 };
1929 static const unsigned int intc_ex_irq5_pins[] = {
1930 /* IRQ5 */
1931 RCAR_GP_PIN(2, 5),
1932 };
1933 static const unsigned int intc_ex_irq5_mux[] = {
1934 IRQ5_MARK,
1935 };
1936
1937 /* - MSIOF0 ----------------------------------------------------------------- */
1938 static const unsigned int msiof0_clk_pins[] = {
1939 /* SCK */
1940 RCAR_GP_PIN(5, 17),
1941 };
1942 static const unsigned int msiof0_clk_mux[] = {
1943 MSIOF0_SCK_MARK,
1944 };
1945 static const unsigned int msiof0_sync_pins[] = {
1946 /* SYNC */
1947 RCAR_GP_PIN(5, 18),
1948 };
1949 static const unsigned int msiof0_sync_mux[] = {
1950 MSIOF0_SYNC_MARK,
1951 };
1952 static const unsigned int msiof0_ss1_pins[] = {
1953 /* SS1 */
1954 RCAR_GP_PIN(5, 19),
1955 };
1956 static const unsigned int msiof0_ss1_mux[] = {
1957 MSIOF0_SS1_MARK,
1958 };
1959 static const unsigned int msiof0_ss2_pins[] = {
1960 /* SS2 */
1961 RCAR_GP_PIN(5, 21),
1962 };
1963 static const unsigned int msiof0_ss2_mux[] = {
1964 MSIOF0_SS2_MARK,
1965 };
1966 static const unsigned int msiof0_txd_pins[] = {
1967 /* TXD */
1968 RCAR_GP_PIN(5, 20),
1969 };
1970 static const unsigned int msiof0_txd_mux[] = {
1971 MSIOF0_TXD_MARK,
1972 };
1973 static const unsigned int msiof0_rxd_pins[] = {
1974 /* RXD */
1975 RCAR_GP_PIN(5, 22),
1976 };
1977 static const unsigned int msiof0_rxd_mux[] = {
1978 MSIOF0_RXD_MARK,
1979 };
1980 /* - MSIOF1 ----------------------------------------------------------------- */
1981 static const unsigned int msiof1_clk_a_pins[] = {
1982 /* SCK */
1983 RCAR_GP_PIN(6, 8),
1984 };
1985 static const unsigned int msiof1_clk_a_mux[] = {
1986 MSIOF1_SCK_A_MARK,
1987 };
1988 static const unsigned int msiof1_sync_a_pins[] = {
1989 /* SYNC */
1990 RCAR_GP_PIN(6, 9),
1991 };
1992 static const unsigned int msiof1_sync_a_mux[] = {
1993 MSIOF1_SYNC_A_MARK,
1994 };
1995 static const unsigned int msiof1_ss1_a_pins[] = {
1996 /* SS1 */
1997 RCAR_GP_PIN(6, 5),
1998 };
1999 static const unsigned int msiof1_ss1_a_mux[] = {
2000 MSIOF1_SS1_A_MARK,
2001 };
2002 static const unsigned int msiof1_ss2_a_pins[] = {
2003 /* SS2 */
2004 RCAR_GP_PIN(6, 6),
2005 };
2006 static const unsigned int msiof1_ss2_a_mux[] = {
2007 MSIOF1_SS2_A_MARK,
2008 };
2009 static const unsigned int msiof1_txd_a_pins[] = {
2010 /* TXD */
2011 RCAR_GP_PIN(6, 7),
2012 };
2013 static const unsigned int msiof1_txd_a_mux[] = {
2014 MSIOF1_TXD_A_MARK,
2015 };
2016 static const unsigned int msiof1_rxd_a_pins[] = {
2017 /* RXD */
2018 RCAR_GP_PIN(6, 10),
2019 };
2020 static const unsigned int msiof1_rxd_a_mux[] = {
2021 MSIOF1_RXD_A_MARK,
2022 };
2023 static const unsigned int msiof1_clk_b_pins[] = {
2024 /* SCK */
2025 RCAR_GP_PIN(5, 9),
2026 };
2027 static const unsigned int msiof1_clk_b_mux[] = {
2028 MSIOF1_SCK_B_MARK,
2029 };
2030 static const unsigned int msiof1_sync_b_pins[] = {
2031 /* SYNC */
2032 RCAR_GP_PIN(5, 3),
2033 };
2034 static const unsigned int msiof1_sync_b_mux[] = {
2035 MSIOF1_SYNC_B_MARK,
2036 };
2037 static const unsigned int msiof1_ss1_b_pins[] = {
2038 /* SS1 */
2039 RCAR_GP_PIN(5, 4),
2040 };
2041 static const unsigned int msiof1_ss1_b_mux[] = {
2042 MSIOF1_SS1_B_MARK,
2043 };
2044 static const unsigned int msiof1_ss2_b_pins[] = {
2045 /* SS2 */
2046 RCAR_GP_PIN(5, 0),
2047 };
2048 static const unsigned int msiof1_ss2_b_mux[] = {
2049 MSIOF1_SS2_B_MARK,
2050 };
2051 static const unsigned int msiof1_txd_b_pins[] = {
2052 /* TXD */
2053 RCAR_GP_PIN(5, 8),
2054 };
2055 static const unsigned int msiof1_txd_b_mux[] = {
2056 MSIOF1_TXD_B_MARK,
2057 };
2058 static const unsigned int msiof1_rxd_b_pins[] = {
2059 /* RXD */
2060 RCAR_GP_PIN(5, 7),
2061 };
2062 static const unsigned int msiof1_rxd_b_mux[] = {
2063 MSIOF1_RXD_B_MARK,
2064 };
2065 static const unsigned int msiof1_clk_c_pins[] = {
2066 /* SCK */
2067 RCAR_GP_PIN(6, 17),
2068 };
2069 static const unsigned int msiof1_clk_c_mux[] = {
2070 MSIOF1_SCK_C_MARK,
2071 };
2072 static const unsigned int msiof1_sync_c_pins[] = {
2073 /* SYNC */
2074 RCAR_GP_PIN(6, 18),
2075 };
2076 static const unsigned int msiof1_sync_c_mux[] = {
2077 MSIOF1_SYNC_C_MARK,
2078 };
2079 static const unsigned int msiof1_ss1_c_pins[] = {
2080 /* SS1 */
2081 RCAR_GP_PIN(6, 21),
2082 };
2083 static const unsigned int msiof1_ss1_c_mux[] = {
2084 MSIOF1_SS1_C_MARK,
2085 };
2086 static const unsigned int msiof1_ss2_c_pins[] = {
2087 /* SS2 */
2088 RCAR_GP_PIN(6, 27),
2089 };
2090 static const unsigned int msiof1_ss2_c_mux[] = {
2091 MSIOF1_SS2_C_MARK,
2092 };
2093 static const unsigned int msiof1_txd_c_pins[] = {
2094 /* TXD */
2095 RCAR_GP_PIN(6, 20),
2096 };
2097 static const unsigned int msiof1_txd_c_mux[] = {
2098 MSIOF1_TXD_C_MARK,
2099 };
2100 static const unsigned int msiof1_rxd_c_pins[] = {
2101 /* RXD */
2102 RCAR_GP_PIN(6, 19),
2103 };
2104 static const unsigned int msiof1_rxd_c_mux[] = {
2105 MSIOF1_RXD_C_MARK,
2106 };
2107 static const unsigned int msiof1_clk_d_pins[] = {
2108 /* SCK */
2109 RCAR_GP_PIN(5, 12),
2110 };
2111 static const unsigned int msiof1_clk_d_mux[] = {
2112 MSIOF1_SCK_D_MARK,
2113 };
2114 static const unsigned int msiof1_sync_d_pins[] = {
2115 /* SYNC */
2116 RCAR_GP_PIN(5, 15),
2117 };
2118 static const unsigned int msiof1_sync_d_mux[] = {
2119 MSIOF1_SYNC_D_MARK,
2120 };
2121 static const unsigned int msiof1_ss1_d_pins[] = {
2122 /* SS1 */
2123 RCAR_GP_PIN(5, 16),
2124 };
2125 static const unsigned int msiof1_ss1_d_mux[] = {
2126 MSIOF1_SS1_D_MARK,
2127 };
2128 static const unsigned int msiof1_ss2_d_pins[] = {
2129 /* SS2 */
2130 RCAR_GP_PIN(5, 21),
2131 };
2132 static const unsigned int msiof1_ss2_d_mux[] = {
2133 MSIOF1_SS2_D_MARK,
2134 };
2135 static const unsigned int msiof1_txd_d_pins[] = {
2136 /* TXD */
2137 RCAR_GP_PIN(5, 14),
2138 };
2139 static const unsigned int msiof1_txd_d_mux[] = {
2140 MSIOF1_TXD_D_MARK,
2141 };
2142 static const unsigned int msiof1_rxd_d_pins[] = {
2143 /* RXD */
2144 RCAR_GP_PIN(5, 13),
2145 };
2146 static const unsigned int msiof1_rxd_d_mux[] = {
2147 MSIOF1_RXD_D_MARK,
2148 };
2149 static const unsigned int msiof1_clk_e_pins[] = {
2150 /* SCK */
2151 RCAR_GP_PIN(3, 0),
2152 };
2153 static const unsigned int msiof1_clk_e_mux[] = {
2154 MSIOF1_SCK_E_MARK,
2155 };
2156 static const unsigned int msiof1_sync_e_pins[] = {
2157 /* SYNC */
2158 RCAR_GP_PIN(3, 1),
2159 };
2160 static const unsigned int msiof1_sync_e_mux[] = {
2161 MSIOF1_SYNC_E_MARK,
2162 };
2163 static const unsigned int msiof1_ss1_e_pins[] = {
2164 /* SS1 */
2165 RCAR_GP_PIN(3, 4),
2166 };
2167 static const unsigned int msiof1_ss1_e_mux[] = {
2168 MSIOF1_SS1_E_MARK,
2169 };
2170 static const unsigned int msiof1_ss2_e_pins[] = {
2171 /* SS2 */
2172 RCAR_GP_PIN(3, 5),
2173 };
2174 static const unsigned int msiof1_ss2_e_mux[] = {
2175 MSIOF1_SS2_E_MARK,
2176 };
2177 static const unsigned int msiof1_txd_e_pins[] = {
2178 /* TXD */
2179 RCAR_GP_PIN(3, 3),
2180 };
2181 static const unsigned int msiof1_txd_e_mux[] = {
2182 MSIOF1_TXD_E_MARK,
2183 };
2184 static const unsigned int msiof1_rxd_e_pins[] = {
2185 /* RXD */
2186 RCAR_GP_PIN(3, 2),
2187 };
2188 static const unsigned int msiof1_rxd_e_mux[] = {
2189 MSIOF1_RXD_E_MARK,
2190 };
2191 static const unsigned int msiof1_clk_f_pins[] = {
2192 /* SCK */
2193 RCAR_GP_PIN(5, 23),
2194 };
2195 static const unsigned int msiof1_clk_f_mux[] = {
2196 MSIOF1_SCK_F_MARK,
2197 };
2198 static const unsigned int msiof1_sync_f_pins[] = {
2199 /* SYNC */
2200 RCAR_GP_PIN(5, 24),
2201 };
2202 static const unsigned int msiof1_sync_f_mux[] = {
2203 MSIOF1_SYNC_F_MARK,
2204 };
2205 static const unsigned int msiof1_ss1_f_pins[] = {
2206 /* SS1 */
2207 RCAR_GP_PIN(6, 1),
2208 };
2209 static const unsigned int msiof1_ss1_f_mux[] = {
2210 MSIOF1_SS1_F_MARK,
2211 };
2212 static const unsigned int msiof1_ss2_f_pins[] = {
2213 /* SS2 */
2214 RCAR_GP_PIN(6, 2),
2215 };
2216 static const unsigned int msiof1_ss2_f_mux[] = {
2217 MSIOF1_SS2_F_MARK,
2218 };
2219 static const unsigned int msiof1_txd_f_pins[] = {
2220 /* TXD */
2221 RCAR_GP_PIN(6, 0),
2222 };
2223 static const unsigned int msiof1_txd_f_mux[] = {
2224 MSIOF1_TXD_F_MARK,
2225 };
2226 static const unsigned int msiof1_rxd_f_pins[] = {
2227 /* RXD */
2228 RCAR_GP_PIN(5, 25),
2229 };
2230 static const unsigned int msiof1_rxd_f_mux[] = {
2231 MSIOF1_RXD_F_MARK,
2232 };
2233 static const unsigned int msiof1_clk_g_pins[] = {
2234 /* SCK */
2235 RCAR_GP_PIN(3, 6),
2236 };
2237 static const unsigned int msiof1_clk_g_mux[] = {
2238 MSIOF1_SCK_G_MARK,
2239 };
2240 static const unsigned int msiof1_sync_g_pins[] = {
2241 /* SYNC */
2242 RCAR_GP_PIN(3, 7),
2243 };
2244 static const unsigned int msiof1_sync_g_mux[] = {
2245 MSIOF1_SYNC_G_MARK,
2246 };
2247 static const unsigned int msiof1_ss1_g_pins[] = {
2248 /* SS1 */
2249 RCAR_GP_PIN(3, 10),
2250 };
2251 static const unsigned int msiof1_ss1_g_mux[] = {
2252 MSIOF1_SS1_G_MARK,
2253 };
2254 static const unsigned int msiof1_ss2_g_pins[] = {
2255 /* SS2 */
2256 RCAR_GP_PIN(3, 11),
2257 };
2258 static const unsigned int msiof1_ss2_g_mux[] = {
2259 MSIOF1_SS2_G_MARK,
2260 };
2261 static const unsigned int msiof1_txd_g_pins[] = {
2262 /* TXD */
2263 RCAR_GP_PIN(3, 9),
2264 };
2265 static const unsigned int msiof1_txd_g_mux[] = {
2266 MSIOF1_TXD_G_MARK,
2267 };
2268 static const unsigned int msiof1_rxd_g_pins[] = {
2269 /* RXD */
2270 RCAR_GP_PIN(3, 8),
2271 };
2272 static const unsigned int msiof1_rxd_g_mux[] = {
2273 MSIOF1_RXD_G_MARK,
2274 };
2275 /* - MSIOF2 ----------------------------------------------------------------- */
2276 static const unsigned int msiof2_clk_a_pins[] = {
2277 /* SCK */
2278 RCAR_GP_PIN(1, 9),
2279 };
2280 static const unsigned int msiof2_clk_a_mux[] = {
2281 MSIOF2_SCK_A_MARK,
2282 };
2283 static const unsigned int msiof2_sync_a_pins[] = {
2284 /* SYNC */
2285 RCAR_GP_PIN(1, 8),
2286 };
2287 static const unsigned int msiof2_sync_a_mux[] = {
2288 MSIOF2_SYNC_A_MARK,
2289 };
2290 static const unsigned int msiof2_ss1_a_pins[] = {
2291 /* SS1 */
2292 RCAR_GP_PIN(1, 6),
2293 };
2294 static const unsigned int msiof2_ss1_a_mux[] = {
2295 MSIOF2_SS1_A_MARK,
2296 };
2297 static const unsigned int msiof2_ss2_a_pins[] = {
2298 /* SS2 */
2299 RCAR_GP_PIN(1, 7),
2300 };
2301 static const unsigned int msiof2_ss2_a_mux[] = {
2302 MSIOF2_SS2_A_MARK,
2303 };
2304 static const unsigned int msiof2_txd_a_pins[] = {
2305 /* TXD */
2306 RCAR_GP_PIN(1, 11),
2307 };
2308 static const unsigned int msiof2_txd_a_mux[] = {
2309 MSIOF2_TXD_A_MARK,
2310 };
2311 static const unsigned int msiof2_rxd_a_pins[] = {
2312 /* RXD */
2313 RCAR_GP_PIN(1, 10),
2314 };
2315 static const unsigned int msiof2_rxd_a_mux[] = {
2316 MSIOF2_RXD_A_MARK,
2317 };
2318 static const unsigned int msiof2_clk_b_pins[] = {
2319 /* SCK */
2320 RCAR_GP_PIN(0, 4),
2321 };
2322 static const unsigned int msiof2_clk_b_mux[] = {
2323 MSIOF2_SCK_B_MARK,
2324 };
2325 static const unsigned int msiof2_sync_b_pins[] = {
2326 /* SYNC */
2327 RCAR_GP_PIN(0, 5),
2328 };
2329 static const unsigned int msiof2_sync_b_mux[] = {
2330 MSIOF2_SYNC_B_MARK,
2331 };
2332 static const unsigned int msiof2_ss1_b_pins[] = {
2333 /* SS1 */
2334 RCAR_GP_PIN(0, 0),
2335 };
2336 static const unsigned int msiof2_ss1_b_mux[] = {
2337 MSIOF2_SS1_B_MARK,
2338 };
2339 static const unsigned int msiof2_ss2_b_pins[] = {
2340 /* SS2 */
2341 RCAR_GP_PIN(0, 1),
2342 };
2343 static const unsigned int msiof2_ss2_b_mux[] = {
2344 MSIOF2_SS2_B_MARK,
2345 };
2346 static const unsigned int msiof2_txd_b_pins[] = {
2347 /* TXD */
2348 RCAR_GP_PIN(0, 7),
2349 };
2350 static const unsigned int msiof2_txd_b_mux[] = {
2351 MSIOF2_TXD_B_MARK,
2352 };
2353 static const unsigned int msiof2_rxd_b_pins[] = {
2354 /* RXD */
2355 RCAR_GP_PIN(0, 6),
2356 };
2357 static const unsigned int msiof2_rxd_b_mux[] = {
2358 MSIOF2_RXD_B_MARK,
2359 };
2360 static const unsigned int msiof2_clk_c_pins[] = {
2361 /* SCK */
2362 RCAR_GP_PIN(2, 12),
2363 };
2364 static const unsigned int msiof2_clk_c_mux[] = {
2365 MSIOF2_SCK_C_MARK,
2366 };
2367 static const unsigned int msiof2_sync_c_pins[] = {
2368 /* SYNC */
2369 RCAR_GP_PIN(2, 11),
2370 };
2371 static const unsigned int msiof2_sync_c_mux[] = {
2372 MSIOF2_SYNC_C_MARK,
2373 };
2374 static const unsigned int msiof2_ss1_c_pins[] = {
2375 /* SS1 */
2376 RCAR_GP_PIN(2, 10),
2377 };
2378 static const unsigned int msiof2_ss1_c_mux[] = {
2379 MSIOF2_SS1_C_MARK,
2380 };
2381 static const unsigned int msiof2_ss2_c_pins[] = {
2382 /* SS2 */
2383 RCAR_GP_PIN(2, 9),
2384 };
2385 static const unsigned int msiof2_ss2_c_mux[] = {
2386 MSIOF2_SS2_C_MARK,
2387 };
2388 static const unsigned int msiof2_txd_c_pins[] = {
2389 /* TXD */
2390 RCAR_GP_PIN(2, 14),
2391 };
2392 static const unsigned int msiof2_txd_c_mux[] = {
2393 MSIOF2_TXD_C_MARK,
2394 };
2395 static const unsigned int msiof2_rxd_c_pins[] = {
2396 /* RXD */
2397 RCAR_GP_PIN(2, 13),
2398 };
2399 static const unsigned int msiof2_rxd_c_mux[] = {
2400 MSIOF2_RXD_C_MARK,
2401 };
2402 static const unsigned int msiof2_clk_d_pins[] = {
2403 /* SCK */
2404 RCAR_GP_PIN(0, 8),
2405 };
2406 static const unsigned int msiof2_clk_d_mux[] = {
2407 MSIOF2_SCK_D_MARK,
2408 };
2409 static const unsigned int msiof2_sync_d_pins[] = {
2410 /* SYNC */
2411 RCAR_GP_PIN(0, 9),
2412 };
2413 static const unsigned int msiof2_sync_d_mux[] = {
2414 MSIOF2_SYNC_D_MARK,
2415 };
2416 static const unsigned int msiof2_ss1_d_pins[] = {
2417 /* SS1 */
2418 RCAR_GP_PIN(0, 12),
2419 };
2420 static const unsigned int msiof2_ss1_d_mux[] = {
2421 MSIOF2_SS1_D_MARK,
2422 };
2423 static const unsigned int msiof2_ss2_d_pins[] = {
2424 /* SS2 */
2425 RCAR_GP_PIN(0, 13),
2426 };
2427 static const unsigned int msiof2_ss2_d_mux[] = {
2428 MSIOF2_SS2_D_MARK,
2429 };
2430 static const unsigned int msiof2_txd_d_pins[] = {
2431 /* TXD */
2432 RCAR_GP_PIN(0, 11),
2433 };
2434 static const unsigned int msiof2_txd_d_mux[] = {
2435 MSIOF2_TXD_D_MARK,
2436 };
2437 static const unsigned int msiof2_rxd_d_pins[] = {
2438 /* RXD */
2439 RCAR_GP_PIN(0, 10),
2440 };
2441 static const unsigned int msiof2_rxd_d_mux[] = {
2442 MSIOF2_RXD_D_MARK,
2443 };
2444 /* - MSIOF3 ----------------------------------------------------------------- */
2445 static const unsigned int msiof3_clk_a_pins[] = {
2446 /* SCK */
2447 RCAR_GP_PIN(0, 0),
2448 };
2449 static const unsigned int msiof3_clk_a_mux[] = {
2450 MSIOF3_SCK_A_MARK,
2451 };
2452 static const unsigned int msiof3_sync_a_pins[] = {
2453 /* SYNC */
2454 RCAR_GP_PIN(0, 1),
2455 };
2456 static const unsigned int msiof3_sync_a_mux[] = {
2457 MSIOF3_SYNC_A_MARK,
2458 };
2459 static const unsigned int msiof3_ss1_a_pins[] = {
2460 /* SS1 */
2461 RCAR_GP_PIN(0, 14),
2462 };
2463 static const unsigned int msiof3_ss1_a_mux[] = {
2464 MSIOF3_SS1_A_MARK,
2465 };
2466 static const unsigned int msiof3_ss2_a_pins[] = {
2467 /* SS2 */
2468 RCAR_GP_PIN(0, 15),
2469 };
2470 static const unsigned int msiof3_ss2_a_mux[] = {
2471 MSIOF3_SS2_A_MARK,
2472 };
2473 static const unsigned int msiof3_txd_a_pins[] = {
2474 /* TXD */
2475 RCAR_GP_PIN(0, 3),
2476 };
2477 static const unsigned int msiof3_txd_a_mux[] = {
2478 MSIOF3_TXD_A_MARK,
2479 };
2480 static const unsigned int msiof3_rxd_a_pins[] = {
2481 /* RXD */
2482 RCAR_GP_PIN(0, 2),
2483 };
2484 static const unsigned int msiof3_rxd_a_mux[] = {
2485 MSIOF3_RXD_A_MARK,
2486 };
2487 static const unsigned int msiof3_clk_b_pins[] = {
2488 /* SCK */
2489 RCAR_GP_PIN(1, 2),
2490 };
2491 static const unsigned int msiof3_clk_b_mux[] = {
2492 MSIOF3_SCK_B_MARK,
2493 };
2494 static const unsigned int msiof3_sync_b_pins[] = {
2495 /* SYNC */
2496 RCAR_GP_PIN(1, 0),
2497 };
2498 static const unsigned int msiof3_sync_b_mux[] = {
2499 MSIOF3_SYNC_B_MARK,
2500 };
2501 static const unsigned int msiof3_ss1_b_pins[] = {
2502 /* SS1 */
2503 RCAR_GP_PIN(1, 4),
2504 };
2505 static const unsigned int msiof3_ss1_b_mux[] = {
2506 MSIOF3_SS1_B_MARK,
2507 };
2508 static const unsigned int msiof3_ss2_b_pins[] = {
2509 /* SS2 */
2510 RCAR_GP_PIN(1, 5),
2511 };
2512 static const unsigned int msiof3_ss2_b_mux[] = {
2513 MSIOF3_SS2_B_MARK,
2514 };
2515 static const unsigned int msiof3_txd_b_pins[] = {
2516 /* TXD */
2517 RCAR_GP_PIN(1, 1),
2518 };
2519 static const unsigned int msiof3_txd_b_mux[] = {
2520 MSIOF3_TXD_B_MARK,
2521 };
2522 static const unsigned int msiof3_rxd_b_pins[] = {
2523 /* RXD */
2524 RCAR_GP_PIN(1, 3),
2525 };
2526 static const unsigned int msiof3_rxd_b_mux[] = {
2527 MSIOF3_RXD_B_MARK,
2528 };
2529 static const unsigned int msiof3_clk_c_pins[] = {
2530 /* SCK */
2531 RCAR_GP_PIN(1, 12),
2532 };
2533 static const unsigned int msiof3_clk_c_mux[] = {
2534 MSIOF3_SCK_C_MARK,
2535 };
2536 static const unsigned int msiof3_sync_c_pins[] = {
2537 /* SYNC */
2538 RCAR_GP_PIN(1, 13),
2539 };
2540 static const unsigned int msiof3_sync_c_mux[] = {
2541 MSIOF3_SYNC_C_MARK,
2542 };
2543 static const unsigned int msiof3_txd_c_pins[] = {
2544 /* TXD */
2545 RCAR_GP_PIN(1, 15),
2546 };
2547 static const unsigned int msiof3_txd_c_mux[] = {
2548 MSIOF3_TXD_C_MARK,
2549 };
2550 static const unsigned int msiof3_rxd_c_pins[] = {
2551 /* RXD */
2552 RCAR_GP_PIN(1, 14),
2553 };
2554 static const unsigned int msiof3_rxd_c_mux[] = {
2555 MSIOF3_RXD_C_MARK,
2556 };
2557 static const unsigned int msiof3_clk_d_pins[] = {
2558 /* SCK */
2559 RCAR_GP_PIN(1, 22),
2560 };
2561 static const unsigned int msiof3_clk_d_mux[] = {
2562 MSIOF3_SCK_D_MARK,
2563 };
2564 static const unsigned int msiof3_sync_d_pins[] = {
2565 /* SYNC */
2566 RCAR_GP_PIN(1, 23),
2567 };
2568 static const unsigned int msiof3_sync_d_mux[] = {
2569 MSIOF3_SYNC_D_MARK,
2570 };
2571 static const unsigned int msiof3_ss1_d_pins[] = {
2572 /* SS1 */
2573 RCAR_GP_PIN(1, 26),
2574 };
2575 static const unsigned int msiof3_ss1_d_mux[] = {
2576 MSIOF3_SS1_D_MARK,
2577 };
2578 static const unsigned int msiof3_txd_d_pins[] = {
2579 /* TXD */
2580 RCAR_GP_PIN(1, 25),
2581 };
2582 static const unsigned int msiof3_txd_d_mux[] = {
2583 MSIOF3_TXD_D_MARK,
2584 };
2585 static const unsigned int msiof3_rxd_d_pins[] = {
2586 /* RXD */
2587 RCAR_GP_PIN(1, 24),
2588 };
2589 static const unsigned int msiof3_rxd_d_mux[] = {
2590 MSIOF3_RXD_D_MARK,
2591 };
2592
2593 /* - PWM0 --------------------------------------------------------------------*/
2594 static const unsigned int pwm0_pins[] = {
2595 /* PWM */
2596 RCAR_GP_PIN(2, 6),
2597 };
2598 static const unsigned int pwm0_mux[] = {
2599 PWM0_MARK,
2600 };
2601 /* - PWM1 --------------------------------------------------------------------*/
2602 static const unsigned int pwm1_a_pins[] = {
2603 /* PWM */
2604 RCAR_GP_PIN(2, 7),
2605 };
2606 static const unsigned int pwm1_a_mux[] = {
2607 PWM1_A_MARK,
2608 };
2609 static const unsigned int pwm1_b_pins[] = {
2610 /* PWM */
2611 RCAR_GP_PIN(1, 8),
2612 };
2613 static const unsigned int pwm1_b_mux[] = {
2614 PWM1_B_MARK,
2615 };
2616 /* - PWM2 --------------------------------------------------------------------*/
2617 static const unsigned int pwm2_a_pins[] = {
2618 /* PWM */
2619 RCAR_GP_PIN(2, 8),
2620 };
2621 static const unsigned int pwm2_a_mux[] = {
2622 PWM2_A_MARK,
2623 };
2624 static const unsigned int pwm2_b_pins[] = {
2625 /* PWM */
2626 RCAR_GP_PIN(1, 11),
2627 };
2628 static const unsigned int pwm2_b_mux[] = {
2629 PWM2_B_MARK,
2630 };
2631 /* - PWM3 --------------------------------------------------------------------*/
2632 static const unsigned int pwm3_a_pins[] = {
2633 /* PWM */
2634 RCAR_GP_PIN(1, 0),
2635 };
2636 static const unsigned int pwm3_a_mux[] = {
2637 PWM3_A_MARK,
2638 };
2639 static const unsigned int pwm3_b_pins[] = {
2640 /* PWM */
2641 RCAR_GP_PIN(2, 2),
2642 };
2643 static const unsigned int pwm3_b_mux[] = {
2644 PWM3_B_MARK,
2645 };
2646 /* - PWM4 --------------------------------------------------------------------*/
2647 static const unsigned int pwm4_a_pins[] = {
2648 /* PWM */
2649 RCAR_GP_PIN(1, 1),
2650 };
2651 static const unsigned int pwm4_a_mux[] = {
2652 PWM4_A_MARK,
2653 };
2654 static const unsigned int pwm4_b_pins[] = {
2655 /* PWM */
2656 RCAR_GP_PIN(2, 3),
2657 };
2658 static const unsigned int pwm4_b_mux[] = {
2659 PWM4_B_MARK,
2660 };
2661 /* - PWM5 --------------------------------------------------------------------*/
2662 static const unsigned int pwm5_a_pins[] = {
2663 /* PWM */
2664 RCAR_GP_PIN(1, 2),
2665 };
2666 static const unsigned int pwm5_a_mux[] = {
2667 PWM5_A_MARK,
2668 };
2669 static const unsigned int pwm5_b_pins[] = {
2670 /* PWM */
2671 RCAR_GP_PIN(2, 4),
2672 };
2673 static const unsigned int pwm5_b_mux[] = {
2674 PWM5_B_MARK,
2675 };
2676 /* - PWM6 --------------------------------------------------------------------*/
2677 static const unsigned int pwm6_a_pins[] = {
2678 /* PWM */
2679 RCAR_GP_PIN(1, 3),
2680 };
2681 static const unsigned int pwm6_a_mux[] = {
2682 PWM6_A_MARK,
2683 };
2684 static const unsigned int pwm6_b_pins[] = {
2685 /* PWM */
2686 RCAR_GP_PIN(2, 5),
2687 };
2688 static const unsigned int pwm6_b_mux[] = {
2689 PWM6_B_MARK,
2690 };
2691
2692 /* - SATA --------------------------------------------------------------------*/
2693 static const unsigned int sata0_devslp_a_pins[] = {
2694 /* DEVSLP */
2695 RCAR_GP_PIN(6, 16),
2696 };
2697 static const unsigned int sata0_devslp_a_mux[] = {
2698 SATA_DEVSLP_A_MARK,
2699 };
2700 static const unsigned int sata0_devslp_b_pins[] = {
2701 /* DEVSLP */
2702 RCAR_GP_PIN(4, 6),
2703 };
2704 static const unsigned int sata0_devslp_b_mux[] = {
2705 SATA_DEVSLP_B_MARK,
2706 };
2707
2708 /* - SCIF0 ------------------------------------------------------------------ */
2709 static const unsigned int scif0_data_pins[] = {
2710 /* RX, TX */
2711 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2712 };
2713 static const unsigned int scif0_data_mux[] = {
2714 RX0_MARK, TX0_MARK,
2715 };
2716 static const unsigned int scif0_clk_pins[] = {
2717 /* SCK */
2718 RCAR_GP_PIN(5, 0),
2719 };
2720 static const unsigned int scif0_clk_mux[] = {
2721 SCK0_MARK,
2722 };
2723 static const unsigned int scif0_ctrl_pins[] = {
2724 /* RTS, CTS */
2725 RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 3),
2726 };
2727 static const unsigned int scif0_ctrl_mux[] = {
2728 RTS0_N_TANS_MARK, CTS0_N_MARK,
2729 };
2730 /* - SCIF1 ------------------------------------------------------------------ */
2731 static const unsigned int scif1_data_a_pins[] = {
2732 /* RX, TX */
2733 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2734 };
2735 static const unsigned int scif1_data_a_mux[] = {
2736 RX1_A_MARK, TX1_A_MARK,
2737 };
2738 static const unsigned int scif1_clk_pins[] = {
2739 /* SCK */
2740 RCAR_GP_PIN(6, 21),
2741 };
2742 static const unsigned int scif1_clk_mux[] = {
2743 SCK1_MARK,
2744 };
2745 static const unsigned int scif1_ctrl_pins[] = {
2746 /* RTS, CTS */
2747 RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 7),
2748 };
2749 static const unsigned int scif1_ctrl_mux[] = {
2750 RTS1_N_TANS_MARK, CTS1_N_MARK,
2751 };
2752
2753 static const unsigned int scif1_data_b_pins[] = {
2754 /* RX, TX */
2755 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 25),
2756 };
2757 static const unsigned int scif1_data_b_mux[] = {
2758 RX1_B_MARK, TX1_B_MARK,
2759 };
2760 /* - SCIF2 ------------------------------------------------------------------ */
2761 static const unsigned int scif2_data_a_pins[] = {
2762 /* RX, TX */
2763 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2764 };
2765 static const unsigned int scif2_data_a_mux[] = {
2766 RX2_A_MARK, TX2_A_MARK,
2767 };
2768 static const unsigned int scif2_clk_pins[] = {
2769 /* SCK */
2770 RCAR_GP_PIN(5, 9),
2771 };
2772 static const unsigned int scif2_clk_mux[] = {
2773 SCK2_MARK,
2774 };
2775 static const unsigned int scif2_data_b_pins[] = {
2776 /* RX, TX */
2777 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2778 };
2779 static const unsigned int scif2_data_b_mux[] = {
2780 RX2_B_MARK, TX2_B_MARK,
2781 };
2782 /* - SCIF3 ------------------------------------------------------------------ */
2783 static const unsigned int scif3_data_a_pins[] = {
2784 /* RX, TX */
2785 RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 24),
2786 };
2787 static const unsigned int scif3_data_a_mux[] = {
2788 RX3_A_MARK, TX3_A_MARK,
2789 };
2790 static const unsigned int scif3_clk_pins[] = {
2791 /* SCK */
2792 RCAR_GP_PIN(1, 22),
2793 };
2794 static const unsigned int scif3_clk_mux[] = {
2795 SCK3_MARK,
2796 };
2797 static const unsigned int scif3_ctrl_pins[] = {
2798 /* RTS, CTS */
2799 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 25),
2800 };
2801 static const unsigned int scif3_ctrl_mux[] = {
2802 RTS3_N_TANS_MARK, CTS3_N_MARK,
2803 };
2804 static const unsigned int scif3_data_b_pins[] = {
2805 /* RX, TX */
2806 RCAR_GP_PIN(1, 8), RCAR_GP_PIN(1, 11),
2807 };
2808 static const unsigned int scif3_data_b_mux[] = {
2809 RX3_B_MARK, TX3_B_MARK,
2810 };
2811 /* - SCIF4 ------------------------------------------------------------------ */
2812 static const unsigned int scif4_data_a_pins[] = {
2813 /* RX, TX */
2814 RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2815 };
2816 static const unsigned int scif4_data_a_mux[] = {
2817 RX4_A_MARK, TX4_A_MARK,
2818 };
2819 static const unsigned int scif4_clk_a_pins[] = {
2820 /* SCK */
2821 RCAR_GP_PIN(2, 10),
2822 };
2823 static const unsigned int scif4_clk_a_mux[] = {
2824 SCK4_A_MARK,
2825 };
2826 static const unsigned int scif4_ctrl_a_pins[] = {
2827 /* RTS, CTS */
2828 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2829 };
2830 static const unsigned int scif4_ctrl_a_mux[] = {
2831 RTS4_N_TANS_A_MARK, CTS4_N_A_MARK,
2832 };
2833 static const unsigned int scif4_data_b_pins[] = {
2834 /* RX, TX */
2835 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2836 };
2837 static const unsigned int scif4_data_b_mux[] = {
2838 RX4_B_MARK, TX4_B_MARK,
2839 };
2840 static const unsigned int scif4_clk_b_pins[] = {
2841 /* SCK */
2842 RCAR_GP_PIN(1, 5),
2843 };
2844 static const unsigned int scif4_clk_b_mux[] = {
2845 SCK4_B_MARK,
2846 };
2847 static const unsigned int scif4_ctrl_b_pins[] = {
2848 /* RTS, CTS */
2849 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 9),
2850 };
2851 static const unsigned int scif4_ctrl_b_mux[] = {
2852 RTS4_N_TANS_B_MARK, CTS4_N_B_MARK,
2853 };
2854 static const unsigned int scif4_data_c_pins[] = {
2855 /* RX, TX */
2856 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
2857 };
2858 static const unsigned int scif4_data_c_mux[] = {
2859 RX4_C_MARK, TX4_C_MARK,
2860 };
2861 static const unsigned int scif4_clk_c_pins[] = {
2862 /* SCK */
2863 RCAR_GP_PIN(0, 8),
2864 };
2865 static const unsigned int scif4_clk_c_mux[] = {
2866 SCK4_C_MARK,
2867 };
2868 static const unsigned int scif4_ctrl_c_pins[] = {
2869 /* RTS, CTS */
2870 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 10),
2871 };
2872 static const unsigned int scif4_ctrl_c_mux[] = {
2873 RTS4_N_TANS_C_MARK, CTS4_N_C_MARK,
2874 };
2875 /* - SCIF5 ------------------------------------------------------------------ */
2876 static const unsigned int scif5_data_pins[] = {
2877 /* RX, TX */
2878 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
2879 };
2880 static const unsigned int scif5_data_mux[] = {
2881 RX5_MARK, TX5_MARK,
2882 };
2883 static const unsigned int scif5_clk_pins[] = {
2884 /* SCK */
2885 RCAR_GP_PIN(6, 21),
2886 };
2887 static const unsigned int scif5_clk_mux[] = {
2888 SCK5_MARK,
2889 };
2890 /* - SDHI0 ------------------------------------------------------------------ */
2891 static const unsigned int sdhi0_data1_pins[] = {
2892 /* D0 */
2893 RCAR_GP_PIN(3, 2),
2894 };
2895 static const unsigned int sdhi0_data1_mux[] = {
2896 SD0_DAT0_MARK,
2897 };
2898 static const unsigned int sdhi0_data4_pins[] = {
2899 /* D[0:3] */
2900 RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
2901 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
2902 };
2903 static const unsigned int sdhi0_data4_mux[] = {
2904 SD0_DAT0_MARK, SD0_DAT1_MARK,
2905 SD0_DAT2_MARK, SD0_DAT3_MARK,
2906 };
2907 static const unsigned int sdhi0_ctrl_pins[] = {
2908 /* CLK, CMD */
2909 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2910 };
2911 static const unsigned int sdhi0_ctrl_mux[] = {
2912 SD0_CLK_MARK, SD0_CMD_MARK,
2913 };
2914 static const unsigned int sdhi0_cd_pins[] = {
2915 /* CD */
2916 RCAR_GP_PIN(3, 12),
2917 };
2918 static const unsigned int sdhi0_cd_mux[] = {
2919 SD0_CD_MARK,
2920 };
2921 static const unsigned int sdhi0_wp_pins[] = {
2922 /* WP */
2923 RCAR_GP_PIN(3, 13),
2924 };
2925 static const unsigned int sdhi0_wp_mux[] = {
2926 SD0_WP_MARK,
2927 };
2928 /* - SDHI1 ------------------------------------------------------------------ */
2929 static const unsigned int sdhi1_data1_pins[] = {
2930 /* D0 */
2931 RCAR_GP_PIN(3, 8),
2932 };
2933 static const unsigned int sdhi1_data1_mux[] = {
2934 SD1_DAT0_MARK,
2935 };
2936 static const unsigned int sdhi1_data4_pins[] = {
2937 /* D[0:3] */
2938 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2939 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2940 };
2941 static const unsigned int sdhi1_data4_mux[] = {
2942 SD1_DAT0_MARK, SD1_DAT1_MARK,
2943 SD1_DAT2_MARK, SD1_DAT3_MARK,
2944 };
2945 static const unsigned int sdhi1_ctrl_pins[] = {
2946 /* CLK, CMD */
2947 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2948 };
2949 static const unsigned int sdhi1_ctrl_mux[] = {
2950 SD1_CLK_MARK, SD1_CMD_MARK,
2951 };
2952 static const unsigned int sdhi1_cd_pins[] = {
2953 /* CD */
2954 RCAR_GP_PIN(3, 14),
2955 };
2956 static const unsigned int sdhi1_cd_mux[] = {
2957 SD1_CD_MARK,
2958 };
2959 static const unsigned int sdhi1_wp_pins[] = {
2960 /* WP */
2961 RCAR_GP_PIN(3, 15),
2962 };
2963 static const unsigned int sdhi1_wp_mux[] = {
2964 SD1_WP_MARK,
2965 };
2966 /* - SDHI2 ------------------------------------------------------------------ */
2967 static const unsigned int sdhi2_data1_pins[] = {
2968 /* D0 */
2969 RCAR_GP_PIN(4, 2),
2970 };
2971 static const unsigned int sdhi2_data1_mux[] = {
2972 SD2_DAT0_MARK,
2973 };
2974 static const unsigned int sdhi2_data4_pins[] = {
2975 /* D[0:3] */
2976 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2977 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2978 };
2979 static const unsigned int sdhi2_data4_mux[] = {
2980 SD2_DAT0_MARK, SD2_DAT1_MARK,
2981 SD2_DAT2_MARK, SD2_DAT3_MARK,
2982 };
2983 static const unsigned int sdhi2_data8_pins[] = {
2984 /* D[0:7] */
2985 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2986 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 5),
2987 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2988 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2989 };
2990 static const unsigned int sdhi2_data8_mux[] = {
2991 SD2_DAT0_MARK, SD2_DAT1_MARK,
2992 SD2_DAT2_MARK, SD2_DAT3_MARK,
2993 SD2_DAT4_MARK, SD2_DAT5_MARK,
2994 SD2_DAT6_MARK, SD2_DAT7_MARK,
2995 };
2996 static const unsigned int sdhi2_ctrl_pins[] = {
2997 /* CLK, CMD */
2998 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2999 };
3000 static const unsigned int sdhi2_ctrl_mux[] = {
3001 SD2_CLK_MARK, SD2_CMD_MARK,
3002 };
3003 static const unsigned int sdhi2_cd_a_pins[] = {
3004 /* CD */
3005 RCAR_GP_PIN(4, 13),
3006 };
3007 static const unsigned int sdhi2_cd_a_mux[] = {
3008 SD2_CD_A_MARK,
3009 };
3010 static const unsigned int sdhi2_cd_b_pins[] = {
3011 /* CD */
3012 RCAR_GP_PIN(5, 10),
3013 };
3014 static const unsigned int sdhi2_cd_b_mux[] = {
3015 SD2_CD_B_MARK,
3016 };
3017 static const unsigned int sdhi2_wp_a_pins[] = {
3018 /* WP */
3019 RCAR_GP_PIN(4, 14),
3020 };
3021 static const unsigned int sdhi2_wp_a_mux[] = {
3022 SD2_WP_A_MARK,
3023 };
3024 static const unsigned int sdhi2_wp_b_pins[] = {
3025 /* WP */
3026 RCAR_GP_PIN(5, 11),
3027 };
3028 static const unsigned int sdhi2_wp_b_mux[] = {
3029 SD2_WP_B_MARK,
3030 };
3031 static const unsigned int sdhi2_ds_pins[] = {
3032 /* DS */
3033 RCAR_GP_PIN(4, 6),
3034 };
3035 static const unsigned int sdhi2_ds_mux[] = {
3036 SD2_DS_MARK,
3037 };
3038 /* - SDHI3 ------------------------------------------------------------------ */
3039 static const unsigned int sdhi3_data1_pins[] = {
3040 /* D0 */
3041 RCAR_GP_PIN(4, 9),
3042 };
3043 static const unsigned int sdhi3_data1_mux[] = {
3044 SD3_DAT0_MARK,
3045 };
3046 static const unsigned int sdhi3_data4_pins[] = {
3047 /* D[0:3] */
3048 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3049 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3050 };
3051 static const unsigned int sdhi3_data4_mux[] = {
3052 SD3_DAT0_MARK, SD3_DAT1_MARK,
3053 SD3_DAT2_MARK, SD3_DAT3_MARK,
3054 };
3055 static const unsigned int sdhi3_data8_pins[] = {
3056 /* D[0:7] */
3057 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3058 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3059 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
3060 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3061 };
3062 static const unsigned int sdhi3_data8_mux[] = {
3063 SD3_DAT0_MARK, SD3_DAT1_MARK,
3064 SD3_DAT2_MARK, SD3_DAT3_MARK,
3065 SD3_DAT4_MARK, SD3_DAT5_MARK,
3066 SD3_DAT6_MARK, SD3_DAT7_MARK,
3067 };
3068 static const unsigned int sdhi3_ctrl_pins[] = {
3069 /* CLK, CMD */
3070 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
3071 };
3072 static const unsigned int sdhi3_ctrl_mux[] = {
3073 SD3_CLK_MARK, SD3_CMD_MARK,
3074 };
3075 static const unsigned int sdhi3_cd_pins[] = {
3076 /* CD */
3077 RCAR_GP_PIN(4, 15),
3078 };
3079 static const unsigned int sdhi3_cd_mux[] = {
3080 SD3_CD_MARK,
3081 };
3082 static const unsigned int sdhi3_wp_pins[] = {
3083 /* WP */
3084 RCAR_GP_PIN(4, 16),
3085 };
3086 static const unsigned int sdhi3_wp_mux[] = {
3087 SD3_WP_MARK,
3088 };
3089 static const unsigned int sdhi3_ds_pins[] = {
3090 /* DS */
3091 RCAR_GP_PIN(4, 17),
3092 };
3093 static const unsigned int sdhi3_ds_mux[] = {
3094 SD3_DS_MARK,
3095 };
3096
3097 /* - SCIF Clock ------------------------------------------------------------- */
3098 static const unsigned int scif_clk_a_pins[] = {
3099 /* SCIF_CLK */
3100 RCAR_GP_PIN(6, 23),
3101 };
3102 static const unsigned int scif_clk_a_mux[] = {
3103 SCIF_CLK_A_MARK,
3104 };
3105 static const unsigned int scif_clk_b_pins[] = {
3106 /* SCIF_CLK */
3107 RCAR_GP_PIN(5, 9),
3108 };
3109 static const unsigned int scif_clk_b_mux[] = {
3110 SCIF_CLK_B_MARK,
3111 };
3112
3113 /* - SSI -------------------------------------------------------------------- */
3114 static const unsigned int ssi0_data_pins[] = {
3115 /* SDATA */
3116 RCAR_GP_PIN(6, 2),
3117 };
3118 static const unsigned int ssi0_data_mux[] = {
3119 SSI_SDATA0_MARK,
3120 };
3121 static const unsigned int ssi01239_ctrl_pins[] = {
3122 /* SCK, WS */
3123 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
3124 };
3125 static const unsigned int ssi01239_ctrl_mux[] = {
3126 SSI_SCK01239_MARK, SSI_WS01239_MARK,
3127 };
3128 static const unsigned int ssi1_data_a_pins[] = {
3129 /* SDATA */
3130 RCAR_GP_PIN(6, 3),
3131 };
3132 static const unsigned int ssi1_data_a_mux[] = {
3133 SSI_SDATA1_A_MARK,
3134 };
3135 static const unsigned int ssi1_data_b_pins[] = {
3136 /* SDATA */
3137 RCAR_GP_PIN(5, 12),
3138 };
3139 static const unsigned int ssi1_data_b_mux[] = {
3140 SSI_SDATA1_B_MARK,
3141 };
3142 static const unsigned int ssi1_ctrl_a_pins[] = {
3143 /* SCK, WS */
3144 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3145 };
3146 static const unsigned int ssi1_ctrl_a_mux[] = {
3147 SSI_SCK1_A_MARK, SSI_WS1_A_MARK,
3148 };
3149 static const unsigned int ssi1_ctrl_b_pins[] = {
3150 /* SCK, WS */
3151 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 21),
3152 };
3153 static const unsigned int ssi1_ctrl_b_mux[] = {
3154 SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
3155 };
3156 static const unsigned int ssi2_data_a_pins[] = {
3157 /* SDATA */
3158 RCAR_GP_PIN(6, 4),
3159 };
3160 static const unsigned int ssi2_data_a_mux[] = {
3161 SSI_SDATA2_A_MARK,
3162 };
3163 static const unsigned int ssi2_data_b_pins[] = {
3164 /* SDATA */
3165 RCAR_GP_PIN(5, 13),
3166 };
3167 static const unsigned int ssi2_data_b_mux[] = {
3168 SSI_SDATA2_B_MARK,
3169 };
3170 static const unsigned int ssi2_ctrl_a_pins[] = {
3171 /* SCK, WS */
3172 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 21),
3173 };
3174 static const unsigned int ssi2_ctrl_a_mux[] = {
3175 SSI_SCK2_A_MARK, SSI_WS2_A_MARK,
3176 };
3177 static const unsigned int ssi2_ctrl_b_pins[] = {
3178 /* SCK, WS */
3179 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3180 };
3181 static const unsigned int ssi2_ctrl_b_mux[] = {
3182 SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3183 };
3184 static const unsigned int ssi3_data_pins[] = {
3185 /* SDATA */
3186 RCAR_GP_PIN(6, 7),
3187 };
3188 static const unsigned int ssi3_data_mux[] = {
3189 SSI_SDATA3_MARK,
3190 };
3191 static const unsigned int ssi34_ctrl_pins[] = {
3192 /* SCK, WS */
3193 RCAR_GP_PIN(6, 5), RCAR_GP_PIN(6, 6),
3194 };
3195 static const unsigned int ssi34_ctrl_mux[] = {
3196 SSI_SCK34_MARK, SSI_WS34_MARK,
3197 };
3198 static const unsigned int ssi4_data_pins[] = {
3199 /* SDATA */
3200 RCAR_GP_PIN(6, 10),
3201 };
3202 static const unsigned int ssi4_data_mux[] = {
3203 SSI_SDATA4_MARK,
3204 };
3205 static const unsigned int ssi4_ctrl_pins[] = {
3206 /* SCK, WS */
3207 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
3208 };
3209 static const unsigned int ssi4_ctrl_mux[] = {
3210 SSI_SCK4_MARK, SSI_WS4_MARK,
3211 };
3212 static const unsigned int ssi5_data_pins[] = {
3213 /* SDATA */
3214 RCAR_GP_PIN(6, 13),
3215 };
3216 static const unsigned int ssi5_data_mux[] = {
3217 SSI_SDATA5_MARK,
3218 };
3219 static const unsigned int ssi5_ctrl_pins[] = {
3220 /* SCK, WS */
3221 RCAR_GP_PIN(6, 11), RCAR_GP_PIN(6, 12),
3222 };
3223 static const unsigned int ssi5_ctrl_mux[] = {
3224 SSI_SCK5_MARK, SSI_WS5_MARK,
3225 };
3226 static const unsigned int ssi6_data_pins[] = {
3227 /* SDATA */
3228 RCAR_GP_PIN(6, 16),
3229 };
3230 static const unsigned int ssi6_data_mux[] = {
3231 SSI_SDATA6_MARK,
3232 };
3233 static const unsigned int ssi6_ctrl_pins[] = {
3234 /* SCK, WS */
3235 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3236 };
3237 static const unsigned int ssi6_ctrl_mux[] = {
3238 SSI_SCK6_MARK, SSI_WS6_MARK,
3239 };
3240 static const unsigned int ssi7_data_pins[] = {
3241 /* SDATA */
3242 RCAR_GP_PIN(6, 19),
3243 };
3244 static const unsigned int ssi7_data_mux[] = {
3245 SSI_SDATA7_MARK,
3246 };
3247 static const unsigned int ssi78_ctrl_pins[] = {
3248 /* SCK, WS */
3249 RCAR_GP_PIN(6, 17), RCAR_GP_PIN(6, 18),
3250 };
3251 static const unsigned int ssi78_ctrl_mux[] = {
3252 SSI_SCK78_MARK, SSI_WS78_MARK,
3253 };
3254 static const unsigned int ssi8_data_pins[] = {
3255 /* SDATA */
3256 RCAR_GP_PIN(6, 20),
3257 };
3258 static const unsigned int ssi8_data_mux[] = {
3259 SSI_SDATA8_MARK,
3260 };
3261 static const unsigned int ssi9_data_a_pins[] = {
3262 /* SDATA */
3263 RCAR_GP_PIN(6, 21),
3264 };
3265 static const unsigned int ssi9_data_a_mux[] = {
3266 SSI_SDATA9_A_MARK,
3267 };
3268 static const unsigned int ssi9_data_b_pins[] = {
3269 /* SDATA */
3270 RCAR_GP_PIN(5, 14),
3271 };
3272 static const unsigned int ssi9_data_b_mux[] = {
3273 SSI_SDATA9_B_MARK,
3274 };
3275 static const unsigned int ssi9_ctrl_a_pins[] = {
3276 /* SCK, WS */
3277 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
3278 };
3279 static const unsigned int ssi9_ctrl_a_mux[] = {
3280 SSI_SCK9_A_MARK, SSI_WS9_A_MARK,
3281 };
3282 static const unsigned int ssi9_ctrl_b_pins[] = {
3283 /* SCK, WS */
3284 RCAR_GP_PIN(6, 30), RCAR_GP_PIN(6, 31),
3285 };
3286 static const unsigned int ssi9_ctrl_b_mux[] = {
3287 SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3288 };
3289
3290 /* - USB0 ------------------------------------------------------------------- */
3291 static const unsigned int usb0_pins[] = {
3292 /* PWEN, OVC */
3293 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
3294 };
3295 static const unsigned int usb0_mux[] = {
3296 USB0_PWEN_MARK, USB0_OVC_MARK,
3297 };
3298 /* - USB1 ------------------------------------------------------------------- */
3299 static const unsigned int usb1_pins[] = {
3300 /* PWEN, OVC */
3301 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3302 };
3303 static const unsigned int usb1_mux[] = {
3304 USB1_PWEN_MARK, USB1_OVC_MARK,
3305 };
3306 /* - USB2 ------------------------------------------------------------------- */
3307 static const unsigned int usb2_pins[] = {
3308 /* PWEN, OVC */
3309 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
3310 };
3311 static const unsigned int usb2_mux[] = {
3312 USB2_PWEN_MARK, USB2_OVC_MARK,
3313 };
3314
3315 static const struct sh_pfc_pin_group pinmux_groups[] = {
3316 SH_PFC_PIN_GROUP(audio_clk_a_a),
3317 SH_PFC_PIN_GROUP(audio_clk_a_b),
3318 SH_PFC_PIN_GROUP(audio_clk_a_c),
3319 SH_PFC_PIN_GROUP(audio_clk_b_a),
3320 SH_PFC_PIN_GROUP(audio_clk_b_b),
3321 SH_PFC_PIN_GROUP(audio_clk_c_a),
3322 SH_PFC_PIN_GROUP(audio_clk_c_b),
3323 SH_PFC_PIN_GROUP(audio_clkout_a),
3324 SH_PFC_PIN_GROUP(audio_clkout_b),
3325 SH_PFC_PIN_GROUP(audio_clkout_c),
3326 SH_PFC_PIN_GROUP(audio_clkout_d),
3327 SH_PFC_PIN_GROUP(audio_clkout1_a),
3328 SH_PFC_PIN_GROUP(audio_clkout1_b),
3329 SH_PFC_PIN_GROUP(audio_clkout2_a),
3330 SH_PFC_PIN_GROUP(audio_clkout2_b),
3331 SH_PFC_PIN_GROUP(audio_clkout3_a),
3332 SH_PFC_PIN_GROUP(audio_clkout3_b),
3333 SH_PFC_PIN_GROUP(avb_link),
3334 SH_PFC_PIN_GROUP(avb_magic),
3335 SH_PFC_PIN_GROUP(avb_phy_int),
3336 SH_PFC_PIN_GROUP(avb_mdc),
3337 SH_PFC_PIN_GROUP(avb_avtp_pps),
3338 SH_PFC_PIN_GROUP(avb_avtp_match_a),
3339 SH_PFC_PIN_GROUP(avb_avtp_capture_a),
3340 SH_PFC_PIN_GROUP(avb_avtp_match_b),
3341 SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3342 SH_PFC_PIN_GROUP(can0_data_a),
3343 SH_PFC_PIN_GROUP(can0_data_b),
3344 SH_PFC_PIN_GROUP(can1_data),
3345 SH_PFC_PIN_GROUP(can_clk),
3346 SH_PFC_PIN_GROUP(canfd0_data_a),
3347 SH_PFC_PIN_GROUP(canfd0_data_b),
3348 SH_PFC_PIN_GROUP(canfd1_data),
3349 SH_PFC_PIN_GROUP(hscif0_data),
3350 SH_PFC_PIN_GROUP(hscif0_clk),
3351 SH_PFC_PIN_GROUP(hscif0_ctrl),
3352 SH_PFC_PIN_GROUP(hscif1_data_a),
3353 SH_PFC_PIN_GROUP(hscif1_clk_a),
3354 SH_PFC_PIN_GROUP(hscif1_ctrl_a),
3355 SH_PFC_PIN_GROUP(hscif1_data_b),
3356 SH_PFC_PIN_GROUP(hscif1_clk_b),
3357 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3358 SH_PFC_PIN_GROUP(hscif2_data_a),
3359 SH_PFC_PIN_GROUP(hscif2_clk_a),
3360 SH_PFC_PIN_GROUP(hscif2_ctrl_a),
3361 SH_PFC_PIN_GROUP(hscif2_data_b),
3362 SH_PFC_PIN_GROUP(hscif2_clk_b),
3363 SH_PFC_PIN_GROUP(hscif2_ctrl_b),
3364 SH_PFC_PIN_GROUP(hscif3_data_a),
3365 SH_PFC_PIN_GROUP(hscif3_clk),
3366 SH_PFC_PIN_GROUP(hscif3_ctrl),
3367 SH_PFC_PIN_GROUP(hscif3_data_b),
3368 SH_PFC_PIN_GROUP(hscif3_data_c),
3369 SH_PFC_PIN_GROUP(hscif3_data_d),
3370 SH_PFC_PIN_GROUP(hscif4_data_a),
3371 SH_PFC_PIN_GROUP(hscif4_clk),
3372 SH_PFC_PIN_GROUP(hscif4_ctrl),
3373 SH_PFC_PIN_GROUP(hscif4_data_b),
3374 SH_PFC_PIN_GROUP(i2c1_a),
3375 SH_PFC_PIN_GROUP(i2c1_b),
3376 SH_PFC_PIN_GROUP(i2c2_a),
3377 SH_PFC_PIN_GROUP(i2c2_b),
3378 SH_PFC_PIN_GROUP(i2c6_a),
3379 SH_PFC_PIN_GROUP(i2c6_b),
3380 SH_PFC_PIN_GROUP(i2c6_c),
3381 SH_PFC_PIN_GROUP(intc_ex_irq0),
3382 SH_PFC_PIN_GROUP(intc_ex_irq1),
3383 SH_PFC_PIN_GROUP(intc_ex_irq2),
3384 SH_PFC_PIN_GROUP(intc_ex_irq3),
3385 SH_PFC_PIN_GROUP(intc_ex_irq4),
3386 SH_PFC_PIN_GROUP(intc_ex_irq5),
3387 SH_PFC_PIN_GROUP(msiof0_clk),
3388 SH_PFC_PIN_GROUP(msiof0_sync),
3389 SH_PFC_PIN_GROUP(msiof0_ss1),
3390 SH_PFC_PIN_GROUP(msiof0_ss2),
3391 SH_PFC_PIN_GROUP(msiof0_txd),
3392 SH_PFC_PIN_GROUP(msiof0_rxd),
3393 SH_PFC_PIN_GROUP(msiof1_clk_a),
3394 SH_PFC_PIN_GROUP(msiof1_sync_a),
3395 SH_PFC_PIN_GROUP(msiof1_ss1_a),
3396 SH_PFC_PIN_GROUP(msiof1_ss2_a),
3397 SH_PFC_PIN_GROUP(msiof1_txd_a),
3398 SH_PFC_PIN_GROUP(msiof1_rxd_a),
3399 SH_PFC_PIN_GROUP(msiof1_clk_b),
3400 SH_PFC_PIN_GROUP(msiof1_sync_b),
3401 SH_PFC_PIN_GROUP(msiof1_ss1_b),
3402 SH_PFC_PIN_GROUP(msiof1_ss2_b),
3403 SH_PFC_PIN_GROUP(msiof1_txd_b),
3404 SH_PFC_PIN_GROUP(msiof1_rxd_b),
3405 SH_PFC_PIN_GROUP(msiof1_clk_c),
3406 SH_PFC_PIN_GROUP(msiof1_sync_c),
3407 SH_PFC_PIN_GROUP(msiof1_ss1_c),
3408 SH_PFC_PIN_GROUP(msiof1_ss2_c),
3409 SH_PFC_PIN_GROUP(msiof1_txd_c),
3410 SH_PFC_PIN_GROUP(msiof1_rxd_c),
3411 SH_PFC_PIN_GROUP(msiof1_clk_d),
3412 SH_PFC_PIN_GROUP(msiof1_sync_d),
3413 SH_PFC_PIN_GROUP(msiof1_ss1_d),
3414 SH_PFC_PIN_GROUP(msiof1_ss2_d),
3415 SH_PFC_PIN_GROUP(msiof1_txd_d),
3416 SH_PFC_PIN_GROUP(msiof1_rxd_d),
3417 SH_PFC_PIN_GROUP(msiof1_clk_e),
3418 SH_PFC_PIN_GROUP(msiof1_sync_e),
3419 SH_PFC_PIN_GROUP(msiof1_ss1_e),
3420 SH_PFC_PIN_GROUP(msiof1_ss2_e),
3421 SH_PFC_PIN_GROUP(msiof1_txd_e),
3422 SH_PFC_PIN_GROUP(msiof1_rxd_e),
3423 SH_PFC_PIN_GROUP(msiof1_clk_f),
3424 SH_PFC_PIN_GROUP(msiof1_sync_f),
3425 SH_PFC_PIN_GROUP(msiof1_ss1_f),
3426 SH_PFC_PIN_GROUP(msiof1_ss2_f),
3427 SH_PFC_PIN_GROUP(msiof1_txd_f),
3428 SH_PFC_PIN_GROUP(msiof1_rxd_f),
3429 SH_PFC_PIN_GROUP(msiof1_clk_g),
3430 SH_PFC_PIN_GROUP(msiof1_sync_g),
3431 SH_PFC_PIN_GROUP(msiof1_ss1_g),
3432 SH_PFC_PIN_GROUP(msiof1_ss2_g),
3433 SH_PFC_PIN_GROUP(msiof1_txd_g),
3434 SH_PFC_PIN_GROUP(msiof1_rxd_g),
3435 SH_PFC_PIN_GROUP(msiof2_clk_a),
3436 SH_PFC_PIN_GROUP(msiof2_sync_a),
3437 SH_PFC_PIN_GROUP(msiof2_ss1_a),
3438 SH_PFC_PIN_GROUP(msiof2_ss2_a),
3439 SH_PFC_PIN_GROUP(msiof2_txd_a),
3440 SH_PFC_PIN_GROUP(msiof2_rxd_a),
3441 SH_PFC_PIN_GROUP(msiof2_clk_b),
3442 SH_PFC_PIN_GROUP(msiof2_sync_b),
3443 SH_PFC_PIN_GROUP(msiof2_ss1_b),
3444 SH_PFC_PIN_GROUP(msiof2_ss2_b),
3445 SH_PFC_PIN_GROUP(msiof2_txd_b),
3446 SH_PFC_PIN_GROUP(msiof2_rxd_b),
3447 SH_PFC_PIN_GROUP(msiof2_clk_c),
3448 SH_PFC_PIN_GROUP(msiof2_sync_c),
3449 SH_PFC_PIN_GROUP(msiof2_ss1_c),
3450 SH_PFC_PIN_GROUP(msiof2_ss2_c),
3451 SH_PFC_PIN_GROUP(msiof2_txd_c),
3452 SH_PFC_PIN_GROUP(msiof2_rxd_c),
3453 SH_PFC_PIN_GROUP(msiof2_clk_d),
3454 SH_PFC_PIN_GROUP(msiof2_sync_d),
3455 SH_PFC_PIN_GROUP(msiof2_ss1_d),
3456 SH_PFC_PIN_GROUP(msiof2_ss2_d),
3457 SH_PFC_PIN_GROUP(msiof2_txd_d),
3458 SH_PFC_PIN_GROUP(msiof2_rxd_d),
3459 SH_PFC_PIN_GROUP(msiof3_clk_a),
3460 SH_PFC_PIN_GROUP(msiof3_sync_a),
3461 SH_PFC_PIN_GROUP(msiof3_ss1_a),
3462 SH_PFC_PIN_GROUP(msiof3_ss2_a),
3463 SH_PFC_PIN_GROUP(msiof3_txd_a),
3464 SH_PFC_PIN_GROUP(msiof3_rxd_a),
3465 SH_PFC_PIN_GROUP(msiof3_clk_b),
3466 SH_PFC_PIN_GROUP(msiof3_sync_b),
3467 SH_PFC_PIN_GROUP(msiof3_ss1_b),
3468 SH_PFC_PIN_GROUP(msiof3_ss2_b),
3469 SH_PFC_PIN_GROUP(msiof3_txd_b),
3470 SH_PFC_PIN_GROUP(msiof3_rxd_b),
3471 SH_PFC_PIN_GROUP(msiof3_clk_c),
3472 SH_PFC_PIN_GROUP(msiof3_sync_c),
3473 SH_PFC_PIN_GROUP(msiof3_txd_c),
3474 SH_PFC_PIN_GROUP(msiof3_rxd_c),
3475 SH_PFC_PIN_GROUP(msiof3_clk_d),
3476 SH_PFC_PIN_GROUP(msiof3_sync_d),
3477 SH_PFC_PIN_GROUP(msiof3_ss1_d),
3478 SH_PFC_PIN_GROUP(msiof3_txd_d),
3479 SH_PFC_PIN_GROUP(msiof3_rxd_d),
3480 SH_PFC_PIN_GROUP(pwm0),
3481 SH_PFC_PIN_GROUP(pwm1_a),
3482 SH_PFC_PIN_GROUP(pwm1_b),
3483 SH_PFC_PIN_GROUP(pwm2_a),
3484 SH_PFC_PIN_GROUP(pwm2_b),
3485 SH_PFC_PIN_GROUP(pwm3_a),
3486 SH_PFC_PIN_GROUP(pwm3_b),
3487 SH_PFC_PIN_GROUP(pwm4_a),
3488 SH_PFC_PIN_GROUP(pwm4_b),
3489 SH_PFC_PIN_GROUP(pwm5_a),
3490 SH_PFC_PIN_GROUP(pwm5_b),
3491 SH_PFC_PIN_GROUP(pwm6_a),
3492 SH_PFC_PIN_GROUP(pwm6_b),
3493 SH_PFC_PIN_GROUP(sata0_devslp_a),
3494 SH_PFC_PIN_GROUP(sata0_devslp_b),
3495 SH_PFC_PIN_GROUP(scif0_data),
3496 SH_PFC_PIN_GROUP(scif0_clk),
3497 SH_PFC_PIN_GROUP(scif0_ctrl),
3498 SH_PFC_PIN_GROUP(scif1_data_a),
3499 SH_PFC_PIN_GROUP(scif1_clk),
3500 SH_PFC_PIN_GROUP(scif1_ctrl),
3501 SH_PFC_PIN_GROUP(scif1_data_b),
3502 SH_PFC_PIN_GROUP(scif2_data_a),
3503 SH_PFC_PIN_GROUP(scif2_clk),
3504 SH_PFC_PIN_GROUP(scif2_data_b),
3505 SH_PFC_PIN_GROUP(scif3_data_a),
3506 SH_PFC_PIN_GROUP(scif3_clk),
3507 SH_PFC_PIN_GROUP(scif3_ctrl),
3508 SH_PFC_PIN_GROUP(scif3_data_b),
3509 SH_PFC_PIN_GROUP(scif4_data_a),
3510 SH_PFC_PIN_GROUP(scif4_clk_a),
3511 SH_PFC_PIN_GROUP(scif4_ctrl_a),
3512 SH_PFC_PIN_GROUP(scif4_data_b),
3513 SH_PFC_PIN_GROUP(scif4_clk_b),
3514 SH_PFC_PIN_GROUP(scif4_ctrl_b),
3515 SH_PFC_PIN_GROUP(scif4_data_c),
3516 SH_PFC_PIN_GROUP(scif4_clk_c),
3517 SH_PFC_PIN_GROUP(scif4_ctrl_c),
3518 SH_PFC_PIN_GROUP(scif5_data),
3519 SH_PFC_PIN_GROUP(scif5_clk),
3520 SH_PFC_PIN_GROUP(scif_clk_a),
3521 SH_PFC_PIN_GROUP(scif_clk_b),
3522 SH_PFC_PIN_GROUP(sdhi0_data1),
3523 SH_PFC_PIN_GROUP(sdhi0_data4),
3524 SH_PFC_PIN_GROUP(sdhi0_ctrl),
3525 SH_PFC_PIN_GROUP(sdhi0_cd),
3526 SH_PFC_PIN_GROUP(sdhi0_wp),
3527 SH_PFC_PIN_GROUP(sdhi1_data1),
3528 SH_PFC_PIN_GROUP(sdhi1_data4),
3529 SH_PFC_PIN_GROUP(sdhi1_ctrl),
3530 SH_PFC_PIN_GROUP(sdhi1_cd),
3531 SH_PFC_PIN_GROUP(sdhi1_wp),
3532 SH_PFC_PIN_GROUP(sdhi2_data1),
3533 SH_PFC_PIN_GROUP(sdhi2_data4),
3534 SH_PFC_PIN_GROUP(sdhi2_data8),
3535 SH_PFC_PIN_GROUP(sdhi2_ctrl),
3536 SH_PFC_PIN_GROUP(sdhi2_cd_a),
3537 SH_PFC_PIN_GROUP(sdhi2_wp_a),
3538 SH_PFC_PIN_GROUP(sdhi2_cd_b),
3539 SH_PFC_PIN_GROUP(sdhi2_wp_b),
3540 SH_PFC_PIN_GROUP(sdhi2_ds),
3541 SH_PFC_PIN_GROUP(sdhi3_data1),
3542 SH_PFC_PIN_GROUP(sdhi3_data4),
3543 SH_PFC_PIN_GROUP(sdhi3_data8),
3544 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3545 SH_PFC_PIN_GROUP(sdhi3_cd),
3546 SH_PFC_PIN_GROUP(sdhi3_wp),
3547 SH_PFC_PIN_GROUP(sdhi3_ds),
3548 SH_PFC_PIN_GROUP(ssi0_data),
3549 SH_PFC_PIN_GROUP(ssi01239_ctrl),
3550 SH_PFC_PIN_GROUP(ssi1_data_a),
3551 SH_PFC_PIN_GROUP(ssi1_data_b),
3552 SH_PFC_PIN_GROUP(ssi1_ctrl_a),
3553 SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3554 SH_PFC_PIN_GROUP(ssi2_data_a),
3555 SH_PFC_PIN_GROUP(ssi2_data_b),
3556 SH_PFC_PIN_GROUP(ssi2_ctrl_a),
3557 SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3558 SH_PFC_PIN_GROUP(ssi3_data),
3559 SH_PFC_PIN_GROUP(ssi34_ctrl),
3560 SH_PFC_PIN_GROUP(ssi4_data),
3561 SH_PFC_PIN_GROUP(ssi4_ctrl),
3562 SH_PFC_PIN_GROUP(ssi5_data),
3563 SH_PFC_PIN_GROUP(ssi5_ctrl),
3564 SH_PFC_PIN_GROUP(ssi6_data),
3565 SH_PFC_PIN_GROUP(ssi6_ctrl),
3566 SH_PFC_PIN_GROUP(ssi7_data),
3567 SH_PFC_PIN_GROUP(ssi78_ctrl),
3568 SH_PFC_PIN_GROUP(ssi8_data),
3569 SH_PFC_PIN_GROUP(ssi9_data_a),
3570 SH_PFC_PIN_GROUP(ssi9_data_b),
3571 SH_PFC_PIN_GROUP(ssi9_ctrl_a),
3572 SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3573 SH_PFC_PIN_GROUP(usb0),
3574 SH_PFC_PIN_GROUP(usb1),
3575 SH_PFC_PIN_GROUP(usb2),
3576 };
3577
3578 static const char * const audio_clk_groups[] = {
3579 "audio_clk_a_a",
3580 "audio_clk_a_b",
3581 "audio_clk_a_c",
3582 "audio_clk_b_a",
3583 "audio_clk_b_b",
3584 "audio_clk_c_a",
3585 "audio_clk_c_b",
3586 "audio_clkout_a",
3587 "audio_clkout_b",
3588 "audio_clkout_c",
3589 "audio_clkout_d",
3590 "audio_clkout1_a",
3591 "audio_clkout1_b",
3592 "audio_clkout2_a",
3593 "audio_clkout2_b",
3594 "audio_clkout3_a",
3595 "audio_clkout3_b",
3596 };
3597
3598 static const char * const avb_groups[] = {
3599 "avb_link",
3600 "avb_magic",
3601 "avb_phy_int",
3602 "avb_mdc",
3603 "avb_avtp_pps",
3604 "avb_avtp_match_a",
3605 "avb_avtp_capture_a",
3606 "avb_avtp_match_b",
3607 "avb_avtp_capture_b",
3608 };
3609
3610 static const char * const can0_groups[] = {
3611 "can0_data_a",
3612 "can0_data_b",
3613 };
3614
3615 static const char * const can1_groups[] = {
3616 "can1_data",
3617 };
3618
3619 static const char * const can_clk_groups[] = {
3620 "can_clk",
3621 };
3622
3623 static const char * const canfd0_groups[] = {
3624 "canfd0_data_a",
3625 "canfd0_data_b",
3626 };
3627
3628 static const char * const canfd1_groups[] = {
3629 "canfd1_data",
3630 };
3631
3632 static const char * const hscif0_groups[] = {
3633 "hscif0_data",
3634 "hscif0_clk",
3635 "hscif0_ctrl",
3636 };
3637
3638 static const char * const hscif1_groups[] = {
3639 "hscif1_data_a",
3640 "hscif1_clk_a",
3641 "hscif1_ctrl_a",
3642 "hscif1_data_b",
3643 "hscif1_clk_b",
3644 "hscif1_ctrl_b",
3645 };
3646
3647 static const char * const hscif2_groups[] = {
3648 "hscif2_data_a",
3649 "hscif2_clk_a",
3650 "hscif2_ctrl_a",
3651 "hscif2_data_b",
3652 "hscif2_clk_b",
3653 "hscif2_ctrl_b",
3654 };
3655
3656 static const char * const hscif3_groups[] = {
3657 "hscif3_data_a",
3658 "hscif3_clk",
3659 "hscif3_ctrl",
3660 "hscif3_data_b",
3661 "hscif3_data_c",
3662 "hscif3_data_d",
3663 };
3664
3665 static const char * const hscif4_groups[] = {
3666 "hscif4_data_a",
3667 "hscif4_clk",
3668 "hscif4_ctrl",
3669 "hscif4_data_b",
3670 };
3671
3672 static const char * const i2c1_groups[] = {
3673 "i2c1_a",
3674 "i2c1_b",
3675 };
3676
3677 static const char * const i2c2_groups[] = {
3678 "i2c2_a",
3679 "i2c2_b",
3680 };
3681
3682 static const char * const i2c6_groups[] = {
3683 "i2c6_a",
3684 "i2c6_b",
3685 "i2c6_c",
3686 };
3687
3688 static const char * const intc_ex_groups[] = {
3689 "intc_ex_irq0",
3690 "intc_ex_irq1",
3691 "intc_ex_irq2",
3692 "intc_ex_irq3",
3693 "intc_ex_irq4",
3694 "intc_ex_irq5",
3695 };
3696
3697 static const char * const msiof0_groups[] = {
3698 "msiof0_clk",
3699 "msiof0_sync",
3700 "msiof0_ss1",
3701 "msiof0_ss2",
3702 "msiof0_txd",
3703 "msiof0_rxd",
3704 };
3705
3706 static const char * const msiof1_groups[] = {
3707 "msiof1_clk_a",
3708 "msiof1_sync_a",
3709 "msiof1_ss1_a",
3710 "msiof1_ss2_a",
3711 "msiof1_txd_a",
3712 "msiof1_rxd_a",
3713 "msiof1_clk_b",
3714 "msiof1_sync_b",
3715 "msiof1_ss1_b",
3716 "msiof1_ss2_b",
3717 "msiof1_txd_b",
3718 "msiof1_rxd_b",
3719 "msiof1_clk_c",
3720 "msiof1_sync_c",
3721 "msiof1_ss1_c",
3722 "msiof1_ss2_c",
3723 "msiof1_txd_c",
3724 "msiof1_rxd_c",
3725 "msiof1_clk_d",
3726 "msiof1_sync_d",
3727 "msiof1_ss1_d",
3728 "msiof1_ss2_d",
3729 "msiof1_txd_d",
3730 "msiof1_rxd_d",
3731 "msiof1_clk_e",
3732 "msiof1_sync_e",
3733 "msiof1_ss1_e",
3734 "msiof1_ss2_e",
3735 "msiof1_txd_e",
3736 "msiof1_rxd_e",
3737 "msiof1_clk_f",
3738 "msiof1_sync_f",
3739 "msiof1_ss1_f",
3740 "msiof1_ss2_f",
3741 "msiof1_txd_f",
3742 "msiof1_rxd_f",
3743 "msiof1_clk_g",
3744 "msiof1_sync_g",
3745 "msiof1_ss1_g",
3746 "msiof1_ss2_g",
3747 "msiof1_txd_g",
3748 "msiof1_rxd_g",
3749 };
3750
3751 static const char * const msiof2_groups[] = {
3752 "msiof2_clk_a",
3753 "msiof2_sync_a",
3754 "msiof2_ss1_a",
3755 "msiof2_ss2_a",
3756 "msiof2_txd_a",
3757 "msiof2_rxd_a",
3758 "msiof2_clk_b",
3759 "msiof2_sync_b",
3760 "msiof2_ss1_b",
3761 "msiof2_ss2_b",
3762 "msiof2_txd_b",
3763 "msiof2_rxd_b",
3764 "msiof2_clk_c",
3765 "msiof2_sync_c",
3766 "msiof2_ss1_c",
3767 "msiof2_ss2_c",
3768 "msiof2_txd_c",
3769 "msiof2_rxd_c",
3770 "msiof2_clk_d",
3771 "msiof2_sync_d",
3772 "msiof2_ss1_d",
3773 "msiof2_ss2_d",
3774 "msiof2_txd_d",
3775 "msiof2_rxd_d",
3776 };
3777
3778 static const char * const msiof3_groups[] = {
3779 "msiof3_clk_a",
3780 "msiof3_sync_a",
3781 "msiof3_ss1_a",
3782 "msiof3_ss2_a",
3783 "msiof3_txd_a",
3784 "msiof3_rxd_a",
3785 "msiof3_clk_b",
3786 "msiof3_sync_b",
3787 "msiof3_ss1_b",
3788 "msiof3_ss2_b",
3789 "msiof3_txd_b",
3790 "msiof3_rxd_b",
3791 "msiof3_clk_c",
3792 "msiof3_sync_c",
3793 "msiof3_txd_c",
3794 "msiof3_rxd_c",
3795 "msiof3_clk_d",
3796 "msiof3_sync_d",
3797 "msiof3_ss1_d",
3798 "msiof3_txd_d",
3799 "msiof3_rxd_d",
3800 };
3801
3802 static const char * const pwm0_groups[] = {
3803 "pwm0",
3804 };
3805
3806 static const char * const pwm1_groups[] = {
3807 "pwm1_a",
3808 "pwm1_b",
3809 };
3810
3811 static const char * const pwm2_groups[] = {
3812 "pwm2_a",
3813 "pwm2_b",
3814 };
3815
3816 static const char * const pwm3_groups[] = {
3817 "pwm3_a",
3818 "pwm3_b",
3819 };
3820
3821 static const char * const pwm4_groups[] = {
3822 "pwm4_a",
3823 "pwm4_b",
3824 };
3825
3826 static const char * const pwm5_groups[] = {
3827 "pwm5_a",
3828 "pwm5_b",
3829 };
3830
3831 static const char * const pwm6_groups[] = {
3832 "pwm6_a",
3833 "pwm6_b",
3834 };
3835
3836 static const char * const sata0_groups[] = {
3837 "sata0_devslp_a",
3838 "sata0_devslp_b",
3839 };
3840
3841 static const char * const scif0_groups[] = {
3842 "scif0_data",
3843 "scif0_clk",
3844 "scif0_ctrl",
3845 };
3846
3847 static const char * const scif1_groups[] = {
3848 "scif1_data_a",
3849 "scif1_clk",
3850 "scif1_ctrl",
3851 "scif1_data_b",
3852 };
3853
3854 static const char * const scif2_groups[] = {
3855 "scif2_data_a",
3856 "scif2_clk",
3857 "scif2_data_b",
3858 };
3859
3860 static const char * const scif3_groups[] = {
3861 "scif3_data_a",
3862 "scif3_clk",
3863 "scif3_ctrl",
3864 "scif3_data_b",
3865 };
3866
3867 static const char * const scif4_groups[] = {
3868 "scif4_data_a",
3869 "scif4_clk_a",
3870 "scif4_ctrl_a",
3871 "scif4_data_b",
3872 "scif4_clk_b",
3873 "scif4_ctrl_b",
3874 "scif4_data_c",
3875 "scif4_clk_c",
3876 "scif4_ctrl_c",
3877 };
3878
3879 static const char * const scif5_groups[] = {
3880 "scif5_data",
3881 "scif5_clk",
3882 };
3883
3884 static const char * const scif_clk_groups[] = {
3885 "scif_clk_a",
3886 "scif_clk_b",
3887 };
3888
3889 static const char * const sdhi0_groups[] = {
3890 "sdhi0_data1",
3891 "sdhi0_data4",
3892 "sdhi0_ctrl",
3893 "sdhi0_cd",
3894 "sdhi0_wp",
3895 };
3896
3897 static const char * const sdhi1_groups[] = {
3898 "sdhi1_data1",
3899 "sdhi1_data4",
3900 "sdhi1_ctrl",
3901 "sdhi1_cd",
3902 "sdhi1_wp",
3903 };
3904
3905 static const char * const sdhi2_groups[] = {
3906 "sdhi2_data1",
3907 "sdhi2_data4",
3908 "sdhi2_data8",
3909 "sdhi2_ctrl",
3910 "sdhi2_cd_a",
3911 "sdhi2_wp_a",
3912 "sdhi2_cd_b",
3913 "sdhi2_wp_b",
3914 "sdhi2_ds",
3915 };
3916
3917 static const char * const sdhi3_groups[] = {
3918 "sdhi3_data1",
3919 "sdhi3_data4",
3920 "sdhi3_data8",
3921 "sdhi3_ctrl",
3922 "sdhi3_cd",
3923 "sdhi3_wp",
3924 "sdhi3_ds",
3925 };
3926
3927 static const char * const ssi_groups[] = {
3928 "ssi0_data",
3929 "ssi01239_ctrl",
3930 "ssi1_data_a",
3931 "ssi1_data_b",
3932 "ssi1_ctrl_a",
3933 "ssi1_ctrl_b",
3934 "ssi2_data_a",
3935 "ssi2_data_b",
3936 "ssi2_ctrl_a",
3937 "ssi2_ctrl_b",
3938 "ssi3_data",
3939 "ssi34_ctrl",
3940 "ssi4_data",
3941 "ssi4_ctrl",
3942 "ssi5_data",
3943 "ssi5_ctrl",
3944 "ssi6_data",
3945 "ssi6_ctrl",
3946 "ssi7_data",
3947 "ssi78_ctrl",
3948 "ssi8_data",
3949 "ssi9_data_a",
3950 "ssi9_data_b",
3951 "ssi9_ctrl_a",
3952 "ssi9_ctrl_b",
3953 };
3954
3955 static const char * const usb0_groups[] = {
3956 "usb0",
3957 };
3958
3959 static const char * const usb1_groups[] = {
3960 "usb1",
3961 };
3962
3963 static const char * const usb2_groups[] = {
3964 "usb2",
3965 };
3966
3967 static const struct sh_pfc_function pinmux_functions[] = {
3968 SH_PFC_FUNCTION(audio_clk),
3969 SH_PFC_FUNCTION(avb),
3970 SH_PFC_FUNCTION(can0),
3971 SH_PFC_FUNCTION(can1),
3972 SH_PFC_FUNCTION(can_clk),
3973 SH_PFC_FUNCTION(canfd0),
3974 SH_PFC_FUNCTION(canfd1),
3975 SH_PFC_FUNCTION(hscif0),
3976 SH_PFC_FUNCTION(hscif1),
3977 SH_PFC_FUNCTION(hscif2),
3978 SH_PFC_FUNCTION(hscif3),
3979 SH_PFC_FUNCTION(hscif4),
3980 SH_PFC_FUNCTION(i2c1),
3981 SH_PFC_FUNCTION(i2c2),
3982 SH_PFC_FUNCTION(i2c6),
3983 SH_PFC_FUNCTION(intc_ex),
3984 SH_PFC_FUNCTION(msiof0),
3985 SH_PFC_FUNCTION(msiof1),
3986 SH_PFC_FUNCTION(msiof2),
3987 SH_PFC_FUNCTION(msiof3),
3988 SH_PFC_FUNCTION(pwm0),
3989 SH_PFC_FUNCTION(pwm1),
3990 SH_PFC_FUNCTION(pwm2),
3991 SH_PFC_FUNCTION(pwm3),
3992 SH_PFC_FUNCTION(pwm4),
3993 SH_PFC_FUNCTION(pwm5),
3994 SH_PFC_FUNCTION(pwm6),
3995 SH_PFC_FUNCTION(sata0),
3996 SH_PFC_FUNCTION(scif0),
3997 SH_PFC_FUNCTION(scif1),
3998 SH_PFC_FUNCTION(scif2),
3999 SH_PFC_FUNCTION(scif3),
4000 SH_PFC_FUNCTION(scif4),
4001 SH_PFC_FUNCTION(scif5),
4002 SH_PFC_FUNCTION(scif_clk),
4003 SH_PFC_FUNCTION(sdhi0),
4004 SH_PFC_FUNCTION(sdhi1),
4005 SH_PFC_FUNCTION(sdhi2),
4006 SH_PFC_FUNCTION(sdhi3),
4007 SH_PFC_FUNCTION(ssi),
4008 SH_PFC_FUNCTION(usb0),
4009 SH_PFC_FUNCTION(usb1),
4010 SH_PFC_FUNCTION(usb2),
4011 };
4012
4013 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4014 #define F_(x, y) FN_##y
4015 #define FM(x) FN_##x
4016 { PINMUX_CFG_REG("GPSR0", 0xe6060100, 32, 1) {
4017 0, 0,
4018 0, 0,
4019 0, 0,
4020 0, 0,
4021 0, 0,
4022 0, 0,
4023 0, 0,
4024 0, 0,
4025 0, 0,
4026 0, 0,
4027 0, 0,
4028 0, 0,
4029 0, 0,
4030 0, 0,
4031 0, 0,
4032 0, 0,
4033 GP_0_15_FN, GPSR0_15,
4034 GP_0_14_FN, GPSR0_14,
4035 GP_0_13_FN, GPSR0_13,
4036 GP_0_12_FN, GPSR0_12,
4037 GP_0_11_FN, GPSR0_11,
4038 GP_0_10_FN, GPSR0_10,
4039 GP_0_9_FN, GPSR0_9,
4040 GP_0_8_FN, GPSR0_8,
4041 GP_0_7_FN, GPSR0_7,
4042 GP_0_6_FN, GPSR0_6,
4043 GP_0_5_FN, GPSR0_5,
4044 GP_0_4_FN, GPSR0_4,
4045 GP_0_3_FN, GPSR0_3,
4046 GP_0_2_FN, GPSR0_2,
4047 GP_0_1_FN, GPSR0_1,
4048 GP_0_0_FN, GPSR0_0, }
4049 },
4050 { PINMUX_CFG_REG("GPSR1", 0xe6060104, 32, 1) {
4051 0, 0,
4052 0, 0,
4053 0, 0,
4054 0, 0,
4055 GP_1_27_FN, GPSR1_27,
4056 GP_1_26_FN, GPSR1_26,
4057 GP_1_25_FN, GPSR1_25,
4058 GP_1_24_FN, GPSR1_24,
4059 GP_1_23_FN, GPSR1_23,
4060 GP_1_22_FN, GPSR1_22,
4061 GP_1_21_FN, GPSR1_21,
4062 GP_1_20_FN, GPSR1_20,
4063 GP_1_19_FN, GPSR1_19,
4064 GP_1_18_FN, GPSR1_18,
4065 GP_1_17_FN, GPSR1_17,
4066 GP_1_16_FN, GPSR1_16,
4067 GP_1_15_FN, GPSR1_15,
4068 GP_1_14_FN, GPSR1_14,
4069 GP_1_13_FN, GPSR1_13,
4070 GP_1_12_FN, GPSR1_12,
4071 GP_1_11_FN, GPSR1_11,
4072 GP_1_10_FN, GPSR1_10,
4073 GP_1_9_FN, GPSR1_9,
4074 GP_1_8_FN, GPSR1_8,
4075 GP_1_7_FN, GPSR1_7,
4076 GP_1_6_FN, GPSR1_6,
4077 GP_1_5_FN, GPSR1_5,
4078 GP_1_4_FN, GPSR1_4,
4079 GP_1_3_FN, GPSR1_3,
4080 GP_1_2_FN, GPSR1_2,
4081 GP_1_1_FN, GPSR1_1,
4082 GP_1_0_FN, GPSR1_0, }
4083 },
4084 { PINMUX_CFG_REG("GPSR2", 0xe6060108, 32, 1) {
4085 0, 0,
4086 0, 0,
4087 0, 0,
4088 0, 0,
4089 0, 0,
4090 0, 0,
4091 0, 0,
4092 0, 0,
4093 0, 0,
4094 0, 0,
4095 0, 0,
4096 0, 0,
4097 0, 0,
4098 0, 0,
4099 0, 0,
4100 0, 0,
4101 0, 0,
4102 GP_2_14_FN, GPSR2_14,
4103 GP_2_13_FN, GPSR2_13,
4104 GP_2_12_FN, GPSR2_12,
4105 GP_2_11_FN, GPSR2_11,
4106 GP_2_10_FN, GPSR2_10,
4107 GP_2_9_FN, GPSR2_9,
4108 GP_2_8_FN, GPSR2_8,
4109 GP_2_7_FN, GPSR2_7,
4110 GP_2_6_FN, GPSR2_6,
4111 GP_2_5_FN, GPSR2_5,
4112 GP_2_4_FN, GPSR2_4,
4113 GP_2_3_FN, GPSR2_3,
4114 GP_2_2_FN, GPSR2_2,
4115 GP_2_1_FN, GPSR2_1,
4116 GP_2_0_FN, GPSR2_0, }
4117 },
4118 { PINMUX_CFG_REG("GPSR3", 0xe606010c, 32, 1) {
4119 0, 0,
4120 0, 0,
4121 0, 0,
4122 0, 0,
4123 0, 0,
4124 0, 0,
4125 0, 0,
4126 0, 0,
4127 0, 0,
4128 0, 0,
4129 0, 0,
4130 0, 0,
4131 0, 0,
4132 0, 0,
4133 0, 0,
4134 0, 0,
4135 GP_3_15_FN, GPSR3_15,
4136 GP_3_14_FN, GPSR3_14,
4137 GP_3_13_FN, GPSR3_13,
4138 GP_3_12_FN, GPSR3_12,
4139 GP_3_11_FN, GPSR3_11,
4140 GP_3_10_FN, GPSR3_10,
4141 GP_3_9_FN, GPSR3_9,
4142 GP_3_8_FN, GPSR3_8,
4143 GP_3_7_FN, GPSR3_7,
4144 GP_3_6_FN, GPSR3_6,
4145 GP_3_5_FN, GPSR3_5,
4146 GP_3_4_FN, GPSR3_4,
4147 GP_3_3_FN, GPSR3_3,
4148 GP_3_2_FN, GPSR3_2,
4149 GP_3_1_FN, GPSR3_1,
4150 GP_3_0_FN, GPSR3_0, }
4151 },
4152 { PINMUX_CFG_REG("GPSR4", 0xe6060110, 32, 1) {
4153 0, 0,
4154 0, 0,
4155 0, 0,
4156 0, 0,
4157 0, 0,
4158 0, 0,
4159 0, 0,
4160 0, 0,
4161 0, 0,
4162 0, 0,
4163 0, 0,
4164 0, 0,
4165 0, 0,
4166 0, 0,
4167 GP_4_17_FN, GPSR4_17,
4168 GP_4_16_FN, GPSR4_16,
4169 GP_4_15_FN, GPSR4_15,
4170 GP_4_14_FN, GPSR4_14,
4171 GP_4_13_FN, GPSR4_13,
4172 GP_4_12_FN, GPSR4_12,
4173 GP_4_11_FN, GPSR4_11,
4174 GP_4_10_FN, GPSR4_10,
4175 GP_4_9_FN, GPSR4_9,
4176 GP_4_8_FN, GPSR4_8,
4177 GP_4_7_FN, GPSR4_7,
4178 GP_4_6_FN, GPSR4_6,
4179 GP_4_5_FN, GPSR4_5,
4180 GP_4_4_FN, GPSR4_4,
4181 GP_4_3_FN, GPSR4_3,
4182 GP_4_2_FN, GPSR4_2,
4183 GP_4_1_FN, GPSR4_1,
4184 GP_4_0_FN, GPSR4_0, }
4185 },
4186 { PINMUX_CFG_REG("GPSR5", 0xe6060114, 32, 1) {
4187 0, 0,
4188 0, 0,
4189 0, 0,
4190 0, 0,
4191 0, 0,
4192 0, 0,
4193 GP_5_25_FN, GPSR5_25,
4194 GP_5_24_FN, GPSR5_24,
4195 GP_5_23_FN, GPSR5_23,
4196 GP_5_22_FN, GPSR5_22,
4197 GP_5_21_FN, GPSR5_21,
4198 GP_5_20_FN, GPSR5_20,
4199 GP_5_19_FN, GPSR5_19,
4200 GP_5_18_FN, GPSR5_18,
4201 GP_5_17_FN, GPSR5_17,
4202 GP_5_16_FN, GPSR5_16,
4203 GP_5_15_FN, GPSR5_15,
4204 GP_5_14_FN, GPSR5_14,
4205 GP_5_13_FN, GPSR5_13,
4206 GP_5_12_FN, GPSR5_12,
4207 GP_5_11_FN, GPSR5_11,
4208 GP_5_10_FN, GPSR5_10,
4209 GP_5_9_FN, GPSR5_9,
4210 GP_5_8_FN, GPSR5_8,
4211 GP_5_7_FN, GPSR5_7,
4212 GP_5_6_FN, GPSR5_6,
4213 GP_5_5_FN, GPSR5_5,
4214 GP_5_4_FN, GPSR5_4,
4215 GP_5_3_FN, GPSR5_3,
4216 GP_5_2_FN, GPSR5_2,
4217 GP_5_1_FN, GPSR5_1,
4218 GP_5_0_FN, GPSR5_0, }
4219 },
4220 { PINMUX_CFG_REG("GPSR6", 0xe6060118, 32, 1) {
4221 GP_6_31_FN, GPSR6_31,
4222 GP_6_30_FN, GPSR6_30,
4223 GP_6_29_FN, GPSR6_29,
4224 GP_6_28_FN, GPSR6_28,
4225 GP_6_27_FN, GPSR6_27,
4226 GP_6_26_FN, GPSR6_26,
4227 GP_6_25_FN, GPSR6_25,
4228 GP_6_24_FN, GPSR6_24,
4229 GP_6_23_FN, GPSR6_23,
4230 GP_6_22_FN, GPSR6_22,
4231 GP_6_21_FN, GPSR6_21,
4232 GP_6_20_FN, GPSR6_20,
4233 GP_6_19_FN, GPSR6_19,
4234 GP_6_18_FN, GPSR6_18,
4235 GP_6_17_FN, GPSR6_17,
4236 GP_6_16_FN, GPSR6_16,
4237 GP_6_15_FN, GPSR6_15,
4238 GP_6_14_FN, GPSR6_14,
4239 GP_6_13_FN, GPSR6_13,
4240 GP_6_12_FN, GPSR6_12,
4241 GP_6_11_FN, GPSR6_11,
4242 GP_6_10_FN, GPSR6_10,
4243 GP_6_9_FN, GPSR6_9,
4244 GP_6_8_FN, GPSR6_8,
4245 GP_6_7_FN, GPSR6_7,
4246 GP_6_6_FN, GPSR6_6,
4247 GP_6_5_FN, GPSR6_5,
4248 GP_6_4_FN, GPSR6_4,
4249 GP_6_3_FN, GPSR6_3,
4250 GP_6_2_FN, GPSR6_2,
4251 GP_6_1_FN, GPSR6_1,
4252 GP_6_0_FN, GPSR6_0, }
4253 },
4254 { PINMUX_CFG_REG("GPSR7", 0xe606011c, 32, 1) {
4255 0, 0,
4256 0, 0,
4257 0, 0,
4258 0, 0,
4259 0, 0,
4260 0, 0,
4261 0, 0,
4262 0, 0,
4263 0, 0,
4264 0, 0,
4265 0, 0,
4266 0, 0,
4267 0, 0,
4268 0, 0,
4269 0, 0,
4270 0, 0,
4271 0, 0,
4272 0, 0,
4273 0, 0,
4274 0, 0,
4275 0, 0,
4276 0, 0,
4277 0, 0,
4278 0, 0,
4279 0, 0,
4280 0, 0,
4281 0, 0,
4282 0, 0,
4283 GP_7_3_FN, GPSR7_3,
4284 GP_7_2_FN, GPSR7_2,
4285 GP_7_1_FN, GPSR7_1,
4286 GP_7_0_FN, GPSR7_0, }
4287 },
4288 #undef F_
4289 #undef FM
4290
4291 #define F_(x, y) x,
4292 #define FM(x) FN_##x,
4293 { PINMUX_CFG_REG("IPSR0", 0xe6060200, 32, 4) {
4294 IP0_31_28
4295 IP0_27_24
4296 IP0_23_20
4297 IP0_19_16
4298 IP0_15_12
4299 IP0_11_8
4300 IP0_7_4
4301 IP0_3_0 }
4302 },
4303 { PINMUX_CFG_REG("IPSR1", 0xe6060204, 32, 4) {
4304 IP1_31_28
4305 IP1_27_24
4306 IP1_23_20
4307 IP1_19_16
4308 IP1_15_12
4309 IP1_11_8
4310 IP1_7_4
4311 IP1_3_0 }
4312 },
4313 { PINMUX_CFG_REG("IPSR2", 0xe6060208, 32, 4) {
4314 IP2_31_28
4315 IP2_27_24
4316 IP2_23_20
4317 IP2_19_16
4318 IP2_15_12
4319 IP2_11_8
4320 IP2_7_4
4321 IP2_3_0 }
4322 },
4323 { PINMUX_CFG_REG("IPSR3", 0xe606020c, 32, 4) {
4324 IP3_31_28
4325 IP3_27_24
4326 IP3_23_20
4327 IP3_19_16
4328 IP3_15_12
4329 IP3_11_8
4330 IP3_7_4
4331 IP3_3_0 }
4332 },
4333 { PINMUX_CFG_REG("IPSR4", 0xe6060210, 32, 4) {
4334 IP4_31_28
4335 IP4_27_24
4336 IP4_23_20
4337 IP4_19_16
4338 IP4_15_12
4339 IP4_11_8
4340 IP4_7_4
4341 IP4_3_0 }
4342 },
4343 { PINMUX_CFG_REG("IPSR5", 0xe6060214, 32, 4) {
4344 IP5_31_28
4345 IP5_27_24
4346 IP5_23_20
4347 IP5_19_16
4348 IP5_15_12
4349 IP5_11_8
4350 IP5_7_4
4351 IP5_3_0 }
4352 },
4353 { PINMUX_CFG_REG("IPSR6", 0xe6060218, 32, 4) {
4354 IP6_31_28
4355 IP6_27_24
4356 IP6_23_20
4357 IP6_19_16
4358 IP6_15_12
4359 IP6_11_8
4360 IP6_7_4
4361 IP6_3_0 }
4362 },
4363 { PINMUX_CFG_REG("IPSR7", 0xe606021c, 32, 4) {
4364 IP7_31_28
4365 IP7_27_24
4366 IP7_23_20
4367 IP7_19_16
4368 IP7_15_12
4369 IP7_11_8
4370 IP7_7_4
4371 IP7_3_0 }
4372 },
4373 { PINMUX_CFG_REG("IPSR8", 0xe6060220, 32, 4) {
4374 IP8_31_28
4375 IP8_27_24
4376 IP8_23_20
4377 IP8_19_16
4378 IP8_15_12
4379 IP8_11_8
4380 IP8_7_4
4381 IP8_3_0 }
4382 },
4383 { PINMUX_CFG_REG("IPSR9", 0xe6060224, 32, 4) {
4384 IP9_31_28
4385 IP9_27_24
4386 IP9_23_20
4387 IP9_19_16
4388 IP9_15_12
4389 IP9_11_8
4390 IP9_7_4
4391 IP9_3_0 }
4392 },
4393 { PINMUX_CFG_REG("IPSR10", 0xe6060228, 32, 4) {
4394 IP10_31_28
4395 IP10_27_24
4396 IP10_23_20
4397 IP10_19_16
4398 IP10_15_12
4399 IP10_11_8
4400 IP10_7_4
4401 IP10_3_0 }
4402 },
4403 { PINMUX_CFG_REG("IPSR11", 0xe606022c, 32, 4) {
4404 IP11_31_28
4405 IP11_27_24
4406 IP11_23_20
4407 IP11_19_16
4408 IP11_15_12
4409 IP11_11_8
4410 IP11_7_4
4411 IP11_3_0 }
4412 },
4413 { PINMUX_CFG_REG("IPSR12", 0xe6060230, 32, 4) {
4414 IP12_31_28
4415 IP12_27_24
4416 IP12_23_20
4417 IP12_19_16
4418 IP12_15_12
4419 IP12_11_8
4420 IP12_7_4
4421 IP12_3_0 }
4422 },
4423 { PINMUX_CFG_REG("IPSR13", 0xe6060234, 32, 4) {
4424 IP13_31_28
4425 IP13_27_24
4426 IP13_23_20
4427 IP13_19_16
4428 IP13_15_12
4429 IP13_11_8
4430 IP13_7_4
4431 IP13_3_0 }
4432 },
4433 { PINMUX_CFG_REG("IPSR14", 0xe6060238, 32, 4) {
4434 IP14_31_28
4435 IP14_27_24
4436 IP14_23_20
4437 IP14_19_16
4438 IP14_15_12
4439 IP14_11_8
4440 IP14_7_4
4441 IP14_3_0 }
4442 },
4443 { PINMUX_CFG_REG("IPSR15", 0xe606023c, 32, 4) {
4444 IP15_31_28
4445 IP15_27_24
4446 IP15_23_20
4447 IP15_19_16
4448 IP15_15_12
4449 IP15_11_8
4450 IP15_7_4
4451 IP15_3_0 }
4452 },
4453 { PINMUX_CFG_REG("IPSR16", 0xe6060240, 32, 4) {
4454 IP16_31_28
4455 IP16_27_24
4456 IP16_23_20
4457 IP16_19_16
4458 IP16_15_12
4459 IP16_11_8
4460 IP16_7_4
4461 IP16_3_0 }
4462 },
4463 { PINMUX_CFG_REG("IPSR17", 0xe6060244, 32, 4) {
4464 /* IP17_31_28 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4465 /* IP17_27_24 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4466 /* IP17_23_20 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4467 /* IP17_19_16 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4468 /* IP17_15_12 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4469 /* IP17_11_8 */ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4470 IP17_7_4
4471 IP17_3_0 }
4472 },
4473 #undef F_
4474 #undef FM
4475
4476 #define F_(x, y) x,
4477 #define FM(x) FN_##x,
4478 { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xe6060500, 32,
4479 1, 2, 2, 3, 1, 1, 2, 1, 1, 1,
4480 2, 1, 1, 1, 1, 1, 1, 1, 2, 2, 1, 2, 1) {
4481 0, 0, /* RESERVED 31 */
4482 MOD_SEL0_30_29
4483 MOD_SEL0_28_27
4484 MOD_SEL0_26_25_24
4485 MOD_SEL0_23
4486 MOD_SEL0_22
4487 MOD_SEL0_21_20
4488 MOD_SEL0_19
4489 MOD_SEL0_18
4490 MOD_SEL0_17
4491 MOD_SEL0_16_15
4492 MOD_SEL0_14
4493 MOD_SEL0_13
4494 MOD_SEL0_12
4495 MOD_SEL0_11
4496 MOD_SEL0_10
4497 MOD_SEL0_9
4498 MOD_SEL0_8
4499 MOD_SEL0_7_6
4500 MOD_SEL0_5_4
4501 MOD_SEL0_3
4502 MOD_SEL0_2_1
4503 0, 0, /* RESERVED 0 */ }
4504 },
4505 { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xe6060504, 32,
4506 2, 3, 1, 2, 3, 1, 1, 2, 1,
4507 2, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
4508 MOD_SEL1_31_30
4509 MOD_SEL1_29_28_27
4510 MOD_SEL1_26
4511 MOD_SEL1_25_24
4512 MOD_SEL1_23_22_21
4513 MOD_SEL1_20
4514 MOD_SEL1_19
4515 MOD_SEL1_18_17
4516 MOD_SEL1_16
4517 MOD_SEL1_15_14
4518 MOD_SEL1_13
4519 MOD_SEL1_12
4520 MOD_SEL1_11
4521 MOD_SEL1_10
4522 MOD_SEL1_9
4523 0, 0, 0, 0, /* RESERVED 8, 7 */
4524 MOD_SEL1_6
4525 MOD_SEL1_5
4526 MOD_SEL1_4
4527 MOD_SEL1_3
4528 MOD_SEL1_2
4529 MOD_SEL1_1
4530 MOD_SEL1_0 }
4531 },
4532 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xe6060508, 32,
4533 1, 1, 1, 1, 4, 4, 4,
4534 4, 4, 4, 1, 2, 1) {
4535 MOD_SEL2_31
4536 MOD_SEL2_30
4537 MOD_SEL2_29
4538 /* RESERVED 28 */
4539 0, 0,
4540 /* RESERVED 27, 26, 25, 24 */
4541 0, 0, 0, 0, 0, 0, 0, 0,
4542 0, 0, 0, 0, 0, 0, 0, 0,
4543 /* RESERVED 23, 22, 21, 20 */
4544 0, 0, 0, 0, 0, 0, 0, 0,
4545 0, 0, 0, 0, 0, 0, 0, 0,
4546 /* RESERVED 19, 18, 17, 16 */
4547 0, 0, 0, 0, 0, 0, 0, 0,
4548 0, 0, 0, 0, 0, 0, 0, 0,
4549 /* RESERVED 15, 14, 13, 12 */
4550 0, 0, 0, 0, 0, 0, 0, 0,
4551 0, 0, 0, 0, 0, 0, 0, 0,
4552 /* RESERVED 11, 10, 9, 8 */
4553 0, 0, 0, 0, 0, 0, 0, 0,
4554 0, 0, 0, 0, 0, 0, 0, 0,
4555 /* RESERVED 7, 6, 5, 4 */
4556 0, 0, 0, 0, 0, 0, 0, 0,
4557 0, 0, 0, 0, 0, 0, 0, 0,
4558 /* RESERVED 3 */
4559 0, 0,
4560 /* RESERVED 2, 1 */
4561 0, 0, 0, 0,
4562 MOD_SEL2_0 }
4563 },
4564 { },
4565 };
4566
4567 static const struct pinmux_drive_reg pinmux_drive_regs[] = {
4568 { PINMUX_DRIVE_REG("DRVCTRL3", 0xe606030c) {
4569 { RCAR_GP_PIN(2, 9), 8, 3 }, /* AVB_MDC */
4570 { RCAR_GP_PIN(2, 10), 4, 3 }, /* AVB_MAGIC */
4571 { RCAR_GP_PIN(2, 11), 0, 3 }, /* AVB_PHY_INT */
4572 } },
4573 { PINMUX_DRIVE_REG("DRVCTRL4", 0xe6060310) {
4574 { RCAR_GP_PIN(2, 12), 28, 3 }, /* AVB_LINK */
4575 { RCAR_GP_PIN(2, 13), 24, 3 }, /* AVB_AVTP_MATCH */
4576 { RCAR_GP_PIN(2, 14), 20, 3 }, /* AVB_AVTP_CAPTURE */
4577 { RCAR_GP_PIN(2, 0), 16, 3 }, /* IRQ0 */
4578 { RCAR_GP_PIN(2, 1), 12, 3 }, /* IRQ1 */
4579 { RCAR_GP_PIN(2, 2), 8, 3 }, /* IRQ2 */
4580 { RCAR_GP_PIN(2, 3), 4, 3 }, /* IRQ3 */
4581 { RCAR_GP_PIN(2, 4), 0, 3 }, /* IRQ4 */
4582 } },
4583 { PINMUX_DRIVE_REG("DRVCTRL5", 0xe6060314) {
4584 { RCAR_GP_PIN(2, 5), 28, 3 }, /* IRQ5 */
4585 { RCAR_GP_PIN(2, 6), 24, 3 }, /* PWM0 */
4586 { RCAR_GP_PIN(2, 7), 20, 3 }, /* PWM1 */
4587 { RCAR_GP_PIN(2, 8), 16, 3 }, /* PWM2 */
4588 { RCAR_GP_PIN(1, 0), 12, 3 }, /* A0 */
4589 { RCAR_GP_PIN(1, 1), 8, 3 }, /* A1 */
4590 { RCAR_GP_PIN(1, 2), 4, 3 }, /* A2 */
4591 { RCAR_GP_PIN(1, 3), 0, 3 }, /* A3 */
4592 } },
4593 { PINMUX_DRIVE_REG("DRVCTRL6", 0xe6060318) {
4594 { RCAR_GP_PIN(1, 4), 28, 3 }, /* A4 */
4595 { RCAR_GP_PIN(1, 5), 24, 3 }, /* A5 */
4596 { RCAR_GP_PIN(1, 6), 20, 3 }, /* A6 */
4597 { RCAR_GP_PIN(1, 7), 16, 3 }, /* A7 */
4598 { RCAR_GP_PIN(1, 8), 12, 3 }, /* A8 */
4599 { RCAR_GP_PIN(1, 9), 8, 3 }, /* A9 */
4600 { RCAR_GP_PIN(1, 10), 4, 3 }, /* A10 */
4601 { RCAR_GP_PIN(1, 11), 0, 3 }, /* A11 */
4602 } },
4603 { PINMUX_DRIVE_REG("DRVCTRL7", 0xe606031c) {
4604 { RCAR_GP_PIN(1, 12), 28, 3 }, /* A12 */
4605 { RCAR_GP_PIN(1, 13), 24, 3 }, /* A13 */
4606 { RCAR_GP_PIN(1, 14), 20, 3 }, /* A14 */
4607 { RCAR_GP_PIN(1, 15), 16, 3 }, /* A15 */
4608 { RCAR_GP_PIN(1, 16), 12, 3 }, /* A16 */
4609 { RCAR_GP_PIN(1, 17), 8, 3 }, /* A17 */
4610 { RCAR_GP_PIN(1, 18), 4, 3 }, /* A18 */
4611 { RCAR_GP_PIN(1, 19), 0, 3 }, /* A19 */
4612 } },
4613 { PINMUX_DRIVE_REG("DRVCTRL8", 0xe6060320) {
4614 { RCAR_GP_PIN(1, 20), 24, 3 }, /* CS0 */
4615 { RCAR_GP_PIN(1, 21), 20, 3 }, /* CS1_A26 */
4616 { RCAR_GP_PIN(1, 22), 16, 3 }, /* BS */
4617 { RCAR_GP_PIN(1, 23), 12, 3 }, /* RD */
4618 { RCAR_GP_PIN(1, 24), 8, 3 }, /* RD_WR */
4619 { RCAR_GP_PIN(1, 25), 4, 3 }, /* WE0 */
4620 { RCAR_GP_PIN(1, 26), 0, 3 }, /* WE1 */
4621 } },
4622 { PINMUX_DRIVE_REG("DRVCTRL9", 0xe6060324) {
4623 { RCAR_GP_PIN(1, 27), 28, 3 }, /* EX_WAIT0 */
4624 { RCAR_GP_PIN(0, 0), 20, 3 }, /* D0 */
4625 { RCAR_GP_PIN(0, 1), 16, 3 }, /* D1 */
4626 { RCAR_GP_PIN(0, 2), 12, 3 }, /* D2 */
4627 { RCAR_GP_PIN(0, 3), 8, 3 }, /* D3 */
4628 { RCAR_GP_PIN(0, 4), 4, 3 }, /* D4 */
4629 { RCAR_GP_PIN(0, 5), 0, 3 }, /* D5 */
4630 } },
4631 { PINMUX_DRIVE_REG("DRVCTRL10", 0xe6060328) {
4632 { RCAR_GP_PIN(0, 6), 28, 3 }, /* D6 */
4633 { RCAR_GP_PIN(0, 7), 24, 3 }, /* D7 */
4634 { RCAR_GP_PIN(0, 8), 20, 3 }, /* D8 */
4635 { RCAR_GP_PIN(0, 9), 16, 3 }, /* D9 */
4636 { RCAR_GP_PIN(0, 10), 12, 3 }, /* D10 */
4637 { RCAR_GP_PIN(0, 11), 8, 3 }, /* D11 */
4638 { RCAR_GP_PIN(0, 12), 4, 3 }, /* D12 */
4639 { RCAR_GP_PIN(0, 13), 0, 3 }, /* D13 */
4640 } },
4641 { PINMUX_DRIVE_REG("DRVCTRL11", 0xe606032c) {
4642 { RCAR_GP_PIN(0, 14), 28, 3 }, /* D14 */
4643 { RCAR_GP_PIN(0, 15), 24, 3 }, /* D15 */
4644 { RCAR_GP_PIN(7, 0), 20, 3 }, /* AVS1 */
4645 { RCAR_GP_PIN(7, 1), 16, 3 }, /* AVS2 */
4646 { RCAR_GP_PIN(7, 2), 12, 3 }, /* HDMI0_CEC */
4647 { RCAR_GP_PIN(7, 3), 8, 3 }, /* HDMI1_CEC */
4648 } },
4649 { PINMUX_DRIVE_REG("DRVCTRL13", 0xe6060334) {
4650 { RCAR_GP_PIN(3, 0), 20, 3 }, /* SD0_CLK */
4651 { RCAR_GP_PIN(3, 1), 16, 3 }, /* SD0_CMD */
4652 { RCAR_GP_PIN(3, 2), 12, 3 }, /* SD0_DAT0 */
4653 { RCAR_GP_PIN(3, 3), 8, 3 }, /* SD0_DAT1 */
4654 { RCAR_GP_PIN(3, 4), 4, 3 }, /* SD0_DAT2 */
4655 { RCAR_GP_PIN(3, 5), 0, 3 }, /* SD0_DAT3 */
4656 } },
4657 { PINMUX_DRIVE_REG("DRVCTRL14", 0xe6060338) {
4658 { RCAR_GP_PIN(3, 6), 28, 3 }, /* SD1_CLK */
4659 { RCAR_GP_PIN(3, 7), 24, 3 }, /* SD1_CMD */
4660 { RCAR_GP_PIN(3, 8), 20, 3 }, /* SD1_DAT0 */
4661 { RCAR_GP_PIN(3, 9), 16, 3 }, /* SD1_DAT1 */
4662 { RCAR_GP_PIN(3, 10), 12, 3 }, /* SD1_DAT2 */
4663 { RCAR_GP_PIN(3, 11), 8, 3 }, /* SD1_DAT3 */
4664 { RCAR_GP_PIN(4, 0), 4, 3 }, /* SD2_CLK */
4665 { RCAR_GP_PIN(4, 1), 0, 3 }, /* SD2_CMD */
4666 } },
4667 { PINMUX_DRIVE_REG("DRVCTRL15", 0xe606033c) {
4668 { RCAR_GP_PIN(4, 2), 28, 3 }, /* SD2_DAT0 */
4669 { RCAR_GP_PIN(4, 3), 24, 3 }, /* SD2_DAT1 */
4670 { RCAR_GP_PIN(4, 4), 20, 3 }, /* SD2_DAT2 */
4671 { RCAR_GP_PIN(4, 5), 16, 3 }, /* SD2_DAT3 */
4672 { RCAR_GP_PIN(4, 6), 12, 3 }, /* SD2_DS */
4673 { RCAR_GP_PIN(4, 7), 8, 3 }, /* SD3_CLK */
4674 { RCAR_GP_PIN(4, 8), 4, 3 }, /* SD3_CMD */
4675 { RCAR_GP_PIN(4, 9), 0, 3 }, /* SD3_DAT0 */
4676 } },
4677 { PINMUX_DRIVE_REG("DRVCTRL16", 0xe6060340) {
4678 { RCAR_GP_PIN(4, 10), 28, 3 }, /* SD3_DAT1 */
4679 { RCAR_GP_PIN(4, 11), 24, 3 }, /* SD3_DAT2 */
4680 { RCAR_GP_PIN(4, 12), 20, 3 }, /* SD3_DAT3 */
4681 { RCAR_GP_PIN(4, 13), 16, 3 }, /* SD3_DAT4 */
4682 { RCAR_GP_PIN(4, 14), 12, 3 }, /* SD3_DAT5 */
4683 { RCAR_GP_PIN(4, 15), 8, 3 }, /* SD3_DAT6 */
4684 { RCAR_GP_PIN(4, 16), 4, 3 }, /* SD3_DAT7 */
4685 { RCAR_GP_PIN(4, 17), 0, 3 }, /* SD3_DS */
4686 } },
4687 { PINMUX_DRIVE_REG("DRVCTRL17", 0xe6060344) {
4688 { RCAR_GP_PIN(3, 12), 28, 3 }, /* SD0_CD */
4689 { RCAR_GP_PIN(3, 13), 24, 3 }, /* SD0_WP */
4690 { RCAR_GP_PIN(3, 14), 20, 3 }, /* SD1_CD */
4691 { RCAR_GP_PIN(3, 15), 16, 3 }, /* SD1_WP */
4692 { RCAR_GP_PIN(5, 0), 12, 3 }, /* SCK0 */
4693 { RCAR_GP_PIN(5, 1), 8, 3 }, /* RX0 */
4694 { RCAR_GP_PIN(5, 2), 4, 3 }, /* TX0 */
4695 { RCAR_GP_PIN(5, 3), 0, 3 }, /* CTS0 */
4696 } },
4697 { PINMUX_DRIVE_REG("DRVCTRL18", 0xe6060348) {
4698 { RCAR_GP_PIN(5, 4), 28, 3 }, /* RTS0_TANS */
4699 { RCAR_GP_PIN(5, 5), 24, 3 }, /* RX1 */
4700 { RCAR_GP_PIN(5, 6), 20, 3 }, /* TX1 */
4701 { RCAR_GP_PIN(5, 7), 16, 3 }, /* CTS1 */
4702 { RCAR_GP_PIN(5, 8), 12, 3 }, /* RTS1_TANS */
4703 { RCAR_GP_PIN(5, 9), 8, 3 }, /* SCK2 */
4704 { RCAR_GP_PIN(5, 10), 4, 3 }, /* TX2 */
4705 { RCAR_GP_PIN(5, 11), 0, 3 }, /* RX2 */
4706 } },
4707 { PINMUX_DRIVE_REG("DRVCTRL19", 0xe606034c) {
4708 { RCAR_GP_PIN(5, 12), 28, 3 }, /* HSCK0 */
4709 { RCAR_GP_PIN(5, 13), 24, 3 }, /* HRX0 */
4710 { RCAR_GP_PIN(5, 14), 20, 3 }, /* HTX0 */
4711 { RCAR_GP_PIN(5, 15), 16, 3 }, /* HCTS0 */
4712 { RCAR_GP_PIN(5, 16), 12, 3 }, /* HRTS0 */
4713 { RCAR_GP_PIN(5, 17), 8, 3 }, /* MSIOF0_SCK */
4714 { RCAR_GP_PIN(5, 18), 4, 3 }, /* MSIOF0_SYNC */
4715 { RCAR_GP_PIN(5, 19), 0, 3 }, /* MSIOF0_SS1 */
4716 } },
4717 { PINMUX_DRIVE_REG("DRVCTRL20", 0xe6060350) {
4718 { RCAR_GP_PIN(5, 20), 28, 3 }, /* MSIOF0_TXD */
4719 { RCAR_GP_PIN(5, 21), 24, 3 }, /* MSIOF0_SS2 */
4720 { RCAR_GP_PIN(5, 22), 20, 3 }, /* MSIOF0_RXD */
4721 { RCAR_GP_PIN(5, 23), 16, 3 }, /* MLB_CLK */
4722 { RCAR_GP_PIN(5, 24), 12, 3 }, /* MLB_SIG */
4723 { RCAR_GP_PIN(5, 25), 8, 3 }, /* MLB_DAT */
4724 { RCAR_GP_PIN(6, 0), 0, 3 }, /* SSI_SCK01239 */
4725 } },
4726 { PINMUX_DRIVE_REG("DRVCTRL21", 0xe6060354) {
4727 { RCAR_GP_PIN(6, 1), 28, 3 }, /* SSI_WS01239 */
4728 { RCAR_GP_PIN(6, 2), 24, 3 }, /* SSI_SDATA0 */
4729 { RCAR_GP_PIN(6, 3), 20, 3 }, /* SSI_SDATA1 */
4730 { RCAR_GP_PIN(6, 4), 16, 3 }, /* SSI_SDATA2 */
4731 { RCAR_GP_PIN(6, 5), 12, 3 }, /* SSI_SCK34 */
4732 { RCAR_GP_PIN(6, 6), 8, 3 }, /* SSI_WS34 */
4733 { RCAR_GP_PIN(6, 7), 4, 3 }, /* SSI_SDATA3 */
4734 { RCAR_GP_PIN(6, 8), 0, 3 }, /* SSI_SCK4 */
4735 } },
4736 { PINMUX_DRIVE_REG("DRVCTRL22", 0xe6060358) {
4737 { RCAR_GP_PIN(6, 9), 28, 3 }, /* SSI_WS4 */
4738 { RCAR_GP_PIN(6, 10), 24, 3 }, /* SSI_SDATA4 */
4739 { RCAR_GP_PIN(6, 11), 20, 3 }, /* SSI_SCK5 */
4740 { RCAR_GP_PIN(6, 12), 16, 3 }, /* SSI_WS5 */
4741 { RCAR_GP_PIN(6, 13), 12, 3 }, /* SSI_SDATA5 */
4742 { RCAR_GP_PIN(6, 14), 8, 3 }, /* SSI_SCK6 */
4743 { RCAR_GP_PIN(6, 15), 4, 3 }, /* SSI_WS6 */
4744 { RCAR_GP_PIN(6, 16), 0, 3 }, /* SSI_SDATA6 */
4745 } },
4746 { PINMUX_DRIVE_REG("DRVCTRL23", 0xe606035c) {
4747 { RCAR_GP_PIN(6, 17), 28, 3 }, /* SSI_SCK78 */
4748 { RCAR_GP_PIN(6, 18), 24, 3 }, /* SSI_WS78 */
4749 { RCAR_GP_PIN(6, 19), 20, 3 }, /* SSI_SDATA7 */
4750 { RCAR_GP_PIN(6, 20), 16, 3 }, /* SSI_SDATA8 */
4751 { RCAR_GP_PIN(6, 21), 12, 3 }, /* SSI_SDATA9 */
4752 { RCAR_GP_PIN(6, 22), 8, 3 }, /* AUDIO_CLKA */
4753 { RCAR_GP_PIN(6, 23), 4, 3 }, /* AUDIO_CLKB */
4754 { RCAR_GP_PIN(6, 24), 0, 3 }, /* USB0_PWEN */
4755 } },
4756 { PINMUX_DRIVE_REG("DRVCTRL24", 0xe6060360) {
4757 { RCAR_GP_PIN(6, 25), 28, 3 }, /* USB0_OVC */
4758 { RCAR_GP_PIN(6, 26), 24, 3 }, /* USB1_PWEN */
4759 { RCAR_GP_PIN(6, 27), 20, 3 }, /* USB1_OVC */
4760 { RCAR_GP_PIN(6, 28), 16, 3 }, /* USB30_PWEN */
4761 { RCAR_GP_PIN(6, 29), 12, 3 }, /* USB30_OVC */
4762 { RCAR_GP_PIN(6, 30), 8, 3 }, /* USB31_PWEN */
4763 { RCAR_GP_PIN(6, 31), 4, 3 }, /* USB31_OVC */
4764 } },
4765 { },
4766 };
4767
4768 const struct sh_pfc_soc_info r8a7795_pinmux_info = {
4769 .name = "r8a77950_pfc",
4770 .unlock_reg = 0xe6060000, /* PMMR */
4771
4772 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4773
4774 .pins = pinmux_pins,
4775 .nr_pins = ARRAY_SIZE(pinmux_pins),
4776 .groups = pinmux_groups,
4777 .nr_groups = ARRAY_SIZE(pinmux_groups),
4778 .functions = pinmux_functions,
4779 .nr_functions = ARRAY_SIZE(pinmux_functions),
4780
4781 .cfg_regs = pinmux_config_regs,
4782 .drive_regs = pinmux_drive_regs,
4783
4784 .pinmux_data = pinmux_data,
4785 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4786 };
Linux with added FPC-III support