drivers/edac/amd8111_edac.c

   1 /*
   2  * amd8111_edac.c, AMD8111 Hyper Transport chip EDAC kernel module
   3  *
   4  * Copyright (c) 2008 Wind River Systems, Inc.
   5  *
   6  * Authors:     Cao Qingtao <qingtao.cao@windriver.com>
   7  *              Benjamin Walsh <benjamin.walsh@windriver.com>
   8  *              Hu Yongqi <yongqi.hu@windriver.com>
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  17  * See the GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22  */
  23
  24 #include <linux/module.h>
  25 #include <linux/init.h>
  26 #include <linux/interrupt.h>
  27 #include <linux/bitops.h>
  28 #include <linux/edac.h>
  29 #include <linux/pci_ids.h>
  30 #include <asm/io.h>
  31
  32 #include "edac_core.h"
  33 #include "edac_module.h"
  34 #include "amd8111_edac.h"
  35
  36 #define AMD8111_EDAC_REVISION   " Ver: 1.0.0 " __DATE__
  37 #define AMD8111_EDAC_MOD_STR    "amd8111_edac"
  38
  39 #define PCI_DEVICE_ID_AMD_8111_PCI      0x7460
  40 static int edac_dev_idx;
  41
  42 enum amd8111_edac_devs {
  43         LPC_BRIDGE = 0,
  44 };
  45
  46 enum amd8111_edac_pcis {
  47         PCI_BRIDGE = 0,
  48 };
  49
  50 /* Wrapper functions for accessing PCI configuration space */
  51 static int edac_pci_read_dword(struct pci_dev *dev, int reg, u32 *val32)
  52 {
  53         int ret;
  54
  55         ret = pci_read_config_dword(dev, reg, val32);
  56         if (ret != 0)
  57                 printk(KERN_ERR AMD8111_EDAC_MOD_STR
  58                         " PCI Access Read Error at 0x%x\n", reg);
  59
  60         return ret;
  61 }
  62
  63 static void edac_pci_read_byte(struct pci_dev *dev, int reg, u8 *val8)
  64 {
  65         int ret;
  66
  67         ret = pci_read_config_byte(dev, reg, val8);
  68         if (ret != 0)
  69                 printk(KERN_ERR AMD8111_EDAC_MOD_STR
  70                         " PCI Access Read Error at 0x%x\n", reg);
  71 }
  72
  73 static void edac_pci_write_dword(struct pci_dev *dev, int reg, u32 val32)
  74 {
  75         int ret;
  76
  77         ret = pci_write_config_dword(dev, reg, val32);
  78         if (ret != 0)
  79                 printk(KERN_ERR AMD8111_EDAC_MOD_STR
  80                         " PCI Access Write Error at 0x%x\n", reg);
  81 }
  82
  83 static void edac_pci_write_byte(struct pci_dev *dev, int reg, u8 val8)
  84 {
  85         int ret;
  86
  87         ret = pci_write_config_byte(dev, reg, val8);
  88         if (ret != 0)
  89                 printk(KERN_ERR AMD8111_EDAC_MOD_STR
  90                         " PCI Access Write Error at 0x%x\n", reg);
  91 }
  92
  93 /*
  94  * device-specific methods for amd8111 PCI Bridge Controller
  95  *
  96  * Error Reporting and Handling for amd8111 chipset could be found
  97  * in its datasheet 3.1.2 section, P37
  98  */
  99 static void amd8111_pci_bridge_init(struct amd8111_pci_info *pci_info)
 100 {
 101         u32 val32;
 102         struct pci_dev *dev = pci_info->dev;
 103
 104         /* First clear error detection flags on the host interface */
 105
 106         /* Clear SSE/SMA/STA flags in the global status register*/
 107         edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
 108         if (val32 & PCI_STSCMD_CLEAR_MASK)
 109                 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
 110
 111         /* Clear CRC and Link Fail flags in HT Link Control reg */
 112         edac_pci_read_dword(dev, REG_HT_LINK, &val32);
 113         if (val32 & HT_LINK_CLEAR_MASK)
 114                 edac_pci_write_dword(dev, REG_HT_LINK, val32);
 115
 116         /* Second clear all fault on the secondary interface */
 117
 118         /* Clear error flags in the memory-base limit reg. */
 119         edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
 120         if (val32 & MEM_LIMIT_CLEAR_MASK)
 121                 edac_pci_write_dword(dev, REG_MEM_LIM, val32);
 122
 123         /* Clear Discard Timer Expired flag in Interrupt/Bridge Control reg */
 124         edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
 125         if (val32 & PCI_INTBRG_CTRL_CLEAR_MASK)
 126                 edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
 127
 128         /* Last enable error detections */
 129         if (edac_op_state == EDAC_OPSTATE_POLL) {
 130                 /* Enable System Error reporting in global status register */
 131                 edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
 132                 val32 |= PCI_STSCMD_SERREN;
 133                 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
 134
 135                 /* Enable CRC Sync flood packets to HyperTransport Link */
 136                 edac_pci_read_dword(dev, REG_HT_LINK, &val32);
 137                 val32 |= HT_LINK_CRCFEN;
 138                 edac_pci_write_dword(dev, REG_HT_LINK, val32);
 139
 140                 /* Enable SSE reporting etc in Interrupt control reg */
 141                 edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
 142                 val32 |= PCI_INTBRG_CTRL_POLL_MASK;
 143                 edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
 144         }
 145 }
 146
 147 static void amd8111_pci_bridge_exit(struct amd8111_pci_info *pci_info)
 148 {
 149         u32 val32;
 150         struct pci_dev *dev = pci_info->dev;
 151
 152         if (edac_op_state == EDAC_OPSTATE_POLL) {
 153                 /* Disable System Error reporting */
 154                 edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
 155                 val32 &= ~PCI_STSCMD_SERREN;
 156                 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
 157
 158                 /* Disable CRC flood packets */
 159                 edac_pci_read_dword(dev, REG_HT_LINK, &val32);
 160                 val32 &= ~HT_LINK_CRCFEN;
 161                 edac_pci_write_dword(dev, REG_HT_LINK, val32);
 162
 163                 /* Disable DTSERREN/MARSP/SERREN in Interrupt Control reg */
 164                 edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
 165                 val32 &= ~PCI_INTBRG_CTRL_POLL_MASK;
 166                 edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
 167         }
 168 }
 169
 170 static void amd8111_pci_bridge_check(struct edac_pci_ctl_info *edac_dev)
 171 {
 172         struct amd8111_pci_info *pci_info = edac_dev->pvt_info;
 173         struct pci_dev *dev = pci_info->dev;
 174         u32 val32;
 175
 176         /* Check out PCI Bridge Status and Command Register */
 177         edac_pci_read_dword(dev, REG_PCI_STSCMD, &val32);
 178         if (val32 & PCI_STSCMD_CLEAR_MASK) {
 179                 printk(KERN_INFO "Error(s) in PCI bridge status and command"
 180                         "register on device %s\n", pci_info->ctl_name);
 181                 printk(KERN_INFO "SSE: %d, RMA: %d, RTA: %d\n",
 182                         (val32 & PCI_STSCMD_SSE) != 0,
 183                         (val32 & PCI_STSCMD_RMA) != 0,
 184                         (val32 & PCI_STSCMD_RTA) != 0);
 185
 186                 val32 |= PCI_STSCMD_CLEAR_MASK;
 187                 edac_pci_write_dword(dev, REG_PCI_STSCMD, val32);
 188
 189                 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
 190         }
 191
 192         /* Check out HyperTransport Link Control Register */
 193         edac_pci_read_dword(dev, REG_HT_LINK, &val32);
 194         if (val32 & HT_LINK_LKFAIL) {
 195                 printk(KERN_INFO "Error(s) in hypertransport link control"
 196                         "register on device %s\n", pci_info->ctl_name);
 197                 printk(KERN_INFO "LKFAIL: %d\n",
 198                         (val32 & HT_LINK_LKFAIL) != 0);
 199
 200                 val32 |= HT_LINK_LKFAIL;
 201                 edac_pci_write_dword(dev, REG_HT_LINK, val32);
 202
 203                 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
 204         }
 205
 206         /* Check out PCI Interrupt and Bridge Control Register */
 207         edac_pci_read_dword(dev, REG_PCI_INTBRG_CTRL, &val32);
 208         if (val32 & PCI_INTBRG_CTRL_DTSTAT) {
 209                 printk(KERN_INFO "Error(s) in PCI interrupt and bridge control"
 210                         "register on device %s\n", pci_info->ctl_name);
 211                 printk(KERN_INFO "DTSTAT: %d\n",
 212                         (val32 & PCI_INTBRG_CTRL_DTSTAT) != 0);
 213
 214                 val32 |= PCI_INTBRG_CTRL_DTSTAT;
 215                 edac_pci_write_dword(dev, REG_PCI_INTBRG_CTRL, val32);
 216
 217                 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
 218         }
 219
 220         /* Check out PCI Bridge Memory Base-Limit Register */
 221         edac_pci_read_dword(dev, REG_MEM_LIM, &val32);
 222         if (val32 & MEM_LIMIT_CLEAR_MASK) {
 223                 printk(KERN_INFO
 224                         "Error(s) in mem limit register on %s device\n",
 225                         pci_info->ctl_name);
 226                 printk(KERN_INFO "DPE: %d, RSE: %d, RMA: %d\n"
 227                         "RTA: %d, STA: %d, MDPE: %d\n",
 228                         (val32 & MEM_LIMIT_DPE)  != 0,
 229                         (val32 & MEM_LIMIT_RSE)  != 0,
 230                         (val32 & MEM_LIMIT_RMA)  != 0,
 231                         (val32 & MEM_LIMIT_RTA)  != 0,
 232                         (val32 & MEM_LIMIT_STA)  != 0,
 233                         (val32 & MEM_LIMIT_MDPE) != 0);
 234
 235                 val32 |= MEM_LIMIT_CLEAR_MASK;
 236                 edac_pci_write_dword(dev, REG_MEM_LIM, val32);
 237
 238                 edac_pci_handle_npe(edac_dev, edac_dev->ctl_name);
 239         }
 240 }
 241
 242 static struct resource *legacy_io_res;
 243 static int at_compat_reg_broken;
 244 #define LEGACY_NR_PORTS 1
 245
 246 /* device-specific methods for amd8111 LPC Bridge device */
 247 static void amd8111_lpc_bridge_init(struct amd8111_dev_info *dev_info)
 248 {
 249         u8 val8;
 250         struct pci_dev *dev = dev_info->dev;
 251
 252         /* First clear REG_AT_COMPAT[SERR, IOCHK] if necessary */
 253         legacy_io_res = request_region(REG_AT_COMPAT, LEGACY_NR_PORTS,
 254                                         AMD8111_EDAC_MOD_STR);
 255         if (!legacy_io_res)
 256                 printk(KERN_INFO "%s: failed to request legacy I/O region "
 257                         "start %d, len %d\n", __func__,
 258                         REG_AT_COMPAT, LEGACY_NR_PORTS);
 259         else {
 260                 val8 = __do_inb(REG_AT_COMPAT);
 261                 if (val8 == 0xff) { /* buggy port */
 262                         printk(KERN_INFO "%s: port %d is buggy, not supported"
 263                                 " by hardware?\n", __func__, REG_AT_COMPAT);
 264                         at_compat_reg_broken = 1;
 265                         release_region(REG_AT_COMPAT, LEGACY_NR_PORTS);
 266                         legacy_io_res = NULL;
 267                 } else {
 268                         u8 out8 = 0;
 269                         if (val8 & AT_COMPAT_SERR)
 270                                 out8 = AT_COMPAT_CLRSERR;
 271                         if (val8 & AT_COMPAT_IOCHK)
 272                                 out8 |= AT_COMPAT_CLRIOCHK;
 273                         if (out8 > 0)
 274                                 __do_outb(out8, REG_AT_COMPAT);
 275                 }
 276         }
 277
 278         /* Second clear error flags on LPC bridge */
 279         edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
 280         if (val8 & IO_CTRL_1_CLEAR_MASK)
 281                 edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);
 282 }
 283
 284 static void amd8111_lpc_bridge_exit(struct amd8111_dev_info *dev_info)
 285 {
 286         if (legacy_io_res)
 287                 release_region(REG_AT_COMPAT, LEGACY_NR_PORTS);
 288 }
 289
 290 static void amd8111_lpc_bridge_check(struct edac_device_ctl_info *edac_dev)
 291 {
 292         struct amd8111_dev_info *dev_info = edac_dev->pvt_info;
 293         struct pci_dev *dev = dev_info->dev;
 294         u8 val8;
 295
 296         edac_pci_read_byte(dev, REG_IO_CTRL_1, &val8);
 297         if (val8 & IO_CTRL_1_CLEAR_MASK) {
 298                 printk(KERN_INFO
 299                         "Error(s) in IO control register on %s device\n",
 300                         dev_info->ctl_name);
 301                 printk(KERN_INFO "LPC ERR: %d, PW2LPC: %d\n",
 302                         (val8 & IO_CTRL_1_LPC_ERR) != 0,
 303                         (val8 & IO_CTRL_1_PW2LPC) != 0);
 304
 305                 val8 |= IO_CTRL_1_CLEAR_MASK;
 306                 edac_pci_write_byte(dev, REG_IO_CTRL_1, val8);
 307
 308                 edac_device_handle_ue(edac_dev, 0, 0, edac_dev->ctl_name);
 309         }
 310
 311         if (at_compat_reg_broken == 0) {
 312                 u8 out8 = 0;
 313                 val8 = __do_inb(REG_AT_COMPAT);
 314                 if (val8 & AT_COMPAT_SERR)
 315                         out8 = AT_COMPAT_CLRSERR;
 316                 if (val8 & AT_COMPAT_IOCHK)
 317                         out8 |= AT_COMPAT_CLRIOCHK;
 318                 if (out8 > 0) {
 319                         __do_outb(out8, REG_AT_COMPAT);
 320                         edac_device_handle_ue(edac_dev, 0, 0,
 321                                                 edac_dev->ctl_name);
 322                 }
 323         }
 324 }
 325
 326 /* General devices represented by edac_device_ctl_info */
 327 static struct amd8111_dev_info amd8111_devices[] = {
 328         [LPC_BRIDGE] = {
 329                 .err_dev = PCI_DEVICE_ID_AMD_8111_LPC,
 330                 .ctl_name = "lpc",
 331                 .init = amd8111_lpc_bridge_init,
 332                 .exit = amd8111_lpc_bridge_exit,
 333                 .check = amd8111_lpc_bridge_check,
 334         },
 335         {0},
 336 };
 337
 338 /* PCI controllers represented by edac_pci_ctl_info */
 339 static struct amd8111_pci_info amd8111_pcis[] = {
 340         [PCI_BRIDGE] = {
 341                 .err_dev = PCI_DEVICE_ID_AMD_8111_PCI,
 342                 .ctl_name = "AMD8111_PCI_Controller",
 343                 .init = amd8111_pci_bridge_init,
 344                 .exit = amd8111_pci_bridge_exit,
 345                 .check = amd8111_pci_bridge_check,
 346         },
 347         {0},
 348 };
 349
 350 static int amd8111_dev_probe(struct pci_dev *dev,
 351                                 const struct pci_device_id *id)
 352 {
 353         struct amd8111_dev_info *dev_info = &amd8111_devices[id->driver_data];
 354
 355         dev_info->dev = pci_get_device(PCI_VENDOR_ID_AMD,
 356                                         dev_info->err_dev, NULL);
 357
 358         if (!dev_info->dev) {
 359                 printk(KERN_ERR "EDAC device not found:"
 360                         "vendor %x, device %x, name %s\n",
 361                         PCI_VENDOR_ID_AMD, dev_info->err_dev,
 362                         dev_info->ctl_name);
 363                 return -ENODEV;
 364         }
 365
 366         if (pci_enable_device(dev_info->dev)) {
 367                 pci_dev_put(dev_info->dev);
 368                 printk(KERN_ERR "failed to enable:"
 369                         "vendor %x, device %x, name %s\n",
 370                         PCI_VENDOR_ID_AMD, dev_info->err_dev,
 371                         dev_info->ctl_name);
 372                 return -ENODEV;
 373         }
 374
 375         /*
 376          * we do not allocate extra private structure for
 377          * edac_device_ctl_info, but make use of existing
 378          * one instead.
 379         */
 380         dev_info->edac_idx = edac_dev_idx++;
 381         dev_info->edac_dev =
 382                 edac_device_alloc_ctl_info(0, dev_info->ctl_name, 1,
 383                                            NULL, 0, 0,
 384                                            NULL, 0, dev_info->edac_idx);
 385         if (!dev_info->edac_dev)
 386                 return -ENOMEM;
 387
 388         dev_info->edac_dev->pvt_info = dev_info;
 389         dev_info->edac_dev->dev = &dev_info->dev->dev;
 390         dev_info->edac_dev->mod_name = AMD8111_EDAC_MOD_STR;
 391         dev_info->edac_dev->ctl_name = dev_info->ctl_name;
 392         dev_info->edac_dev->dev_name = dev_info->dev->dev.bus_id;
 393
 394         if (edac_op_state == EDAC_OPSTATE_POLL)
 395                 dev_info->edac_dev->edac_check = dev_info->check;
 396
 397         if (dev_info->init)
 398                 dev_info->init(dev_info);
 399
 400         if (edac_device_add_device(dev_info->edac_dev) > 0) {
 401                 printk(KERN_ERR "failed to add edac_dev for %s\n",
 402                         dev_info->ctl_name);
 403                 edac_device_free_ctl_info(dev_info->edac_dev);
 404                 return -ENODEV;
 405         }
 406
 407         printk(KERN_INFO "added one edac_dev on AMD8111 "
 408                 "vendor %x, device %x, name %s\n",
 409                 PCI_VENDOR_ID_AMD, dev_info->err_dev,
 410                 dev_info->ctl_name);
 411
 412         return 0;
 413 }
 414
 415 static void amd8111_dev_remove(struct pci_dev *dev)
 416 {
 417         struct amd8111_dev_info *dev_info;
 418
 419         for (dev_info = amd8111_devices; dev_info->err_dev; dev_info++)
 420                 if (dev_info->dev->device == dev->device)
 421                         break;
 422
 423         if (!dev_info->err_dev) /* should never happen */
 424                 return;
 425
 426         if (dev_info->edac_dev) {
 427                 edac_device_del_device(dev_info->edac_dev->dev);
 428                 edac_device_free_ctl_info(dev_info->edac_dev);
 429         }
 430
 431         if (dev_info->exit)
 432                 dev_info->exit(dev_info);
 433
 434         pci_dev_put(dev_info->dev);
 435 }
 436
 437 static int amd8111_pci_probe(struct pci_dev *dev,
 438                                 const struct pci_device_id *id)
 439 {
 440         struct amd8111_pci_info *pci_info = &amd8111_pcis[id->driver_data];
 441
 442         pci_info->dev = pci_get_device(PCI_VENDOR_ID_AMD,
 443                                         pci_info->err_dev, NULL);
 444
 445         if (!pci_info->dev) {
 446                 printk(KERN_ERR "EDAC device not found:"
 447                         "vendor %x, device %x, name %s\n",
 448                         PCI_VENDOR_ID_AMD, pci_info->err_dev,
 449                         pci_info->ctl_name);
 450                 return -ENODEV;
 451         }
 452
 453         if (pci_enable_device(pci_info->dev)) {
 454                 pci_dev_put(pci_info->dev);
 455                 printk(KERN_ERR "failed to enable:"
 456                         "vendor %x, device %x, name %s\n",
 457                         PCI_VENDOR_ID_AMD, pci_info->err_dev,
 458                         pci_info->ctl_name);
 459                 return -ENODEV;
 460         }
 461
 462         /*
 463          * we do not allocate extra private structure for
 464          * edac_pci_ctl_info, but make use of existing
 465          * one instead.
 466         */
 467         pci_info->edac_idx = edac_pci_alloc_index();
 468         pci_info->edac_dev = edac_pci_alloc_ctl_info(0, pci_info->ctl_name);
 469         if (!pci_info->edac_dev)
 470                 return -ENOMEM;
 471
 472         pci_info->edac_dev->pvt_info = pci_info;
 473         pci_info->edac_dev->dev = &pci_info->dev->dev;
 474         pci_info->edac_dev->mod_name = AMD8111_EDAC_MOD_STR;
 475         pci_info->edac_dev->ctl_name = pci_info->ctl_name;
 476         pci_info->edac_dev->dev_name = pci_info->dev->dev.bus_id;
 477
 478         if (edac_op_state == EDAC_OPSTATE_POLL)
 479                 pci_info->edac_dev->edac_check = pci_info->check;
 480
 481         if (pci_info->init)
 482                 pci_info->init(pci_info);
 483
 484         if (edac_pci_add_device(pci_info->edac_dev, pci_info->edac_idx) > 0) {
 485                 printk(KERN_ERR "failed to add edac_pci for %s\n",
 486                         pci_info->ctl_name);
 487                 edac_pci_free_ctl_info(pci_info->edac_dev);
 488                 return -ENODEV;
 489         }
 490
 491         printk(KERN_INFO "added one edac_pci on AMD8111 "
 492                 "vendor %x, device %x, name %s\n",
 493                 PCI_VENDOR_ID_AMD, pci_info->err_dev,
 494                 pci_info->ctl_name);
 495
 496         return 0;
 497 }
 498
 499 static void amd8111_pci_remove(struct pci_dev *dev)
 500 {
 501         struct amd8111_pci_info *pci_info;
 502
 503         for (pci_info = amd8111_pcis; pci_info->err_dev; pci_info++)
 504                 if (pci_info->dev->device == dev->device)
 505                         break;
 506
 507         if (!pci_info->err_dev) /* should never happen */
 508                 return;
 509
 510         if (pci_info->edac_dev) {
 511                 edac_pci_del_device(pci_info->edac_dev->dev);
 512                 edac_pci_free_ctl_info(pci_info->edac_dev);
 513         }
 514
 515         if (pci_info->exit)
 516                 pci_info->exit(pci_info);
 517
 518         pci_dev_put(pci_info->dev);
 519 }
 520
 521 /* PCI Device ID talbe for general EDAC device */
 522 static const struct pci_device_id amd8111_edac_dev_tbl[] = {
 523         {
 524         PCI_VEND_DEV(AMD, 8111_LPC),
 525         .subvendor = PCI_ANY_ID,
 526         .subdevice = PCI_ANY_ID,
 527         .class = 0,
 528         .class_mask = 0,
 529         .driver_data = LPC_BRIDGE,
 530         },
 531         {
 532         0,
 533         }                       /* table is NULL-terminated */
 534 };
 535 MODULE_DEVICE_TABLE(pci, amd8111_edac_dev_tbl);
 536
 537 static struct pci_driver amd8111_edac_dev_driver = {
 538         .name = "AMD8111_EDAC_DEV",
 539         .probe = amd8111_dev_probe,
 540         .remove = amd8111_dev_remove,
 541         .id_table = amd8111_edac_dev_tbl,
 542 };
 543
 544 /* PCI Device ID table for EDAC PCI controller */
 545 static const struct pci_device_id amd8111_edac_pci_tbl[] = {
 546         {
 547         PCI_VEND_DEV(AMD, 8111_PCI),
 548         .subvendor = PCI_ANY_ID,
 549         .subdevice = PCI_ANY_ID,
 550         .class = 0,
 551         .class_mask = 0,
 552         .driver_data = PCI_BRIDGE,
 553         },
 554         {
 555         0,
 556         }                       /* table is NULL-terminated */
 557 };
 558 MODULE_DEVICE_TABLE(pci, amd8111_edac_pci_tbl);
 559
 560 static struct pci_driver amd8111_edac_pci_driver = {
 561         .name = "AMD8111_EDAC_PCI",
 562         .probe = amd8111_pci_probe,
 563         .remove = amd8111_pci_remove,
 564         .id_table = amd8111_edac_pci_tbl,
 565 };
 566
 567 static int __init amd8111_edac_init(void)
 568 {
 569         int val;
 570
 571         printk(KERN_INFO "AMD8111 EDAC driver " AMD8111_EDAC_REVISION "\n");
 572         printk(KERN_INFO "\t(c) 2008 Wind River Systems, Inc.\n");
 573
 574         /* Only POLL mode supported so far */
 575         edac_op_state = EDAC_OPSTATE_POLL;
 576
 577         val = pci_register_driver(&amd8111_edac_dev_driver);
 578         val |= pci_register_driver(&amd8111_edac_pci_driver);
 579
 580         return val;
 581 }
 582
 583 static void __exit amd8111_edac_exit(void)
 584 {
 585         pci_unregister_driver(&amd8111_edac_pci_driver);
 586         pci_unregister_driver(&amd8111_edac_dev_driver);
 587 }
 588
 589
 590 module_init(amd8111_edac_init);
 591 module_exit(amd8111_edac_exit);
 592
 593 MODULE_LICENSE("GPL");
 594 MODULE_AUTHOR("Cao Qingtao <qingtao.cao@windriver.com>\n");
 595 MODULE_DESCRIPTION("AMD8111 HyperTransport I/O Hub EDAC kernel module");