drivers/misc/mei/hw-txe-regs.h

   1 /******************************************************************************
   2  * Intel Management Engine Interface (Intel MEI) Linux driver
   3  * Intel MEI Interface Header
   4  *
   5  * This file is provided under a dual BSD/GPLv2 license.  When using or
   6  * redistributing this file, you may do so under either license.
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  10  * Copyright(c) 2013 - 2014 Intel Corporation. All rights reserved.
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  61 #ifndef _MEI_HW_TXE_REGS_H_
  62 #define _MEI_HW_TXE_REGS_H_
  63
  64 #include "hw.h"
  65
  66 #define SEC_ALIVENESS_TIMER_TIMEOUT        (5 * MSEC_PER_SEC)
  67 #define SEC_ALIVENESS_WAIT_TIMEOUT         (1 * MSEC_PER_SEC)
  68 #define SEC_RESET_WAIT_TIMEOUT             (1 * MSEC_PER_SEC)
  69 #define SEC_READY_WAIT_TIMEOUT             (5 * MSEC_PER_SEC)
  70 #define START_MESSAGE_RESPONSE_WAIT_TIMEOUT (5 * MSEC_PER_SEC)
  71 #define RESET_CANCEL_WAIT_TIMEOUT          (1 * MSEC_PER_SEC)
  72
  73 enum {
  74         SEC_BAR,
  75         BRIDGE_BAR,
  76
  77         NUM_OF_MEM_BARS
  78 };
  79
  80 /* SeC FW Status Register
  81  *
  82  * FW uses this register in order to report its status to host.
  83  * This register resides in PCI-E config space.
  84  */
  85 #define PCI_CFG_TXE_FW_STS0   0x40
  86 #  define PCI_CFG_TXE_FW_STS0_WRK_ST_MSK    0x0000000F
  87 #  define PCI_CFG_TXE_FW_STS0_OP_ST_MSK     0x000001C0
  88 #  define PCI_CFG_TXE_FW_STS0_FW_INIT_CMPLT 0x00000200
  89 #  define PCI_CFG_TXE_FW_STS0_ERR_CODE_MSK  0x0000F000
  90 #  define PCI_CFG_TXE_FW_STS0_OP_MODE_MSK   0x000F0000
  91 #  define PCI_CFG_TXE_FW_STS0_RST_CNT_MSK   0x00F00000
  92 #define PCI_CFG_TXE_FW_STS1   0x48
  93
  94 #define IPC_BASE_ADDR   0x80400 /* SeC IPC Base Address */
  95
  96 /* IPC Input Doorbell Register */
  97 #define SEC_IPC_INPUT_DOORBELL_REG       (0x0000 + IPC_BASE_ADDR)
  98
  99 /* IPC Input Status Register
 100  * This register indicates whether or not processing of
 101  * the most recent command has been completed by the SEC
 102  * New commands and payloads should not be written by the Host
 103  * until this indicates that the previous command has been processed.
 104  */
 105 #define SEC_IPC_INPUT_STATUS_REG         (0x0008 + IPC_BASE_ADDR)
 106 #  define SEC_IPC_INPUT_STATUS_RDY    BIT(0)
 107
 108 /* IPC Host Interrupt Status Register */
 109 #define SEC_IPC_HOST_INT_STATUS_REG      (0x0010 + IPC_BASE_ADDR)
 110 #define   SEC_IPC_HOST_INT_STATUS_OUT_DB             BIT(0)
 111 #define   SEC_IPC_HOST_INT_STATUS_IN_RDY             BIT(1)
 112 #define   SEC_IPC_HOST_INT_STATUS_HDCP_M0_RCVD       BIT(5)
 113 #define   SEC_IPC_HOST_INT_STATUS_ILL_MEM_ACCESS     BIT(17)
 114 #define   SEC_IPC_HOST_INT_STATUS_AES_HKEY_ERR       BIT(18)
 115 #define   SEC_IPC_HOST_INT_STATUS_DES_HKEY_ERR       BIT(19)
 116 #define   SEC_IPC_HOST_INT_STATUS_TMRMTB_OVERFLOW    BIT(21)
 117
 118 /* Convenient mask for pending interrupts */
 119 #define   SEC_IPC_HOST_INT_STATUS_PENDING \
 120                 (SEC_IPC_HOST_INT_STATUS_OUT_DB| \
 121                 SEC_IPC_HOST_INT_STATUS_IN_RDY)
 122
 123 /* IPC Host Interrupt Mask Register */
 124 #define SEC_IPC_HOST_INT_MASK_REG        (0x0014 + IPC_BASE_ADDR)
 125
 126 #  define SEC_IPC_HOST_INT_MASK_OUT_DB  BIT(0) /* Output Doorbell Int Mask */
 127 #  define SEC_IPC_HOST_INT_MASK_IN_RDY  BIT(1) /* Input Ready Int Mask */
 128
 129 /* IPC Input Payload RAM */
 130 #define SEC_IPC_INPUT_PAYLOAD_REG        (0x0100 + IPC_BASE_ADDR)
 131 /* IPC Shared Payload RAM */
 132 #define IPC_SHARED_PAYLOAD_REG           (0x0200 + IPC_BASE_ADDR)
 133
 134 /* SeC Address Translation Table Entry 2 - Ctrl
 135  *
 136  * This register resides also in SeC's PCI-E Memory space.
 137  */
 138 #define SATT2_CTRL_REG                   0x1040
 139 #  define SATT2_CTRL_VALID_MSK            BIT(0)
 140 #  define SATT2_CTRL_BR_BASE_ADDR_REG_SHIFT 8
 141 #  define SATT2_CTRL_BRIDGE_HOST_EN_MSK   BIT(12)
 142
 143 /* SATT Table Entry 2 SAP Base Address Register */
 144 #define SATT2_SAP_BA_REG                 0x1044
 145 /* SATT Table Entry 2 SAP Size Register. */
 146 #define SATT2_SAP_SIZE_REG               0x1048
 147  /* SATT Table Entry 2 SAP Bridge Address - LSB Register */
 148 #define SATT2_BRG_BA_LSB_REG             0x104C
 149
 150 /* Host High-level Interrupt Status Register */
 151 #define HHISR_REG                        0x2020
 152 /* Host High-level Interrupt Enable Register
 153  *
 154  * Resides in PCI memory space. This is the top hierarchy for
 155  * interrupts from SeC to host, aggregating both interrupts that
 156  * arrive through HICR registers as well as interrupts
 157  * that arrive via IPC.
 158  */
 159 #define HHIER_REG                        0x2024
 160 #define   IPC_HHIER_SEC BIT(0)
 161 #define   IPC_HHIER_BRIDGE      BIT(1)
 162 #define   IPC_HHIER_MSK (IPC_HHIER_SEC | IPC_HHIER_BRIDGE)
 163
 164 /* Host High-level Interrupt Mask Register.
 165  *
 166  * Resides in PCI memory space.
 167  * This is the top hierarchy for masking interrupts from SeC to host.
 168  */
 169 #define HHIMR_REG                        0x2028
 170 #define   IPC_HHIMR_SEC       BIT(0)
 171 #define   IPC_HHIMR_BRIDGE    BIT(1)
 172
 173 /* Host High-level IRQ Status Register */
 174 #define HHIRQSR_REG                      0x202C
 175
 176 /* Host Interrupt Cause Register 0 - SeC IPC Readiness
 177  *
 178  * This register is both an ICR to Host from PCI Memory Space
 179  * and it is also exposed in the SeC memory space.
 180  * This register is used by SeC's IPC driver in order
 181  * to synchronize with host about IPC interface state.
 182  */
 183 #define HICR_SEC_IPC_READINESS_REG       0x2040
 184 #define   HICR_SEC_IPC_READINESS_HOST_RDY  BIT(0)
 185 #define   HICR_SEC_IPC_READINESS_SEC_RDY   BIT(1)
 186 #define   HICR_SEC_IPC_READINESS_SYS_RDY     \
 187           (HICR_SEC_IPC_READINESS_HOST_RDY | \
 188            HICR_SEC_IPC_READINESS_SEC_RDY)
 189 #define   HICR_SEC_IPC_READINESS_RDY_CLR   BIT(2)
 190
 191 /* Host Interrupt Cause Register 1 - Aliveness Response */
 192 /* This register is both an ICR to Host from PCI Memory Space
 193  * and it is also exposed in the SeC memory space.
 194  * The register may be used by SeC to ACK a host request for aliveness.
 195  */
 196 #define HICR_HOST_ALIVENESS_RESP_REG     0x2044
 197 #define   HICR_HOST_ALIVENESS_RESP_ACK    BIT(0)
 198
 199 /* Host Interrupt Cause Register 2 - SeC IPC Output Doorbell */
 200 #define HICR_SEC_IPC_OUTPUT_DOORBELL_REG 0x2048
 201
 202 /* Host Interrupt Status Register.
 203  *
 204  * Resides in PCI memory space.
 205  * This is the main register involved in generating interrupts
 206  * from SeC to host via HICRs.
 207  * The interrupt generation rules are as follows:
 208  * An interrupt will be generated whenever for any i,
 209  * there is a transition from a state where at least one of
 210  * the following conditions did not hold, to a state where
 211  * ALL the following conditions hold:
 212  * A) HISR.INT[i]_STS == 1.
 213  * B) HIER.INT[i]_EN == 1.
 214  */
 215 #define HISR_REG                         0x2060
 216 #define   HISR_INT_0_STS      BIT(0)
 217 #define   HISR_INT_1_STS      BIT(1)
 218 #define   HISR_INT_2_STS      BIT(2)
 219 #define   HISR_INT_3_STS      BIT(3)
 220 #define   HISR_INT_4_STS      BIT(4)
 221 #define   HISR_INT_5_STS      BIT(5)
 222 #define   HISR_INT_6_STS      BIT(6)
 223 #define   HISR_INT_7_STS      BIT(7)
 224 #define   HISR_INT_STS_MSK \
 225         (HISR_INT_0_STS | HISR_INT_1_STS | HISR_INT_2_STS)
 226
 227 /* Host Interrupt Enable Register. Resides in PCI memory space. */
 228 #define HIER_REG                         0x2064
 229 #define   HIER_INT_0_EN      BIT(0)
 230 #define   HIER_INT_1_EN      BIT(1)
 231 #define   HIER_INT_2_EN      BIT(2)
 232 #define   HIER_INT_3_EN      BIT(3)
 233 #define   HIER_INT_4_EN      BIT(4)
 234 #define   HIER_INT_5_EN      BIT(5)
 235 #define   HIER_INT_6_EN      BIT(6)
 236 #define   HIER_INT_7_EN      BIT(7)
 237
 238 #define   HIER_INT_EN_MSK \
 239          (HIER_INT_0_EN | HIER_INT_1_EN | HIER_INT_2_EN)
 240
 241
 242 /* SEC Memory Space IPC output payload.
 243  *
 244  * This register is part of the output payload which SEC provides to host.
 245  */
 246 #define BRIDGE_IPC_OUTPUT_PAYLOAD_REG    0x20C0
 247
 248 /* SeC Interrupt Cause Register - Host Aliveness Request
 249  * This register is both an ICR to SeC and it is also exposed
 250  * in the host-visible PCI memory space.
 251  * The register is used by host to request SeC aliveness.
 252  */
 253 #define SICR_HOST_ALIVENESS_REQ_REG      0x214C
 254 #define   SICR_HOST_ALIVENESS_REQ_REQUESTED    BIT(0)
 255
 256
 257 /* SeC Interrupt Cause Register - Host IPC Readiness
 258  *
 259  * This register is both an ICR to SeC and it is also exposed
 260  * in the host-visible PCI memory space.
 261  * This register is used by the host's SeC driver uses in order
 262  * to synchronize with SeC about IPC interface state.
 263  */
 264 #define SICR_HOST_IPC_READINESS_REQ_REG  0x2150
 265
 266
 267 #define SICR_HOST_IPC_READINESS_HOST_RDY  BIT(0)
 268 #define SICR_HOST_IPC_READINESS_SEC_RDY   BIT(1)
 269 #define SICR_HOST_IPC_READINESS_SYS_RDY     \
 270         (SICR_HOST_IPC_READINESS_HOST_RDY | \
 271          SICR_HOST_IPC_READINESS_SEC_RDY)
 272 #define SICR_HOST_IPC_READINESS_RDY_CLR   BIT(2)
 273
 274 /* SeC Interrupt Cause Register - SeC IPC Output Status
 275  *
 276  * This register indicates whether or not processing of the most recent
 277  * command has been completed by the Host.
 278  * New commands and payloads should not be written by SeC until this
 279  * register indicates that the previous command has been processed.
 280  */
 281 #define SICR_SEC_IPC_OUTPUT_STATUS_REG   0x2154
 282 #  define SEC_IPC_OUTPUT_STATUS_RDY BIT(0)
 283
 284
 285
 286 /*  MEI IPC Message payload size 64 bytes */
 287 #define PAYLOAD_SIZE        64
 288
 289 /* MAX size for SATT range 32MB */
 290 #define SATT_RANGE_MAX     (32 << 20)
 291
 292
 293 #endif /* _MEI_HW_TXE_REGS_H_ */
 294