drivers/clocksource/timer-prima2.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * System timer for CSR SiRFprimaII
   4  *
   5  * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
   6  */
   7
   8 #include <linux/kernel.h>
   9 #include <linux/interrupt.h>
  10 #include <linux/clockchips.h>
  11 #include <linux/clocksource.h>
  12 #include <linux/bitops.h>
  13 #include <linux/irq.h>
  14 #include <linux/clk.h>
  15 #include <linux/err.h>
  16 #include <linux/slab.h>
  17 #include <linux/of.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_address.h>
  20 #include <linux/sched_clock.h>
  21
  22 #define PRIMA2_CLOCK_FREQ 1000000
  23
  24 #define SIRFSOC_TIMER_COUNTER_LO        0x0000
  25 #define SIRFSOC_TIMER_COUNTER_HI        0x0004
  26 #define SIRFSOC_TIMER_MATCH_0           0x0008
  27 #define SIRFSOC_TIMER_MATCH_1           0x000C
  28 #define SIRFSOC_TIMER_MATCH_2           0x0010
  29 #define SIRFSOC_TIMER_MATCH_3           0x0014
  30 #define SIRFSOC_TIMER_MATCH_4           0x0018
  31 #define SIRFSOC_TIMER_MATCH_5           0x001C
  32 #define SIRFSOC_TIMER_STATUS            0x0020
  33 #define SIRFSOC_TIMER_INT_EN            0x0024
  34 #define SIRFSOC_TIMER_WATCHDOG_EN       0x0028
  35 #define SIRFSOC_TIMER_DIV               0x002C
  36 #define SIRFSOC_TIMER_LATCH             0x0030
  37 #define SIRFSOC_TIMER_LATCHED_LO        0x0034
  38 #define SIRFSOC_TIMER_LATCHED_HI        0x0038
  39
  40 #define SIRFSOC_TIMER_WDT_INDEX         5
  41
  42 #define SIRFSOC_TIMER_LATCH_BIT  BIT(0)
  43
  44 #define SIRFSOC_TIMER_REG_CNT 11
  45
  46 static const u32 sirfsoc_timer_reg_list[SIRFSOC_TIMER_REG_CNT] = {
  47         SIRFSOC_TIMER_MATCH_0, SIRFSOC_TIMER_MATCH_1, SIRFSOC_TIMER_MATCH_2,
  48         SIRFSOC_TIMER_MATCH_3, SIRFSOC_TIMER_MATCH_4, SIRFSOC_TIMER_MATCH_5,
  49         SIRFSOC_TIMER_INT_EN, SIRFSOC_TIMER_WATCHDOG_EN, SIRFSOC_TIMER_DIV,
  50         SIRFSOC_TIMER_LATCHED_LO, SIRFSOC_TIMER_LATCHED_HI,
  51 };
  52
  53 static u32 sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT];
  54
  55 static void __iomem *sirfsoc_timer_base;
  56
  57 /* timer0 interrupt handler */
  58 static irqreturn_t sirfsoc_timer_interrupt(int irq, void *dev_id)
  59 {
  60         struct clock_event_device *ce = dev_id;
  61
  62         WARN_ON(!(readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_STATUS) &
  63                 BIT(0)));
  64
  65         /* clear timer0 interrupt */
  66         writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
  67
  68         ce->event_handler(ce);
  69
  70         return IRQ_HANDLED;
  71 }
  72
  73 /* read 64-bit timer counter */
  74 static u64 notrace sirfsoc_timer_read(struct clocksource *cs)
  75 {
  76         u64 cycles;
  77
  78         /* latch the 64-bit timer counter */
  79         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
  80                 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  81         cycles = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_HI);
  82         cycles = (cycles << 32) |
  83                 readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  84
  85         return cycles;
  86 }
  87
  88 static int sirfsoc_timer_set_next_event(unsigned long delta,
  89         struct clock_event_device *ce)
  90 {
  91         unsigned long now, next;
  92
  93         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
  94                 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
  95         now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
  96         next = now + delta;
  97         writel_relaxed(next, sirfsoc_timer_base + SIRFSOC_TIMER_MATCH_0);
  98         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
  99                 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
 100         now = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_LATCHED_LO);
 101
 102         return next - now > delta ? -ETIME : 0;
 103 }
 104
 105 static int sirfsoc_timer_shutdown(struct clock_event_device *evt)
 106 {
 107         u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 108
 109         writel_relaxed(val & ~BIT(0),
 110                        sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 111         return 0;
 112 }
 113
 114 static int sirfsoc_timer_set_oneshot(struct clock_event_device *evt)
 115 {
 116         u32 val = readl_relaxed(sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 117
 118         writel_relaxed(val | BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_INT_EN);
 119         return 0;
 120 }
 121
 122 static void sirfsoc_clocksource_suspend(struct clocksource *cs)
 123 {
 124         int i;
 125
 126         writel_relaxed(SIRFSOC_TIMER_LATCH_BIT,
 127                 sirfsoc_timer_base + SIRFSOC_TIMER_LATCH);
 128
 129         for (i = 0; i < SIRFSOC_TIMER_REG_CNT; i++)
 130                 sirfsoc_timer_reg_val[i] =
 131                         readl_relaxed(sirfsoc_timer_base +
 132                                 sirfsoc_timer_reg_list[i]);
 133 }
 134
 135 static void sirfsoc_clocksource_resume(struct clocksource *cs)
 136 {
 137         int i;
 138
 139         for (i = 0; i < SIRFSOC_TIMER_REG_CNT - 2; i++)
 140                 writel_relaxed(sirfsoc_timer_reg_val[i],
 141                         sirfsoc_timer_base + sirfsoc_timer_reg_list[i]);
 142
 143         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 2],
 144                 sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
 145         writel_relaxed(sirfsoc_timer_reg_val[SIRFSOC_TIMER_REG_CNT - 1],
 146                 sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 147 }
 148
 149 static struct clock_event_device sirfsoc_clockevent = {
 150         .name = "sirfsoc_clockevent",
 151         .rating = 200,
 152         .features = CLOCK_EVT_FEAT_ONESHOT,
 153         .set_state_shutdown = sirfsoc_timer_shutdown,
 154         .set_state_oneshot = sirfsoc_timer_set_oneshot,
 155         .set_next_event = sirfsoc_timer_set_next_event,
 156 };
 157
 158 static struct clocksource sirfsoc_clocksource = {
 159         .name = "sirfsoc_clocksource",
 160         .rating = 200,
 161         .mask = CLOCKSOURCE_MASK(64),
 162         .flags = CLOCK_SOURCE_IS_CONTINUOUS,
 163         .read = sirfsoc_timer_read,
 164         .suspend = sirfsoc_clocksource_suspend,
 165         .resume = sirfsoc_clocksource_resume,
 166 };
 167
 168 static struct irqaction sirfsoc_timer_irq = {
 169         .name = "sirfsoc_timer0",
 170         .flags = IRQF_TIMER,
 171         .irq = 0,
 172         .handler = sirfsoc_timer_interrupt,
 173         .dev_id = &sirfsoc_clockevent,
 174 };
 175
 176 /* Overwrite weak default sched_clock with more precise one */
 177 static u64 notrace sirfsoc_read_sched_clock(void)
 178 {
 179         return sirfsoc_timer_read(NULL);
 180 }
 181
 182 static void __init sirfsoc_clockevent_init(void)
 183 {
 184         sirfsoc_clockevent.cpumask = cpumask_of(0);
 185         clockevents_config_and_register(&sirfsoc_clockevent, PRIMA2_CLOCK_FREQ,
 186                                         2, -2);
 187 }
 188
 189 /* initialize the kernel jiffy timer source */
 190 static int __init sirfsoc_prima2_timer_init(struct device_node *np)
 191 {
 192         unsigned long rate;
 193         struct clk *clk;
 194         int ret;
 195
 196         clk = of_clk_get(np, 0);
 197         if (IS_ERR(clk)) {
 198                 pr_err("Failed to get clock\n");
 199                 return PTR_ERR(clk);
 200         }
 201
 202         ret = clk_prepare_enable(clk);
 203         if (ret) {
 204                 pr_err("Failed to enable clock\n");
 205                 return ret;
 206         }
 207
 208         rate = clk_get_rate(clk);
 209
 210         if (rate < PRIMA2_CLOCK_FREQ || rate % PRIMA2_CLOCK_FREQ) {
 211                 pr_err("Invalid clock rate\n");
 212                 return -EINVAL;
 213         }
 214
 215         sirfsoc_timer_base = of_iomap(np, 0);
 216         if (!sirfsoc_timer_base) {
 217                 pr_err("unable to map timer cpu registers\n");
 218                 return -ENXIO;
 219         }
 220
 221         sirfsoc_timer_irq.irq = irq_of_parse_and_map(np, 0);
 222
 223         writel_relaxed(rate / PRIMA2_CLOCK_FREQ / 2 - 1,
 224                 sirfsoc_timer_base + SIRFSOC_TIMER_DIV);
 225         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_LO);
 226         writel_relaxed(0, sirfsoc_timer_base + SIRFSOC_TIMER_COUNTER_HI);
 227         writel_relaxed(BIT(0), sirfsoc_timer_base + SIRFSOC_TIMER_STATUS);
 228
 229         ret = clocksource_register_hz(&sirfsoc_clocksource, PRIMA2_CLOCK_FREQ);
 230         if (ret) {
 231                 pr_err("Failed to register clocksource\n");
 232                 return ret;
 233         }
 234
 235         sched_clock_register(sirfsoc_read_sched_clock, 64, PRIMA2_CLOCK_FREQ);
 236
 237         ret = setup_irq(sirfsoc_timer_irq.irq, &sirfsoc_timer_irq);
 238         if (ret) {
 239                 pr_err("Failed to setup irq\n");
 240                 return ret;
 241         }
 242
 243         sirfsoc_clockevent_init();
 244
 245         return 0;
 246 }
 247 TIMER_OF_DECLARE(sirfsoc_prima2_timer,
 248         "sirf,prima2-tick", sirfsoc_prima2_timer_init);