drivers/mtd/spi-nor/nxp-spifi.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * SPI-NOR driver for NXP SPI Flash Interface (SPIFI)
   4  *
   5  * Copyright (C) 2015 Joachim Eastwood <manabian@gmail.com>
   6  *
   7  * Based on Freescale QuadSPI driver:
   8  * Copyright (C) 2013 Freescale Semiconductor, Inc.
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/err.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/module.h>
  16 #include <linux/mtd/mtd.h>
  17 #include <linux/mtd/partitions.h>
  18 #include <linux/mtd/spi-nor.h>
  19 #include <linux/of.h>
  20 #include <linux/of_device.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spi/spi.h>
  23
  24 /* NXP SPIFI registers, bits and macros */
  25 #define SPIFI_CTRL                              0x000
  26 #define  SPIFI_CTRL_TIMEOUT(timeout)            (timeout)
  27 #define  SPIFI_CTRL_CSHIGH(cshigh)              ((cshigh) << 16)
  28 #define  SPIFI_CTRL_MODE3                       BIT(23)
  29 #define  SPIFI_CTRL_DUAL                        BIT(28)
  30 #define  SPIFI_CTRL_FBCLK                       BIT(30)
  31 #define SPIFI_CMD                               0x004
  32 #define  SPIFI_CMD_DATALEN(dlen)                ((dlen) & 0x3fff)
  33 #define  SPIFI_CMD_DOUT                         BIT(15)
  34 #define  SPIFI_CMD_INTLEN(ilen)                 ((ilen) << 16)
  35 #define  SPIFI_CMD_FIELDFORM(field)             ((field) << 19)
  36 #define  SPIFI_CMD_FIELDFORM_ALL_SERIAL         SPIFI_CMD_FIELDFORM(0x0)
  37 #define  SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA     SPIFI_CMD_FIELDFORM(0x1)
  38 #define  SPIFI_CMD_FRAMEFORM(frame)             ((frame) << 21)
  39 #define  SPIFI_CMD_FRAMEFORM_OPCODE_ONLY        SPIFI_CMD_FRAMEFORM(0x1)
  40 #define  SPIFI_CMD_OPCODE(op)                   ((op) << 24)
  41 #define SPIFI_ADDR                              0x008
  42 #define SPIFI_IDATA                             0x00c
  43 #define SPIFI_CLIMIT                            0x010
  44 #define SPIFI_DATA                              0x014
  45 #define SPIFI_MCMD                              0x018
  46 #define SPIFI_STAT                              0x01c
  47 #define  SPIFI_STAT_MCINIT                      BIT(0)
  48 #define  SPIFI_STAT_CMD                         BIT(1)
  49 #define  SPIFI_STAT_RESET                       BIT(4)
  50
  51 #define SPI_NOR_MAX_ID_LEN      6
  52
  53 struct nxp_spifi {
  54         struct device *dev;
  55         struct clk *clk_spifi;
  56         struct clk *clk_reg;
  57         void __iomem *io_base;
  58         void __iomem *flash_base;
  59         struct spi_nor nor;
  60         bool memory_mode;
  61         u32 mcmd;
  62 };
  63
  64 static int nxp_spifi_wait_for_cmd(struct nxp_spifi *spifi)
  65 {
  66         u8 stat;
  67         int ret;
  68
  69         ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
  70                                  !(stat & SPIFI_STAT_CMD), 10, 30);
  71         if (ret)
  72                 dev_warn(spifi->dev, "command timed out\n");
  73
  74         return ret;
  75 }
  76
  77 static int nxp_spifi_reset(struct nxp_spifi *spifi)
  78 {
  79         u8 stat;
  80         int ret;
  81
  82         writel(SPIFI_STAT_RESET, spifi->io_base + SPIFI_STAT);
  83         ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
  84                                  !(stat & SPIFI_STAT_RESET), 10, 30);
  85         if (ret)
  86                 dev_warn(spifi->dev, "state reset timed out\n");
  87
  88         return ret;
  89 }
  90
  91 static int nxp_spifi_set_memory_mode_off(struct nxp_spifi *spifi)
  92 {
  93         int ret;
  94
  95         if (!spifi->memory_mode)
  96                 return 0;
  97
  98         ret = nxp_spifi_reset(spifi);
  99         if (ret)
 100                 dev_err(spifi->dev, "unable to enter command mode\n");
 101         else
 102                 spifi->memory_mode = false;
 103
 104         return ret;
 105 }
 106
 107 static int nxp_spifi_set_memory_mode_on(struct nxp_spifi *spifi)
 108 {
 109         u8 stat;
 110         int ret;
 111
 112         if (spifi->memory_mode)
 113                 return 0;
 114
 115         writel(spifi->mcmd, spifi->io_base + SPIFI_MCMD);
 116         ret = readb_poll_timeout(spifi->io_base + SPIFI_STAT, stat,
 117                                  stat & SPIFI_STAT_MCINIT, 10, 30);
 118         if (ret)
 119                 dev_err(spifi->dev, "unable to enter memory mode\n");
 120         else
 121                 spifi->memory_mode = true;
 122
 123         return ret;
 124 }
 125
 126 static int nxp_spifi_read_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 127 {
 128         struct nxp_spifi *spifi = nor->priv;
 129         u32 cmd;
 130         int ret;
 131
 132         ret = nxp_spifi_set_memory_mode_off(spifi);
 133         if (ret)
 134                 return ret;
 135
 136         cmd = SPIFI_CMD_DATALEN(len) |
 137               SPIFI_CMD_OPCODE(opcode) |
 138               SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 139               SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
 140         writel(cmd, spifi->io_base + SPIFI_CMD);
 141
 142         while (len--)
 143                 *buf++ = readb(spifi->io_base + SPIFI_DATA);
 144
 145         return nxp_spifi_wait_for_cmd(spifi);
 146 }
 147
 148 static int nxp_spifi_write_reg(struct spi_nor *nor, u8 opcode, u8 *buf, int len)
 149 {
 150         struct nxp_spifi *spifi = nor->priv;
 151         u32 cmd;
 152         int ret;
 153
 154         ret = nxp_spifi_set_memory_mode_off(spifi);
 155         if (ret)
 156                 return ret;
 157
 158         cmd = SPIFI_CMD_DOUT |
 159               SPIFI_CMD_DATALEN(len) |
 160               SPIFI_CMD_OPCODE(opcode) |
 161               SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 162               SPIFI_CMD_FRAMEFORM_OPCODE_ONLY;
 163         writel(cmd, spifi->io_base + SPIFI_CMD);
 164
 165         while (len--)
 166                 writeb(*buf++, spifi->io_base + SPIFI_DATA);
 167
 168         return nxp_spifi_wait_for_cmd(spifi);
 169 }
 170
 171 static ssize_t nxp_spifi_read(struct spi_nor *nor, loff_t from, size_t len,
 172                               u_char *buf)
 173 {
 174         struct nxp_spifi *spifi = nor->priv;
 175         int ret;
 176
 177         ret = nxp_spifi_set_memory_mode_on(spifi);
 178         if (ret)
 179                 return ret;
 180
 181         memcpy_fromio(buf, spifi->flash_base + from, len);
 182
 183         return len;
 184 }
 185
 186 static ssize_t nxp_spifi_write(struct spi_nor *nor, loff_t to, size_t len,
 187                                const u_char *buf)
 188 {
 189         struct nxp_spifi *spifi = nor->priv;
 190         u32 cmd;
 191         int ret;
 192         size_t i;
 193
 194         ret = nxp_spifi_set_memory_mode_off(spifi);
 195         if (ret)
 196                 return ret;
 197
 198         writel(to, spifi->io_base + SPIFI_ADDR);
 199
 200         cmd = SPIFI_CMD_DOUT |
 201               SPIFI_CMD_DATALEN(len) |
 202               SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 203               SPIFI_CMD_OPCODE(nor->program_opcode) |
 204               SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
 205         writel(cmd, spifi->io_base + SPIFI_CMD);
 206
 207         for (i = 0; i < len; i++)
 208                 writeb(buf[i], spifi->io_base + SPIFI_DATA);
 209
 210         ret = nxp_spifi_wait_for_cmd(spifi);
 211         if (ret)
 212                 return ret;
 213
 214         return len;
 215 }
 216
 217 static int nxp_spifi_erase(struct spi_nor *nor, loff_t offs)
 218 {
 219         struct nxp_spifi *spifi = nor->priv;
 220         u32 cmd;
 221         int ret;
 222
 223         ret = nxp_spifi_set_memory_mode_off(spifi);
 224         if (ret)
 225                 return ret;
 226
 227         writel(offs, spifi->io_base + SPIFI_ADDR);
 228
 229         cmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL |
 230               SPIFI_CMD_OPCODE(nor->erase_opcode) |
 231               SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
 232         writel(cmd, spifi->io_base + SPIFI_CMD);
 233
 234         return nxp_spifi_wait_for_cmd(spifi);
 235 }
 236
 237 static int nxp_spifi_setup_memory_cmd(struct nxp_spifi *spifi)
 238 {
 239         switch (spifi->nor.read_proto) {
 240         case SNOR_PROTO_1_1_1:
 241                 spifi->mcmd = SPIFI_CMD_FIELDFORM_ALL_SERIAL;
 242                 break;
 243         case SNOR_PROTO_1_1_2:
 244         case SNOR_PROTO_1_1_4:
 245                 spifi->mcmd = SPIFI_CMD_FIELDFORM_QUAD_DUAL_DATA;
 246                 break;
 247         default:
 248                 dev_err(spifi->dev, "unsupported SPI read mode\n");
 249                 return -EINVAL;
 250         }
 251
 252         /* Memory mode supports address length between 1 and 4 */
 253         if (spifi->nor.addr_width < 1 || spifi->nor.addr_width > 4)
 254                 return -EINVAL;
 255
 256         spifi->mcmd |= SPIFI_CMD_OPCODE(spifi->nor.read_opcode) |
 257                        SPIFI_CMD_INTLEN(spifi->nor.read_dummy / 8) |
 258                        SPIFI_CMD_FRAMEFORM(spifi->nor.addr_width + 1);
 259
 260         return 0;
 261 }
 262
 263 static void nxp_spifi_dummy_id_read(struct spi_nor *nor)
 264 {
 265         u8 id[SPI_NOR_MAX_ID_LEN];
 266         nor->read_reg(nor, SPINOR_OP_RDID, id, SPI_NOR_MAX_ID_LEN);
 267 }
 268
 269 static int nxp_spifi_setup_flash(struct nxp_spifi *spifi,
 270                                  struct device_node *np)
 271 {
 272         struct spi_nor_hwcaps hwcaps = {
 273                 .mask = SNOR_HWCAPS_READ |
 274                         SNOR_HWCAPS_READ_FAST |
 275                         SNOR_HWCAPS_PP,
 276         };
 277         u32 ctrl, property;
 278         u16 mode = 0;
 279         int ret;
 280
 281         if (!of_property_read_u32(np, "spi-rx-bus-width", &property)) {
 282                 switch (property) {
 283                 case 1:
 284                         break;
 285                 case 2:
 286                         mode |= SPI_RX_DUAL;
 287                         break;
 288                 case 4:
 289                         mode |= SPI_RX_QUAD;
 290                         break;
 291                 default:
 292                         dev_err(spifi->dev, "unsupported rx-bus-width\n");
 293                         return -EINVAL;
 294                 }
 295         }
 296
 297         if (of_find_property(np, "spi-cpha", NULL))
 298                 mode |= SPI_CPHA;
 299
 300         if (of_find_property(np, "spi-cpol", NULL))
 301                 mode |= SPI_CPOL;
 302
 303         /* Setup control register defaults */
 304         ctrl = SPIFI_CTRL_TIMEOUT(1000) |
 305                SPIFI_CTRL_CSHIGH(15) |
 306                SPIFI_CTRL_FBCLK;
 307
 308         if (mode & SPI_RX_DUAL) {
 309                 ctrl |= SPIFI_CTRL_DUAL;
 310                 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_2;
 311         } else if (mode & SPI_RX_QUAD) {
 312                 ctrl &= ~SPIFI_CTRL_DUAL;
 313                 hwcaps.mask |= SNOR_HWCAPS_READ_1_1_4;
 314         } else {
 315                 ctrl |= SPIFI_CTRL_DUAL;
 316         }
 317
 318         switch (mode & (SPI_CPHA | SPI_CPOL)) {
 319         case SPI_MODE_0:
 320                 ctrl &= ~SPIFI_CTRL_MODE3;
 321                 break;
 322         case SPI_MODE_3:
 323                 ctrl |= SPIFI_CTRL_MODE3;
 324                 break;
 325         default:
 326                 dev_err(spifi->dev, "only mode 0 and 3 supported\n");
 327                 return -EINVAL;
 328         }
 329
 330         writel(ctrl, spifi->io_base + SPIFI_CTRL);
 331
 332         spifi->nor.dev   = spifi->dev;
 333         spi_nor_set_flash_node(&spifi->nor, np);
 334         spifi->nor.priv  = spifi;
 335         spifi->nor.read  = nxp_spifi_read;
 336         spifi->nor.write = nxp_spifi_write;
 337         spifi->nor.erase = nxp_spifi_erase;
 338         spifi->nor.read_reg  = nxp_spifi_read_reg;
 339         spifi->nor.write_reg = nxp_spifi_write_reg;
 340
 341         /*
 342          * The first read on a hard reset isn't reliable so do a
 343          * dummy read of the id before calling spi_nor_scan().
 344          * The reason for this problem is unknown.
 345          *
 346          * The official NXP spifilib uses more or less the same
 347          * workaround that is applied here by reading the device
 348          * id multiple times.
 349          */
 350         nxp_spifi_dummy_id_read(&spifi->nor);
 351
 352         ret = spi_nor_scan(&spifi->nor, NULL, &hwcaps);
 353         if (ret) {
 354                 dev_err(spifi->dev, "device scan failed\n");
 355                 return ret;
 356         }
 357
 358         ret = nxp_spifi_setup_memory_cmd(spifi);
 359         if (ret) {
 360                 dev_err(spifi->dev, "memory command setup failed\n");
 361                 return ret;
 362         }
 363
 364         ret = mtd_device_register(&spifi->nor.mtd, NULL, 0);
 365         if (ret) {
 366                 dev_err(spifi->dev, "mtd device parse failed\n");
 367                 return ret;
 368         }
 369
 370         return 0;
 371 }
 372
 373 static int nxp_spifi_probe(struct platform_device *pdev)
 374 {
 375         struct device_node *flash_np;
 376         struct nxp_spifi *spifi;
 377         struct resource *res;
 378         int ret;
 379
 380         spifi = devm_kzalloc(&pdev->dev, sizeof(*spifi), GFP_KERNEL);
 381         if (!spifi)
 382                 return -ENOMEM;
 383
 384         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "spifi");
 385         spifi->io_base = devm_ioremap_resource(&pdev->dev, res);
 386         if (IS_ERR(spifi->io_base))
 387                 return PTR_ERR(spifi->io_base);
 388
 389         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "flash");
 390         spifi->flash_base = devm_ioremap_resource(&pdev->dev, res);
 391         if (IS_ERR(spifi->flash_base))
 392                 return PTR_ERR(spifi->flash_base);
 393
 394         spifi->clk_spifi = devm_clk_get(&pdev->dev, "spifi");
 395         if (IS_ERR(spifi->clk_spifi)) {
 396                 dev_err(&pdev->dev, "spifi clock not found\n");
 397                 return PTR_ERR(spifi->clk_spifi);
 398         }
 399
 400         spifi->clk_reg = devm_clk_get(&pdev->dev, "reg");
 401         if (IS_ERR(spifi->clk_reg)) {
 402                 dev_err(&pdev->dev, "reg clock not found\n");
 403                 return PTR_ERR(spifi->clk_reg);
 404         }
 405
 406         ret = clk_prepare_enable(spifi->clk_reg);
 407         if (ret) {
 408                 dev_err(&pdev->dev, "unable to enable reg clock\n");
 409                 return ret;
 410         }
 411
 412         ret = clk_prepare_enable(spifi->clk_spifi);
 413         if (ret) {
 414                 dev_err(&pdev->dev, "unable to enable spifi clock\n");
 415                 goto dis_clk_reg;
 416         }
 417
 418         spifi->dev = &pdev->dev;
 419         platform_set_drvdata(pdev, spifi);
 420
 421         /* Initialize and reset device */
 422         nxp_spifi_reset(spifi);
 423         writel(0, spifi->io_base + SPIFI_IDATA);
 424         writel(0, spifi->io_base + SPIFI_MCMD);
 425         nxp_spifi_reset(spifi);
 426
 427         flash_np = of_get_next_available_child(pdev->dev.of_node, NULL);
 428         if (!flash_np) {
 429                 dev_err(&pdev->dev, "no SPI flash device to configure\n");
 430                 ret = -ENODEV;
 431                 goto dis_clks;
 432         }
 433
 434         ret = nxp_spifi_setup_flash(spifi, flash_np);
 435         of_node_put(flash_np);
 436         if (ret) {
 437                 dev_err(&pdev->dev, "unable to setup flash chip\n");
 438                 goto dis_clks;
 439         }
 440
 441         return 0;
 442
 443 dis_clks:
 444         clk_disable_unprepare(spifi->clk_spifi);
 445 dis_clk_reg:
 446         clk_disable_unprepare(spifi->clk_reg);
 447         return ret;
 448 }
 449
 450 static int nxp_spifi_remove(struct platform_device *pdev)
 451 {
 452         struct nxp_spifi *spifi = platform_get_drvdata(pdev);
 453
 454         mtd_device_unregister(&spifi->nor.mtd);
 455         clk_disable_unprepare(spifi->clk_spifi);
 456         clk_disable_unprepare(spifi->clk_reg);
 457
 458         return 0;
 459 }
 460
 461 static const struct of_device_id nxp_spifi_match[] = {
 462         {.compatible = "nxp,lpc1773-spifi"},
 463         { /* sentinel */ }
 464 };
 465 MODULE_DEVICE_TABLE(of, nxp_spifi_match);
 466
 467 static struct platform_driver nxp_spifi_driver = {
 468         .probe  = nxp_spifi_probe,
 469         .remove = nxp_spifi_remove,
 470         .driver = {
 471                 .name = "nxp-spifi",
 472                 .of_match_table = nxp_spifi_match,
 473         },
 474 };
 475 module_platform_driver(nxp_spifi_driver);
 476
 477 MODULE_DESCRIPTION("NXP SPI Flash Interface driver");
 478 MODULE_AUTHOR("Joachim Eastwood <manabian@gmail.com>");
 479 MODULE_LICENSE("GPL v2");