net: DCB: Validate DCB_ATTR_DCB_BUFFER argument
[linux/fpc-iii.git] / drivers / usb / host / ohci-tmio.c
blobfb6f5e9ae5c620e54aa85c2542339314f634d10e
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * OHCI HCD(Host Controller Driver) for USB.
5 *(C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
6 *(C) Copyright 2000-2002 David Brownell <dbrownell@users.sourceforge.net>
7 *(C) Copyright 2002 Hewlett-Packard Company
9 * Bus glue for Toshiba Mobile IO(TMIO) Controller's OHCI core
10 * (C) Copyright 2005 Chris Humbert <mahadri-usb@drigon.com>
11 * (C) Copyright 2007, 2008 Dmitry Baryshkov <dbaryshkov@gmail.com>
13 * This is known to work with the following variants:
14 * TC6393XB revision 3 (32kB SRAM)
16 * The TMIO's OHCI core DMAs through a small internal buffer that
17 * is directly addressable by the CPU.
19 * Written from sparse documentation from Toshiba and Sharp's driver
20 * for the 2.4 kernel,
21 * usb-ohci-tc6393.c(C) Copyright 2004 Lineo Solutions, Inc.
24 /*#include <linux/fs.h>
25 #include <linux/mount.h>
26 #include <linux/pagemap.h>
27 #include <linux/namei.h>
28 #include <linux/sched.h>*/
29 #include <linux/platform_device.h>
30 #include <linux/mfd/core.h>
31 #include <linux/mfd/tmio.h>
32 #include <linux/dma-mapping.h>
34 /*-------------------------------------------------------------------------*/
37 * USB Host Controller Configuration Register
39 #define CCR_REVID 0x08 /* b Revision ID */
40 #define CCR_BASE 0x10 /* l USB Control Register Base Address Low */
41 #define CCR_ILME 0x40 /* b Internal Local Memory Enable */
42 #define CCR_PM 0x4c /* w Power Management */
43 #define CCR_INTC 0x50 /* b INT Control */
44 #define CCR_LMW1L 0x54 /* w Local Memory Window 1 LMADRS Low */
45 #define CCR_LMW1H 0x56 /* w Local Memory Window 1 LMADRS High */
46 #define CCR_LMW1BL 0x58 /* w Local Memory Window 1 Base Address Low */
47 #define CCR_LMW1BH 0x5A /* w Local Memory Window 1 Base Address High */
48 #define CCR_LMW2L 0x5C /* w Local Memory Window 2 LMADRS Low */
49 #define CCR_LMW2H 0x5E /* w Local Memory Window 2 LMADRS High */
50 #define CCR_LMW2BL 0x60 /* w Local Memory Window 2 Base Address Low */
51 #define CCR_LMW2BH 0x62 /* w Local Memory Window 2 Base Address High */
52 #define CCR_MISC 0xFC /* b MISC */
54 #define CCR_PM_GKEN 0x0001
55 #define CCR_PM_CKRNEN 0x0002
56 #define CCR_PM_USBPW1 0x0004
57 #define CCR_PM_USBPW2 0x0008
58 #define CCR_PM_USBPW3 0x0010
59 #define CCR_PM_PMEE 0x0100
60 #define CCR_PM_PMES 0x8000
62 /*-------------------------------------------------------------------------*/
64 struct tmio_hcd {
65 void __iomem *ccr;
66 spinlock_t lock; /* protects RMW cycles */
69 #define hcd_to_tmio(hcd) ((struct tmio_hcd *)(hcd_to_ohci(hcd) + 1))
71 /*-------------------------------------------------------------------------*/
73 static void tmio_write_pm(struct platform_device *dev)
75 struct usb_hcd *hcd = platform_get_drvdata(dev);
76 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
77 u16 pm;
78 unsigned long flags;
80 spin_lock_irqsave(&tmio->lock, flags);
82 pm = CCR_PM_GKEN | CCR_PM_CKRNEN |
83 CCR_PM_PMEE | CCR_PM_PMES;
85 tmio_iowrite16(pm, tmio->ccr + CCR_PM);
86 spin_unlock_irqrestore(&tmio->lock, flags);
89 static void tmio_stop_hc(struct platform_device *dev)
91 struct usb_hcd *hcd = platform_get_drvdata(dev);
92 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
93 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
94 u16 pm;
96 pm = CCR_PM_GKEN | CCR_PM_CKRNEN;
97 switch (ohci->num_ports) {
98 default:
99 dev_err(&dev->dev, "Unsupported amount of ports: %d\n", ohci->num_ports);
100 /* fall through */
101 case 3:
102 pm |= CCR_PM_USBPW3;
103 /* fall through */
104 case 2:
105 pm |= CCR_PM_USBPW2;
106 /* fall through */
107 case 1:
108 pm |= CCR_PM_USBPW1;
110 tmio_iowrite8(0, tmio->ccr + CCR_INTC);
111 tmio_iowrite8(0, tmio->ccr + CCR_ILME);
112 tmio_iowrite16(0, tmio->ccr + CCR_BASE);
113 tmio_iowrite16(0, tmio->ccr + CCR_BASE + 2);
114 tmio_iowrite16(pm, tmio->ccr + CCR_PM);
117 static void tmio_start_hc(struct platform_device *dev)
119 struct usb_hcd *hcd = platform_get_drvdata(dev);
120 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
121 unsigned long base = hcd->rsrc_start;
123 tmio_write_pm(dev);
124 tmio_iowrite16(base, tmio->ccr + CCR_BASE);
125 tmio_iowrite16(base >> 16, tmio->ccr + CCR_BASE + 2);
126 tmio_iowrite8(1, tmio->ccr + CCR_ILME);
127 tmio_iowrite8(2, tmio->ccr + CCR_INTC);
129 dev_info(&dev->dev, "revision %d @ 0x%08llx, irq %d\n",
130 tmio_ioread8(tmio->ccr + CCR_REVID),
131 (u64) hcd->rsrc_start, hcd->irq);
134 static int ohci_tmio_start(struct usb_hcd *hcd)
136 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
137 int ret;
139 if ((ret = ohci_init(ohci)) < 0)
140 return ret;
142 if ((ret = ohci_run(ohci)) < 0) {
143 dev_err(hcd->self.controller, "can't start %s\n",
144 hcd->self.bus_name);
145 ohci_stop(hcd);
146 return ret;
149 return 0;
152 static const struct hc_driver ohci_tmio_hc_driver = {
153 .description = hcd_name,
154 .product_desc = "TMIO OHCI USB Host Controller",
155 .hcd_priv_size = sizeof(struct ohci_hcd) + sizeof (struct tmio_hcd),
157 /* generic hardware linkage */
158 .irq = ohci_irq,
159 .flags = HCD_USB11 | HCD_MEMORY,
161 /* basic lifecycle operations */
162 .start = ohci_tmio_start,
163 .stop = ohci_stop,
164 .shutdown = ohci_shutdown,
166 /* managing i/o requests and associated device resources */
167 .urb_enqueue = ohci_urb_enqueue,
168 .urb_dequeue = ohci_urb_dequeue,
169 .endpoint_disable = ohci_endpoint_disable,
171 /* scheduling support */
172 .get_frame_number = ohci_get_frame,
174 /* root hub support */
175 .hub_status_data = ohci_hub_status_data,
176 .hub_control = ohci_hub_control,
177 #ifdef CONFIG_PM
178 .bus_suspend = ohci_bus_suspend,
179 .bus_resume = ohci_bus_resume,
180 #endif
181 .start_port_reset = ohci_start_port_reset,
184 /*-------------------------------------------------------------------------*/
185 static struct platform_driver ohci_hcd_tmio_driver;
187 static int ohci_hcd_tmio_drv_probe(struct platform_device *dev)
189 const struct mfd_cell *cell = mfd_get_cell(dev);
190 struct resource *regs = platform_get_resource(dev, IORESOURCE_MEM, 0);
191 struct resource *config = platform_get_resource(dev, IORESOURCE_MEM, 1);
192 struct resource *sram = platform_get_resource(dev, IORESOURCE_MEM, 2);
193 int irq = platform_get_irq(dev, 0);
194 struct tmio_hcd *tmio;
195 struct ohci_hcd *ohci;
196 struct usb_hcd *hcd;
197 int ret;
199 if (usb_disabled())
200 return -ENODEV;
202 if (!cell)
203 return -EINVAL;
205 hcd = usb_create_hcd(&ohci_tmio_hc_driver, &dev->dev, dev_name(&dev->dev));
206 if (!hcd) {
207 ret = -ENOMEM;
208 goto err_usb_create_hcd;
211 hcd->rsrc_start = regs->start;
212 hcd->rsrc_len = resource_size(regs);
214 tmio = hcd_to_tmio(hcd);
216 spin_lock_init(&tmio->lock);
218 tmio->ccr = ioremap(config->start, resource_size(config));
219 if (!tmio->ccr) {
220 ret = -ENOMEM;
221 goto err_ioremap_ccr;
224 hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
225 if (!hcd->regs) {
226 ret = -ENOMEM;
227 goto err_ioremap_regs;
230 if (cell->enable) {
231 ret = cell->enable(dev);
232 if (ret)
233 goto err_enable;
236 tmio_start_hc(dev);
237 ohci = hcd_to_ohci(hcd);
238 ohci_hcd_init(ohci);
240 ret = usb_hcd_setup_local_mem(hcd, sram->start, sram->start,
241 resource_size(sram));
242 if (ret < 0)
243 goto err_enable;
245 ret = usb_add_hcd(hcd, irq, 0);
246 if (ret)
247 goto err_add_hcd;
249 device_wakeup_enable(hcd->self.controller);
250 if (ret == 0)
251 return ret;
253 usb_remove_hcd(hcd);
255 err_add_hcd:
256 tmio_stop_hc(dev);
257 if (cell->disable)
258 cell->disable(dev);
259 err_enable:
260 iounmap(hcd->regs);
261 err_ioremap_regs:
262 iounmap(tmio->ccr);
263 err_ioremap_ccr:
264 usb_put_hcd(hcd);
265 err_usb_create_hcd:
267 return ret;
270 static int ohci_hcd_tmio_drv_remove(struct platform_device *dev)
272 struct usb_hcd *hcd = platform_get_drvdata(dev);
273 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
274 const struct mfd_cell *cell = mfd_get_cell(dev);
276 usb_remove_hcd(hcd);
277 tmio_stop_hc(dev);
278 if (cell->disable)
279 cell->disable(dev);
280 iounmap(hcd->regs);
281 iounmap(tmio->ccr);
282 usb_put_hcd(hcd);
284 return 0;
287 #ifdef CONFIG_PM
288 static int ohci_hcd_tmio_drv_suspend(struct platform_device *dev, pm_message_t state)
290 const struct mfd_cell *cell = mfd_get_cell(dev);
291 struct usb_hcd *hcd = platform_get_drvdata(dev);
292 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
293 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
294 unsigned long flags;
295 u8 misc;
296 int ret;
298 if (time_before(jiffies, ohci->next_statechange))
299 msleep(5);
300 ohci->next_statechange = jiffies;
302 spin_lock_irqsave(&tmio->lock, flags);
304 misc = tmio_ioread8(tmio->ccr + CCR_MISC);
305 misc |= 1 << 3; /* USSUSP */
306 tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
308 spin_unlock_irqrestore(&tmio->lock, flags);
310 if (cell->suspend) {
311 ret = cell->suspend(dev);
312 if (ret)
313 return ret;
315 return 0;
318 static int ohci_hcd_tmio_drv_resume(struct platform_device *dev)
320 const struct mfd_cell *cell = mfd_get_cell(dev);
321 struct usb_hcd *hcd = platform_get_drvdata(dev);
322 struct ohci_hcd *ohci = hcd_to_ohci(hcd);
323 struct tmio_hcd *tmio = hcd_to_tmio(hcd);
324 unsigned long flags;
325 u8 misc;
326 int ret;
328 if (time_before(jiffies, ohci->next_statechange))
329 msleep(5);
330 ohci->next_statechange = jiffies;
332 if (cell->resume) {
333 ret = cell->resume(dev);
334 if (ret)
335 return ret;
338 tmio_start_hc(dev);
340 spin_lock_irqsave(&tmio->lock, flags);
342 misc = tmio_ioread8(tmio->ccr + CCR_MISC);
343 misc &= ~(1 << 3); /* USSUSP */
344 tmio_iowrite8(misc, tmio->ccr + CCR_MISC);
346 spin_unlock_irqrestore(&tmio->lock, flags);
348 ohci_resume(hcd, false);
350 return 0;
352 #else
353 #define ohci_hcd_tmio_drv_suspend NULL
354 #define ohci_hcd_tmio_drv_resume NULL
355 #endif
357 static struct platform_driver ohci_hcd_tmio_driver = {
358 .probe = ohci_hcd_tmio_drv_probe,
359 .remove = ohci_hcd_tmio_drv_remove,
360 .shutdown = usb_hcd_platform_shutdown,
361 .suspend = ohci_hcd_tmio_drv_suspend,
362 .resume = ohci_hcd_tmio_drv_resume,
363 .driver = {
364 .name = "tmio-ohci",