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net: DCB: Validate DCB_ATTR_DCB_BUFFER argument
[linux/fpc-iii.git] / drivers / usb / host / xhci-tegra.c
blobb8e24ccba9f3ec636f0a5eaccc21d0bad8e8e0be
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * NVIDIA Tegra xHCI host controller driver
4 *
5 * Copyright (C) 2014 NVIDIA Corporation
6 * Copyright (C) 2014 Google, Inc.
7 */
8
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/firmware.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/of_device.h>
17 #include <linux/phy/phy.h>
18 #include <linux/phy/tegra/xusb.h>
19 #include <linux/platform_device.h>
20 #include <linux/pm.h>
21 #include <linux/pm_domain.h>
22 #include <linux/pm_runtime.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/slab.h>
26 #include <soc/tegra/pmc.h>
27
28 #include "xhci.h"
29
30 #define TEGRA_XHCI_SS_HIGH_SPEED 120000000
31 #define TEGRA_XHCI_SS_LOW_SPEED 12000000
32
33 /* FPCI CFG registers */
34 #define XUSB_CFG_1 0x004
35 #define XUSB_IO_SPACE_EN BIT(0)
36 #define XUSB_MEM_SPACE_EN BIT(1)
37 #define XUSB_BUS_MASTER_EN BIT(2)
38 #define XUSB_CFG_4 0x010
39 #define XUSB_BASE_ADDR_SHIFT 15
40 #define XUSB_BASE_ADDR_MASK 0x1ffff
41 #define XUSB_CFG_ARU_C11_CSBRANGE 0x41c
42 #define XUSB_CFG_CSB_BASE_ADDR 0x800
43
44 /* FPCI mailbox registers */
45 #define XUSB_CFG_ARU_MBOX_CMD 0x0e4
46 #define MBOX_DEST_FALC BIT(27)
47 #define MBOX_DEST_PME BIT(28)
48 #define MBOX_DEST_SMI BIT(29)
49 #define MBOX_DEST_XHCI BIT(30)
50 #define MBOX_INT_EN BIT(31)
51 #define XUSB_CFG_ARU_MBOX_DATA_IN 0x0e8
52 #define CMD_DATA_SHIFT 0
53 #define CMD_DATA_MASK 0xffffff
54 #define CMD_TYPE_SHIFT 24
55 #define CMD_TYPE_MASK 0xff
56 #define XUSB_CFG_ARU_MBOX_DATA_OUT 0x0ec
57 #define XUSB_CFG_ARU_MBOX_OWNER 0x0f0
58 #define MBOX_OWNER_NONE 0
59 #define MBOX_OWNER_FW 1
60 #define MBOX_OWNER_SW 2
61 #define XUSB_CFG_ARU_SMI_INTR 0x428
62 #define MBOX_SMI_INTR_FW_HANG BIT(1)
63 #define MBOX_SMI_INTR_EN BIT(3)
64
65 /* IPFS registers */
66 #define IPFS_XUSB_HOST_CONFIGURATION_0 0x180
67 #define IPFS_EN_FPCI BIT(0)
68 #define IPFS_XUSB_HOST_INTR_MASK_0 0x188
69 #define IPFS_IP_INT_MASK BIT(16)
70 #define IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0 0x1bc
71
72 #define CSB_PAGE_SELECT_MASK 0x7fffff
73 #define CSB_PAGE_SELECT_SHIFT 9
74 #define CSB_PAGE_OFFSET_MASK 0x1ff
75 #define CSB_PAGE_SELECT(addr) ((addr) >> (CSB_PAGE_SELECT_SHIFT) & \
76 CSB_PAGE_SELECT_MASK)
77 #define CSB_PAGE_OFFSET(addr) ((addr) & CSB_PAGE_OFFSET_MASK)
78
79 /* Falcon CSB registers */
80 #define XUSB_FALC_CPUCTL 0x100
81 #define CPUCTL_STARTCPU BIT(1)
82 #define CPUCTL_STATE_HALTED BIT(4)
83 #define CPUCTL_STATE_STOPPED BIT(5)
84 #define XUSB_FALC_BOOTVEC 0x104
85 #define XUSB_FALC_DMACTL 0x10c
86 #define XUSB_FALC_IMFILLRNG1 0x154
87 #define IMFILLRNG1_TAG_MASK 0xffff
88 #define IMFILLRNG1_TAG_LO_SHIFT 0
89 #define IMFILLRNG1_TAG_HI_SHIFT 16
90 #define XUSB_FALC_IMFILLCTL 0x158
91
92 /* MP CSB registers */
93 #define XUSB_CSB_MP_ILOAD_ATTR 0x101a00
94 #define XUSB_CSB_MP_ILOAD_BASE_LO 0x101a04
95 #define XUSB_CSB_MP_ILOAD_BASE_HI 0x101a08
96 #define XUSB_CSB_MP_L2IMEMOP_SIZE 0x101a10
97 #define L2IMEMOP_SIZE_SRC_OFFSET_SHIFT 8
98 #define L2IMEMOP_SIZE_SRC_OFFSET_MASK 0x3ff
99 #define L2IMEMOP_SIZE_SRC_COUNT_SHIFT 24
100 #define L2IMEMOP_SIZE_SRC_COUNT_MASK 0xff
101 #define XUSB_CSB_MP_L2IMEMOP_TRIG 0x101a14
102 #define L2IMEMOP_ACTION_SHIFT 24
103 #define L2IMEMOP_INVALIDATE_ALL (0x40 << L2IMEMOP_ACTION_SHIFT)
104 #define L2IMEMOP_LOAD_LOCKED_RESULT (0x11 << L2IMEMOP_ACTION_SHIFT)
105 #define XUSB_CSB_MP_APMAP 0x10181c
106 #define APMAP_BOOTPATH BIT(31)
107
108 #define IMEM_BLOCK_SIZE 256
109
110 struct tegra_xusb_fw_header {
111 __le32 boot_loadaddr_in_imem;
112 __le32 boot_codedfi_offset;
113 __le32 boot_codetag;
114 __le32 boot_codesize;
115 __le32 phys_memaddr;
116 __le16 reqphys_memsize;
117 __le16 alloc_phys_memsize;
118 __le32 rodata_img_offset;
119 __le32 rodata_section_start;
120 __le32 rodata_section_end;
121 __le32 main_fnaddr;
122 __le32 fwimg_cksum;
123 __le32 fwimg_created_time;
124 __le32 imem_resident_start;
125 __le32 imem_resident_end;
126 __le32 idirect_start;
127 __le32 idirect_end;
128 __le32 l2_imem_start;
129 __le32 l2_imem_end;
130 __le32 version_id;
131 u8 init_ddirect;
132 u8 reserved[3];
133 __le32 phys_addr_log_buffer;
134 __le32 total_log_entries;
135 __le32 dequeue_ptr;
136 __le32 dummy_var[2];
137 __le32 fwimg_len;
138 u8 magic[8];
139 __le32 ss_low_power_entry_timeout;
140 u8 num_hsic_port;
141 u8 padding[139]; /* Pad to 256 bytes */
142 };
143
144 struct tegra_xusb_phy_type {
145 const char *name;
146 unsigned int num;
147 };
148
149 struct tegra_xusb_soc {
150 const char *firmware;
151 const char * const *supply_names;
152 unsigned int num_supplies;
153 const struct tegra_xusb_phy_type *phy_types;
154 unsigned int num_types;
155
156 struct {
157 struct {
158 unsigned int offset;
159 unsigned int count;
160 } usb2, ulpi, hsic, usb3;
161 } ports;
162
163 bool scale_ss_clock;
164 bool has_ipfs;
165 };
166
167 struct tegra_xusb {
168 struct device *dev;
169 void __iomem *regs;
170 struct usb_hcd *hcd;
171
172 struct mutex lock;
173
174 int xhci_irq;
175 int mbox_irq;
176
177 void __iomem *ipfs_base;
178 void __iomem *fpci_base;
179
180 const struct tegra_xusb_soc *soc;
181
182 struct regulator_bulk_data *supplies;
183
184 struct tegra_xusb_padctl *padctl;
185
186 struct clk *host_clk;
187 struct clk *falcon_clk;
188 struct clk *ss_clk;
189 struct clk *ss_src_clk;
190 struct clk *hs_src_clk;
191 struct clk *fs_src_clk;
192 struct clk *pll_u_480m;
193 struct clk *clk_m;
194 struct clk *pll_e;
195
196 struct reset_control *host_rst;
197 struct reset_control *ss_rst;
198
199 struct device *genpd_dev_host;
200 struct device *genpd_dev_ss;
201 struct device_link *genpd_dl_host;
202 struct device_link *genpd_dl_ss;
203
204 struct phy **phys;
205 unsigned int num_phys;
206
207 /* Firmware loading related */
208 struct {
209 size_t size;
210 void *virt;
211 dma_addr_t phys;
212 } fw;
213 };
214
215 static struct hc_driver __read_mostly tegra_xhci_hc_driver;
216
217 static inline u32 fpci_readl(struct tegra_xusb *tegra, unsigned int offset)
218 {
219 return readl(tegra->fpci_base + offset);
220 }
221
222 static inline void fpci_writel(struct tegra_xusb *tegra, u32 value,
223 unsigned int offset)
224 {
225 writel(value, tegra->fpci_base + offset);
226 }
227
228 static inline u32 ipfs_readl(struct tegra_xusb *tegra, unsigned int offset)
229 {
230 return readl(tegra->ipfs_base + offset);
231 }
232
233 static inline void ipfs_writel(struct tegra_xusb *tegra, u32 value,
234 unsigned int offset)
235 {
236 writel(value, tegra->ipfs_base + offset);
237 }
238
239 static u32 csb_readl(struct tegra_xusb *tegra, unsigned int offset)
240 {
241 u32 page = CSB_PAGE_SELECT(offset);
242 u32 ofs = CSB_PAGE_OFFSET(offset);
243
244 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
245
246 return fpci_readl(tegra, XUSB_CFG_CSB_BASE_ADDR + ofs);
247 }
248
249 static void csb_writel(struct tegra_xusb *tegra, u32 value,
250 unsigned int offset)
251 {
252 u32 page = CSB_PAGE_SELECT(offset);
253 u32 ofs = CSB_PAGE_OFFSET(offset);
254
255 fpci_writel(tegra, page, XUSB_CFG_ARU_C11_CSBRANGE);
256 fpci_writel(tegra, value, XUSB_CFG_CSB_BASE_ADDR + ofs);
257 }
258
259 static int tegra_xusb_set_ss_clk(struct tegra_xusb *tegra,
260 unsigned long rate)
261 {
262 unsigned long new_parent_rate, old_parent_rate;
263 struct clk *clk = tegra->ss_src_clk;
264 unsigned int div;
265 int err;
266
267 if (clk_get_rate(clk) == rate)
268 return 0;
269
270 switch (rate) {
271 case TEGRA_XHCI_SS_HIGH_SPEED:
272 /*
273 * Reparent to PLLU_480M. Set divider first to avoid
274 * overclocking.
275 */
276 old_parent_rate = clk_get_rate(clk_get_parent(clk));
277 new_parent_rate = clk_get_rate(tegra->pll_u_480m);
278 div = new_parent_rate / rate;
279
280 err = clk_set_rate(clk, old_parent_rate / div);
281 if (err)
282 return err;
283
284 err = clk_set_parent(clk, tegra->pll_u_480m);
285 if (err)
286 return err;
287
288 /*
289 * The rate should already be correct, but set it again just
290 * to be sure.
291 */
292 err = clk_set_rate(clk, rate);
293 if (err)
294 return err;
295
296 break;
297
298 case TEGRA_XHCI_SS_LOW_SPEED:
299 /* Reparent to CLK_M */
300 err = clk_set_parent(clk, tegra->clk_m);
301 if (err)
302 return err;
303
304 err = clk_set_rate(clk, rate);
305 if (err)
306 return err;
307
308 break;
309
310 default:
311 dev_err(tegra->dev, "Invalid SS rate: %lu Hz\n", rate);
312 return -EINVAL;
313 }
314
315 if (clk_get_rate(clk) != rate) {
316 dev_err(tegra->dev, "SS clock doesn't match requested rate\n");
317 return -EINVAL;
318 }
319
320 return 0;
321 }
322
323 static unsigned long extract_field(u32 value, unsigned int start,
324 unsigned int count)
325 {
326 return (value >> start) & ((1 << count) - 1);
327 }
328
329 /* Command requests from the firmware */
330 enum tegra_xusb_mbox_cmd {
331 MBOX_CMD_MSG_ENABLED = 1,
332 MBOX_CMD_INC_FALC_CLOCK,
333 MBOX_CMD_DEC_FALC_CLOCK,
334 MBOX_CMD_INC_SSPI_CLOCK,
335 MBOX_CMD_DEC_SSPI_CLOCK,
336 MBOX_CMD_SET_BW, /* no ACK/NAK required */
337 MBOX_CMD_SET_SS_PWR_GATING,
338 MBOX_CMD_SET_SS_PWR_UNGATING,
339 MBOX_CMD_SAVE_DFE_CTLE_CTX,
340 MBOX_CMD_AIRPLANE_MODE_ENABLED, /* unused */
341 MBOX_CMD_AIRPLANE_MODE_DISABLED, /* unused */
342 MBOX_CMD_START_HSIC_IDLE,
343 MBOX_CMD_STOP_HSIC_IDLE,
344 MBOX_CMD_DBC_WAKE_STACK, /* unused */
345 MBOX_CMD_HSIC_PRETEND_CONNECT,
346 MBOX_CMD_RESET_SSPI,
347 MBOX_CMD_DISABLE_SS_LFPS_DETECTION,
348 MBOX_CMD_ENABLE_SS_LFPS_DETECTION,
349
350 MBOX_CMD_MAX,
351
352 /* Response message to above commands */
353 MBOX_CMD_ACK = 128,
354 MBOX_CMD_NAK
355 };
356
357 struct tegra_xusb_mbox_msg {
358 u32 cmd;
359 u32 data;
360 };
361
362 static inline u32 tegra_xusb_mbox_pack(const struct tegra_xusb_mbox_msg *msg)
363 {
364 return (msg->cmd & CMD_TYPE_MASK) << CMD_TYPE_SHIFT |
365 (msg->data & CMD_DATA_MASK) << CMD_DATA_SHIFT;
366 }
367 static inline void tegra_xusb_mbox_unpack(struct tegra_xusb_mbox_msg *msg,
368 u32 value)
369 {
370 msg->cmd = (value >> CMD_TYPE_SHIFT) & CMD_TYPE_MASK;
371 msg->data = (value >> CMD_DATA_SHIFT) & CMD_DATA_MASK;
372 }
373
374 static bool tegra_xusb_mbox_cmd_requires_ack(enum tegra_xusb_mbox_cmd cmd)
375 {
376 switch (cmd) {
377 case MBOX_CMD_SET_BW:
378 case MBOX_CMD_ACK:
379 case MBOX_CMD_NAK:
380 return false;
381
382 default:
383 return true;
384 }
385 }
386
387 static int tegra_xusb_mbox_send(struct tegra_xusb *tegra,
388 const struct tegra_xusb_mbox_msg *msg)
389 {
390 bool wait_for_idle = false;
391 u32 value;
392
393 /*
394 * Acquire the mailbox. The firmware still owns the mailbox for
395 * ACK/NAK messages.
396 */
397 if (!(msg->cmd == MBOX_CMD_ACK || msg->cmd == MBOX_CMD_NAK)) {
398 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
399 if (value != MBOX_OWNER_NONE) {
400 dev_err(tegra->dev, "mailbox is busy\n");
401 return -EBUSY;
402 }
403
404 fpci_writel(tegra, MBOX_OWNER_SW, XUSB_CFG_ARU_MBOX_OWNER);
405
406 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
407 if (value != MBOX_OWNER_SW) {
408 dev_err(tegra->dev, "failed to acquire mailbox\n");
409 return -EBUSY;
410 }
411
412 wait_for_idle = true;
413 }
414
415 value = tegra_xusb_mbox_pack(msg);
416 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_DATA_IN);
417
418 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
419 value |= MBOX_INT_EN | MBOX_DEST_FALC;
420 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
421
422 if (wait_for_idle) {
423 unsigned long timeout = jiffies + msecs_to_jiffies(250);
424
425 while (time_before(jiffies, timeout)) {
426 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
427 if (value == MBOX_OWNER_NONE)
428 break;
429
430 usleep_range(10, 20);
431 }
432
433 if (time_after(jiffies, timeout))
434 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_OWNER);
435
436 if (value != MBOX_OWNER_NONE)
437 return -ETIMEDOUT;
438 }
439
440 return 0;
441 }
442
443 static irqreturn_t tegra_xusb_mbox_irq(int irq, void *data)
444 {
445 struct tegra_xusb *tegra = data;
446 u32 value;
447
448 /* clear mailbox interrupts */
449 value = fpci_readl(tegra, XUSB_CFG_ARU_SMI_INTR);
450 fpci_writel(tegra, value, XUSB_CFG_ARU_SMI_INTR);
451
452 if (value & MBOX_SMI_INTR_FW_HANG)
453 dev_err(tegra->dev, "controller firmware hang\n");
454
455 return IRQ_WAKE_THREAD;
456 }
457
458 static void tegra_xusb_mbox_handle(struct tegra_xusb *tegra,
459 const struct tegra_xusb_mbox_msg *msg)
460 {
461 struct tegra_xusb_padctl *padctl = tegra->padctl;
462 const struct tegra_xusb_soc *soc = tegra->soc;
463 struct device *dev = tegra->dev;
464 struct tegra_xusb_mbox_msg rsp;
465 unsigned long mask;
466 unsigned int port;
467 bool idle, enable;
468 int err = 0;
469
470 memset(&rsp, 0, sizeof(rsp));
471
472 switch (msg->cmd) {
473 case MBOX_CMD_INC_FALC_CLOCK:
474 case MBOX_CMD_DEC_FALC_CLOCK:
475 rsp.data = clk_get_rate(tegra->falcon_clk) / 1000;
476 if (rsp.data != msg->data)
477 rsp.cmd = MBOX_CMD_NAK;
478 else
479 rsp.cmd = MBOX_CMD_ACK;
480
481 break;
482
483 case MBOX_CMD_INC_SSPI_CLOCK:
484 case MBOX_CMD_DEC_SSPI_CLOCK:
485 if (tegra->soc->scale_ss_clock) {
486 err = tegra_xusb_set_ss_clk(tegra, msg->data * 1000);
487 if (err < 0)
488 rsp.cmd = MBOX_CMD_NAK;
489 else
490 rsp.cmd = MBOX_CMD_ACK;
491
492 rsp.data = clk_get_rate(tegra->ss_src_clk) / 1000;
493 } else {
494 rsp.cmd = MBOX_CMD_ACK;
495 rsp.data = msg->data;
496 }
497
498 break;
499
500 case MBOX_CMD_SET_BW:
501 /*
502 * TODO: Request bandwidth once EMC scaling is supported.
503 * Ignore for now since ACK/NAK is not required for SET_BW
504 * messages.
505 */
506 break;
507
508 case MBOX_CMD_SAVE_DFE_CTLE_CTX:
509 err = tegra_xusb_padctl_usb3_save_context(padctl, msg->data);
510 if (err < 0) {
511 dev_err(dev, "failed to save context for USB3#%u: %d\n",
512 msg->data, err);
513 rsp.cmd = MBOX_CMD_NAK;
514 } else {
515 rsp.cmd = MBOX_CMD_ACK;
516 }
517
518 rsp.data = msg->data;
519 break;
520
521 case MBOX_CMD_START_HSIC_IDLE:
522 case MBOX_CMD_STOP_HSIC_IDLE:
523 if (msg->cmd == MBOX_CMD_STOP_HSIC_IDLE)
524 idle = false;
525 else
526 idle = true;
527
528 mask = extract_field(msg->data, 1 + soc->ports.hsic.offset,
529 soc->ports.hsic.count);
530
531 for_each_set_bit(port, &mask, 32) {
532 err = tegra_xusb_padctl_hsic_set_idle(padctl, port,
533 idle);
534 if (err < 0)
535 break;
536 }
537
538 if (err < 0) {
539 dev_err(dev, "failed to set HSIC#%u %s: %d\n", port,
540 idle ? "idle" : "busy", err);
541 rsp.cmd = MBOX_CMD_NAK;
542 } else {
543 rsp.cmd = MBOX_CMD_ACK;
544 }
545
546 rsp.data = msg->data;
547 break;
548
549 case MBOX_CMD_DISABLE_SS_LFPS_DETECTION:
550 case MBOX_CMD_ENABLE_SS_LFPS_DETECTION:
551 if (msg->cmd == MBOX_CMD_DISABLE_SS_LFPS_DETECTION)
552 enable = false;
553 else
554 enable = true;
555
556 mask = extract_field(msg->data, 1 + soc->ports.usb3.offset,
557 soc->ports.usb3.count);
558
559 for_each_set_bit(port, &mask, soc->ports.usb3.count) {
560 err = tegra_xusb_padctl_usb3_set_lfps_detect(padctl,
561 port,
562 enable);
563 if (err < 0)
564 break;
565 }
566
567 if (err < 0) {
568 dev_err(dev,
569 "failed to %s LFPS detection on USB3#%u: %d\n",
570 enable ? "enable" : "disable", port, err);
571 rsp.cmd = MBOX_CMD_NAK;
572 } else {
573 rsp.cmd = MBOX_CMD_ACK;
574 }
575
576 rsp.data = msg->data;
577 break;
578
579 default:
580 dev_warn(dev, "unknown message: %#x\n", msg->cmd);
581 break;
582 }
583
584 if (rsp.cmd) {
585 const char *cmd = (rsp.cmd == MBOX_CMD_ACK) ? "ACK" : "NAK";
586
587 err = tegra_xusb_mbox_send(tegra, &rsp);
588 if (err < 0)
589 dev_err(dev, "failed to send %s: %d\n", cmd, err);
590 }
591 }
592
593 static irqreturn_t tegra_xusb_mbox_thread(int irq, void *data)
594 {
595 struct tegra_xusb *tegra = data;
596 struct tegra_xusb_mbox_msg msg;
597 u32 value;
598
599 mutex_lock(&tegra->lock);
600
601 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_DATA_OUT);
602 tegra_xusb_mbox_unpack(&msg, value);
603
604 value = fpci_readl(tegra, XUSB_CFG_ARU_MBOX_CMD);
605 value &= ~MBOX_DEST_SMI;
606 fpci_writel(tegra, value, XUSB_CFG_ARU_MBOX_CMD);
607
608 /* clear mailbox owner if no ACK/NAK is required */
609 if (!tegra_xusb_mbox_cmd_requires_ack(msg.cmd))
610 fpci_writel(tegra, MBOX_OWNER_NONE, XUSB_CFG_ARU_MBOX_OWNER);
611
612 tegra_xusb_mbox_handle(tegra, &msg);
613
614 mutex_unlock(&tegra->lock);
615 return IRQ_HANDLED;
616 }
617
618 static void tegra_xusb_config(struct tegra_xusb *tegra,
619 struct resource *regs)
620 {
621 u32 value;
622
623 if (tegra->soc->has_ipfs) {
624 value = ipfs_readl(tegra, IPFS_XUSB_HOST_CONFIGURATION_0);
625 value |= IPFS_EN_FPCI;
626 ipfs_writel(tegra, value, IPFS_XUSB_HOST_CONFIGURATION_0);
627
628 usleep_range(10, 20);
629 }
630
631 /* Program BAR0 space */
632 value = fpci_readl(tegra, XUSB_CFG_4);
633 value &= ~(XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
634 value |= regs->start & (XUSB_BASE_ADDR_MASK << XUSB_BASE_ADDR_SHIFT);
635 fpci_writel(tegra, value, XUSB_CFG_4);
636
637 usleep_range(100, 200);
638
639 /* Enable bus master */
640 value = fpci_readl(tegra, XUSB_CFG_1);
641 value |= XUSB_IO_SPACE_EN | XUSB_MEM_SPACE_EN | XUSB_BUS_MASTER_EN;
642 fpci_writel(tegra, value, XUSB_CFG_1);
643
644 if (tegra->soc->has_ipfs) {
645 /* Enable interrupt assertion */
646 value = ipfs_readl(tegra, IPFS_XUSB_HOST_INTR_MASK_0);
647 value |= IPFS_IP_INT_MASK;
648 ipfs_writel(tegra, value, IPFS_XUSB_HOST_INTR_MASK_0);
649
650 /* Set hysteresis */
651 ipfs_writel(tegra, 0x80, IPFS_XUSB_HOST_CLKGATE_HYSTERESIS_0);
652 }
653 }
654
655 static int tegra_xusb_clk_enable(struct tegra_xusb *tegra)
656 {
657 int err;
658
659 err = clk_prepare_enable(tegra->pll_e);
660 if (err < 0)
661 return err;
662
663 err = clk_prepare_enable(tegra->host_clk);
664 if (err < 0)
665 goto disable_plle;
666
667 err = clk_prepare_enable(tegra->ss_clk);
668 if (err < 0)
669 goto disable_host;
670
671 err = clk_prepare_enable(tegra->falcon_clk);
672 if (err < 0)
673 goto disable_ss;
674
675 err = clk_prepare_enable(tegra->fs_src_clk);
676 if (err < 0)
677 goto disable_falc;
678
679 err = clk_prepare_enable(tegra->hs_src_clk);
680 if (err < 0)
681 goto disable_fs_src;
682
683 if (tegra->soc->scale_ss_clock) {
684 err = tegra_xusb_set_ss_clk(tegra, TEGRA_XHCI_SS_HIGH_SPEED);
685 if (err < 0)
686 goto disable_hs_src;
687 }
688
689 return 0;
690
691 disable_hs_src:
692 clk_disable_unprepare(tegra->hs_src_clk);
693 disable_fs_src:
694 clk_disable_unprepare(tegra->fs_src_clk);
695 disable_falc:
696 clk_disable_unprepare(tegra->falcon_clk);
697 disable_ss:
698 clk_disable_unprepare(tegra->ss_clk);
699 disable_host:
700 clk_disable_unprepare(tegra->host_clk);
701 disable_plle:
702 clk_disable_unprepare(tegra->pll_e);
703 return err;
704 }
705
706 static void tegra_xusb_clk_disable(struct tegra_xusb *tegra)
707 {
708 clk_disable_unprepare(tegra->pll_e);
709 clk_disable_unprepare(tegra->host_clk);
710 clk_disable_unprepare(tegra->ss_clk);
711 clk_disable_unprepare(tegra->falcon_clk);
712 clk_disable_unprepare(tegra->fs_src_clk);
713 clk_disable_unprepare(tegra->hs_src_clk);
714 }
715
716 static int tegra_xusb_phy_enable(struct tegra_xusb *tegra)
717 {
718 unsigned int i;
719 int err;
720
721 for (i = 0; i < tegra->num_phys; i++) {
722 err = phy_init(tegra->phys[i]);
723 if (err)
724 goto disable_phy;
725
726 err = phy_power_on(tegra->phys[i]);
727 if (err) {
728 phy_exit(tegra->phys[i]);
729 goto disable_phy;
730 }
731 }
732
733 return 0;
734
735 disable_phy:
736 while (i--) {
737 phy_power_off(tegra->phys[i]);
738 phy_exit(tegra->phys[i]);
739 }
740
741 return err;
742 }
743
744 static void tegra_xusb_phy_disable(struct tegra_xusb *tegra)
745 {
746 unsigned int i;
747
748 for (i = 0; i < tegra->num_phys; i++) {
749 phy_power_off(tegra->phys[i]);
750 phy_exit(tegra->phys[i]);
751 }
752 }
753
754 static int tegra_xusb_runtime_suspend(struct device *dev)
755 {
756 struct tegra_xusb *tegra = dev_get_drvdata(dev);
757
758 regulator_bulk_disable(tegra->soc->num_supplies, tegra->supplies);
759 tegra_xusb_clk_disable(tegra);
760
761 return 0;
762 }
763
764 static int tegra_xusb_runtime_resume(struct device *dev)
765 {
766 struct tegra_xusb *tegra = dev_get_drvdata(dev);
767 int err;
768
769 err = tegra_xusb_clk_enable(tegra);
770 if (err) {
771 dev_err(dev, "failed to enable clocks: %d\n", err);
772 return err;
773 }
774
775 err = regulator_bulk_enable(tegra->soc->num_supplies, tegra->supplies);
776 if (err) {
777 dev_err(dev, "failed to enable regulators: %d\n", err);
778 goto disable_clk;
779 }
780
781 return 0;
782
783 disable_clk:
784 tegra_xusb_clk_disable(tegra);
785 return err;
786 }
787
788 static int tegra_xusb_load_firmware(struct tegra_xusb *tegra)
789 {
790 unsigned int code_tag_blocks, code_size_blocks, code_blocks;
791 struct tegra_xusb_fw_header *header;
792 struct device *dev = tegra->dev;
793 const struct firmware *fw;
794 unsigned long timeout;
795 time64_t timestamp;
796 struct tm time;
797 u64 address;
798 u32 value;
799 int err;
800
801 err = request_firmware(&fw, tegra->soc->firmware, tegra->dev);
802 if (err < 0) {
803 dev_err(tegra->dev, "failed to request firmware: %d\n", err);
804 return err;
805 }
806
807 /* Load Falcon controller with its firmware. */
808 header = (struct tegra_xusb_fw_header *)fw->data;
809 tegra->fw.size = le32_to_cpu(header->fwimg_len);
810
811 tegra->fw.virt = dma_alloc_coherent(tegra->dev, tegra->fw.size,
812 &tegra->fw.phys, GFP_KERNEL);
813 if (!tegra->fw.virt) {
814 dev_err(tegra->dev, "failed to allocate memory for firmware\n");
815 release_firmware(fw);
816 return -ENOMEM;
817 }
818
819 header = (struct tegra_xusb_fw_header *)tegra->fw.virt;
820 memcpy(tegra->fw.virt, fw->data, tegra->fw.size);
821 release_firmware(fw);
822
823 if (csb_readl(tegra, XUSB_CSB_MP_ILOAD_BASE_LO) != 0) {
824 dev_info(dev, "Firmware already loaded, Falcon state %#x\n",
825 csb_readl(tegra, XUSB_FALC_CPUCTL));
826 return 0;
827 }
828
829 /* Program the size of DFI into ILOAD_ATTR. */
830 csb_writel(tegra, tegra->fw.size, XUSB_CSB_MP_ILOAD_ATTR);
831
832 /*
833 * Boot code of the firmware reads the ILOAD_BASE registers
834 * to get to the start of the DFI in system memory.
835 */
836 address = tegra->fw.phys + sizeof(*header);
837 csb_writel(tegra, address >> 32, XUSB_CSB_MP_ILOAD_BASE_HI);
838 csb_writel(tegra, address, XUSB_CSB_MP_ILOAD_BASE_LO);
839
840 /* Set BOOTPATH to 1 in APMAP. */
841 csb_writel(tegra, APMAP_BOOTPATH, XUSB_CSB_MP_APMAP);
842
843 /* Invalidate L2IMEM. */
844 csb_writel(tegra, L2IMEMOP_INVALIDATE_ALL, XUSB_CSB_MP_L2IMEMOP_TRIG);
845
846 /*
847 * Initiate fetch of bootcode from system memory into L2IMEM.
848 * Program bootcode location and size in system memory.
849 */
850 code_tag_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codetag),
851 IMEM_BLOCK_SIZE);
852 code_size_blocks = DIV_ROUND_UP(le32_to_cpu(header->boot_codesize),
853 IMEM_BLOCK_SIZE);
854 code_blocks = code_tag_blocks + code_size_blocks;
855
856 value = ((code_tag_blocks & L2IMEMOP_SIZE_SRC_OFFSET_MASK) <<
857 L2IMEMOP_SIZE_SRC_OFFSET_SHIFT) |
858 ((code_size_blocks & L2IMEMOP_SIZE_SRC_COUNT_MASK) <<
859 L2IMEMOP_SIZE_SRC_COUNT_SHIFT);
860 csb_writel(tegra, value, XUSB_CSB_MP_L2IMEMOP_SIZE);
861
862 /* Trigger L2IMEM load operation. */
863 csb_writel(tegra, L2IMEMOP_LOAD_LOCKED_RESULT,
864 XUSB_CSB_MP_L2IMEMOP_TRIG);
865
866 /* Setup Falcon auto-fill. */
867 csb_writel(tegra, code_size_blocks, XUSB_FALC_IMFILLCTL);
868
869 value = ((code_tag_blocks & IMFILLRNG1_TAG_MASK) <<
870 IMFILLRNG1_TAG_LO_SHIFT) |
871 ((code_blocks & IMFILLRNG1_TAG_MASK) <<
872 IMFILLRNG1_TAG_HI_SHIFT);
873 csb_writel(tegra, value, XUSB_FALC_IMFILLRNG1);
874
875 csb_writel(tegra, 0, XUSB_FALC_DMACTL);
876
877 msleep(50);
878
879 csb_writel(tegra, le32_to_cpu(header->boot_codetag),
880 XUSB_FALC_BOOTVEC);
881
882 /* Boot Falcon CPU and wait for it to enter the STOPPED (idle) state. */
883 timeout = jiffies + msecs_to_jiffies(5);
884
885 csb_writel(tegra, CPUCTL_STARTCPU, XUSB_FALC_CPUCTL);
886
887 while (time_before(jiffies, timeout)) {
888 if (csb_readl(tegra, XUSB_FALC_CPUCTL) == CPUCTL_STATE_STOPPED)
889 break;
890
891 usleep_range(100, 200);
892 }
893
894 if (csb_readl(tegra, XUSB_FALC_CPUCTL) != CPUCTL_STATE_STOPPED) {
895 dev_err(dev, "Falcon failed to start, state: %#x\n",
896 csb_readl(tegra, XUSB_FALC_CPUCTL));
897 return -EIO;
898 }
899
900 timestamp = le32_to_cpu(header->fwimg_created_time);
901 time64_to_tm(timestamp, 0, &time);
902
903 dev_info(dev, "Firmware timestamp: %ld-%02d-%02d %02d:%02d:%02d UTC\n",
904 time.tm_year + 1900, time.tm_mon + 1, time.tm_mday,
905 time.tm_hour, time.tm_min, time.tm_sec);
906
907 return 0;
908 }
909
910 static void tegra_xusb_powerdomain_remove(struct device *dev,
911 struct tegra_xusb *tegra)
912 {
913 if (tegra->genpd_dl_ss)
914 device_link_del(tegra->genpd_dl_ss);
915 if (tegra->genpd_dl_host)
916 device_link_del(tegra->genpd_dl_host);
917 if (!IS_ERR_OR_NULL(tegra->genpd_dev_ss))
918 dev_pm_domain_detach(tegra->genpd_dev_ss, true);
919 if (!IS_ERR_OR_NULL(tegra->genpd_dev_host))
920 dev_pm_domain_detach(tegra->genpd_dev_host, true);
921 }
922
923 static int tegra_xusb_powerdomain_init(struct device *dev,
924 struct tegra_xusb *tegra)
925 {
926 int err;
927
928 tegra->genpd_dev_host = dev_pm_domain_attach_by_name(dev, "xusb_host");
929 if (IS_ERR(tegra->genpd_dev_host)) {
930 err = PTR_ERR(tegra->genpd_dev_host);
931 dev_err(dev, "failed to get host pm-domain: %d\n", err);
932 return err;
933 }
934
935 tegra->genpd_dev_ss = dev_pm_domain_attach_by_name(dev, "xusb_ss");
936 if (IS_ERR(tegra->genpd_dev_ss)) {
937 err = PTR_ERR(tegra->genpd_dev_ss);
938 dev_err(dev, "failed to get superspeed pm-domain: %d\n", err);
939 return err;
940 }
941
942 tegra->genpd_dl_host = device_link_add(dev, tegra->genpd_dev_host,
943 DL_FLAG_PM_RUNTIME |
944 DL_FLAG_STATELESS);
945 if (!tegra->genpd_dl_host) {
946 dev_err(dev, "adding host device link failed!\n");
947 return -ENODEV;
948 }
949
950 tegra->genpd_dl_ss = device_link_add(dev, tegra->genpd_dev_ss,
951 DL_FLAG_PM_RUNTIME |
952 DL_FLAG_STATELESS);
953 if (!tegra->genpd_dl_ss) {
954 dev_err(dev, "adding superspeed device link failed!\n");
955 return -ENODEV;
956 }
957
958 return 0;
959 }
960
961 static int tegra_xusb_probe(struct platform_device *pdev)
962 {
963 struct tegra_xusb_mbox_msg msg;
964 struct resource *res, *regs;
965 struct tegra_xusb *tegra;
966 struct xhci_hcd *xhci;
967 unsigned int i, j, k;
968 struct phy *phy;
969 int err;
970
971 BUILD_BUG_ON(sizeof(struct tegra_xusb_fw_header) != 256);
972
973 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
974 if (!tegra)
975 return -ENOMEM;
976
977 tegra->soc = of_device_get_match_data(&pdev->dev);
978 mutex_init(&tegra->lock);
979 tegra->dev = &pdev->dev;
980
981 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
982 tegra->regs = devm_ioremap_resource(&pdev->dev, regs);
983 if (IS_ERR(tegra->regs))
984 return PTR_ERR(tegra->regs);
985
986 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
987 tegra->fpci_base = devm_ioremap_resource(&pdev->dev, res);
988 if (IS_ERR(tegra->fpci_base))
989 return PTR_ERR(tegra->fpci_base);
990
991 if (tegra->soc->has_ipfs) {
992 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
993 tegra->ipfs_base = devm_ioremap_resource(&pdev->dev, res);
994 if (IS_ERR(tegra->ipfs_base))
995 return PTR_ERR(tegra->ipfs_base);
996 }
997
998 tegra->xhci_irq = platform_get_irq(pdev, 0);
999 if (tegra->xhci_irq < 0)
1000 return tegra->xhci_irq;
1001
1002 tegra->mbox_irq = platform_get_irq(pdev, 1);
1003 if (tegra->mbox_irq < 0)
1004 return tegra->mbox_irq;
1005
1006 tegra->padctl = tegra_xusb_padctl_get(&pdev->dev);
1007 if (IS_ERR(tegra->padctl))
1008 return PTR_ERR(tegra->padctl);
1009
1010 tegra->host_clk = devm_clk_get(&pdev->dev, "xusb_host");
1011 if (IS_ERR(tegra->host_clk)) {
1012 err = PTR_ERR(tegra->host_clk);
1013 dev_err(&pdev->dev, "failed to get xusb_host: %d\n", err);
1014 goto put_padctl;
1015 }
1016
1017 tegra->falcon_clk = devm_clk_get(&pdev->dev, "xusb_falcon_src");
1018 if (IS_ERR(tegra->falcon_clk)) {
1019 err = PTR_ERR(tegra->falcon_clk);
1020 dev_err(&pdev->dev, "failed to get xusb_falcon_src: %d\n", err);
1021 goto put_padctl;
1022 }
1023
1024 tegra->ss_clk = devm_clk_get(&pdev->dev, "xusb_ss");
1025 if (IS_ERR(tegra->ss_clk)) {
1026 err = PTR_ERR(tegra->ss_clk);
1027 dev_err(&pdev->dev, "failed to get xusb_ss: %d\n", err);
1028 goto put_padctl;
1029 }
1030
1031 tegra->ss_src_clk = devm_clk_get(&pdev->dev, "xusb_ss_src");
1032 if (IS_ERR(tegra->ss_src_clk)) {
1033 err = PTR_ERR(tegra->ss_src_clk);
1034 dev_err(&pdev->dev, "failed to get xusb_ss_src: %d\n", err);
1035 goto put_padctl;
1036 }
1037
1038 tegra->hs_src_clk = devm_clk_get(&pdev->dev, "xusb_hs_src");
1039 if (IS_ERR(tegra->hs_src_clk)) {
1040 err = PTR_ERR(tegra->hs_src_clk);
1041 dev_err(&pdev->dev, "failed to get xusb_hs_src: %d\n", err);
1042 goto put_padctl;
1043 }
1044
1045 tegra->fs_src_clk = devm_clk_get(&pdev->dev, "xusb_fs_src");
1046 if (IS_ERR(tegra->fs_src_clk)) {
1047 err = PTR_ERR(tegra->fs_src_clk);
1048 dev_err(&pdev->dev, "failed to get xusb_fs_src: %d\n", err);
1049 goto put_padctl;
1050 }
1051
1052 tegra->pll_u_480m = devm_clk_get(&pdev->dev, "pll_u_480m");
1053 if (IS_ERR(tegra->pll_u_480m)) {
1054 err = PTR_ERR(tegra->pll_u_480m);
1055 dev_err(&pdev->dev, "failed to get pll_u_480m: %d\n", err);
1056 goto put_padctl;
1057 }
1058
1059 tegra->clk_m = devm_clk_get(&pdev->dev, "clk_m");
1060 if (IS_ERR(tegra->clk_m)) {
1061 err = PTR_ERR(tegra->clk_m);
1062 dev_err(&pdev->dev, "failed to get clk_m: %d\n", err);
1063 goto put_padctl;
1064 }
1065
1066 tegra->pll_e = devm_clk_get(&pdev->dev, "pll_e");
1067 if (IS_ERR(tegra->pll_e)) {
1068 err = PTR_ERR(tegra->pll_e);
1069 dev_err(&pdev->dev, "failed to get pll_e: %d\n", err);
1070 goto put_padctl;
1071 }
1072
1073 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1074 tegra->host_rst = devm_reset_control_get(&pdev->dev,
1075 "xusb_host");
1076 if (IS_ERR(tegra->host_rst)) {
1077 err = PTR_ERR(tegra->host_rst);
1078 dev_err(&pdev->dev,
1079 "failed to get xusb_host reset: %d\n", err);
1080 goto put_padctl;
1081 }
1082
1083 tegra->ss_rst = devm_reset_control_get(&pdev->dev, "xusb_ss");
1084 if (IS_ERR(tegra->ss_rst)) {
1085 err = PTR_ERR(tegra->ss_rst);
1086 dev_err(&pdev->dev, "failed to get xusb_ss reset: %d\n",
1087 err);
1088 goto put_padctl;
1089 }
1090
1091 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBA,
1092 tegra->ss_clk,
1093 tegra->ss_rst);
1094 if (err) {
1095 dev_err(&pdev->dev,
1096 "failed to enable XUSBA domain: %d\n", err);
1097 goto put_padctl;
1098 }
1099
1100 err = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_XUSBC,
1101 tegra->host_clk,
1102 tegra->host_rst);
1103 if (err) {
1104 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1105 dev_err(&pdev->dev,
1106 "failed to enable XUSBC domain: %d\n", err);
1107 goto put_padctl;
1108 }
1109 } else {
1110 err = tegra_xusb_powerdomain_init(&pdev->dev, tegra);
1111 if (err)
1112 goto put_powerdomains;
1113 }
1114
1115 tegra->supplies = devm_kcalloc(&pdev->dev, tegra->soc->num_supplies,
1116 sizeof(*tegra->supplies), GFP_KERNEL);
1117 if (!tegra->supplies) {
1118 err = -ENOMEM;
1119 goto put_powerdomains;
1120 }
1121
1122 for (i = 0; i < tegra->soc->num_supplies; i++)
1123 tegra->supplies[i].supply = tegra->soc->supply_names[i];
1124
1125 err = devm_regulator_bulk_get(&pdev->dev, tegra->soc->num_supplies,
1126 tegra->supplies);
1127 if (err) {
1128 dev_err(&pdev->dev, "failed to get regulators: %d\n", err);
1129 goto put_powerdomains;
1130 }
1131
1132 for (i = 0; i < tegra->soc->num_types; i++)
1133 tegra->num_phys += tegra->soc->phy_types[i].num;
1134
1135 tegra->phys = devm_kcalloc(&pdev->dev, tegra->num_phys,
1136 sizeof(*tegra->phys), GFP_KERNEL);
1137 if (!tegra->phys) {
1138 err = -ENOMEM;
1139 goto put_powerdomains;
1140 }
1141
1142 for (i = 0, k = 0; i < tegra->soc->num_types; i++) {
1143 char prop[8];
1144
1145 for (j = 0; j < tegra->soc->phy_types[i].num; j++) {
1146 snprintf(prop, sizeof(prop), "%s-%d",
1147 tegra->soc->phy_types[i].name, j);
1148
1149 phy = devm_phy_optional_get(&pdev->dev, prop);
1150 if (IS_ERR(phy)) {
1151 dev_err(&pdev->dev,
1152 "failed to get PHY %s: %ld\n", prop,
1153 PTR_ERR(phy));
1154 err = PTR_ERR(phy);
1155 goto put_powerdomains;
1156 }
1157
1158 tegra->phys[k++] = phy;
1159 }
1160 }
1161
1162 tegra->hcd = usb_create_hcd(&tegra_xhci_hc_driver, &pdev->dev,
1163 dev_name(&pdev->dev));
1164 if (!tegra->hcd) {
1165 err = -ENOMEM;
1166 goto put_powerdomains;
1167 }
1168
1169 /*
1170 * This must happen after usb_create_hcd(), because usb_create_hcd()
1171 * will overwrite the drvdata of the device with the hcd it creates.
1172 */
1173 platform_set_drvdata(pdev, tegra);
1174
1175 err = tegra_xusb_phy_enable(tegra);
1176 if (err < 0) {
1177 dev_err(&pdev->dev, "failed to enable PHYs: %d\n", err);
1178 goto put_hcd;
1179 }
1180
1181 pm_runtime_enable(&pdev->dev);
1182 if (pm_runtime_enabled(&pdev->dev))
1183 err = pm_runtime_get_sync(&pdev->dev);
1184 else
1185 err = tegra_xusb_runtime_resume(&pdev->dev);
1186
1187 if (err < 0) {
1188 dev_err(&pdev->dev, "failed to enable device: %d\n", err);
1189 goto disable_phy;
1190 }
1191
1192 tegra_xusb_config(tegra, regs);
1193
1194 /*
1195 * The XUSB Falcon microcontroller can only address 40 bits, so set
1196 * the DMA mask accordingly.
1197 */
1198 err = dma_set_mask_and_coherent(tegra->dev, DMA_BIT_MASK(40));
1199 if (err < 0) {
1200 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err);
1201 goto put_rpm;
1202 }
1203
1204 err = tegra_xusb_load_firmware(tegra);
1205 if (err < 0) {
1206 dev_err(&pdev->dev, "failed to load firmware: %d\n", err);
1207 goto put_rpm;
1208 }
1209
1210 tegra->hcd->regs = tegra->regs;
1211 tegra->hcd->rsrc_start = regs->start;
1212 tegra->hcd->rsrc_len = resource_size(regs);
1213
1214 err = usb_add_hcd(tegra->hcd, tegra->xhci_irq, IRQF_SHARED);
1215 if (err < 0) {
1216 dev_err(&pdev->dev, "failed to add USB HCD: %d\n", err);
1217 goto put_rpm;
1218 }
1219
1220 device_wakeup_enable(tegra->hcd->self.controller);
1221
1222 xhci = hcd_to_xhci(tegra->hcd);
1223
1224 xhci->shared_hcd = usb_create_shared_hcd(&tegra_xhci_hc_driver,
1225 &pdev->dev,
1226 dev_name(&pdev->dev),
1227 tegra->hcd);
1228 if (!xhci->shared_hcd) {
1229 dev_err(&pdev->dev, "failed to create shared HCD\n");
1230 err = -ENOMEM;
1231 goto remove_usb2;
1232 }
1233
1234 err = usb_add_hcd(xhci->shared_hcd, tegra->xhci_irq, IRQF_SHARED);
1235 if (err < 0) {
1236 dev_err(&pdev->dev, "failed to add shared HCD: %d\n", err);
1237 goto put_usb3;
1238 }
1239
1240 mutex_lock(&tegra->lock);
1241
1242 /* Enable firmware messages from controller. */
1243 msg.cmd = MBOX_CMD_MSG_ENABLED;
1244 msg.data = 0;
1245
1246 err = tegra_xusb_mbox_send(tegra, &msg);
1247 if (err < 0) {
1248 dev_err(&pdev->dev, "failed to enable messages: %d\n", err);
1249 mutex_unlock(&tegra->lock);
1250 goto remove_usb3;
1251 }
1252
1253 mutex_unlock(&tegra->lock);
1254
1255 err = devm_request_threaded_irq(&pdev->dev, tegra->mbox_irq,
1256 tegra_xusb_mbox_irq,
1257 tegra_xusb_mbox_thread, 0,
1258 dev_name(&pdev->dev), tegra);
1259 if (err < 0) {
1260 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
1261 goto remove_usb3;
1262 }
1263
1264 return 0;
1265
1266 remove_usb3:
1267 usb_remove_hcd(xhci->shared_hcd);
1268 put_usb3:
1269 usb_put_hcd(xhci->shared_hcd);
1270 remove_usb2:
1271 usb_remove_hcd(tegra->hcd);
1272 put_rpm:
1273 if (!pm_runtime_status_suspended(&pdev->dev))
1274 tegra_xusb_runtime_suspend(&pdev->dev);
1275 put_hcd:
1276 usb_put_hcd(tegra->hcd);
1277 disable_phy:
1278 tegra_xusb_phy_disable(tegra);
1279 pm_runtime_disable(&pdev->dev);
1280 put_powerdomains:
1281 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1282 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1283 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1284 } else {
1285 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1286 }
1287 put_padctl:
1288 tegra_xusb_padctl_put(tegra->padctl);
1289 return err;
1290 }
1291
1292 static int tegra_xusb_remove(struct platform_device *pdev)
1293 {
1294 struct tegra_xusb *tegra = platform_get_drvdata(pdev);
1295 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1296
1297 usb_remove_hcd(xhci->shared_hcd);
1298 usb_put_hcd(xhci->shared_hcd);
1299 xhci->shared_hcd = NULL;
1300 usb_remove_hcd(tegra->hcd);
1301 usb_put_hcd(tegra->hcd);
1302
1303 dma_free_coherent(&pdev->dev, tegra->fw.size, tegra->fw.virt,
1304 tegra->fw.phys);
1305
1306 pm_runtime_put_sync(&pdev->dev);
1307 pm_runtime_disable(&pdev->dev);
1308
1309 if (!of_property_read_bool(pdev->dev.of_node, "power-domains")) {
1310 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBC);
1311 tegra_powergate_power_off(TEGRA_POWERGATE_XUSBA);
1312 } else {
1313 tegra_xusb_powerdomain_remove(&pdev->dev, tegra);
1314 }
1315
1316 tegra_xusb_phy_disable(tegra);
1317
1318 tegra_xusb_padctl_put(tegra->padctl);
1319
1320 return 0;
1321 }
1322
1323 #ifdef CONFIG_PM_SLEEP
1324 static int tegra_xusb_suspend(struct device *dev)
1325 {
1326 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1327 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1328 bool wakeup = device_may_wakeup(dev);
1329
1330 /* TODO: Powergate controller across suspend/resume. */
1331 return xhci_suspend(xhci, wakeup);
1332 }
1333
1334 static int tegra_xusb_resume(struct device *dev)
1335 {
1336 struct tegra_xusb *tegra = dev_get_drvdata(dev);
1337 struct xhci_hcd *xhci = hcd_to_xhci(tegra->hcd);
1338
1339 return xhci_resume(xhci, 0);
1340 }
1341 #endif
1342
1343 static const struct dev_pm_ops tegra_xusb_pm_ops = {
1344 SET_RUNTIME_PM_OPS(tegra_xusb_runtime_suspend,
1345 tegra_xusb_runtime_resume, NULL)
1346 SET_SYSTEM_SLEEP_PM_OPS(tegra_xusb_suspend, tegra_xusb_resume)
1347 };
1348
1349 static const char * const tegra124_supply_names[] = {
1350 "avddio-pex",
1351 "dvddio-pex",
1352 "avdd-usb",
1353 "avdd-pll-utmip",
1354 "avdd-pll-erefe",
1355 "avdd-usb-ss-pll",
1356 "hvdd-usb-ss",
1357 "hvdd-usb-ss-pll-e",
1358 };
1359
1360 static const struct tegra_xusb_phy_type tegra124_phy_types[] = {
1361 { .name = "usb3", .num = 2, },
1362 { .name = "usb2", .num = 3, },
1363 { .name = "hsic", .num = 2, },
1364 };
1365
1366 static const struct tegra_xusb_soc tegra124_soc = {
1367 .firmware = "nvidia/tegra124/xusb.bin",
1368 .supply_names = tegra124_supply_names,
1369 .num_supplies = ARRAY_SIZE(tegra124_supply_names),
1370 .phy_types = tegra124_phy_types,
1371 .num_types = ARRAY_SIZE(tegra124_phy_types),
1372 .ports = {
1373 .usb2 = { .offset = 4, .count = 4, },
1374 .hsic = { .offset = 6, .count = 2, },
1375 .usb3 = { .offset = 0, .count = 2, },
1376 },
1377 .scale_ss_clock = true,
1378 .has_ipfs = true,
1379 };
1380 MODULE_FIRMWARE("nvidia/tegra124/xusb.bin");
1381
1382 static const char * const tegra210_supply_names[] = {
1383 "dvddio-pex",
1384 "hvddio-pex",
1385 "avdd-usb",
1386 "avdd-pll-utmip",
1387 "avdd-pll-uerefe",
1388 "dvdd-pex-pll",
1389 "hvdd-pex-pll-e",
1390 };
1391
1392 static const struct tegra_xusb_phy_type tegra210_phy_types[] = {
1393 { .name = "usb3", .num = 4, },
1394 { .name = "usb2", .num = 4, },
1395 { .name = "hsic", .num = 1, },
1396 };
1397
1398 static const struct tegra_xusb_soc tegra210_soc = {
1399 .firmware = "nvidia/tegra210/xusb.bin",
1400 .supply_names = tegra210_supply_names,
1401 .num_supplies = ARRAY_SIZE(tegra210_supply_names),
1402 .phy_types = tegra210_phy_types,
1403 .num_types = ARRAY_SIZE(tegra210_phy_types),
1404 .ports = {
1405 .usb2 = { .offset = 4, .count = 4, },
1406 .hsic = { .offset = 8, .count = 1, },
1407 .usb3 = { .offset = 0, .count = 4, },
1408 },
1409 .scale_ss_clock = false,
1410 .has_ipfs = true,
1411 };
1412 MODULE_FIRMWARE("nvidia/tegra210/xusb.bin");
1413
1414 static const char * const tegra186_supply_names[] = {
1415 };
1416 MODULE_FIRMWARE("nvidia/tegra186/xusb.bin");
1417
1418 static const struct tegra_xusb_phy_type tegra186_phy_types[] = {
1419 { .name = "usb3", .num = 3, },
1420 { .name = "usb2", .num = 3, },
1421 { .name = "hsic", .num = 1, },
1422 };
1423
1424 static const struct tegra_xusb_soc tegra186_soc = {
1425 .firmware = "nvidia/tegra186/xusb.bin",
1426 .supply_names = tegra186_supply_names,
1427 .num_supplies = ARRAY_SIZE(tegra186_supply_names),
1428 .phy_types = tegra186_phy_types,
1429 .num_types = ARRAY_SIZE(tegra186_phy_types),
1430 .ports = {
1431 .usb3 = { .offset = 0, .count = 3, },
1432 .usb2 = { .offset = 3, .count = 3, },
1433 .hsic = { .offset = 6, .count = 1, },
1434 },
1435 .scale_ss_clock = false,
1436 .has_ipfs = false,
1437 };
1438
1439 static const struct of_device_id tegra_xusb_of_match[] = {
1440 { .compatible = "nvidia,tegra124-xusb", .data = &tegra124_soc },
1441 { .compatible = "nvidia,tegra210-xusb", .data = &tegra210_soc },
1442 { .compatible = "nvidia,tegra186-xusb", .data = &tegra186_soc },
1443 { },
1444 };
1445 MODULE_DEVICE_TABLE(of, tegra_xusb_of_match);
1446
1447 static struct platform_driver tegra_xusb_driver = {
1448 .probe = tegra_xusb_probe,
1449 .remove = tegra_xusb_remove,
1450 .driver = {
1451 .name = "tegra-xusb",
1452 .pm = &tegra_xusb_pm_ops,
1453 .of_match_table = tegra_xusb_of_match,
1454 },
1455 };
1456
1457 static void tegra_xhci_quirks(struct device *dev, struct xhci_hcd *xhci)
1458 {
1459 xhci->quirks |= XHCI_PLAT;
1460 }
1461
1462 static int tegra_xhci_setup(struct usb_hcd *hcd)
1463 {
1464 return xhci_gen_setup(hcd, tegra_xhci_quirks);
1465 }
1466
1467 static const struct xhci_driver_overrides tegra_xhci_overrides __initconst = {
1468 .reset = tegra_xhci_setup,
1469 };
1470
1471 static int __init tegra_xusb_init(void)
1472 {
1473 xhci_init_driver(&tegra_xhci_hc_driver, &tegra_xhci_overrides);
1474
1475 return platform_driver_register(&tegra_xusb_driver);
1476 }
1477 module_init(tegra_xusb_init);
1478
1479 static void __exit tegra_xusb_exit(void)
1480 {
1481 platform_driver_unregister(&tegra_xusb_driver);
1482 }
1483 module_exit(tegra_xusb_exit);
1484
1485 MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
1486 MODULE_DESCRIPTION("NVIDIA Tegra XUSB xHCI host-controller driver");
1487 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support