1 ARM Broadcom STB platforms Device Tree Bindings
2 -----------------------------------------------
3 Boards with Broadcom Brahma15 ARM-based BCMxxxx (generally BCM7xxx variants)
4 SoC shall have the following DT organization:
6 Required root node properties:
7 - compatible: "brcm,bcm<chip_id>", "brcm,brcmstb"
13 model = "Broadcom STB (bcm7445)";
14 compatible = "brcm,bcm7445", "brcm,brcmstb";
16 Further, syscon nodes that map platform-specific registers used for general
17 system control is required:
19 - compatible: "brcm,bcm<chip_id>-sun-top-ctrl", "syscon"
20 - compatible: "brcm,bcm<chip_id>-hif-cpubiuctrl", "syscon"
21 - compatible: "brcm,bcm<chip_id>-hif-continuation", "syscon"
25 SoCs with Broadcom Brahma15 ARM-based CPUs have a specific Bus Interface Unit
26 (BIU) block which controls and interfaces the CPU complex to the different
27 Memory Controller Ports (MCP), one per memory controller (MEMC). This BIU block
28 offers a feature called Write Pairing which consists in collapsing two adjacent
29 cache lines into a single (bursted) write transaction towards the memory
30 controller (MEMC) to maximize write bandwidth.
34 - compatible: must be "brcm,bcm7445-hif-cpubiuctrl", "syscon"
39 Boolean property, which when present indicates that the chip
40 supports write-pairing.
46 compatible = "simple-bus";
47 ranges = <0 0x00 0xf0000000 0x1000000>;
49 sun_top_ctrl: syscon@404000 {
50 compatible = "brcm,bcm7445-sun-top-ctrl", "syscon";
51 reg = <0x404000 0x51c>;
54 hif_cpubiuctrl: syscon@3e2400 {
55 compatible = "brcm,bcm7445-hif-cpubiuctrl", "syscon";
56 reg = <0x3e2400 0x5b4>;
60 hif_continuation: syscon@452000 {
61 compatible = "brcm,bcm7445-hif-continuation", "syscon";
62 reg = <0x452000 0x100>;
66 Nodes that allow for support of SMP initialization and reboot are required:
73 The string "brcm,brcmstb-smpboot".
76 A phandle / integer array property which lets the BSP know the location
77 of certain CPU power-on registers.
79 The layout of the property is as follows:
80 o a phandle to the "hif_cpubiuctrl" syscon node
81 o offset to the base CPU power zone register
82 o offset to the base CPU reset register
85 A phandle pointing to the syscon node which describes the CPU boot
86 continuation registers.
87 o a phandle to the "hif_continuation" syscon node
91 compatible = "brcm,brcmstb-smpboot";
92 syscon-cpu = <&hif_cpubiuctrl 0x88 0x178>;
93 syscon-cont = <&hif_continuation>;
101 The string property "brcm,brcmstb-reboot" for 40nm/28nm chips with
102 the new SYS_CTRL interface, or "brcm,bcm7038-reboot" for 65nm
103 chips with the old SUN_TOP_CTRL interface.
106 A phandle / integer array that points to the syscon node which describes
107 the general system reset registers.
108 o a phandle to "sun_top_ctrl"
109 o offset to the "reset source enable" register
110 o offset to the "software master reset" register
114 compatible = "brcm,brcmstb-reboot";
115 syscon = <&sun_top_ctrl 0x304 0x308>;
123 For power management (particularly, S2/S3/S5 system suspend), the following SoC
124 components are needed:
126 = Always-On control block (AON CTRL)
128 This hardware provides control registers for the "always-on" (even in low-power
129 modes) hardware, such as the Power Management State Machine (PMSM).
132 - compatible : should contain "brcm,brcmstb-aon-ctrl"
133 - reg : the register start and length for the AON CTRL block
138 compatible = "brcm,brcmstb-aon-ctrl";
139 reg = <0x410000 0x400>;
144 A Broadcom STB SoC typically has a number of independent memory controllers,
145 each of which may have several associated hardware blocks, which are versioned
146 independently (control registers, DDR PHYs, etc.). One might consider
147 describing these controllers as a parent "memory controllers" block, which
148 contains N sub-nodes (one for each controller in the system), each of which is
149 associated with a number of hardware register resources (e.g., its PHY). See
150 the example device tree snippet below.
152 == MEMC (MEMory Controller)
154 Represents a single memory controller instance.
157 - compatible : should contain "brcm,brcmstb-memc" and "simple-bus"
159 Should contain subnodes for any of the following relevant hardware resources:
163 Control registers for this memory controller's DDR PHY.
166 - compatible : should contain one of these
167 "brcm,brcmstb-ddr-phy-v225.1"
168 "brcm,brcmstb-ddr-phy-v240.1"
169 "brcm,brcmstb-ddr-phy-v240.2"
171 - reg : the DDR PHY register range
175 Control registers for this memory controller's DDR SHIMPHY.
178 - compatible : should contain "brcm,brcmstb-ddr-shimphy-v1.0"
179 - reg : the DDR SHIMPHY register range
183 Sequencer DRAM parameters and control registers. Used for Self-Refresh
184 Power-Down (SRPD), among other things.
187 - compatible : should contain "brcm,brcmstb-memc-ddr"
188 - reg : the MEMC DDR register range
194 compatible = "simple-bus";
197 compatible = "brcm,brcmstb-memc", "simple-bus";
201 compatible = "brcm,brcmstb-ddr-phy-v240.1";
202 reg = <0xf1106000 0x21c>;
206 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
207 reg = <0xf1108000 0xe4>;
211 reg = <0xf1102000 0x800>;
212 compatible = "brcm,brcmstb-memc-ddr";
217 compatible = "brcm,brcmstb-memc", "simple-bus";
221 compatible = "brcm,brcmstb-ddr-phy-v240.1";
222 reg = <0xf1186000 0x21c>;
226 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
227 reg = <0xf1188000 0xe4>;
231 reg = <0xf1182000 0x800>;
232 compatible = "brcm,brcmstb-memc-ddr";
237 compatible = "brcm,brcmstb-memc", "simple-bus";
241 compatible = "brcm,brcmstb-ddr-phy-v240.1";
242 reg = <0xf1206000 0x21c>;
246 compatible = "brcm,brcmstb-ddr-shimphy-v1.0";
247 reg = <0xf1208000 0xe4>;
251 reg = <0xf1202000 0x800>;
252 compatible = "brcm,brcmstb-memc-ddr";