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[linux/fpc-iii.git] / Documentation / devicetree / bindings / arm / cci.txt
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1 =======================================================
2 ARM CCI cache coherent interconnect binding description
3 =======================================================
5 ARM multi-cluster systems maintain intra-cluster coherency through a
6 cache coherent interconnect (CCI) that is capable of monitoring bus
7 transactions and manage coherency, TLB invalidations and memory barriers.
9 It allows snooping and distributed virtual memory message broadcast across
10 clusters, through memory mapped interface, with a global control register
11 space and multiple sets of interface control registers, one per slave
12 interface.
14 Bindings for the CCI node follow the ePAPR standard, available from:
16 www.power.org/documentation/epapr-version-1-1/
18 with the addition of the bindings described in this document which are
19 specific to ARM.
21 * CCI interconnect node
23         Description: Describes a CCI cache coherent Interconnect component
25         Node name must be "cci".
26         Node's parent must be the root node /, and the address space visible
27         through the CCI interconnect is the same as the one seen from the
28         root node (ie from CPUs perspective as per DT standard).
29         Every CCI node has to define the following properties:
31         - compatible
32                 Usage: required
33                 Value type: <string>
34                 Definition: must contain one of the following:
35                             "arm,cci-400"
36                             "arm,cci-500"
37                             "arm,cci-550"
39         - reg
40                 Usage: required
41                 Value type: Integer cells. A register entry, expressed as a pair
42                             of cells, containing base and size.
43                 Definition: A standard property. Specifies base physical
44                             address of CCI control registers common to all
45                             interfaces.
47         - ranges:
48                 Usage: required
49                 Value type: Integer cells. An array of range entries, expressed
50                             as a tuple of cells, containing child address,
51                             parent address and the size of the region in the
52                             child address space.
53                 Definition: A standard property. Follow rules in the ePAPR for
54                             hierarchical bus addressing. CCI interfaces
55                             addresses refer to the parent node addressing
56                             scheme to declare their register bases.
58         CCI interconnect node can define the following child nodes:
60         - CCI control interface nodes
62                 Node name must be "slave-if".
63                 Parent node must be CCI interconnect node.
65                 A CCI control interface node must contain the following
66                 properties:
68                 - compatible
69                         Usage: required
70                         Value type: <string>
71                         Definition: must be set to
72                                     "arm,cci-400-ctrl-if"
74                 - interface-type:
75                         Usage: required
76                         Value type: <string>
77                         Definition: must be set to one of {"ace", "ace-lite"}
78                                     depending on the interface type the node
79                                     represents.
81                 - reg:
82                         Usage: required
83                         Value type: Integer cells. A register entry, expressed
84                                     as a pair of cells, containing base and
85                                     size.
86                         Definition: the base address and size of the
87                                     corresponding interface programming
88                                     registers.
90         - CCI PMU node
92                 Parent node must be CCI interconnect node.
94                 A CCI pmu node must contain the following properties:
96                 - compatible
97                         Usage: required
98                         Value type: <string>
99                         Definition: Must contain one of:
100                                  "arm,cci-400-pmu,r0"
101                                  "arm,cci-400-pmu,r1"
102                                  "arm,cci-400-pmu"  - DEPRECATED, permitted only where OS has
103                                                       secure acces to CCI registers
104                                  "arm,cci-500-pmu,r0"
105                                  "arm,cci-550-pmu,r0"
106                 - reg:
107                         Usage: required
108                         Value type: Integer cells. A register entry, expressed
109                                     as a pair of cells, containing base and
110                                     size.
111                         Definition: the base address and size of the
112                                     corresponding interface programming
113                                     registers.
115                 - interrupts:
116                         Usage: required
117                         Value type: Integer cells. Array of interrupt specifier
118                                     entries, as defined in
119                                     ../interrupt-controller/interrupts.txt.
120                         Definition: list of counter overflow interrupts, one per
121                                     counter. The interrupts must be specified
122                                     starting with the cycle counter overflow
123                                     interrupt, followed by counter0 overflow
124                                     interrupt, counter1 overflow interrupt,...
125                                     ,counterN overflow interrupt.
127                                     The CCI PMU has an interrupt signal for each
128                                     counter. The number of interrupts must be
129                                     equal to the number of counters.
131 * CCI interconnect bus masters
133         Description: masters in the device tree connected to a CCI port
134                      (inclusive of CPUs and their cpu nodes).
136         A CCI interconnect bus master node must contain the following
137         properties:
139         - cci-control-port:
140                 Usage: required
141                 Value type: <phandle>
142                 Definition: a phandle containing the CCI control interface node
143                             the master is connected to.
145 Example:
147         cpus {
148                 #size-cells = <0>;
149                 #address-cells = <1>;
151                 CPU0: cpu@0 {
152                         device_type = "cpu";
153                         compatible = "arm,cortex-a15";
154                         cci-control-port = <&cci_control1>;
155                         reg = <0x0>;
156                 };
158                 CPU1: cpu@1 {
159                         device_type = "cpu";
160                         compatible = "arm,cortex-a15";
161                         cci-control-port = <&cci_control1>;
162                         reg = <0x1>;
163                 };
165                 CPU2: cpu@100 {
166                         device_type = "cpu";
167                         compatible = "arm,cortex-a7";
168                         cci-control-port = <&cci_control2>;
169                         reg = <0x100>;
170                 };
172                 CPU3: cpu@101 {
173                         device_type = "cpu";
174                         compatible = "arm,cortex-a7";
175                         cci-control-port = <&cci_control2>;
176                         reg = <0x101>;
177                 };
179         };
181         dma0: dma@3000000 {
182                 compatible = "arm,pl330", "arm,primecell";
183                 cci-control-port = <&cci_control0>;
184                 reg = <0x0 0x3000000 0x0 0x1000>;
185                 interrupts = <10>;
186                 #dma-cells = <1>;
187                 #dma-channels = <8>;
188                 #dma-requests = <32>;
189         };
191         cci@2c090000 {
192                 compatible = "arm,cci-400";
193                 #address-cells = <1>;
194                 #size-cells = <1>;
195                 reg = <0x0 0x2c090000 0 0x1000>;
196                 ranges = <0x0 0x0 0x2c090000 0x10000>;
198                 cci_control0: slave-if@1000 {
199                         compatible = "arm,cci-400-ctrl-if";
200                         interface-type = "ace-lite";
201                         reg = <0x1000 0x1000>;
202                 };
204                 cci_control1: slave-if@4000 {
205                         compatible = "arm,cci-400-ctrl-if";
206                         interface-type = "ace";
207                         reg = <0x4000 0x1000>;
208                 };
210                 cci_control2: slave-if@5000 {
211                         compatible = "arm,cci-400-ctrl-if";
212                         interface-type = "ace";
213                         reg = <0x5000 0x1000>;
214                 };
216                 pmu@9000 {
217                          compatible = "arm,cci-400-pmu";
218                          reg = <0x9000 0x5000>;
219                          interrupts = <0 101 4>,
220                                       <0 102 4>,
221                                       <0 103 4>,
222                                       <0 104 4>,
223                                       <0 105 4>;
224                 };
225         };
227 This CCI node corresponds to a CCI component whose control registers sits
228 at address 0x000000002c090000.
229 CCI slave interface @0x000000002c091000 is connected to dma controller dma0.
230 CCI slave interface @0x000000002c094000 is connected to CPUs {CPU0, CPU1};
231 CCI slave interface @0x000000002c095000 is connected to CPUs {CPU2, CPU3};