1 * CoreSight Components:
3 CoreSight components are compliant with the ARM CoreSight architecture
4 specification and can be connected in various topologies to suit a particular
5 SoCs tracing needs. These trace components can generally be classified as
6 sinks, links and sources. Trace data produced by one or more sources flows
7 through the intermediate links connecting the source to the currently selected
8 sink. Each CoreSight component device should use these properties to describe
9 its hardware characteristcs.
11 * Required properties for all components *except* non-configurable replicators:
13 * compatible: These have to be supplemented with "arm,primecell" as
14 drivers are using the AMBA bus interface. Possible values include:
15 - "arm,coresight-etb10", "arm,primecell";
16 - "arm,coresight-tpiu", "arm,primecell";
17 - "arm,coresight-tmc", "arm,primecell";
18 - "arm,coresight-funnel", "arm,primecell";
19 - "arm,coresight-etm3x", "arm,primecell";
20 - "arm,coresight-etm4x", "arm,primecell";
21 - "qcom,coresight-replicator1x", "arm,primecell";
23 * reg: physical base address and length of the register
24 set(s) of the component.
26 * clocks: the clocks associated to this component.
28 * clock-names: the name of the clocks referenced by the code.
29 Since we are using the AMBA framework, the name of the clock
30 providing the interconnect should be "apb_pclk", and some
31 coresight blocks also have an additional clock "atclk", which
32 clocks the core of that coresight component. The latter clock
35 * port or ports: The representation of the component's port
36 layout using the generic DT graph presentation found in
39 * Required properties for devices that don't show up on the AMBA bus, such as
40 non-configurable replicators:
42 * compatible: Currently supported value is (note the absence of the
44 - "arm,coresight-replicator"
46 * port or ports: same as above.
48 * Optional properties for ETM/PTMs:
50 * arm,cp14: must be present if the system accesses ETM/PTM management
51 registers via co-processor 14.
53 * cpu: the cpu phandle this ETM/PTM is affined to. When omitted the
54 source is considered to belong to CPU0.
56 * Optional property for TMC:
58 * arm,buffer-size: size of contiguous buffer space for TMC ETR
59 (embedded trace router)
66 compatible = "arm,coresight-etb10", "arm,primecell";
67 reg = <0 0x20010000 0 0x1000>;
70 clock-names = "apb_pclk";
72 etb_in_port: endpoint@0 {
74 remote-endpoint = <&replicator_out_port0>;
80 compatible = "arm,coresight-tpiu", "arm,primecell";
81 reg = <0 0x20030000 0 0x1000>;
84 clock-names = "apb_pclk";
86 tpiu_in_port: endpoint@0 {
88 remote-endpoint = <&replicator_out_port1>;
95 /* non-configurable replicators don't show up on the
96 * AMBA bus. As such no need to add "arm,primecell".
98 compatible = "arm,coresight-replicator";
101 #address-cells = <1>;
104 /* replicator output ports */
107 replicator_out_port0: endpoint {
108 remote-endpoint = <&etb_in_port>;
114 replicator_out_port1: endpoint {
115 remote-endpoint = <&tpiu_in_port>;
119 /* replicator input port */
122 replicator_in_port0: endpoint {
124 remote-endpoint = <&funnel_out_port0>;
131 compatible = "arm,coresight-funnel", "arm,primecell";
132 reg = <0 0x20040000 0 0x1000>;
134 clocks = <&oscclk6a>;
135 clock-names = "apb_pclk";
137 #address-cells = <1>;
140 /* funnel output port */
143 funnel_out_port0: endpoint {
145 <&replicator_in_port0>;
149 /* funnel input ports */
152 funnel_in_port0: endpoint {
154 remote-endpoint = <&ptm0_out_port>;
160 funnel_in_port1: endpoint {
162 remote-endpoint = <&ptm1_out_port>;
168 funnel_in_port2: endpoint {
170 remote-endpoint = <&etm0_out_port>;
179 compatible = "arm,coresight-etm3x", "arm,primecell";
180 reg = <0 0x2201c000 0 0x1000>;
183 clocks = <&oscclk6a>;
184 clock-names = "apb_pclk";
186 ptm0_out_port: endpoint {
187 remote-endpoint = <&funnel_in_port0>;
193 compatible = "arm,coresight-etm3x", "arm,primecell";
194 reg = <0 0x2201d000 0 0x1000>;
197 clocks = <&oscclk6a>;
198 clock-names = "apb_pclk";
200 ptm1_out_port: endpoint {
201 remote-endpoint = <&funnel_in_port1>;