1 Device-Tree bindings for Samsung SoC display controller (FIMD)
3 FIMD (Fully Interactive Mobile Display) is the Display Controller for the
4 Samsung series of SoCs which transfers the image data from a video memory
5 buffer to an external LCD interface.
8 - compatible: value should be one of the following
9 "samsung,s3c2443-fimd"; /* for S3C24XX SoCs */
10 "samsung,s3c6400-fimd"; /* for S3C64XX SoCs */
11 "samsung,s5pv210-fimd"; /* for S5PV210 SoC */
12 "samsung,exynos3250-fimd"; /* for Exynos3250/3472 SoCs */
13 "samsung,exynos4210-fimd"; /* for Exynos4 SoCs */
14 "samsung,exynos4415-fimd"; /* for Exynos4415 SoC */
15 "samsung,exynos5250-fimd"; /* for Exynos5250 SoCs */
16 "samsung,exynos5420-fimd"; /* for Exynos5420/5422/5800 SoCs */
18 - reg: physical base address and length of the FIMD registers set.
20 - interrupt-parent: should be the phandle of the fimd controller's
21 parent interrupt controller.
23 - interrupts: should contain a list of all FIMD IP block interrupts in the
24 order: FIFO Level, VSYNC, LCD_SYSTEM. The interrupt specifier
25 format depends on the interrupt controller used.
27 - interrupt-names: should contain the interrupt names: "fifo", "vsync",
28 "lcd_sys", in the same order as they were listed in the interrupts
31 - pinctrl-0: pin control group to be used for this controller.
33 - pinctrl-names: must contain a "default" entry.
35 - clocks: must include clock specifiers corresponding to entries in the
38 - clock-names: list of clock names sorted in the same order as the clocks
39 property. Must contain "sclk_fimd" and "fimd".
42 - power-domains: a phandle to FIMD power domain node.
43 - samsung,invert-vden: video enable signal is inverted
44 - samsung,invert-vclk: video clock signal is inverted
45 - display-timings: timing settings for FIMD, as described in document [1].
46 Can be used in case timings cannot be provided otherwise
47 or to override timings provided by the panel.
48 - samsung,sysreg: handle to syscon used to control the system registers
49 - i80-if-timings: timing configuration for lcd i80 interface support.
50 - cs-setup: clock cycles for the active period of address signal is enabled
51 until chip select is enabled.
52 If not specified, the default value(0) will be used.
53 - wr-setup: clock cycles for the active period of CS signal is enabled until
54 write signal is enabled.
55 If not specified, the default value(0) will be used.
56 - wr-active: clock cycles for the active period of CS is enabled.
57 If not specified, the default value(1) will be used.
58 - wr-hold: clock cycles for the active period of CS is disabled until write
60 If not specified, the default value(0) will be used.
62 The parameters are defined as:
64 VCLK(internal) __|??????|_____|??????|_____|??????|_____|??????|_____|??
66 Address Output --:<XXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XXXXXXXXXXXX:XX
69 Chip Select ???????????????|____________:____________:____________|??
70 | wr-setup+1 | | wr-hold+1 |
71 |<---------->| |<---------->|
72 Write Enable ????????????????????????????|____________|???????????????
75 Video Data ----------------------------<XXXXXXXXXXXXXXXXXXXXXXXXX>--
77 The device node can contain 'port' child nodes according to the bindings defined
78 in [2]. The following are properties specific to those nodes:
79 - reg: (required) port index, can be:
83 3 - for parallel output,
84 4 - for write-back interface
86 [1]: Documentation/devicetree/bindings/display/display-timing.txt
87 [2]: Documentation/devicetree/bindings/media/video-interfaces.txt
91 SoC specific DT entry:
94 compatible = "samsung,exynos4210-fimd";
95 interrupt-parent = <&combiner>;
96 reg = <0x11c00000 0x20000>;
97 interrupt-names = "fifo", "vsync", "lcd_sys";
98 interrupts = <11 0>, <11 1>, <11 2>;
99 clocks = <&clock 140>, <&clock 283>;
100 clock-names = "sclk_fimd", "fimd";
101 power-domains = <&pd_lcd0>;
105 Board specific DT entry:
108 pinctrl-0 = <&lcd_clk &lcd_data24 &pwm1_out>;
109 pinctrl-names = "default";