1 Integrated Flash Controller
5 - compatible : should contain "fsl,ifc". The version of the integrated
6 flash controller can be found in the IFC_REV register at
9 - #address-cells : Should be either two or three. The first cell is the
10 chipselect number, and the remaining cells are the
11 offset into the chipselect.
12 - #size-cells : Either one or two, depending on how large each chipselect
14 - reg : Offset and length of the register set for the device
15 - interrupts: IFC may have one or two interrupts. If two interrupt
16 specifiers are present, the first is the "common"
17 interrupt (CM_EVTER_STAT), and the second is the NAND
18 interrupt (NAND_EVTER_STAT). If there is only one,
19 that interrupt reports both types of event.
21 - little-endian : If this property is absent, the big-endian mode will
22 be in use as default for registers.
24 - ranges : Each range corresponds to a single chipselect, and covers
25 the entire access window as configured.
27 Child device nodes describe the devices connected to IFC such as NOR (e.g.
28 cfi-flash) and NAND (fsl,ifc-nand). There might be board specific devices
29 like FPGAs, CPLDs, etc.
34 compatible = "fsl,ifc", "simple-bus";
37 reg = <0x0 0xffe1e000 0 0x2000>;
38 interrupts = <16 2 19 2>;
41 /* NOR, NAND Flashes and CPLD on board */
42 ranges = <0x0 0x0 0x0 0xee000000 0x02000000
43 0x1 0x0 0x0 0xffa00000 0x00010000
44 0x3 0x0 0x0 0xffb00000 0x00020000>;
49 compatible = "cfi-flash";
50 reg = <0x0 0x0 0x2000000>;
55 /* 32MB for user data */
56 reg = <0x0 0x02000000>;
64 compatible = "fsl,ifc-nand";
65 reg = <0x1 0x0 0x10000>;
68 /* This location must not be altered */
69 /* 1MB for u-boot Bootloader Image */
70 reg = <0x0 0x00100000>;
71 label = "NAND U-Boot Image";
79 compatible = "fsl,p1010rdb-cpld";
80 reg = <0x3 0x0 0x000001f>;