| blob | b59c625d63362e8e4044215adb24860ef3b1e96a |
1 NVIDIA Tegra124 SoC EMC (external memory controller)
2 ====================================================
4 Required properties :
5 - compatible : Should be "nvidia,tegra124-emc".
6 - reg : physical base address and length of the controller's registers.
7 - nvidia,memory-controller : phandle of the MC driver.
9 The node should contain a "emc-timings" subnode for each supported RAM type
10 (see field RAM_CODE in register PMC_STRAPPING_OPT_A), with its unit address
11 being its RAM_CODE.
13 Required properties for "emc-timings" nodes :
14 - nvidia,ram-code : Should contain the value of RAM_CODE this timing set is
15 used for.
17 Each "emc-timings" node should contain a "timing" subnode for every supported
18 EMC clock rate. The "timing" subnodes should have the clock rate in Hz as
19 their unit address.
21 Required properties for "timing" nodes :
22 - clock-frequency : Should contain the memory clock rate in Hz.
23 - The following properties contain EMC timing characterization values
24 (specified in the board documentation) :
25 - nvidia,emc-auto-cal-config : EMC_AUTO_CAL_CONFIG
26 - nvidia,emc-auto-cal-config2 : EMC_AUTO_CAL_CONFIG2
27 - nvidia,emc-auto-cal-config3 : EMC_AUTO_CAL_CONFIG3
28 - nvidia,emc-auto-cal-interval : EMC_AUTO_CAL_INTERVAL
29 - nvidia,emc-bgbias-ctl0 : EMC_BGBIAS_CTL0
30 - nvidia,emc-cfg : EMC_CFG
31 - nvidia,emc-cfg-2 : EMC_CFG_2
32 - nvidia,emc-ctt-term-ctrl : EMC_CTT_TERM_CTRL
33 - nvidia,emc-mode-1 : Mode Register 1
34 - nvidia,emc-mode-2 : Mode Register 2
35 - nvidia,emc-mode-4 : Mode Register 4
36 - nvidia,emc-mode-reset : Mode Register 0
37 - nvidia,emc-mrs-wait-cnt : EMC_MRS_WAIT_CNT
38 - nvidia,emc-sel-dpd-ctrl : EMC_SEL_DPD_CTRL
39 - nvidia,emc-xm2dqspadctrl2 : EMC_XM2DQSPADCTRL2
40 - nvidia,emc-zcal-cnt-long : EMC_ZCAL_WAIT_CNT after clock change
41 - nvidia,emc-zcal-interval : EMC_ZCAL_INTERVAL
42 - nvidia,emc-configuration : EMC timing characterization data. These are the
43 registers (see section "15.6.2 EMC Registers" in the TRM) whose values need to
44 be specified, according to the board documentation:
46 EMC_RC
47 EMC_RFC
48 EMC_RFC_SLR
49 EMC_RAS
50 EMC_RP
51 EMC_R2W
52 EMC_W2R
53 EMC_R2P
54 EMC_W2P
55 EMC_RD_RCD
56 EMC_WR_RCD
57 EMC_RRD
58 EMC_REXT
59 EMC_WEXT
60 EMC_WDV
61 EMC_WDV_MASK
62 EMC_QUSE
63 EMC_QUSE_WIDTH
64 EMC_IBDLY
65 EMC_EINPUT
66 EMC_EINPUT_DURATION
67 EMC_PUTERM_EXTRA
68 EMC_PUTERM_WIDTH
69 EMC_PUTERM_ADJ
70 EMC_CDB_CNTL_1
71 EMC_CDB_CNTL_2
72 EMC_CDB_CNTL_3
73 EMC_QRST
74 EMC_QSAFE
75 EMC_RDV
76 EMC_RDV_MASK
77 EMC_REFRESH
78 EMC_BURST_REFRESH_NUM
79 EMC_PRE_REFRESH_REQ_CNT
80 EMC_PDEX2WR
81 EMC_PDEX2RD
82 EMC_PCHG2PDEN
83 EMC_ACT2PDEN
84 EMC_AR2PDEN
85 EMC_RW2PDEN
86 EMC_TXSR
87 EMC_TXSRDLL
88 EMC_TCKE
89 EMC_TCKESR
90 EMC_TPD
91 EMC_TFAW
92 EMC_TRPAB
93 EMC_TCLKSTABLE
94 EMC_TCLKSTOP
95 EMC_TREFBW
96 EMC_FBIO_CFG6
97 EMC_ODT_WRITE
98 EMC_ODT_READ
99 EMC_FBIO_CFG5
100 EMC_CFG_DIG_DLL
101 EMC_CFG_DIG_DLL_PERIOD
102 EMC_DLL_XFORM_DQS0
103 EMC_DLL_XFORM_DQS1
104 EMC_DLL_XFORM_DQS2
105 EMC_DLL_XFORM_DQS3
106 EMC_DLL_XFORM_DQS4
107 EMC_DLL_XFORM_DQS5
108 EMC_DLL_XFORM_DQS6
109 EMC_DLL_XFORM_DQS7
110 EMC_DLL_XFORM_DQS8
111 EMC_DLL_XFORM_DQS9
112 EMC_DLL_XFORM_DQS10
113 EMC_DLL_XFORM_DQS11
114 EMC_DLL_XFORM_DQS12
115 EMC_DLL_XFORM_DQS13
116 EMC_DLL_XFORM_DQS14
117 EMC_DLL_XFORM_DQS15
118 EMC_DLL_XFORM_QUSE0
119 EMC_DLL_XFORM_QUSE1
120 EMC_DLL_XFORM_QUSE2
121 EMC_DLL_XFORM_QUSE3
122 EMC_DLL_XFORM_QUSE4
123 EMC_DLL_XFORM_QUSE5
124 EMC_DLL_XFORM_QUSE6
125 EMC_DLL_XFORM_QUSE7
126 EMC_DLL_XFORM_ADDR0
127 EMC_DLL_XFORM_ADDR1
128 EMC_DLL_XFORM_ADDR2
129 EMC_DLL_XFORM_ADDR3
130 EMC_DLL_XFORM_ADDR4
131 EMC_DLL_XFORM_ADDR5
132 EMC_DLL_XFORM_QUSE8
133 EMC_DLL_XFORM_QUSE9
134 EMC_DLL_XFORM_QUSE10
135 EMC_DLL_XFORM_QUSE11
136 EMC_DLL_XFORM_QUSE12
137 EMC_DLL_XFORM_QUSE13
138 EMC_DLL_XFORM_QUSE14
139 EMC_DLL_XFORM_QUSE15
140 EMC_DLI_TRIM_TXDQS0
141 EMC_DLI_TRIM_TXDQS1
142 EMC_DLI_TRIM_TXDQS2
143 EMC_DLI_TRIM_TXDQS3
144 EMC_DLI_TRIM_TXDQS4
145 EMC_DLI_TRIM_TXDQS5
146 EMC_DLI_TRIM_TXDQS6
147 EMC_DLI_TRIM_TXDQS7
148 EMC_DLI_TRIM_TXDQS8
149 EMC_DLI_TRIM_TXDQS9
150 EMC_DLI_TRIM_TXDQS10
151 EMC_DLI_TRIM_TXDQS11
152 EMC_DLI_TRIM_TXDQS12
153 EMC_DLI_TRIM_TXDQS13
154 EMC_DLI_TRIM_TXDQS14
155 EMC_DLI_TRIM_TXDQS15
156 EMC_DLL_XFORM_DQ0
157 EMC_DLL_XFORM_DQ1
158 EMC_DLL_XFORM_DQ2
159 EMC_DLL_XFORM_DQ3
160 EMC_DLL_XFORM_DQ4
161 EMC_DLL_XFORM_DQ5
162 EMC_DLL_XFORM_DQ6
163 EMC_DLL_XFORM_DQ7
164 EMC_XM2CMDPADCTRL
165 EMC_XM2CMDPADCTRL4
166 EMC_XM2CMDPADCTRL5
167 EMC_XM2DQPADCTRL2
168 EMC_XM2DQPADCTRL3
169 EMC_XM2CLKPADCTRL
170 EMC_XM2CLKPADCTRL2
171 EMC_XM2COMPPADCTRL
172 EMC_XM2VTTGENPADCTRL
173 EMC_XM2VTTGENPADCTRL2
174 EMC_XM2VTTGENPADCTRL3
175 EMC_XM2DQSPADCTRL3
176 EMC_XM2DQSPADCTRL4
177 EMC_XM2DQSPADCTRL5
178 EMC_XM2DQSPADCTRL6
179 EMC_DSR_VTTGEN_DRV
180 EMC_TXDSRVTTGEN
181 EMC_FBIO_SPARE
182 EMC_ZCAL_WAIT_CNT
183 EMC_MRS_WAIT_CNT2
184 EMC_CTT
185 EMC_CTT_DURATION
186 EMC_CFG_PIPE
187 EMC_DYN_SELF_REF_CONTROL
188 EMC_QPOP
190 Example SoC include file:
192 / {
193 emc@0,7001b000 {
194 compatible = "nvidia,tegra124-emc";
195 reg = <0x0 0x7001b000 0x0 0x1000>;
197 nvidia,memory-controller = <&mc>;
198 };
199 };
201 Example board file:
203 / {
204 emc@0,7001b000 {
205 emc-timings-3 {
206 nvidia,ram-code = <3>;
208 timing-12750000 {
209 clock-frequency = <12750000>;
211 nvidia,emc-zcal-cnt-long = <0x00000042>;
212 nvidia,emc-auto-cal-interval = <0x001fffff>;
213 nvidia,emc-ctt-term-ctrl = <0x00000802>;
214 nvidia,emc-cfg = <0x73240000>;
215 nvidia,emc-cfg-2 = <0x000008c5>;
216 nvidia,emc-sel-dpd-ctrl = <0x00040128>;
217 nvidia,emc-bgbias-ctl0 = <0x00000008>;
218 nvidia,emc-auto-cal-config = <0xa1430000>;
219 nvidia,emc-auto-cal-config2 = <0x00000000>;
220 nvidia,emc-auto-cal-config3 = <0x00000000>;
221 nvidia,emc-mode-reset = <0x80001221>;
222 nvidia,emc-mode-1 = <0x80100003>;
223 nvidia,emc-mode-2 = <0x80200008>;
224 nvidia,emc-mode-4 = <0x00000000>;
226 nvidia,emc-configuration = <
227 0x00000000 /* EMC_RC */
228 0x00000003 /* EMC_RFC */
229 0x00000000 /* EMC_RFC_SLR */
230 0x00000000 /* EMC_RAS */
231 0x00000000 /* EMC_RP */
232 0x00000004 /* EMC_R2W */
233 0x0000000a /* EMC_W2R */
234 0x00000003 /* EMC_R2P */
235 0x0000000b /* EMC_W2P */
236 0x00000000 /* EMC_RD_RCD */
237 0x00000000 /* EMC_WR_RCD */
238 0x00000003 /* EMC_RRD */
239 0x00000003 /* EMC_REXT */
240 0x00000000 /* EMC_WEXT */
241 0x00000006 /* EMC_WDV */
242 0x00000006 /* EMC_WDV_MASK */
243 0x00000006 /* EMC_QUSE */
244 0x00000002 /* EMC_QUSE_WIDTH */
245 0x00000000 /* EMC_IBDLY */
246 0x00000005 /* EMC_EINPUT */
247 0x00000005 /* EMC_EINPUT_DURATION */
248 0x00010000 /* EMC_PUTERM_EXTRA */
249 0x00000003 /* EMC_PUTERM_WIDTH */
250 0x00000000 /* EMC_PUTERM_ADJ */
251 0x00000000 /* EMC_CDB_CNTL_1 */
252 0x00000000 /* EMC_CDB_CNTL_2 */
253 0x00000000 /* EMC_CDB_CNTL_3 */
254 0x00000004 /* EMC_QRST */
255 0x0000000c /* EMC_QSAFE */
256 0x0000000d /* EMC_RDV */
257 0x0000000f /* EMC_RDV_MASK */
258 0x00000060 /* EMC_REFRESH */
259 0x00000000 /* EMC_BURST_REFRESH_NUM */
260 0x00000018 /* EMC_PRE_REFRESH_REQ_CNT */
261 0x00000002 /* EMC_PDEX2WR */
262 0x00000002 /* EMC_PDEX2RD */
263 0x00000001 /* EMC_PCHG2PDEN */
264 0x00000000 /* EMC_ACT2PDEN */
265 0x00000007 /* EMC_AR2PDEN */
266 0x0000000f /* EMC_RW2PDEN */
267 0x00000005 /* EMC_TXSR */
268 0x00000005 /* EMC_TXSRDLL */
269 0x00000004 /* EMC_TCKE */
270 0x00000005 /* EMC_TCKESR */
271 0x00000004 /* EMC_TPD */
272 0x00000000 /* EMC_TFAW */
273 0x00000000 /* EMC_TRPAB */
274 0x00000005 /* EMC_TCLKSTABLE */
275 0x00000005 /* EMC_TCLKSTOP */
276 0x00000064 /* EMC_TREFBW */
277 0x00000000 /* EMC_FBIO_CFG6 */
278 0x00000000 /* EMC_ODT_WRITE */
279 0x00000000 /* EMC_ODT_READ */
280 0x106aa298 /* EMC_FBIO_CFG5 */
281 0x002c00a0 /* EMC_CFG_DIG_DLL */
282 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */
283 0x00064000 /* EMC_DLL_XFORM_DQS0 */
284 0x00064000 /* EMC_DLL_XFORM_DQS1 */
285 0x00064000 /* EMC_DLL_XFORM_DQS2 */
286 0x00064000 /* EMC_DLL_XFORM_DQS3 */
287 0x00064000 /* EMC_DLL_XFORM_DQS4 */
288 0x00064000 /* EMC_DLL_XFORM_DQS5 */
289 0x00064000 /* EMC_DLL_XFORM_DQS6 */
290 0x00064000 /* EMC_DLL_XFORM_DQS7 */
291 0x00064000 /* EMC_DLL_XFORM_DQS8 */
292 0x00064000 /* EMC_DLL_XFORM_DQS9 */
293 0x00064000 /* EMC_DLL_XFORM_DQS10 */
294 0x00064000 /* EMC_DLL_XFORM_DQS11 */
295 0x00064000 /* EMC_DLL_XFORM_DQS12 */
296 0x00064000 /* EMC_DLL_XFORM_DQS13 */
297 0x00064000 /* EMC_DLL_XFORM_DQS14 */
298 0x00064000 /* EMC_DLL_XFORM_DQS15 */
299 0x00000000 /* EMC_DLL_XFORM_QUSE0 */
300 0x00000000 /* EMC_DLL_XFORM_QUSE1 */
301 0x00000000 /* EMC_DLL_XFORM_QUSE2 */
302 0x00000000 /* EMC_DLL_XFORM_QUSE3 */
303 0x00000000 /* EMC_DLL_XFORM_QUSE4 */
304 0x00000000 /* EMC_DLL_XFORM_QUSE5 */
305 0x00000000 /* EMC_DLL_XFORM_QUSE6 */
306 0x00000000 /* EMC_DLL_XFORM_QUSE7 */
307 0x00000000 /* EMC_DLL_XFORM_ADDR0 */
308 0x00000000 /* EMC_DLL_XFORM_ADDR1 */
309 0x00000000 /* EMC_DLL_XFORM_ADDR2 */
310 0x00000000 /* EMC_DLL_XFORM_ADDR3 */
311 0x00000000 /* EMC_DLL_XFORM_ADDR4 */
312 0x00000000 /* EMC_DLL_XFORM_ADDR5 */
313 0x00000000 /* EMC_DLL_XFORM_QUSE8 */
314 0x00000000 /* EMC_DLL_XFORM_QUSE9 */
315 0x00000000 /* EMC_DLL_XFORM_QUSE10 */
316 0x00000000 /* EMC_DLL_XFORM_QUSE11 */
317 0x00000000 /* EMC_DLL_XFORM_QUSE12 */
318 0x00000000 /* EMC_DLL_XFORM_QUSE13 */
319 0x00000000 /* EMC_DLL_XFORM_QUSE14 */
320 0x00000000 /* EMC_DLL_XFORM_QUSE15 */
321 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */
322 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */
323 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */
324 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */
325 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */
326 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */
327 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */
328 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */
329 0x00000000 /* EMC_DLI_TRIM_TXDQS8 */
330 0x00000000 /* EMC_DLI_TRIM_TXDQS9 */
331 0x00000000 /* EMC_DLI_TRIM_TXDQS10 */
332 0x00000000 /* EMC_DLI_TRIM_TXDQS11 */
333 0x00000000 /* EMC_DLI_TRIM_TXDQS12 */
334 0x00000000 /* EMC_DLI_TRIM_TXDQS13 */
335 0x00000000 /* EMC_DLI_TRIM_TXDQS14 */
336 0x00000000 /* EMC_DLI_TRIM_TXDQS15 */
337 0x000fc000 /* EMC_DLL_XFORM_DQ0 */
338 0x000fc000 /* EMC_DLL_XFORM_DQ1 */
339 0x000fc000 /* EMC_DLL_XFORM_DQ2 */
340 0x000fc000 /* EMC_DLL_XFORM_DQ3 */
341 0x0000fc00 /* EMC_DLL_XFORM_DQ4 */
342 0x0000fc00 /* EMC_DLL_XFORM_DQ5 */
343 0x0000fc00 /* EMC_DLL_XFORM_DQ6 */
344 0x0000fc00 /* EMC_DLL_XFORM_DQ7 */
345 0x10000280 /* EMC_XM2CMDPADCTRL */
346 0x00000000 /* EMC_XM2CMDPADCTRL4 */
347 0x00111111 /* EMC_XM2CMDPADCTRL5 */
348 0x00000000 /* EMC_XM2DQPADCTRL2 */
349 0x00000000 /* EMC_XM2DQPADCTRL3 */
350 0x77ffc081 /* EMC_XM2CLKPADCTRL */
351 0x00000e0e /* EMC_XM2CLKPADCTRL2 */
352 0x81f1f108 /* EMC_XM2COMPPADCTRL */
353 0x07070004 /* EMC_XM2VTTGENPADCTRL */
354 0x0000003f /* EMC_XM2VTTGENPADCTRL2 */
355 0x016eeeee /* EMC_XM2VTTGENPADCTRL3 */
356 0x51451400 /* EMC_XM2DQSPADCTRL3 */
357 0x00514514 /* EMC_XM2DQSPADCTRL4 */
358 0x00514514 /* EMC_XM2DQSPADCTRL5 */
359 0x51451400 /* EMC_XM2DQSPADCTRL6 */
360 0x0000003f /* EMC_DSR_VTTGEN_DRV */
361 0x00000007 /* EMC_TXDSRVTTGEN */
362 0x00000000 /* EMC_FBIO_SPARE */
363 0x00000042 /* EMC_ZCAL_WAIT_CNT */
364 0x000e000e /* EMC_MRS_WAIT_CNT2 */
365 0x00000000 /* EMC_CTT */
366 0x00000003 /* EMC_CTT_DURATION */
367 0x0000f2f3 /* EMC_CFG_PIPE */
368 0x800001c5 /* EMC_DYN_SELF_REF_CONTROL */
369 0x0000000a /* EMC_QPOP */
370 >;
371 };
372 };
373 };
374 };