1 Qualcomm Shared Memory State Machine
3 The Shared Memory State Machine facilitates broadcasting of single bit state
4 information between the processors in a Qualcomm SoC. Each processor is
5 assigned 32 bits of state that can be modified. A processor can through a
6 matrix of bitmaps signal subscription of notifications upon changes to a
7 certain bit owned by a certain remote processor.
12 Definition: must be one of:
17 Value type: <prop-encoded-array>
18 Definition: three entries specifying the outgoing ipc bit used for
19 signaling the N:th remote processor
20 - phandle to a syscon node representing the apcs registers
21 - u32 representing offset to the register within the syscon
22 - u32 representing the ipc bit within the register
27 Definition: identifier of the local processor in the list of hosts, or
28 in other words specifier of the column in the subscription
29 matrix representing the local processor
43 Each processor's state bits are described by a subnode of the smsm device node.
44 Nodes can either be flagged as an interrupt-controller to denote a remote
45 processor's state bits or the local processors bits. The node names are not
51 Definition: specifies the offset, in words, of the first bit for this
55 Usage: required for local entry
57 Definition: must be 1 - denotes bit number
59 - interrupt-controller:
60 Usage: required for remote entries
62 Definition: marks the entry as a interrupt-controller and the state bits
63 to belong to a remote processor
66 Usage: required for remote entries
68 Definition: must be 2 - denotes bit number and IRQ flags
71 Usage: required for remote entries
72 Value type: <prop-encoded-array>
73 Definition: one entry specifying remote IRQ used by the remote processor
74 to signal changes of its state bits
78 The following example shows the SMEM setup for controlling properties of the
79 wireless processor, defined from the 8974 apps processor's point-of-view. It
80 encompasses one outbound entry and the outgoing interrupt for the wireless
84 compatible = "qcom,smsm";
89 qcom,ipc-3 = <&apcs 8 19>;
94 #qcom,state-cells = <1>;
99 interrupts = <0 144 1>;
101 interrupt-controller;
102 #interrupt-cells = <2>;