Documentation/devicetree/bindings/thermal/qoriq-thermal.txt

   1 * Thermal Monitoring Unit (TMU) on Freescale QorIQ SoCs
   2
   3 Required properties:
   4 - compatible : Must include "fsl,qoriq-tmu". The version of the device is
   5         determined by the TMU IP Block Revision Register (IPBRR0) at
   6         offset 0x0BF8.
   7         Table of correspondences between IPBRR0 values and example  chips:
   8                 Value           Device
   9                 ----------      -----
  10                 0x01900102      T1040
  11 - reg : Address range of TMU registers.
  12 - interrupts : Contains the interrupt for TMU.
  13 - fsl,tmu-range : The values to be programmed into TTRnCR, as specified by
  14         the SoC reference manual. The first cell is TTR0CR, the second is
  15         TTR1CR, etc.
  16 - fsl,tmu-calibration : A list of cell pairs containing temperature
  17         calibration data, as specified by the SoC reference manual.
  18         The first cell of each pair is the value to be written to TTCFGR,
  19         and the second is the value to be written to TSCFGR.
  20
  21 Example:
  22
  23 tmu@f0000 {
  24         compatible = "fsl,qoriq-tmu";
  25         reg = <0xf0000 0x1000>;
  26         interrupts = <18 2 0 0>;
  27         fsl,tmu-range = <0x000a0000 0x00090026 0x0008004a 0x0001006a>;
  28         fsl,tmu-calibration = <0x00000000 0x00000025
  29                                0x00000001 0x00000028
  30                                0x00000002 0x0000002d
  31                                0x00000003 0x00000031
  32                                0x00000004 0x00000036
  33                                0x00000005 0x0000003a
  34                                0x00000006 0x00000040
  35                                0x00000007 0x00000044
  36                                0x00000008 0x0000004a
  37                                0x00000009 0x0000004f
  38                                0x0000000a 0x00000054
  39
  40                                0x00010000 0x0000000d
  41                                0x00010001 0x00000013
  42                                0x00010002 0x00000019
  43                                0x00010003 0x0000001f
  44                                0x00010004 0x00000025
  45                                0x00010005 0x0000002d
  46                                0x00010006 0x00000033
  47                                0x00010007 0x00000043
  48                                0x00010008 0x0000004b
  49                                0x00010009 0x00000053
  50
  51                                0x00020000 0x00000010
  52                                0x00020001 0x00000017
  53                                0x00020002 0x0000001f
  54                                0x00020003 0x00000029
  55                                0x00020004 0x00000031
  56                                0x00020005 0x0000003c
  57                                0x00020006 0x00000042
  58                                0x00020007 0x0000004d
  59                                0x00020008 0x00000056
  60
  61                                0x00030000 0x00000012
  62                                0x00030001 0x0000001d>;
  63 };