drivers/gpio/gpio-brcmstb.c

   1 /*
   2  * Copyright (C) 2015 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License as
   6  * published by the Free Software Foundation version 2.
   7  *
   8  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
   9  * kind, whether express or implied; without even the implied warranty
  10  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  11  * GNU General Public License for more details.
  12  */
  13
  14 #include <linux/bitops.h>
  15 #include <linux/gpio/driver.h>
  16 #include <linux/of_device.h>
  17 #include <linux/of_irq.h>
  18 #include <linux/module.h>
  19 #include <linux/irqdomain.h>
  20 #include <linux/irqchip/chained_irq.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/reboot.h>
  23
  24 #define GIO_BANK_SIZE           0x20
  25 #define GIO_ODEN(bank)          (((bank) * GIO_BANK_SIZE) + 0x00)
  26 #define GIO_DATA(bank)          (((bank) * GIO_BANK_SIZE) + 0x04)
  27 #define GIO_IODIR(bank)         (((bank) * GIO_BANK_SIZE) + 0x08)
  28 #define GIO_EC(bank)            (((bank) * GIO_BANK_SIZE) + 0x0c)
  29 #define GIO_EI(bank)            (((bank) * GIO_BANK_SIZE) + 0x10)
  30 #define GIO_MASK(bank)          (((bank) * GIO_BANK_SIZE) + 0x14)
  31 #define GIO_LEVEL(bank)         (((bank) * GIO_BANK_SIZE) + 0x18)
  32 #define GIO_STAT(bank)          (((bank) * GIO_BANK_SIZE) + 0x1c)
  33
  34 struct brcmstb_gpio_bank {
  35         struct list_head node;
  36         int id;
  37         struct gpio_chip gc;
  38         struct brcmstb_gpio_priv *parent_priv;
  39         u32 width;
  40         struct irq_chip irq_chip;
  41 };
  42
  43 struct brcmstb_gpio_priv {
  44         struct list_head bank_list;
  45         void __iomem *reg_base;
  46         struct platform_device *pdev;
  47         int parent_irq;
  48         int gpio_base;
  49         bool can_wake;
  50         int parent_wake_irq;
  51         struct notifier_block reboot_notifier;
  52 };
  53
  54 #define MAX_GPIO_PER_BANK           32
  55 #define GPIO_BANK(gpio)         ((gpio) >> 5)
  56 /* assumes MAX_GPIO_PER_BANK is a multiple of 2 */
  57 #define GPIO_BIT(gpio)          ((gpio) & (MAX_GPIO_PER_BANK - 1))
  58
  59 static inline struct brcmstb_gpio_priv *
  60 brcmstb_gpio_gc_to_priv(struct gpio_chip *gc)
  61 {
  62         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  63         return bank->parent_priv;
  64 }
  65
  66 static void brcmstb_gpio_set_imask(struct brcmstb_gpio_bank *bank,
  67                 unsigned int offset, bool enable)
  68 {
  69         struct gpio_chip *gc = &bank->gc;
  70         struct brcmstb_gpio_priv *priv = bank->parent_priv;
  71         u32 mask = gc->pin2mask(gc, offset);
  72         u32 imask;
  73         unsigned long flags;
  74
  75         spin_lock_irqsave(&gc->bgpio_lock, flags);
  76         imask = gc->read_reg(priv->reg_base + GIO_MASK(bank->id));
  77         if (enable)
  78                 imask |= mask;
  79         else
  80                 imask &= ~mask;
  81         gc->write_reg(priv->reg_base + GIO_MASK(bank->id), imask);
  82         spin_unlock_irqrestore(&gc->bgpio_lock, flags);
  83 }
  84
  85 /* -------------------- IRQ chip functions -------------------- */
  86
  87 static void brcmstb_gpio_irq_mask(struct irq_data *d)
  88 {
  89         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  90         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  91
  92         brcmstb_gpio_set_imask(bank, d->hwirq, false);
  93 }
  94
  95 static void brcmstb_gpio_irq_unmask(struct irq_data *d)
  96 {
  97         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
  98         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
  99
 100         brcmstb_gpio_set_imask(bank, d->hwirq, true);
 101 }
 102
 103 static int brcmstb_gpio_irq_set_type(struct irq_data *d, unsigned int type)
 104 {
 105         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 106         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 107         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 108         u32 mask = BIT(d->hwirq);
 109         u32 edge_insensitive, iedge_insensitive;
 110         u32 edge_config, iedge_config;
 111         u32 level, ilevel;
 112         unsigned long flags;
 113
 114         switch (type) {
 115         case IRQ_TYPE_LEVEL_LOW:
 116                 level = 0;
 117                 edge_config = 0;
 118                 edge_insensitive = 0;
 119                 break;
 120         case IRQ_TYPE_LEVEL_HIGH:
 121                 level = mask;
 122                 edge_config = 0;
 123                 edge_insensitive = 0;
 124                 break;
 125         case IRQ_TYPE_EDGE_FALLING:
 126                 level = 0;
 127                 edge_config = 0;
 128                 edge_insensitive = 0;
 129                 break;
 130         case IRQ_TYPE_EDGE_RISING:
 131                 level = 0;
 132                 edge_config = mask;
 133                 edge_insensitive = 0;
 134                 break;
 135         case IRQ_TYPE_EDGE_BOTH:
 136                 level = 0;
 137                 edge_config = 0;  /* don't care, but want known value */
 138                 edge_insensitive = mask;
 139                 break;
 140         default:
 141                 return -EINVAL;
 142         }
 143
 144         spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
 145
 146         iedge_config = bank->gc.read_reg(priv->reg_base +
 147                         GIO_EC(bank->id)) & ~mask;
 148         iedge_insensitive = bank->gc.read_reg(priv->reg_base +
 149                         GIO_EI(bank->id)) & ~mask;
 150         ilevel = bank->gc.read_reg(priv->reg_base +
 151                         GIO_LEVEL(bank->id)) & ~mask;
 152
 153         bank->gc.write_reg(priv->reg_base + GIO_EC(bank->id),
 154                         iedge_config | edge_config);
 155         bank->gc.write_reg(priv->reg_base + GIO_EI(bank->id),
 156                         iedge_insensitive | edge_insensitive);
 157         bank->gc.write_reg(priv->reg_base + GIO_LEVEL(bank->id),
 158                         ilevel | level);
 159
 160         spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
 161         return 0;
 162 }
 163
 164 static int brcmstb_gpio_priv_set_wake(struct brcmstb_gpio_priv *priv,
 165                 unsigned int enable)
 166 {
 167         int ret = 0;
 168
 169         /*
 170          * Only enable wake IRQ once for however many hwirqs can wake
 171          * since they all use the same wake IRQ.  Mask will be set
 172          * up appropriately thanks to IRQCHIP_MASK_ON_SUSPEND flag.
 173          */
 174         if (enable)
 175                 ret = enable_irq_wake(priv->parent_wake_irq);
 176         else
 177                 ret = disable_irq_wake(priv->parent_wake_irq);
 178         if (ret)
 179                 dev_err(&priv->pdev->dev, "failed to %s wake-up interrupt\n",
 180                                 enable ? "enable" : "disable");
 181         return ret;
 182 }
 183
 184 static int brcmstb_gpio_irq_set_wake(struct irq_data *d, unsigned int enable)
 185 {
 186         struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
 187         struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
 188
 189         return brcmstb_gpio_priv_set_wake(priv, enable);
 190 }
 191
 192 static irqreturn_t brcmstb_gpio_wake_irq_handler(int irq, void *data)
 193 {
 194         struct brcmstb_gpio_priv *priv = data;
 195
 196         if (!priv || irq != priv->parent_wake_irq)
 197                 return IRQ_NONE;
 198         pm_wakeup_event(&priv->pdev->dev, 0);
 199         return IRQ_HANDLED;
 200 }
 201
 202 static void brcmstb_gpio_irq_bank_handler(struct brcmstb_gpio_bank *bank)
 203 {
 204         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 205         struct irq_domain *irq_domain = bank->gc.irqdomain;
 206         void __iomem *reg_base = priv->reg_base;
 207         unsigned long status;
 208         unsigned long flags;
 209
 210         spin_lock_irqsave(&bank->gc.bgpio_lock, flags);
 211         while ((status = bank->gc.read_reg(reg_base + GIO_STAT(bank->id)) &
 212                          bank->gc.read_reg(reg_base + GIO_MASK(bank->id)))) {
 213                 int bit;
 214
 215                 for_each_set_bit(bit, &status, 32) {
 216                         u32 stat = bank->gc.read_reg(reg_base +
 217                                                       GIO_STAT(bank->id));
 218                         if (bit >= bank->width)
 219                                 dev_warn(&priv->pdev->dev,
 220                                          "IRQ for invalid GPIO (bank=%d, offset=%d)\n",
 221                                          bank->id, bit);
 222                         bank->gc.write_reg(reg_base + GIO_STAT(bank->id),
 223                                             stat | BIT(bit));
 224                         generic_handle_irq(irq_find_mapping(irq_domain, bit));
 225                 }
 226         }
 227         spin_unlock_irqrestore(&bank->gc.bgpio_lock, flags);
 228 }
 229
 230 /* Each UPG GIO block has one IRQ for all banks */
 231 static void brcmstb_gpio_irq_handler(struct irq_desc *desc)
 232 {
 233         struct gpio_chip *gc = irq_desc_get_handler_data(desc);
 234         struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
 235         struct irq_chip *chip = irq_desc_get_chip(desc);
 236         struct brcmstb_gpio_bank *bank;
 237
 238         /* Interrupts weren't properly cleared during probe */
 239         BUG_ON(!priv || !chip);
 240
 241         chained_irq_enter(chip, desc);
 242         list_for_each_entry(bank, &priv->bank_list, node)
 243                 brcmstb_gpio_irq_bank_handler(bank);
 244         chained_irq_exit(chip, desc);
 245 }
 246
 247 static int brcmstb_gpio_reboot(struct notifier_block *nb,
 248                 unsigned long action, void *data)
 249 {
 250         struct brcmstb_gpio_priv *priv =
 251                 container_of(nb, struct brcmstb_gpio_priv, reboot_notifier);
 252
 253         /* Enable GPIO for S5 cold boot */
 254         if (action == SYS_POWER_OFF)
 255                 brcmstb_gpio_priv_set_wake(priv, 1);
 256
 257         return NOTIFY_DONE;
 258 }
 259
 260 /* Make sure that the number of banks matches up between properties */
 261 static int brcmstb_gpio_sanity_check_banks(struct device *dev,
 262                 struct device_node *np, struct resource *res)
 263 {
 264         int res_num_banks = resource_size(res) / GIO_BANK_SIZE;
 265         int num_banks =
 266                 of_property_count_u32_elems(np, "brcm,gpio-bank-widths");
 267
 268         if (res_num_banks != num_banks) {
 269                 dev_err(dev, "Mismatch in banks: res had %d, bank-widths had %d\n",
 270                                 res_num_banks, num_banks);
 271                 return -EINVAL;
 272         } else {
 273                 return 0;
 274         }
 275 }
 276
 277 static int brcmstb_gpio_remove(struct platform_device *pdev)
 278 {
 279         struct brcmstb_gpio_priv *priv = platform_get_drvdata(pdev);
 280         struct brcmstb_gpio_bank *bank;
 281         int ret = 0;
 282
 283         if (!priv) {
 284                 dev_err(&pdev->dev, "called %s without drvdata!\n", __func__);
 285                 return -EFAULT;
 286         }
 287
 288         /*
 289          * You can lose return values below, but we report all errors, and it's
 290          * more important to actually perform all of the steps.
 291          */
 292         list_for_each_entry(bank, &priv->bank_list, node)
 293                 gpiochip_remove(&bank->gc);
 294
 295         if (priv->reboot_notifier.notifier_call) {
 296                 ret = unregister_reboot_notifier(&priv->reboot_notifier);
 297                 if (ret)
 298                         dev_err(&pdev->dev,
 299                                 "failed to unregister reboot notifier\n");
 300         }
 301         return ret;
 302 }
 303
 304 static int brcmstb_gpio_of_xlate(struct gpio_chip *gc,
 305                 const struct of_phandle_args *gpiospec, u32 *flags)
 306 {
 307         struct brcmstb_gpio_priv *priv = brcmstb_gpio_gc_to_priv(gc);
 308         struct brcmstb_gpio_bank *bank = gpiochip_get_data(gc);
 309         int offset;
 310
 311         if (gc->of_gpio_n_cells != 2) {
 312                 WARN_ON(1);
 313                 return -EINVAL;
 314         }
 315
 316         if (WARN_ON(gpiospec->args_count < gc->of_gpio_n_cells))
 317                 return -EINVAL;
 318
 319         offset = gpiospec->args[0] - (gc->base - priv->gpio_base);
 320         if (offset >= gc->ngpio || offset < 0)
 321                 return -EINVAL;
 322
 323         if (unlikely(offset >= bank->width)) {
 324                 dev_warn_ratelimited(&priv->pdev->dev,
 325                         "Received request for invalid GPIO offset %d\n",
 326                         gpiospec->args[0]);
 327         }
 328
 329         if (flags)
 330                 *flags = gpiospec->args[1];
 331
 332         return offset;
 333 }
 334
 335 /* Before calling, must have bank->parent_irq set and gpiochip registered */
 336 static int brcmstb_gpio_irq_setup(struct platform_device *pdev,
 337                 struct brcmstb_gpio_bank *bank)
 338 {
 339         struct brcmstb_gpio_priv *priv = bank->parent_priv;
 340         struct device *dev = &pdev->dev;
 341         struct device_node *np = dev->of_node;
 342
 343         bank->irq_chip.name = dev_name(dev);
 344         bank->irq_chip.irq_mask = brcmstb_gpio_irq_mask;
 345         bank->irq_chip.irq_unmask = brcmstb_gpio_irq_unmask;
 346         bank->irq_chip.irq_set_type = brcmstb_gpio_irq_set_type;
 347
 348         /* Ensures that all non-wakeup IRQs are disabled at suspend */
 349         bank->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND;
 350
 351         if (IS_ENABLED(CONFIG_PM_SLEEP) && !priv->can_wake &&
 352                         of_property_read_bool(np, "wakeup-source")) {
 353                 priv->parent_wake_irq = platform_get_irq(pdev, 1);
 354                 if (priv->parent_wake_irq < 0) {
 355                         dev_warn(dev,
 356                                 "Couldn't get wake IRQ - GPIOs will not be able to wake from sleep");
 357                 } else {
 358                         int err;
 359
 360                         /*
 361                          * Set wakeup capability before requesting wakeup
 362                          * interrupt, so we can process boot-time "wakeups"
 363                          * (e.g., from S5 cold boot)
 364                          */
 365                         device_set_wakeup_capable(dev, true);
 366                         device_wakeup_enable(dev);
 367                         err = devm_request_irq(dev, priv->parent_wake_irq,
 368                                         brcmstb_gpio_wake_irq_handler, 0,
 369                                         "brcmstb-gpio-wake", priv);
 370
 371                         if (err < 0) {
 372                                 dev_err(dev, "Couldn't request wake IRQ");
 373                                 return err;
 374                         }
 375
 376                         priv->reboot_notifier.notifier_call =
 377                                 brcmstb_gpio_reboot;
 378                         register_reboot_notifier(&priv->reboot_notifier);
 379                         priv->can_wake = true;
 380                 }
 381         }
 382
 383         if (priv->can_wake)
 384                 bank->irq_chip.irq_set_wake = brcmstb_gpio_irq_set_wake;
 385
 386         gpiochip_irqchip_add(&bank->gc, &bank->irq_chip, 0,
 387                         handle_simple_irq, IRQ_TYPE_NONE);
 388         gpiochip_set_chained_irqchip(&bank->gc, &bank->irq_chip,
 389                         priv->parent_irq, brcmstb_gpio_irq_handler);
 390
 391         return 0;
 392 }
 393
 394 static int brcmstb_gpio_probe(struct platform_device *pdev)
 395 {
 396         struct device *dev = &pdev->dev;
 397         struct device_node *np = dev->of_node;
 398         void __iomem *reg_base;
 399         struct brcmstb_gpio_priv *priv;
 400         struct resource *res;
 401         struct property *prop;
 402         const __be32 *p;
 403         u32 bank_width;
 404         int num_banks = 0;
 405         int err;
 406         static int gpio_base;
 407         unsigned long flags = 0;
 408
 409         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 410         if (!priv)
 411                 return -ENOMEM;
 412         platform_set_drvdata(pdev, priv);
 413         INIT_LIST_HEAD(&priv->bank_list);
 414
 415         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 416         reg_base = devm_ioremap_resource(dev, res);
 417         if (IS_ERR(reg_base))
 418                 return PTR_ERR(reg_base);
 419
 420         priv->gpio_base = gpio_base;
 421         priv->reg_base = reg_base;
 422         priv->pdev = pdev;
 423
 424         if (of_property_read_bool(np, "interrupt-controller")) {
 425                 priv->parent_irq = platform_get_irq(pdev, 0);
 426                 if (priv->parent_irq <= 0) {
 427                         dev_err(dev, "Couldn't get IRQ");
 428                         return -ENOENT;
 429                 }
 430         } else {
 431                 priv->parent_irq = -ENOENT;
 432         }
 433
 434         if (brcmstb_gpio_sanity_check_banks(dev, np, res))
 435                 return -EINVAL;
 436
 437         /*
 438          * MIPS endianness is configured by boot strap, which also reverses all
 439          * bus endianness (i.e., big-endian CPU + big endian bus ==> native
 440          * endian I/O).
 441          *
 442          * Other architectures (e.g., ARM) either do not support big endian, or
 443          * else leave I/O in little endian mode.
 444          */
 445 #if defined(CONFIG_MIPS) && defined(__BIG_ENDIAN)
 446         flags = BGPIOF_BIG_ENDIAN_BYTE_ORDER;
 447 #endif
 448
 449         of_property_for_each_u32(np, "brcm,gpio-bank-widths", prop, p,
 450                         bank_width) {
 451                 struct brcmstb_gpio_bank *bank;
 452                 struct gpio_chip *gc;
 453
 454                 bank = devm_kzalloc(dev, sizeof(*bank), GFP_KERNEL);
 455                 if (!bank) {
 456                         err = -ENOMEM;
 457                         goto fail;
 458                 }
 459
 460                 bank->parent_priv = priv;
 461                 bank->id = num_banks;
 462                 if (bank_width <= 0 || bank_width > MAX_GPIO_PER_BANK) {
 463                         dev_err(dev, "Invalid bank width %d\n", bank_width);
 464                         goto fail;
 465                 } else {
 466                         bank->width = bank_width;
 467                 }
 468
 469                 /*
 470                  * Regs are 4 bytes wide, have data reg, no set/clear regs,
 471                  * and direction bits have 0 = output and 1 = input
 472                  */
 473                 gc = &bank->gc;
 474                 err = bgpio_init(gc, dev, 4,
 475                                 reg_base + GIO_DATA(bank->id),
 476                                 NULL, NULL, NULL,
 477                                 reg_base + GIO_IODIR(bank->id), flags);
 478                 if (err) {
 479                         dev_err(dev, "bgpio_init() failed\n");
 480                         goto fail;
 481                 }
 482
 483                 gc->of_node = np;
 484                 gc->owner = THIS_MODULE;
 485                 gc->label = np->full_name;
 486                 gc->base = gpio_base;
 487                 gc->of_gpio_n_cells = 2;
 488                 gc->of_xlate = brcmstb_gpio_of_xlate;
 489                 /* not all ngpio lines are valid, will use bank width later */
 490                 gc->ngpio = MAX_GPIO_PER_BANK;
 491
 492                 /*
 493                  * Mask all interrupts by default, since wakeup interrupts may
 494                  * be retained from S5 cold boot
 495                  */
 496                 gc->write_reg(reg_base + GIO_MASK(bank->id), 0);
 497
 498                 err = gpiochip_add_data(gc, bank);
 499                 if (err) {
 500                         dev_err(dev, "Could not add gpiochip for bank %d\n",
 501                                         bank->id);
 502                         goto fail;
 503                 }
 504                 gpio_base += gc->ngpio;
 505
 506                 if (priv->parent_irq > 0) {
 507                         err = brcmstb_gpio_irq_setup(pdev, bank);
 508                         if (err)
 509                                 goto fail;
 510                 }
 511
 512                 dev_dbg(dev, "bank=%d, base=%d, ngpio=%d, width=%d\n", bank->id,
 513                         gc->base, gc->ngpio, bank->width);
 514
 515                 /* Everything looks good, so add bank to list */
 516                 list_add(&bank->node, &priv->bank_list);
 517
 518                 num_banks++;
 519         }
 520
 521         dev_info(dev, "Registered %d banks (GPIO(s): %d-%d)\n",
 522                         num_banks, priv->gpio_base, gpio_base - 1);
 523
 524         return 0;
 525
 526 fail:
 527         (void) brcmstb_gpio_remove(pdev);
 528         return err;
 529 }
 530
 531 static const struct of_device_id brcmstb_gpio_of_match[] = {
 532         { .compatible = "brcm,brcmstb-gpio" },
 533         {},
 534 };
 535
 536 MODULE_DEVICE_TABLE(of, brcmstb_gpio_of_match);
 537
 538 static struct platform_driver brcmstb_gpio_driver = {
 539         .driver = {
 540                 .name = "brcmstb-gpio",
 541                 .of_match_table = brcmstb_gpio_of_match,
 542         },
 543         .probe = brcmstb_gpio_probe,
 544         .remove = brcmstb_gpio_remove,
 545 };
 546 module_platform_driver(brcmstb_gpio_driver);
 547
 548 MODULE_AUTHOR("Gregory Fong");
 549 MODULE_DESCRIPTION("Driver for Broadcom BRCMSTB SoC UPG GPIO");
 550 MODULE_LICENSE("GPL v2");