drivers/gpio/gpio-em.c

   1 /*
   2  * Emma Mobile GPIO Support - GIO
   3  *
   4  *  Copyright (C) 2012 Magnus Damm
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  18  */
  19
  20 #include <linux/init.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/spinlock.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/ioport.h>
  25 #include <linux/io.h>
  26 #include <linux/irq.h>
  27 #include <linux/irqdomain.h>
  28 #include <linux/bitops.h>
  29 #include <linux/err.h>
  30 #include <linux/gpio.h>
  31 #include <linux/slab.h>
  32 #include <linux/module.h>
  33 #include <linux/pinctrl/consumer.h>
  34
  35 struct em_gio_priv {
  36         void __iomem *base0;
  37         void __iomem *base1;
  38         spinlock_t sense_lock;
  39         struct platform_device *pdev;
  40         struct gpio_chip gpio_chip;
  41         struct irq_chip irq_chip;
  42         struct irq_domain *irq_domain;
  43 };
  44
  45 #define GIO_E1 0x00
  46 #define GIO_E0 0x04
  47 #define GIO_EM 0x04
  48 #define GIO_OL 0x08
  49 #define GIO_OH 0x0c
  50 #define GIO_I 0x10
  51 #define GIO_IIA 0x14
  52 #define GIO_IEN 0x18
  53 #define GIO_IDS 0x1c
  54 #define GIO_IIM 0x1c
  55 #define GIO_RAW 0x20
  56 #define GIO_MST 0x24
  57 #define GIO_IIR 0x28
  58
  59 #define GIO_IDT0 0x40
  60 #define GIO_IDT1 0x44
  61 #define GIO_IDT2 0x48
  62 #define GIO_IDT3 0x4c
  63 #define GIO_RAWBL 0x50
  64 #define GIO_RAWBH 0x54
  65 #define GIO_IRBL 0x58
  66 #define GIO_IRBH 0x5c
  67
  68 #define GIO_IDT(n) (GIO_IDT0 + ((n) * 4))
  69
  70 static inline unsigned long em_gio_read(struct em_gio_priv *p, int offs)
  71 {
  72         if (offs < GIO_IDT0)
  73                 return ioread32(p->base0 + offs);
  74         else
  75                 return ioread32(p->base1 + (offs - GIO_IDT0));
  76 }
  77
  78 static inline void em_gio_write(struct em_gio_priv *p, int offs,
  79                                 unsigned long value)
  80 {
  81         if (offs < GIO_IDT0)
  82                 iowrite32(value, p->base0 + offs);
  83         else
  84                 iowrite32(value, p->base1 + (offs - GIO_IDT0));
  85 }
  86
  87 static void em_gio_irq_disable(struct irq_data *d)
  88 {
  89         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  90
  91         em_gio_write(p, GIO_IDS, BIT(irqd_to_hwirq(d)));
  92 }
  93
  94 static void em_gio_irq_enable(struct irq_data *d)
  95 {
  96         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
  97
  98         em_gio_write(p, GIO_IEN, BIT(irqd_to_hwirq(d)));
  99 }
 100
 101 static int em_gio_irq_reqres(struct irq_data *d)
 102 {
 103         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
 104
 105         if (gpiochip_lock_as_irq(&p->gpio_chip, irqd_to_hwirq(d))) {
 106                 dev_err(p->gpio_chip.parent,
 107                         "unable to lock HW IRQ %lu for IRQ\n",
 108                         irqd_to_hwirq(d));
 109                 return -EINVAL;
 110         }
 111         return 0;
 112 }
 113
 114 static void em_gio_irq_relres(struct irq_data *d)
 115 {
 116         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
 117
 118         gpiochip_unlock_as_irq(&p->gpio_chip, irqd_to_hwirq(d));
 119 }
 120
 121
 122 #define GIO_ASYNC(x) (x + 8)
 123
 124 static unsigned char em_gio_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
 125         [IRQ_TYPE_EDGE_RISING] = GIO_ASYNC(0x00),
 126         [IRQ_TYPE_EDGE_FALLING] = GIO_ASYNC(0x01),
 127         [IRQ_TYPE_LEVEL_HIGH] = GIO_ASYNC(0x02),
 128         [IRQ_TYPE_LEVEL_LOW] = GIO_ASYNC(0x03),
 129         [IRQ_TYPE_EDGE_BOTH] = GIO_ASYNC(0x04),
 130 };
 131
 132 static int em_gio_irq_set_type(struct irq_data *d, unsigned int type)
 133 {
 134         unsigned char value = em_gio_sense_table[type & IRQ_TYPE_SENSE_MASK];
 135         struct em_gio_priv *p = irq_data_get_irq_chip_data(d);
 136         unsigned int reg, offset, shift;
 137         unsigned long flags;
 138         unsigned long tmp;
 139
 140         if (!value)
 141                 return -EINVAL;
 142
 143         offset = irqd_to_hwirq(d);
 144
 145         pr_debug("gio: sense irq = %d, mode = %d\n", offset, value);
 146
 147         /* 8 x 4 bit fields in 4 IDT registers */
 148         reg = GIO_IDT(offset >> 3);
 149         shift = (offset & 0x07) << 4;
 150
 151         spin_lock_irqsave(&p->sense_lock, flags);
 152
 153         /* disable the interrupt in IIA */
 154         tmp = em_gio_read(p, GIO_IIA);
 155         tmp &= ~BIT(offset);
 156         em_gio_write(p, GIO_IIA, tmp);
 157
 158         /* change the sense setting in IDT */
 159         tmp = em_gio_read(p, reg);
 160         tmp &= ~(0xf << shift);
 161         tmp |= value << shift;
 162         em_gio_write(p, reg, tmp);
 163
 164         /* clear pending interrupts */
 165         em_gio_write(p, GIO_IIR, BIT(offset));
 166
 167         /* enable the interrupt in IIA */
 168         tmp = em_gio_read(p, GIO_IIA);
 169         tmp |= BIT(offset);
 170         em_gio_write(p, GIO_IIA, tmp);
 171
 172         spin_unlock_irqrestore(&p->sense_lock, flags);
 173
 174         return 0;
 175 }
 176
 177 static irqreturn_t em_gio_irq_handler(int irq, void *dev_id)
 178 {
 179         struct em_gio_priv *p = dev_id;
 180         unsigned long pending;
 181         unsigned int offset, irqs_handled = 0;
 182
 183         while ((pending = em_gio_read(p, GIO_MST))) {
 184                 offset = __ffs(pending);
 185                 em_gio_write(p, GIO_IIR, BIT(offset));
 186                 generic_handle_irq(irq_find_mapping(p->irq_domain, offset));
 187                 irqs_handled++;
 188         }
 189
 190         return irqs_handled ? IRQ_HANDLED : IRQ_NONE;
 191 }
 192
 193 static inline struct em_gio_priv *gpio_to_priv(struct gpio_chip *chip)
 194 {
 195         return gpiochip_get_data(chip);
 196 }
 197
 198 static int em_gio_direction_input(struct gpio_chip *chip, unsigned offset)
 199 {
 200         em_gio_write(gpio_to_priv(chip), GIO_E0, BIT(offset));
 201         return 0;
 202 }
 203
 204 static int em_gio_get(struct gpio_chip *chip, unsigned offset)
 205 {
 206         return !!(em_gio_read(gpio_to_priv(chip), GIO_I) & BIT(offset));
 207 }
 208
 209 static void __em_gio_set(struct gpio_chip *chip, unsigned int reg,
 210                          unsigned shift, int value)
 211 {
 212         /* upper 16 bits contains mask and lower 16 actual value */
 213         em_gio_write(gpio_to_priv(chip), reg,
 214                      (BIT(shift + 16)) | (value << shift));
 215 }
 216
 217 static void em_gio_set(struct gpio_chip *chip, unsigned offset, int value)
 218 {
 219         /* output is split into two registers */
 220         if (offset < 16)
 221                 __em_gio_set(chip, GIO_OL, offset, value);
 222         else
 223                 __em_gio_set(chip, GIO_OH, offset - 16, value);
 224 }
 225
 226 static int em_gio_direction_output(struct gpio_chip *chip, unsigned offset,
 227                                    int value)
 228 {
 229         /* write GPIO value to output before selecting output mode of pin */
 230         em_gio_set(chip, offset, value);
 231         em_gio_write(gpio_to_priv(chip), GIO_E1, BIT(offset));
 232         return 0;
 233 }
 234
 235 static int em_gio_to_irq(struct gpio_chip *chip, unsigned offset)
 236 {
 237         return irq_create_mapping(gpio_to_priv(chip)->irq_domain, offset);
 238 }
 239
 240 static int em_gio_request(struct gpio_chip *chip, unsigned offset)
 241 {
 242         return pinctrl_request_gpio(chip->base + offset);
 243 }
 244
 245 static void em_gio_free(struct gpio_chip *chip, unsigned offset)
 246 {
 247         pinctrl_free_gpio(chip->base + offset);
 248
 249         /* Set the GPIO as an input to ensure that the next GPIO request won't
 250         * drive the GPIO pin as an output.
 251         */
 252         em_gio_direction_input(chip, offset);
 253 }
 254
 255 static int em_gio_irq_domain_map(struct irq_domain *h, unsigned int irq,
 256                                  irq_hw_number_t hwirq)
 257 {
 258         struct em_gio_priv *p = h->host_data;
 259
 260         pr_debug("gio: map hw irq = %d, irq = %d\n", (int)hwirq, irq);
 261
 262         irq_set_chip_data(irq, h->host_data);
 263         irq_set_chip_and_handler(irq, &p->irq_chip, handle_level_irq);
 264         return 0;
 265 }
 266
 267 static const struct irq_domain_ops em_gio_irq_domain_ops = {
 268         .map    = em_gio_irq_domain_map,
 269         .xlate  = irq_domain_xlate_twocell,
 270 };
 271
 272 static int em_gio_probe(struct platform_device *pdev)
 273 {
 274         struct em_gio_priv *p;
 275         struct resource *io[2], *irq[2];
 276         struct gpio_chip *gpio_chip;
 277         struct irq_chip *irq_chip;
 278         const char *name = dev_name(&pdev->dev);
 279         unsigned int ngpios;
 280         int ret;
 281
 282         p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL);
 283         if (!p) {
 284                 ret = -ENOMEM;
 285                 goto err0;
 286         }
 287
 288         p->pdev = pdev;
 289         platform_set_drvdata(pdev, p);
 290         spin_lock_init(&p->sense_lock);
 291
 292         io[0] = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 293         io[1] = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 294         irq[0] = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
 295         irq[1] = platform_get_resource(pdev, IORESOURCE_IRQ, 1);
 296
 297         if (!io[0] || !io[1] || !irq[0] || !irq[1]) {
 298                 dev_err(&pdev->dev, "missing IRQ or IOMEM\n");
 299                 ret = -EINVAL;
 300                 goto err0;
 301         }
 302
 303         p->base0 = devm_ioremap_nocache(&pdev->dev, io[0]->start,
 304                                         resource_size(io[0]));
 305         if (!p->base0) {
 306                 dev_err(&pdev->dev, "failed to remap low I/O memory\n");
 307                 ret = -ENXIO;
 308                 goto err0;
 309         }
 310
 311         p->base1 = devm_ioremap_nocache(&pdev->dev, io[1]->start,
 312                                    resource_size(io[1]));
 313         if (!p->base1) {
 314                 dev_err(&pdev->dev, "failed to remap high I/O memory\n");
 315                 ret = -ENXIO;
 316                 goto err0;
 317         }
 318
 319         if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
 320                 dev_err(&pdev->dev, "Missing ngpios OF property\n");
 321                 ret = -EINVAL;
 322                 goto err0;
 323         }
 324
 325         gpio_chip = &p->gpio_chip;
 326         gpio_chip->of_node = pdev->dev.of_node;
 327         gpio_chip->direction_input = em_gio_direction_input;
 328         gpio_chip->get = em_gio_get;
 329         gpio_chip->direction_output = em_gio_direction_output;
 330         gpio_chip->set = em_gio_set;
 331         gpio_chip->to_irq = em_gio_to_irq;
 332         gpio_chip->request = em_gio_request;
 333         gpio_chip->free = em_gio_free;
 334         gpio_chip->label = name;
 335         gpio_chip->parent = &pdev->dev;
 336         gpio_chip->owner = THIS_MODULE;
 337         gpio_chip->base = -1;
 338         gpio_chip->ngpio = ngpios;
 339
 340         irq_chip = &p->irq_chip;
 341         irq_chip->name = name;
 342         irq_chip->irq_mask = em_gio_irq_disable;
 343         irq_chip->irq_unmask = em_gio_irq_enable;
 344         irq_chip->irq_set_type = em_gio_irq_set_type;
 345         irq_chip->irq_request_resources = em_gio_irq_reqres;
 346         irq_chip->irq_release_resources = em_gio_irq_relres;
 347         irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND;
 348
 349         p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, ngpios, 0,
 350                                               &em_gio_irq_domain_ops, p);
 351         if (!p->irq_domain) {
 352                 ret = -ENXIO;
 353                 dev_err(&pdev->dev, "cannot initialize irq domain\n");
 354                 goto err0;
 355         }
 356
 357         if (devm_request_irq(&pdev->dev, irq[0]->start,
 358                              em_gio_irq_handler, 0, name, p)) {
 359                 dev_err(&pdev->dev, "failed to request low IRQ\n");
 360                 ret = -ENOENT;
 361                 goto err1;
 362         }
 363
 364         if (devm_request_irq(&pdev->dev, irq[1]->start,
 365                              em_gio_irq_handler, 0, name, p)) {
 366                 dev_err(&pdev->dev, "failed to request high IRQ\n");
 367                 ret = -ENOENT;
 368                 goto err1;
 369         }
 370
 371         ret = gpiochip_add_data(gpio_chip, p);
 372         if (ret) {
 373                 dev_err(&pdev->dev, "failed to add GPIO controller\n");
 374                 goto err1;
 375         }
 376
 377         return 0;
 378
 379 err1:
 380         irq_domain_remove(p->irq_domain);
 381 err0:
 382         return ret;
 383 }
 384
 385 static int em_gio_remove(struct platform_device *pdev)
 386 {
 387         struct em_gio_priv *p = platform_get_drvdata(pdev);
 388
 389         gpiochip_remove(&p->gpio_chip);
 390
 391         irq_domain_remove(p->irq_domain);
 392         return 0;
 393 }
 394
 395 static const struct of_device_id em_gio_dt_ids[] = {
 396         { .compatible = "renesas,em-gio", },
 397         {},
 398 };
 399 MODULE_DEVICE_TABLE(of, em_gio_dt_ids);
 400
 401 static struct platform_driver em_gio_device_driver = {
 402         .probe          = em_gio_probe,
 403         .remove         = em_gio_remove,
 404         .driver         = {
 405                 .name   = "em_gio",
 406                 .of_match_table = em_gio_dt_ids,
 407         }
 408 };
 409
 410 static int __init em_gio_init(void)
 411 {
 412         return platform_driver_register(&em_gio_device_driver);
 413 }
 414 postcore_initcall(em_gio_init);
 415
 416 static void __exit em_gio_exit(void)
 417 {
 418         platform_driver_unregister(&em_gio_device_driver);
 419 }
 420 module_exit(em_gio_exit);
 421
 422 MODULE_AUTHOR("Magnus Damm");
 423 MODULE_DESCRIPTION("Renesas Emma Mobile GIO Driver");
 424 MODULE_LICENSE("GPL v2");