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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-ismt.c
blob7ba795b24e75d4d212972ddfa0675d582a9ef671
1 /*
2 * This file is provided under a dual BSD/GPLv2 license. When using or
3 * redistributing this file, you may do so under either license.
4 *
5 * Copyright(c) 2012 Intel Corporation. All rights reserved.
6 *
7 * GPL LICENSE SUMMARY
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of version 2 of the GNU General Public License as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 * The full GNU General Public License is included in this distribution
18 * in the file called LICENSE.GPL.
19 *
20 * BSD LICENSE
21 *
22 * Redistribution and use in source and binary forms, with or without
23 * modification, are permitted provided that the following conditions
24 * are met:
25 *
26 * * Redistributions of source code must retain the above copyright
27 * notice, this list of conditions and the following disclaimer.
28 * * Redistributions in binary form must reproduce the above copyright
29 * notice, this list of conditions and the following disclaimer in
30 * the documentation and/or other materials provided with the
31 * distribution.
32 * * Neither the name of Intel Corporation nor the names of its
33 * contributors may be used to endorse or promote products derived
34 * from this software without specific prior written permission.
35 *
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
37 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
38 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
39 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
40 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
41 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
42 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
43 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
44 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
45 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
46 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 */
48
49 /*
50 * Supports the SMBus Message Transport (SMT) in the Intel Atom Processor
51 * S12xx Product Family.
52 *
53 * Features supported by this driver:
54 * Hardware PEC yes
55 * Block buffer yes
56 * Block process call transaction no
57 * Slave mode no
58 */
59
60 #include <linux/module.h>
61 #include <linux/pci.h>
62 #include <linux/kernel.h>
63 #include <linux/stddef.h>
64 #include <linux/completion.h>
65 #include <linux/dma-mapping.h>
66 #include <linux/i2c.h>
67 #include <linux/acpi.h>
68 #include <linux/interrupt.h>
69
70 #include <linux/io-64-nonatomic-lo-hi.h>
71
72 /* PCI Address Constants */
73 #define SMBBAR 0
74
75 /* PCI DIDs for the Intel SMBus Message Transport (SMT) Devices */
76 #define PCI_DEVICE_ID_INTEL_S1200_SMT0 0x0c59
77 #define PCI_DEVICE_ID_INTEL_S1200_SMT1 0x0c5a
78 #define PCI_DEVICE_ID_INTEL_AVOTON_SMT 0x1f15
79
80 #define ISMT_DESC_ENTRIES 2 /* number of descriptor entries */
81 #define ISMT_MAX_RETRIES 3 /* number of SMBus retries to attempt */
82
83 /* Hardware Descriptor Constants - Control Field */
84 #define ISMT_DESC_CWRL 0x01 /* Command/Write Length */
85 #define ISMT_DESC_BLK 0X04 /* Perform Block Transaction */
86 #define ISMT_DESC_FAIR 0x08 /* Set fairness flag upon successful arbit. */
87 #define ISMT_DESC_PEC 0x10 /* Packet Error Code */
88 #define ISMT_DESC_I2C 0x20 /* I2C Enable */
89 #define ISMT_DESC_INT 0x40 /* Interrupt */
90 #define ISMT_DESC_SOE 0x80 /* Stop On Error */
91
92 /* Hardware Descriptor Constants - Status Field */
93 #define ISMT_DESC_SCS 0x01 /* Success */
94 #define ISMT_DESC_DLTO 0x04 /* Data Low Time Out */
95 #define ISMT_DESC_NAK 0x08 /* NAK Received */
96 #define ISMT_DESC_CRC 0x10 /* CRC Error */
97 #define ISMT_DESC_CLTO 0x20 /* Clock Low Time Out */
98 #define ISMT_DESC_COL 0x40 /* Collisions */
99 #define ISMT_DESC_LPR 0x80 /* Large Packet Received */
100
101 /* Macros */
102 #define ISMT_DESC_ADDR_RW(addr, rw) (((addr) << 1) | (rw))
103
104 /* iSMT General Register address offsets (SMBBAR + <addr>) */
105 #define ISMT_GR_GCTRL 0x000 /* General Control */
106 #define ISMT_GR_SMTICL 0x008 /* SMT Interrupt Cause Location */
107 #define ISMT_GR_ERRINTMSK 0x010 /* Error Interrupt Mask */
108 #define ISMT_GR_ERRAERMSK 0x014 /* Error AER Mask */
109 #define ISMT_GR_ERRSTS 0x018 /* Error Status */
110 #define ISMT_GR_ERRINFO 0x01c /* Error Information */
111
112 /* iSMT Master Registers */
113 #define ISMT_MSTR_MDBA 0x100 /* Master Descriptor Base Address */
114 #define ISMT_MSTR_MCTRL 0x108 /* Master Control */
115 #define ISMT_MSTR_MSTS 0x10c /* Master Status */
116 #define ISMT_MSTR_MDS 0x110 /* Master Descriptor Size */
117 #define ISMT_MSTR_RPOLICY 0x114 /* Retry Policy */
118
119 /* iSMT Miscellaneous Registers */
120 #define ISMT_SPGT 0x300 /* SMBus PHY Global Timing */
121
122 /* General Control Register (GCTRL) bit definitions */
123 #define ISMT_GCTRL_TRST 0x04 /* Target Reset */
124 #define ISMT_GCTRL_KILL 0x08 /* Kill */
125 #define ISMT_GCTRL_SRST 0x40 /* Soft Reset */
126
127 /* Master Control Register (MCTRL) bit definitions */
128 #define ISMT_MCTRL_SS 0x01 /* Start/Stop */
129 #define ISMT_MCTRL_MEIE 0x10 /* Master Error Interrupt Enable */
130 #define ISMT_MCTRL_FMHP 0x00ff0000 /* Firmware Master Head Ptr (FMHP) */
131
132 /* Master Status Register (MSTS) bit definitions */
133 #define ISMT_MSTS_HMTP 0xff0000 /* HW Master Tail Pointer (HMTP) */
134 #define ISMT_MSTS_MIS 0x20 /* Master Interrupt Status (MIS) */
135 #define ISMT_MSTS_MEIS 0x10 /* Master Error Int Status (MEIS) */
136 #define ISMT_MSTS_IP 0x01 /* In Progress */
137
138 /* Master Descriptor Size (MDS) bit definitions */
139 #define ISMT_MDS_MASK 0xff /* Master Descriptor Size mask (MDS) */
140
141 /* SMBus PHY Global Timing Register (SPGT) bit definitions */
142 #define ISMT_SPGT_SPD_MASK 0xc0000000 /* SMBus Speed mask */
143 #define ISMT_SPGT_SPD_80K 0x00 /* 80 kHz */
144 #define ISMT_SPGT_SPD_100K (0x1 << 30) /* 100 kHz */
145 #define ISMT_SPGT_SPD_400K (0x2 << 30) /* 400 kHz */
146 #define ISMT_SPGT_SPD_1M (0x3 << 30) /* 1 MHz */
147
148
149 /* MSI Control Register (MSICTL) bit definitions */
150 #define ISMT_MSICTL_MSIE 0x01 /* MSI Enable */
151
152 /* iSMT Hardware Descriptor */
153 struct ismt_desc {
154 u8 tgtaddr_rw; /* target address & r/w bit */
155 u8 wr_len_cmd; /* write length in bytes or a command */
156 u8 rd_len; /* read length */
157 u8 control; /* control bits */
158 u8 status; /* status bits */
159 u8 retry; /* collision retry and retry count */
160 u8 rxbytes; /* received bytes */
161 u8 txbytes; /* transmitted bytes */
162 u32 dptr_low; /* lower 32 bit of the data pointer */
163 u32 dptr_high; /* upper 32 bit of the data pointer */
164 } __packed;
165
166 struct ismt_priv {
167 struct i2c_adapter adapter;
168 void __iomem *smba; /* PCI BAR */
169 struct pci_dev *pci_dev;
170 struct ismt_desc *hw; /* descriptor virt base addr */
171 dma_addr_t io_rng_dma; /* descriptor HW base addr */
172 u8 head; /* ring buffer head pointer */
173 struct completion cmp; /* interrupt completion */
174 u8 dma_buffer[I2C_SMBUS_BLOCK_MAX + 1]; /* temp R/W data buffer */
175 };
176
177 /**
178 * ismt_ids - PCI device IDs supported by this driver
179 */
180 static const struct pci_device_id ismt_ids[] = {
181 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT0) },
182 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_S1200_SMT1) },
183 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMT) },
184 { 0, }
185 };
186
187 MODULE_DEVICE_TABLE(pci, ismt_ids);
188
189 /* Bus speed control bits for slow debuggers - refer to the docs for usage */
190 static unsigned int bus_speed;
191 module_param(bus_speed, uint, S_IRUGO);
192 MODULE_PARM_DESC(bus_speed, "Bus Speed in kHz (0 = BIOS default)");
193
194 /**
195 * __ismt_desc_dump() - dump the contents of a specific descriptor
196 */
197 static void __ismt_desc_dump(struct device *dev, const struct ismt_desc *desc)
198 {
199
200 dev_dbg(dev, "Descriptor struct: %p\n", desc);
201 dev_dbg(dev, "\ttgtaddr_rw=0x%02X\n", desc->tgtaddr_rw);
202 dev_dbg(dev, "\twr_len_cmd=0x%02X\n", desc->wr_len_cmd);
203 dev_dbg(dev, "\trd_len= 0x%02X\n", desc->rd_len);
204 dev_dbg(dev, "\tcontrol= 0x%02X\n", desc->control);
205 dev_dbg(dev, "\tstatus= 0x%02X\n", desc->status);
206 dev_dbg(dev, "\tretry= 0x%02X\n", desc->retry);
207 dev_dbg(dev, "\trxbytes= 0x%02X\n", desc->rxbytes);
208 dev_dbg(dev, "\ttxbytes= 0x%02X\n", desc->txbytes);
209 dev_dbg(dev, "\tdptr_low= 0x%08X\n", desc->dptr_low);
210 dev_dbg(dev, "\tdptr_high= 0x%08X\n", desc->dptr_high);
211 }
212 /**
213 * ismt_desc_dump() - dump the contents of a descriptor for debug purposes
214 * @priv: iSMT private data
215 */
216 static void ismt_desc_dump(struct ismt_priv *priv)
217 {
218 struct device *dev = &priv->pci_dev->dev;
219 struct ismt_desc *desc = &priv->hw[priv->head];
220
221 dev_dbg(dev, "Dump of the descriptor struct: 0x%X\n", priv->head);
222 __ismt_desc_dump(dev, desc);
223 }
224
225 /**
226 * ismt_gen_reg_dump() - dump the iSMT General Registers
227 * @priv: iSMT private data
228 */
229 static void ismt_gen_reg_dump(struct ismt_priv *priv)
230 {
231 struct device *dev = &priv->pci_dev->dev;
232
233 dev_dbg(dev, "Dump of the iSMT General Registers\n");
234 dev_dbg(dev, " GCTRL.... : (0x%p)=0x%X\n",
235 priv->smba + ISMT_GR_GCTRL,
236 readl(priv->smba + ISMT_GR_GCTRL));
237 dev_dbg(dev, " SMTICL... : (0x%p)=0x%016llX\n",
238 priv->smba + ISMT_GR_SMTICL,
239 (long long unsigned int)readq(priv->smba + ISMT_GR_SMTICL));
240 dev_dbg(dev, " ERRINTMSK : (0x%p)=0x%X\n",
241 priv->smba + ISMT_GR_ERRINTMSK,
242 readl(priv->smba + ISMT_GR_ERRINTMSK));
243 dev_dbg(dev, " ERRAERMSK : (0x%p)=0x%X\n",
244 priv->smba + ISMT_GR_ERRAERMSK,
245 readl(priv->smba + ISMT_GR_ERRAERMSK));
246 dev_dbg(dev, " ERRSTS... : (0x%p)=0x%X\n",
247 priv->smba + ISMT_GR_ERRSTS,
248 readl(priv->smba + ISMT_GR_ERRSTS));
249 dev_dbg(dev, " ERRINFO.. : (0x%p)=0x%X\n",
250 priv->smba + ISMT_GR_ERRINFO,
251 readl(priv->smba + ISMT_GR_ERRINFO));
252 }
253
254 /**
255 * ismt_mstr_reg_dump() - dump the iSMT Master Registers
256 * @priv: iSMT private data
257 */
258 static void ismt_mstr_reg_dump(struct ismt_priv *priv)
259 {
260 struct device *dev = &priv->pci_dev->dev;
261
262 dev_dbg(dev, "Dump of the iSMT Master Registers\n");
263 dev_dbg(dev, " MDBA..... : (0x%p)=0x%016llX\n",
264 priv->smba + ISMT_MSTR_MDBA,
265 (long long unsigned int)readq(priv->smba + ISMT_MSTR_MDBA));
266 dev_dbg(dev, " MCTRL.... : (0x%p)=0x%X\n",
267 priv->smba + ISMT_MSTR_MCTRL,
268 readl(priv->smba + ISMT_MSTR_MCTRL));
269 dev_dbg(dev, " MSTS..... : (0x%p)=0x%X\n",
270 priv->smba + ISMT_MSTR_MSTS,
271 readl(priv->smba + ISMT_MSTR_MSTS));
272 dev_dbg(dev, " MDS...... : (0x%p)=0x%X\n",
273 priv->smba + ISMT_MSTR_MDS,
274 readl(priv->smba + ISMT_MSTR_MDS));
275 dev_dbg(dev, " RPOLICY.. : (0x%p)=0x%X\n",
276 priv->smba + ISMT_MSTR_RPOLICY,
277 readl(priv->smba + ISMT_MSTR_RPOLICY));
278 dev_dbg(dev, " SPGT..... : (0x%p)=0x%X\n",
279 priv->smba + ISMT_SPGT,
280 readl(priv->smba + ISMT_SPGT));
281 }
282
283 /**
284 * ismt_submit_desc() - add a descriptor to the ring
285 * @priv: iSMT private data
286 */
287 static void ismt_submit_desc(struct ismt_priv *priv)
288 {
289 uint fmhp;
290 uint val;
291
292 ismt_desc_dump(priv);
293 ismt_gen_reg_dump(priv);
294 ismt_mstr_reg_dump(priv);
295
296 /* Set the FMHP (Firmware Master Head Pointer)*/
297 fmhp = ((priv->head + 1) % ISMT_DESC_ENTRIES) << 16;
298 val = readl(priv->smba + ISMT_MSTR_MCTRL);
299 writel((val & ~ISMT_MCTRL_FMHP) | fmhp,
300 priv->smba + ISMT_MSTR_MCTRL);
301
302 /* Set the start bit */
303 val = readl(priv->smba + ISMT_MSTR_MCTRL);
304 writel(val | ISMT_MCTRL_SS,
305 priv->smba + ISMT_MSTR_MCTRL);
306 }
307
308 /**
309 * ismt_process_desc() - handle the completion of the descriptor
310 * @desc: the iSMT hardware descriptor
311 * @data: data buffer from the upper layer
312 * @priv: ismt_priv struct holding our dma buffer
313 * @size: SMBus transaction type
314 * @read_write: flag to indicate if this is a read or write
315 */
316 static int ismt_process_desc(const struct ismt_desc *desc,
317 union i2c_smbus_data *data,
318 struct ismt_priv *priv, int size,
319 char read_write)
320 {
321 u8 *dma_buffer = priv->dma_buffer;
322
323 dev_dbg(&priv->pci_dev->dev, "Processing completed descriptor\n");
324 __ismt_desc_dump(&priv->pci_dev->dev, desc);
325
326 if (desc->status & ISMT_DESC_SCS) {
327 if (read_write == I2C_SMBUS_WRITE &&
328 size != I2C_SMBUS_PROC_CALL)
329 return 0;
330
331 switch (size) {
332 case I2C_SMBUS_BYTE:
333 case I2C_SMBUS_BYTE_DATA:
334 data->byte = dma_buffer[0];
335 break;
336 case I2C_SMBUS_WORD_DATA:
337 case I2C_SMBUS_PROC_CALL:
338 data->word = dma_buffer[0] | (dma_buffer[1] << 8);
339 break;
340 case I2C_SMBUS_BLOCK_DATA:
341 case I2C_SMBUS_I2C_BLOCK_DATA:
342 memcpy(&data->block[1], dma_buffer, desc->rxbytes);
343 data->block[0] = desc->rxbytes;
344 break;
345 }
346 return 0;
347 }
348
349 if (likely(desc->status & ISMT_DESC_NAK))
350 return -ENXIO;
351
352 if (desc->status & ISMT_DESC_CRC)
353 return -EBADMSG;
354
355 if (desc->status & ISMT_DESC_COL)
356 return -EAGAIN;
357
358 if (desc->status & ISMT_DESC_LPR)
359 return -EPROTO;
360
361 if (desc->status & (ISMT_DESC_DLTO | ISMT_DESC_CLTO))
362 return -ETIMEDOUT;
363
364 return -EIO;
365 }
366
367 /**
368 * ismt_access() - process an SMBus command
369 * @adap: the i2c host adapter
370 * @addr: address of the i2c/SMBus target
371 * @flags: command options
372 * @read_write: read from or write to device
373 * @command: the i2c/SMBus command to issue
374 * @size: SMBus transaction type
375 * @data: read/write data buffer
376 */
377 static int ismt_access(struct i2c_adapter *adap, u16 addr,
378 unsigned short flags, char read_write, u8 command,
379 int size, union i2c_smbus_data *data)
380 {
381 int ret;
382 unsigned long time_left;
383 dma_addr_t dma_addr = 0; /* address of the data buffer */
384 u8 dma_size = 0;
385 enum dma_data_direction dma_direction = 0;
386 struct ismt_desc *desc;
387 struct ismt_priv *priv = i2c_get_adapdata(adap);
388 struct device *dev = &priv->pci_dev->dev;
389
390 desc = &priv->hw[priv->head];
391
392 /* Initialize the DMA buffer */
393 memset(priv->dma_buffer, 0, sizeof(priv->dma_buffer));
394
395 /* Initialize the descriptor */
396 memset(desc, 0, sizeof(struct ismt_desc));
397 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, read_write);
398
399 /* Initialize common control bits */
400 if (likely(pci_dev_msi_enabled(priv->pci_dev)))
401 desc->control = ISMT_DESC_INT | ISMT_DESC_FAIR;
402 else
403 desc->control = ISMT_DESC_FAIR;
404
405 if ((flags & I2C_CLIENT_PEC) && (size != I2C_SMBUS_QUICK)
406 && (size != I2C_SMBUS_I2C_BLOCK_DATA))
407 desc->control |= ISMT_DESC_PEC;
408
409 switch (size) {
410 case I2C_SMBUS_QUICK:
411 dev_dbg(dev, "I2C_SMBUS_QUICK\n");
412 break;
413
414 case I2C_SMBUS_BYTE:
415 if (read_write == I2C_SMBUS_WRITE) {
416 /*
417 * Send Byte
418 * The command field contains the write data
419 */
420 dev_dbg(dev, "I2C_SMBUS_BYTE: WRITE\n");
421 desc->control |= ISMT_DESC_CWRL;
422 desc->wr_len_cmd = command;
423 } else {
424 /* Receive Byte */
425 dev_dbg(dev, "I2C_SMBUS_BYTE: READ\n");
426 dma_size = 1;
427 dma_direction = DMA_FROM_DEVICE;
428 desc->rd_len = 1;
429 }
430 break;
431
432 case I2C_SMBUS_BYTE_DATA:
433 if (read_write == I2C_SMBUS_WRITE) {
434 /*
435 * Write Byte
436 * Command plus 1 data byte
437 */
438 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: WRITE\n");
439 desc->wr_len_cmd = 2;
440 dma_size = 2;
441 dma_direction = DMA_TO_DEVICE;
442 priv->dma_buffer[0] = command;
443 priv->dma_buffer[1] = data->byte;
444 } else {
445 /* Read Byte */
446 dev_dbg(dev, "I2C_SMBUS_BYTE_DATA: READ\n");
447 desc->control |= ISMT_DESC_CWRL;
448 desc->wr_len_cmd = command;
449 desc->rd_len = 1;
450 dma_size = 1;
451 dma_direction = DMA_FROM_DEVICE;
452 }
453 break;
454
455 case I2C_SMBUS_WORD_DATA:
456 if (read_write == I2C_SMBUS_WRITE) {
457 /* Write Word */
458 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: WRITE\n");
459 desc->wr_len_cmd = 3;
460 dma_size = 3;
461 dma_direction = DMA_TO_DEVICE;
462 priv->dma_buffer[0] = command;
463 priv->dma_buffer[1] = data->word & 0xff;
464 priv->dma_buffer[2] = data->word >> 8;
465 } else {
466 /* Read Word */
467 dev_dbg(dev, "I2C_SMBUS_WORD_DATA: READ\n");
468 desc->wr_len_cmd = command;
469 desc->control |= ISMT_DESC_CWRL;
470 desc->rd_len = 2;
471 dma_size = 2;
472 dma_direction = DMA_FROM_DEVICE;
473 }
474 break;
475
476 case I2C_SMBUS_PROC_CALL:
477 dev_dbg(dev, "I2C_SMBUS_PROC_CALL\n");
478 desc->wr_len_cmd = 3;
479 desc->rd_len = 2;
480 dma_size = 3;
481 dma_direction = DMA_BIDIRECTIONAL;
482 priv->dma_buffer[0] = command;
483 priv->dma_buffer[1] = data->word & 0xff;
484 priv->dma_buffer[2] = data->word >> 8;
485 break;
486
487 case I2C_SMBUS_BLOCK_DATA:
488 if (read_write == I2C_SMBUS_WRITE) {
489 /* Block Write */
490 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: WRITE\n");
491 dma_size = data->block[0] + 1;
492 dma_direction = DMA_TO_DEVICE;
493 desc->wr_len_cmd = dma_size;
494 desc->control |= ISMT_DESC_BLK;
495 priv->dma_buffer[0] = command;
496 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
497 } else {
498 /* Block Read */
499 dev_dbg(dev, "I2C_SMBUS_BLOCK_DATA: READ\n");
500 dma_size = I2C_SMBUS_BLOCK_MAX;
501 dma_direction = DMA_FROM_DEVICE;
502 desc->rd_len = dma_size;
503 desc->wr_len_cmd = command;
504 desc->control |= (ISMT_DESC_BLK | ISMT_DESC_CWRL);
505 }
506 break;
507
508 case I2C_SMBUS_I2C_BLOCK_DATA:
509 /* Make sure the length is valid */
510 if (data->block[0] < 1)
511 data->block[0] = 1;
512
513 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
514 data->block[0] = I2C_SMBUS_BLOCK_MAX;
515
516 if (read_write == I2C_SMBUS_WRITE) {
517 /* i2c Block Write */
518 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: WRITE\n");
519 dma_size = data->block[0] + 1;
520 dma_direction = DMA_TO_DEVICE;
521 desc->wr_len_cmd = dma_size;
522 desc->control |= ISMT_DESC_I2C;
523 priv->dma_buffer[0] = command;
524 memcpy(&priv->dma_buffer[1], &data->block[1], dma_size - 1);
525 } else {
526 /* i2c Block Read */
527 dev_dbg(dev, "I2C_SMBUS_I2C_BLOCK_DATA: READ\n");
528 dma_size = data->block[0];
529 dma_direction = DMA_FROM_DEVICE;
530 desc->rd_len = dma_size;
531 desc->wr_len_cmd = command;
532 desc->control |= (ISMT_DESC_I2C | ISMT_DESC_CWRL);
533 /*
534 * Per the "Table 15-15. I2C Commands",
535 * in the External Design Specification (EDS),
536 * (Document Number: 508084, Revision: 2.0),
537 * the _rw bit must be 0
538 */
539 desc->tgtaddr_rw = ISMT_DESC_ADDR_RW(addr, 0);
540 }
541 break;
542
543 default:
544 dev_err(dev, "Unsupported transaction %d\n",
545 size);
546 return -EOPNOTSUPP;
547 }
548
549 /* map the data buffer */
550 if (dma_size != 0) {
551 dev_dbg(dev, " dev=%p\n", dev);
552 dev_dbg(dev, " data=%p\n", data);
553 dev_dbg(dev, " dma_buffer=%p\n", priv->dma_buffer);
554 dev_dbg(dev, " dma_size=%d\n", dma_size);
555 dev_dbg(dev, " dma_direction=%d\n", dma_direction);
556
557 dma_addr = dma_map_single(dev,
558 priv->dma_buffer,
559 dma_size,
560 dma_direction);
561
562 if (dma_mapping_error(dev, dma_addr)) {
563 dev_err(dev, "Error in mapping dma buffer %p\n",
564 priv->dma_buffer);
565 return -EIO;
566 }
567
568 dev_dbg(dev, " dma_addr = 0x%016llX\n",
569 (unsigned long long)dma_addr);
570
571 desc->dptr_low = lower_32_bits(dma_addr);
572 desc->dptr_high = upper_32_bits(dma_addr);
573 }
574
575 reinit_completion(&priv->cmp);
576
577 /* Add the descriptor */
578 ismt_submit_desc(priv);
579
580 /* Now we wait for interrupt completion, 1s */
581 time_left = wait_for_completion_timeout(&priv->cmp, HZ*1);
582
583 /* unmap the data buffer */
584 if (dma_size != 0)
585 dma_unmap_single(&adap->dev, dma_addr, dma_size, dma_direction);
586
587 if (unlikely(!time_left)) {
588 dev_err(dev, "completion wait timed out\n");
589 ret = -ETIMEDOUT;
590 goto out;
591 }
592
593 /* do any post processing of the descriptor here */
594 ret = ismt_process_desc(desc, data, priv, size, read_write);
595
596 out:
597 /* Update the ring pointer */
598 priv->head++;
599 priv->head %= ISMT_DESC_ENTRIES;
600
601 return ret;
602 }
603
604 /**
605 * ismt_func() - report which i2c commands are supported by this adapter
606 * @adap: the i2c host adapter
607 */
608 static u32 ismt_func(struct i2c_adapter *adap)
609 {
610 return I2C_FUNC_SMBUS_QUICK |
611 I2C_FUNC_SMBUS_BYTE |
612 I2C_FUNC_SMBUS_BYTE_DATA |
613 I2C_FUNC_SMBUS_WORD_DATA |
614 I2C_FUNC_SMBUS_PROC_CALL |
615 I2C_FUNC_SMBUS_BLOCK_DATA |
616 I2C_FUNC_SMBUS_I2C_BLOCK |
617 I2C_FUNC_SMBUS_PEC;
618 }
619
620 /**
621 * smbus_algorithm - the adapter algorithm and supported functionality
622 * @smbus_xfer: the adapter algorithm
623 * @functionality: functionality supported by the adapter
624 */
625 static const struct i2c_algorithm smbus_algorithm = {
626 .smbus_xfer = ismt_access,
627 .functionality = ismt_func,
628 };
629
630 /**
631 * ismt_handle_isr() - interrupt handler bottom half
632 * @priv: iSMT private data
633 */
634 static irqreturn_t ismt_handle_isr(struct ismt_priv *priv)
635 {
636 complete(&priv->cmp);
637
638 return IRQ_HANDLED;
639 }
640
641
642 /**
643 * ismt_do_interrupt() - IRQ interrupt handler
644 * @vec: interrupt vector
645 * @data: iSMT private data
646 */
647 static irqreturn_t ismt_do_interrupt(int vec, void *data)
648 {
649 u32 val;
650 struct ismt_priv *priv = data;
651
652 /*
653 * check to see it's our interrupt, return IRQ_NONE if not ours
654 * since we are sharing interrupt
655 */
656 val = readl(priv->smba + ISMT_MSTR_MSTS);
657
658 if (!(val & (ISMT_MSTS_MIS | ISMT_MSTS_MEIS)))
659 return IRQ_NONE;
660 else
661 writel(val | ISMT_MSTS_MIS | ISMT_MSTS_MEIS,
662 priv->smba + ISMT_MSTR_MSTS);
663
664 return ismt_handle_isr(priv);
665 }
666
667 /**
668 * ismt_do_msi_interrupt() - MSI interrupt handler
669 * @vec: interrupt vector
670 * @data: iSMT private data
671 */
672 static irqreturn_t ismt_do_msi_interrupt(int vec, void *data)
673 {
674 return ismt_handle_isr(data);
675 }
676
677 /**
678 * ismt_hw_init() - initialize the iSMT hardware
679 * @priv: iSMT private data
680 */
681 static void ismt_hw_init(struct ismt_priv *priv)
682 {
683 u32 val;
684 struct device *dev = &priv->pci_dev->dev;
685
686 /* initialize the Master Descriptor Base Address (MDBA) */
687 writeq(priv->io_rng_dma, priv->smba + ISMT_MSTR_MDBA);
688
689 /* initialize the Master Control Register (MCTRL) */
690 writel(ISMT_MCTRL_MEIE, priv->smba + ISMT_MSTR_MCTRL);
691
692 /* initialize the Master Status Register (MSTS) */
693 writel(0, priv->smba + ISMT_MSTR_MSTS);
694
695 /* initialize the Master Descriptor Size (MDS) */
696 val = readl(priv->smba + ISMT_MSTR_MDS);
697 writel((val & ~ISMT_MDS_MASK) | (ISMT_DESC_ENTRIES - 1),
698 priv->smba + ISMT_MSTR_MDS);
699
700 /*
701 * Set the SMBus speed (could use this for slow HW debuggers)
702 */
703
704 val = readl(priv->smba + ISMT_SPGT);
705
706 switch (bus_speed) {
707 case 0:
708 break;
709
710 case 80:
711 dev_dbg(dev, "Setting SMBus clock to 80 kHz\n");
712 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_80K),
713 priv->smba + ISMT_SPGT);
714 break;
715
716 case 100:
717 dev_dbg(dev, "Setting SMBus clock to 100 kHz\n");
718 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_100K),
719 priv->smba + ISMT_SPGT);
720 break;
721
722 case 400:
723 dev_dbg(dev, "Setting SMBus clock to 400 kHz\n");
724 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_400K),
725 priv->smba + ISMT_SPGT);
726 break;
727
728 case 1000:
729 dev_dbg(dev, "Setting SMBus clock to 1000 kHz\n");
730 writel(((val & ~ISMT_SPGT_SPD_MASK) | ISMT_SPGT_SPD_1M),
731 priv->smba + ISMT_SPGT);
732 break;
733
734 default:
735 dev_warn(dev, "Invalid SMBus clock speed, only 0, 80, 100, 400, and 1000 are valid\n");
736 break;
737 }
738
739 val = readl(priv->smba + ISMT_SPGT);
740
741 switch (val & ISMT_SPGT_SPD_MASK) {
742 case ISMT_SPGT_SPD_80K:
743 bus_speed = 80;
744 break;
745 case ISMT_SPGT_SPD_100K:
746 bus_speed = 100;
747 break;
748 case ISMT_SPGT_SPD_400K:
749 bus_speed = 400;
750 break;
751 case ISMT_SPGT_SPD_1M:
752 bus_speed = 1000;
753 break;
754 }
755 dev_dbg(dev, "SMBus clock is running at %d kHz\n", bus_speed);
756 }
757
758 /**
759 * ismt_dev_init() - initialize the iSMT data structures
760 * @priv: iSMT private data
761 */
762 static int ismt_dev_init(struct ismt_priv *priv)
763 {
764 /* allocate memory for the descriptor */
765 priv->hw = dmam_alloc_coherent(&priv->pci_dev->dev,
766 (ISMT_DESC_ENTRIES
767 * sizeof(struct ismt_desc)),
768 &priv->io_rng_dma,
769 GFP_KERNEL);
770 if (!priv->hw)
771 return -ENOMEM;
772
773 memset(priv->hw, 0, (ISMT_DESC_ENTRIES * sizeof(struct ismt_desc)));
774
775 priv->head = 0;
776 init_completion(&priv->cmp);
777
778 return 0;
779 }
780
781 /**
782 * ismt_int_init() - initialize interrupts
783 * @priv: iSMT private data
784 */
785 static int ismt_int_init(struct ismt_priv *priv)
786 {
787 int err;
788
789 /* Try using MSI interrupts */
790 err = pci_enable_msi(priv->pci_dev);
791 if (err)
792 goto intx;
793
794 err = devm_request_irq(&priv->pci_dev->dev,
795 priv->pci_dev->irq,
796 ismt_do_msi_interrupt,
797 0,
798 "ismt-msi",
799 priv);
800 if (err) {
801 pci_disable_msi(priv->pci_dev);
802 goto intx;
803 }
804
805 return 0;
806
807 /* Try using legacy interrupts */
808 intx:
809 dev_warn(&priv->pci_dev->dev,
810 "Unable to use MSI interrupts, falling back to legacy\n");
811
812 err = devm_request_irq(&priv->pci_dev->dev,
813 priv->pci_dev->irq,
814 ismt_do_interrupt,
815 IRQF_SHARED,
816 "ismt-intx",
817 priv);
818 if (err) {
819 dev_err(&priv->pci_dev->dev, "no usable interrupts\n");
820 return err;
821 }
822
823 return 0;
824 }
825
826 static struct pci_driver ismt_driver;
827
828 /**
829 * ismt_probe() - probe for iSMT devices
830 * @pdev: PCI-Express device
831 * @id: PCI-Express device ID
832 */
833 static int
834 ismt_probe(struct pci_dev *pdev, const struct pci_device_id *id)
835 {
836 int err;
837 struct ismt_priv *priv;
838 unsigned long start, len;
839
840 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
841 if (!priv)
842 return -ENOMEM;
843
844 pci_set_drvdata(pdev, priv);
845
846 i2c_set_adapdata(&priv->adapter, priv);
847 priv->adapter.owner = THIS_MODULE;
848 priv->adapter.class = I2C_CLASS_HWMON;
849 priv->adapter.algo = &smbus_algorithm;
850 priv->adapter.dev.parent = &pdev->dev;
851 ACPI_COMPANION_SET(&priv->adapter.dev, ACPI_COMPANION(&pdev->dev));
852 priv->adapter.retries = ISMT_MAX_RETRIES;
853
854 priv->pci_dev = pdev;
855
856 err = pcim_enable_device(pdev);
857 if (err) {
858 dev_err(&pdev->dev, "Failed to enable SMBus PCI device (%d)\n",
859 err);
860 return err;
861 }
862
863 /* enable bus mastering */
864 pci_set_master(pdev);
865
866 /* Determine the address of the SMBus area */
867 start = pci_resource_start(pdev, SMBBAR);
868 len = pci_resource_len(pdev, SMBBAR);
869 if (!start || !len) {
870 dev_err(&pdev->dev,
871 "SMBus base address uninitialized, upgrade BIOS\n");
872 return -ENODEV;
873 }
874
875 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
876 "SMBus iSMT adapter at %lx", start);
877
878 dev_dbg(&priv->pci_dev->dev, " start=0x%lX\n", start);
879 dev_dbg(&priv->pci_dev->dev, " len=0x%lX\n", len);
880
881 err = acpi_check_resource_conflict(&pdev->resource[SMBBAR]);
882 if (err) {
883 dev_err(&pdev->dev, "ACPI resource conflict!\n");
884 return err;
885 }
886
887 err = pci_request_region(pdev, SMBBAR, ismt_driver.name);
888 if (err) {
889 dev_err(&pdev->dev,
890 "Failed to request SMBus region 0x%lx-0x%lx\n",
891 start, start + len);
892 return err;
893 }
894
895 priv->smba = pcim_iomap(pdev, SMBBAR, len);
896 if (!priv->smba) {
897 dev_err(&pdev->dev, "Unable to ioremap SMBus BAR\n");
898 return -ENODEV;
899 }
900
901 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(64)) != 0) ||
902 (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)) != 0)) {
903 if ((pci_set_dma_mask(pdev, DMA_BIT_MASK(32)) != 0) ||
904 (pci_set_consistent_dma_mask(pdev,
905 DMA_BIT_MASK(32)) != 0)) {
906 dev_err(&pdev->dev, "pci_set_dma_mask fail %p\n",
907 pdev);
908 return -ENODEV;
909 }
910 }
911
912 err = ismt_dev_init(priv);
913 if (err)
914 return err;
915
916 ismt_hw_init(priv);
917
918 err = ismt_int_init(priv);
919 if (err)
920 return err;
921
922 err = i2c_add_adapter(&priv->adapter);
923 if (err) {
924 dev_err(&pdev->dev, "Failed to add SMBus iSMT adapter\n");
925 return -ENODEV;
926 }
927 return 0;
928 }
929
930 /**
931 * ismt_remove() - release driver resources
932 * @pdev: PCI-Express device
933 */
934 static void ismt_remove(struct pci_dev *pdev)
935 {
936 struct ismt_priv *priv = pci_get_drvdata(pdev);
937
938 i2c_del_adapter(&priv->adapter);
939 }
940
941 static struct pci_driver ismt_driver = {
942 .name = "ismt_smbus",
943 .id_table = ismt_ids,
944 .probe = ismt_probe,
945 .remove = ismt_remove,
946 };
947
948 module_pci_driver(ismt_driver);
949
950 MODULE_LICENSE("Dual BSD/GPL");
951 MODULE_AUTHOR("Bill E. Brown <bill.e.brown@intel.com>");
952 MODULE_DESCRIPTION("Intel SMBus Message Transport (iSMT) driver");
Linux with added FPC-III support