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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / i2c / busses / i2c-mt65xx.c
blob453358b4d9ca7af7a6754c698d8dd51ddba286f6
1 /*
2 * Copyright (c) 2014 MediaTek Inc.
3 * Author: Xudong Chen <xudong.chen@mediatek.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/completion.h>
17 #include <linux/delay.h>
18 #include <linux/device.h>
19 #include <linux/dma-mapping.h>
20 #include <linux/err.h>
21 #include <linux/errno.h>
22 #include <linux/i2c.h>
23 #include <linux/init.h>
24 #include <linux/interrupt.h>
25 #include <linux/io.h>
26 #include <linux/kernel.h>
27 #include <linux/mm.h>
28 #include <linux/module.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/platform_device.h>
32 #include <linux/scatterlist.h>
33 #include <linux/sched.h>
34 #include <linux/slab.h>
35
36 #define I2C_RS_TRANSFER (1 << 4)
37 #define I2C_HS_NACKERR (1 << 2)
38 #define I2C_ACKERR (1 << 1)
39 #define I2C_TRANSAC_COMP (1 << 0)
40 #define I2C_TRANSAC_START (1 << 0)
41 #define I2C_RS_MUL_CNFG (1 << 15)
42 #define I2C_RS_MUL_TRIG (1 << 14)
43 #define I2C_DCM_DISABLE 0x0000
44 #define I2C_IO_CONFIG_OPEN_DRAIN 0x0003
45 #define I2C_IO_CONFIG_PUSH_PULL 0x0000
46 #define I2C_SOFT_RST 0x0001
47 #define I2C_FIFO_ADDR_CLR 0x0001
48 #define I2C_DELAY_LEN 0x0002
49 #define I2C_ST_START_CON 0x8001
50 #define I2C_FS_START_CON 0x1800
51 #define I2C_TIME_CLR_VALUE 0x0000
52 #define I2C_TIME_DEFAULT_VALUE 0x0003
53 #define I2C_FS_TIME_INIT_VALUE 0x1303
54 #define I2C_WRRD_TRANAC_VALUE 0x0002
55 #define I2C_RD_TRANAC_VALUE 0x0001
56
57 #define I2C_DMA_CON_TX 0x0000
58 #define I2C_DMA_CON_RX 0x0001
59 #define I2C_DMA_START_EN 0x0001
60 #define I2C_DMA_INT_FLAG_NONE 0x0000
61 #define I2C_DMA_CLR_FLAG 0x0000
62 #define I2C_DMA_HARD_RST 0x0002
63 #define I2C_DMA_4G_MODE 0x0001
64
65 #define I2C_DEFAULT_SPEED 100000 /* hz */
66 #define MAX_FS_MODE_SPEED 400000
67 #define MAX_HS_MODE_SPEED 3400000
68 #define MAX_SAMPLE_CNT_DIV 8
69 #define MAX_STEP_CNT_DIV 64
70 #define MAX_HS_STEP_CNT_DIV 8
71
72 #define I2C_CONTROL_RS (0x1 << 1)
73 #define I2C_CONTROL_DMA_EN (0x1 << 2)
74 #define I2C_CONTROL_CLK_EXT_EN (0x1 << 3)
75 #define I2C_CONTROL_DIR_CHANGE (0x1 << 4)
76 #define I2C_CONTROL_ACKERR_DET_EN (0x1 << 5)
77 #define I2C_CONTROL_TRANSFER_LEN_CHANGE (0x1 << 6)
78 #define I2C_CONTROL_WRAPPER (0x1 << 0)
79
80 #define I2C_DRV_NAME "i2c-mt65xx"
81
82 enum DMA_REGS_OFFSET {
83 OFFSET_INT_FLAG = 0x0,
84 OFFSET_INT_EN = 0x04,
85 OFFSET_EN = 0x08,
86 OFFSET_RST = 0x0c,
87 OFFSET_CON = 0x18,
88 OFFSET_TX_MEM_ADDR = 0x1c,
89 OFFSET_RX_MEM_ADDR = 0x20,
90 OFFSET_TX_LEN = 0x24,
91 OFFSET_RX_LEN = 0x28,
92 OFFSET_TX_4G_MODE = 0x54,
93 OFFSET_RX_4G_MODE = 0x58,
94 };
95
96 enum i2c_trans_st_rs {
97 I2C_TRANS_STOP = 0,
98 I2C_TRANS_REPEATED_START,
99 };
100
101 enum mtk_trans_op {
102 I2C_MASTER_WR = 1,
103 I2C_MASTER_RD,
104 I2C_MASTER_WRRD,
105 };
106
107 enum I2C_REGS_OFFSET {
108 OFFSET_DATA_PORT = 0x0,
109 OFFSET_SLAVE_ADDR = 0x04,
110 OFFSET_INTR_MASK = 0x08,
111 OFFSET_INTR_STAT = 0x0c,
112 OFFSET_CONTROL = 0x10,
113 OFFSET_TRANSFER_LEN = 0x14,
114 OFFSET_TRANSAC_LEN = 0x18,
115 OFFSET_DELAY_LEN = 0x1c,
116 OFFSET_TIMING = 0x20,
117 OFFSET_START = 0x24,
118 OFFSET_EXT_CONF = 0x28,
119 OFFSET_FIFO_STAT = 0x30,
120 OFFSET_FIFO_THRESH = 0x34,
121 OFFSET_FIFO_ADDR_CLR = 0x38,
122 OFFSET_IO_CONFIG = 0x40,
123 OFFSET_RSV_DEBUG = 0x44,
124 OFFSET_HS = 0x48,
125 OFFSET_SOFTRESET = 0x50,
126 OFFSET_DCM_EN = 0x54,
127 OFFSET_PATH_DIR = 0x60,
128 OFFSET_DEBUGSTAT = 0x64,
129 OFFSET_DEBUGCTRL = 0x68,
130 OFFSET_TRANSFER_LEN_AUX = 0x6c,
131 };
132
133 struct mtk_i2c_compatible {
134 const struct i2c_adapter_quirks *quirks;
135 unsigned char pmic_i2c: 1;
136 unsigned char dcm: 1;
137 unsigned char auto_restart: 1;
138 unsigned char aux_len_reg: 1;
139 unsigned char support_33bits: 1;
140 };
141
142 struct mtk_i2c {
143 struct i2c_adapter adap; /* i2c host adapter */
144 struct device *dev;
145 struct completion msg_complete;
146
147 /* set in i2c probe */
148 void __iomem *base; /* i2c base addr */
149 void __iomem *pdmabase; /* dma base address*/
150 struct clk *clk_main; /* main clock for i2c bus */
151 struct clk *clk_dma; /* DMA clock for i2c via DMA */
152 struct clk *clk_pmic; /* PMIC clock for i2c from PMIC */
153 bool have_pmic; /* can use i2c pins from PMIC */
154 bool use_push_pull; /* IO config push-pull mode */
155
156 u16 irq_stat; /* interrupt status */
157 unsigned int speed_hz; /* The speed in transfer */
158 enum mtk_trans_op op;
159 u16 timing_reg;
160 u16 high_speed_reg;
161 unsigned char auto_restart;
162 bool ignore_restart_irq;
163 const struct mtk_i2c_compatible *dev_comp;
164 };
165
166 static const struct i2c_adapter_quirks mt6577_i2c_quirks = {
167 .flags = I2C_AQ_COMB_WRITE_THEN_READ,
168 .max_num_msgs = 1,
169 .max_write_len = 255,
170 .max_read_len = 255,
171 .max_comb_1st_msg_len = 255,
172 .max_comb_2nd_msg_len = 31,
173 };
174
175 static const struct i2c_adapter_quirks mt8173_i2c_quirks = {
176 .max_num_msgs = 65535,
177 .max_write_len = 65535,
178 .max_read_len = 65535,
179 .max_comb_1st_msg_len = 65535,
180 .max_comb_2nd_msg_len = 65535,
181 };
182
183 static const struct mtk_i2c_compatible mt6577_compat = {
184 .quirks = &mt6577_i2c_quirks,
185 .pmic_i2c = 0,
186 .dcm = 1,
187 .auto_restart = 0,
188 .aux_len_reg = 0,
189 .support_33bits = 0,
190 };
191
192 static const struct mtk_i2c_compatible mt6589_compat = {
193 .quirks = &mt6577_i2c_quirks,
194 .pmic_i2c = 1,
195 .dcm = 0,
196 .auto_restart = 0,
197 .aux_len_reg = 0,
198 .support_33bits = 0,
199 };
200
201 static const struct mtk_i2c_compatible mt8173_compat = {
202 .quirks = &mt8173_i2c_quirks,
203 .pmic_i2c = 0,
204 .dcm = 1,
205 .auto_restart = 1,
206 .aux_len_reg = 1,
207 .support_33bits = 1,
208 };
209
210 static const struct of_device_id mtk_i2c_of_match[] = {
211 { .compatible = "mediatek,mt6577-i2c", .data = &mt6577_compat },
212 { .compatible = "mediatek,mt6589-i2c", .data = &mt6589_compat },
213 { .compatible = "mediatek,mt8173-i2c", .data = &mt8173_compat },
214 {}
215 };
216 MODULE_DEVICE_TABLE(of, mtk_i2c_of_match);
217
218 static int mtk_i2c_clock_enable(struct mtk_i2c *i2c)
219 {
220 int ret;
221
222 ret = clk_prepare_enable(i2c->clk_dma);
223 if (ret)
224 return ret;
225
226 ret = clk_prepare_enable(i2c->clk_main);
227 if (ret)
228 goto err_main;
229
230 if (i2c->have_pmic) {
231 ret = clk_prepare_enable(i2c->clk_pmic);
232 if (ret)
233 goto err_pmic;
234 }
235 return 0;
236
237 err_pmic:
238 clk_disable_unprepare(i2c->clk_main);
239 err_main:
240 clk_disable_unprepare(i2c->clk_dma);
241
242 return ret;
243 }
244
245 static void mtk_i2c_clock_disable(struct mtk_i2c *i2c)
246 {
247 if (i2c->have_pmic)
248 clk_disable_unprepare(i2c->clk_pmic);
249
250 clk_disable_unprepare(i2c->clk_main);
251 clk_disable_unprepare(i2c->clk_dma);
252 }
253
254 static void mtk_i2c_init_hw(struct mtk_i2c *i2c)
255 {
256 u16 control_reg;
257
258 writew(I2C_SOFT_RST, i2c->base + OFFSET_SOFTRESET);
259
260 /* Set ioconfig */
261 if (i2c->use_push_pull)
262 writew(I2C_IO_CONFIG_PUSH_PULL, i2c->base + OFFSET_IO_CONFIG);
263 else
264 writew(I2C_IO_CONFIG_OPEN_DRAIN, i2c->base + OFFSET_IO_CONFIG);
265
266 if (i2c->dev_comp->dcm)
267 writew(I2C_DCM_DISABLE, i2c->base + OFFSET_DCM_EN);
268
269 writew(i2c->timing_reg, i2c->base + OFFSET_TIMING);
270 writew(i2c->high_speed_reg, i2c->base + OFFSET_HS);
271
272 /* If use i2c pin from PMIC mt6397 side, need set PATH_DIR first */
273 if (i2c->have_pmic)
274 writew(I2C_CONTROL_WRAPPER, i2c->base + OFFSET_PATH_DIR);
275
276 control_reg = I2C_CONTROL_ACKERR_DET_EN |
277 I2C_CONTROL_CLK_EXT_EN | I2C_CONTROL_DMA_EN;
278 writew(control_reg, i2c->base + OFFSET_CONTROL);
279 writew(I2C_DELAY_LEN, i2c->base + OFFSET_DELAY_LEN);
280
281 writel(I2C_DMA_HARD_RST, i2c->pdmabase + OFFSET_RST);
282 udelay(50);
283 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_RST);
284 }
285
286 /*
287 * Calculate i2c port speed
288 *
289 * Hardware design:
290 * i2c_bus_freq = parent_clk / (clock_div * 2 * sample_cnt * step_cnt)
291 * clock_div: fixed in hardware, but may be various in different SoCs
292 *
293 * The calculation want to pick the highest bus frequency that is still
294 * less than or equal to i2c->speed_hz. The calculation try to get
295 * sample_cnt and step_cn
296 */
297 static int mtk_i2c_set_speed(struct mtk_i2c *i2c, unsigned int parent_clk,
298 unsigned int clock_div)
299 {
300 unsigned int clk_src;
301 unsigned int step_cnt;
302 unsigned int sample_cnt;
303 unsigned int max_step_cnt;
304 unsigned int target_speed;
305 unsigned int base_sample_cnt = MAX_SAMPLE_CNT_DIV;
306 unsigned int base_step_cnt;
307 unsigned int opt_div;
308 unsigned int best_mul;
309 unsigned int cnt_mul;
310
311 clk_src = parent_clk / clock_div;
312 target_speed = i2c->speed_hz;
313
314 if (target_speed > MAX_HS_MODE_SPEED)
315 target_speed = MAX_HS_MODE_SPEED;
316
317 if (target_speed > MAX_FS_MODE_SPEED)
318 max_step_cnt = MAX_HS_STEP_CNT_DIV;
319 else
320 max_step_cnt = MAX_STEP_CNT_DIV;
321
322 base_step_cnt = max_step_cnt;
323 /* Find the best combination */
324 opt_div = DIV_ROUND_UP(clk_src >> 1, target_speed);
325 best_mul = MAX_SAMPLE_CNT_DIV * max_step_cnt;
326
327 /* Search for the best pair (sample_cnt, step_cnt) with
328 * 0 < sample_cnt < MAX_SAMPLE_CNT_DIV
329 * 0 < step_cnt < max_step_cnt
330 * sample_cnt * step_cnt >= opt_div
331 * optimizing for sample_cnt * step_cnt being minimal
332 */
333 for (sample_cnt = 1; sample_cnt <= MAX_SAMPLE_CNT_DIV; sample_cnt++) {
334 step_cnt = DIV_ROUND_UP(opt_div, sample_cnt);
335 cnt_mul = step_cnt * sample_cnt;
336 if (step_cnt > max_step_cnt)
337 continue;
338
339 if (cnt_mul < best_mul) {
340 best_mul = cnt_mul;
341 base_sample_cnt = sample_cnt;
342 base_step_cnt = step_cnt;
343 if (best_mul == opt_div)
344 break;
345 }
346 }
347
348 sample_cnt = base_sample_cnt;
349 step_cnt = base_step_cnt;
350
351 if ((clk_src / (2 * sample_cnt * step_cnt)) > target_speed) {
352 /* In this case, hardware can't support such
353 * low i2c_bus_freq
354 */
355 dev_dbg(i2c->dev, "Unsupported speed (%uhz)\n", target_speed);
356 return -EINVAL;
357 }
358
359 step_cnt--;
360 sample_cnt--;
361
362 if (target_speed > MAX_FS_MODE_SPEED) {
363 /* Set the high speed mode register */
364 i2c->timing_reg = I2C_FS_TIME_INIT_VALUE;
365 i2c->high_speed_reg = I2C_TIME_DEFAULT_VALUE |
366 (sample_cnt << 12) | (step_cnt << 8);
367 } else {
368 i2c->timing_reg = (sample_cnt << 8) | (step_cnt << 0);
369 /* Disable the high speed transaction */
370 i2c->high_speed_reg = I2C_TIME_CLR_VALUE;
371 }
372
373 return 0;
374 }
375
376 static inline u32 mtk_i2c_set_4g_mode(dma_addr_t addr)
377 {
378 return (addr & BIT_ULL(32)) ? I2C_DMA_4G_MODE : I2C_DMA_CLR_FLAG;
379 }
380
381 static int mtk_i2c_do_transfer(struct mtk_i2c *i2c, struct i2c_msg *msgs,
382 int num, int left_num)
383 {
384 u16 addr_reg;
385 u16 start_reg;
386 u16 control_reg;
387 u16 restart_flag = 0;
388 u32 reg_4g_mode;
389 dma_addr_t rpaddr = 0;
390 dma_addr_t wpaddr = 0;
391 int ret;
392
393 i2c->irq_stat = 0;
394
395 if (i2c->auto_restart)
396 restart_flag = I2C_RS_TRANSFER;
397
398 reinit_completion(&i2c->msg_complete);
399
400 control_reg = readw(i2c->base + OFFSET_CONTROL) &
401 ~(I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS);
402 if ((i2c->speed_hz > 400000) || (left_num >= 1))
403 control_reg |= I2C_CONTROL_RS;
404
405 if (i2c->op == I2C_MASTER_WRRD)
406 control_reg |= I2C_CONTROL_DIR_CHANGE | I2C_CONTROL_RS;
407
408 writew(control_reg, i2c->base + OFFSET_CONTROL);
409
410 /* set start condition */
411 if (i2c->speed_hz <= 100000)
412 writew(I2C_ST_START_CON, i2c->base + OFFSET_EXT_CONF);
413 else
414 writew(I2C_FS_START_CON, i2c->base + OFFSET_EXT_CONF);
415
416 addr_reg = msgs->addr << 1;
417 if (i2c->op == I2C_MASTER_RD)
418 addr_reg |= 0x1;
419
420 writew(addr_reg, i2c->base + OFFSET_SLAVE_ADDR);
421
422 /* Clear interrupt status */
423 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
424 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_STAT);
425 writew(I2C_FIFO_ADDR_CLR, i2c->base + OFFSET_FIFO_ADDR_CLR);
426
427 /* Enable interrupt */
428 writew(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
429 I2C_TRANSAC_COMP, i2c->base + OFFSET_INTR_MASK);
430
431 /* Set transfer and transaction len */
432 if (i2c->op == I2C_MASTER_WRRD) {
433 if (i2c->dev_comp->aux_len_reg) {
434 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
435 writew((msgs + 1)->len, i2c->base +
436 OFFSET_TRANSFER_LEN_AUX);
437 } else {
438 writew(msgs->len | ((msgs + 1)->len) << 8,
439 i2c->base + OFFSET_TRANSFER_LEN);
440 }
441 writew(I2C_WRRD_TRANAC_VALUE, i2c->base + OFFSET_TRANSAC_LEN);
442 } else {
443 writew(msgs->len, i2c->base + OFFSET_TRANSFER_LEN);
444 writew(num, i2c->base + OFFSET_TRANSAC_LEN);
445 }
446
447 /* Prepare buffer data to start transfer */
448 if (i2c->op == I2C_MASTER_RD) {
449 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
450 writel(I2C_DMA_CON_RX, i2c->pdmabase + OFFSET_CON);
451 rpaddr = dma_map_single(i2c->dev, msgs->buf,
452 msgs->len, DMA_FROM_DEVICE);
453 if (dma_mapping_error(i2c->dev, rpaddr))
454 return -ENOMEM;
455
456 if (i2c->dev_comp->support_33bits) {
457 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
458 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
459 }
460
461 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
462 writel(msgs->len, i2c->pdmabase + OFFSET_RX_LEN);
463 } else if (i2c->op == I2C_MASTER_WR) {
464 writel(I2C_DMA_INT_FLAG_NONE, i2c->pdmabase + OFFSET_INT_FLAG);
465 writel(I2C_DMA_CON_TX, i2c->pdmabase + OFFSET_CON);
466 wpaddr = dma_map_single(i2c->dev, msgs->buf,
467 msgs->len, DMA_TO_DEVICE);
468 if (dma_mapping_error(i2c->dev, wpaddr))
469 return -ENOMEM;
470
471 if (i2c->dev_comp->support_33bits) {
472 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
473 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
474 }
475
476 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
477 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
478 } else {
479 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_INT_FLAG);
480 writel(I2C_DMA_CLR_FLAG, i2c->pdmabase + OFFSET_CON);
481 wpaddr = dma_map_single(i2c->dev, msgs->buf,
482 msgs->len, DMA_TO_DEVICE);
483 if (dma_mapping_error(i2c->dev, wpaddr))
484 return -ENOMEM;
485 rpaddr = dma_map_single(i2c->dev, (msgs + 1)->buf,
486 (msgs + 1)->len,
487 DMA_FROM_DEVICE);
488 if (dma_mapping_error(i2c->dev, rpaddr)) {
489 dma_unmap_single(i2c->dev, wpaddr,
490 msgs->len, DMA_TO_DEVICE);
491 return -ENOMEM;
492 }
493
494 if (i2c->dev_comp->support_33bits) {
495 reg_4g_mode = mtk_i2c_set_4g_mode(wpaddr);
496 writel(reg_4g_mode, i2c->pdmabase + OFFSET_TX_4G_MODE);
497
498 reg_4g_mode = mtk_i2c_set_4g_mode(rpaddr);
499 writel(reg_4g_mode, i2c->pdmabase + OFFSET_RX_4G_MODE);
500 }
501
502 writel((u32)wpaddr, i2c->pdmabase + OFFSET_TX_MEM_ADDR);
503 writel((u32)rpaddr, i2c->pdmabase + OFFSET_RX_MEM_ADDR);
504 writel(msgs->len, i2c->pdmabase + OFFSET_TX_LEN);
505 writel((msgs + 1)->len, i2c->pdmabase + OFFSET_RX_LEN);
506 }
507
508 writel(I2C_DMA_START_EN, i2c->pdmabase + OFFSET_EN);
509
510 if (!i2c->auto_restart) {
511 start_reg = I2C_TRANSAC_START;
512 } else {
513 start_reg = I2C_TRANSAC_START | I2C_RS_MUL_TRIG;
514 if (left_num >= 1)
515 start_reg |= I2C_RS_MUL_CNFG;
516 }
517 writew(start_reg, i2c->base + OFFSET_START);
518
519 ret = wait_for_completion_timeout(&i2c->msg_complete,
520 i2c->adap.timeout);
521
522 /* Clear interrupt mask */
523 writew(~(restart_flag | I2C_HS_NACKERR | I2C_ACKERR |
524 I2C_TRANSAC_COMP), i2c->base + OFFSET_INTR_MASK);
525
526 if (i2c->op == I2C_MASTER_WR) {
527 dma_unmap_single(i2c->dev, wpaddr,
528 msgs->len, DMA_TO_DEVICE);
529 } else if (i2c->op == I2C_MASTER_RD) {
530 dma_unmap_single(i2c->dev, rpaddr,
531 msgs->len, DMA_FROM_DEVICE);
532 } else {
533 dma_unmap_single(i2c->dev, wpaddr, msgs->len,
534 DMA_TO_DEVICE);
535 dma_unmap_single(i2c->dev, rpaddr, (msgs + 1)->len,
536 DMA_FROM_DEVICE);
537 }
538
539 if (ret == 0) {
540 dev_dbg(i2c->dev, "addr: %x, transfer timeout\n", msgs->addr);
541 mtk_i2c_init_hw(i2c);
542 return -ETIMEDOUT;
543 }
544
545 completion_done(&i2c->msg_complete);
546
547 if (i2c->irq_stat & (I2C_HS_NACKERR | I2C_ACKERR)) {
548 dev_dbg(i2c->dev, "addr: %x, transfer ACK error\n", msgs->addr);
549 mtk_i2c_init_hw(i2c);
550 return -ENXIO;
551 }
552
553 return 0;
554 }
555
556 static int mtk_i2c_transfer(struct i2c_adapter *adap,
557 struct i2c_msg msgs[], int num)
558 {
559 int ret;
560 int left_num = num;
561 struct mtk_i2c *i2c = i2c_get_adapdata(adap);
562
563 ret = mtk_i2c_clock_enable(i2c);
564 if (ret)
565 return ret;
566
567 i2c->auto_restart = i2c->dev_comp->auto_restart;
568
569 /* checking if we can skip restart and optimize using WRRD mode */
570 if (i2c->auto_restart && num == 2) {
571 if (!(msgs[0].flags & I2C_M_RD) && (msgs[1].flags & I2C_M_RD) &&
572 msgs[0].addr == msgs[1].addr) {
573 i2c->auto_restart = 0;
574 }
575 }
576
577 if (i2c->auto_restart && num >= 2 && i2c->speed_hz > MAX_FS_MODE_SPEED)
578 /* ignore the first restart irq after the master code,
579 * otherwise the first transfer will be discarded.
580 */
581 i2c->ignore_restart_irq = true;
582 else
583 i2c->ignore_restart_irq = false;
584
585 while (left_num--) {
586 if (!msgs->buf) {
587 dev_dbg(i2c->dev, "data buffer is NULL.\n");
588 ret = -EINVAL;
589 goto err_exit;
590 }
591
592 if (msgs->flags & I2C_M_RD)
593 i2c->op = I2C_MASTER_RD;
594 else
595 i2c->op = I2C_MASTER_WR;
596
597 if (!i2c->auto_restart) {
598 if (num > 1) {
599 /* combined two messages into one transaction */
600 i2c->op = I2C_MASTER_WRRD;
601 left_num--;
602 }
603 }
604
605 /* always use DMA mode. */
606 ret = mtk_i2c_do_transfer(i2c, msgs, num, left_num);
607 if (ret < 0)
608 goto err_exit;
609
610 msgs++;
611 }
612 /* the return value is number of executed messages */
613 ret = num;
614
615 err_exit:
616 mtk_i2c_clock_disable(i2c);
617 return ret;
618 }
619
620 static irqreturn_t mtk_i2c_irq(int irqno, void *dev_id)
621 {
622 struct mtk_i2c *i2c = dev_id;
623 u16 restart_flag = 0;
624 u16 intr_stat;
625
626 if (i2c->auto_restart)
627 restart_flag = I2C_RS_TRANSFER;
628
629 intr_stat = readw(i2c->base + OFFSET_INTR_STAT);
630 writew(intr_stat, i2c->base + OFFSET_INTR_STAT);
631
632 /*
633 * when occurs ack error, i2c controller generate two interrupts
634 * first is the ack error interrupt, then the complete interrupt
635 * i2c->irq_stat need keep the two interrupt value.
636 */
637 i2c->irq_stat |= intr_stat;
638
639 if (i2c->ignore_restart_irq && (i2c->irq_stat & restart_flag)) {
640 i2c->ignore_restart_irq = false;
641 i2c->irq_stat = 0;
642 writew(I2C_RS_MUL_CNFG | I2C_RS_MUL_TRIG | I2C_TRANSAC_START,
643 i2c->base + OFFSET_START);
644 } else {
645 if (i2c->irq_stat & (I2C_TRANSAC_COMP | restart_flag))
646 complete(&i2c->msg_complete);
647 }
648
649 return IRQ_HANDLED;
650 }
651
652 static u32 mtk_i2c_functionality(struct i2c_adapter *adap)
653 {
654 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
655 }
656
657 static const struct i2c_algorithm mtk_i2c_algorithm = {
658 .master_xfer = mtk_i2c_transfer,
659 .functionality = mtk_i2c_functionality,
660 };
661
662 static int mtk_i2c_parse_dt(struct device_node *np, struct mtk_i2c *i2c,
663 unsigned int *clk_src_div)
664 {
665 int ret;
666
667 ret = of_property_read_u32(np, "clock-frequency", &i2c->speed_hz);
668 if (ret < 0)
669 i2c->speed_hz = I2C_DEFAULT_SPEED;
670
671 ret = of_property_read_u32(np, "clock-div", clk_src_div);
672 if (ret < 0)
673 return ret;
674
675 if (*clk_src_div == 0)
676 return -EINVAL;
677
678 i2c->have_pmic = of_property_read_bool(np, "mediatek,have-pmic");
679 i2c->use_push_pull =
680 of_property_read_bool(np, "mediatek,use-push-pull");
681
682 return 0;
683 }
684
685 static int mtk_i2c_probe(struct platform_device *pdev)
686 {
687 const struct of_device_id *of_id;
688 int ret = 0;
689 struct mtk_i2c *i2c;
690 struct clk *clk;
691 unsigned int clk_src_div;
692 struct resource *res;
693 int irq;
694
695 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
696 if (!i2c)
697 return -ENOMEM;
698
699 ret = mtk_i2c_parse_dt(pdev->dev.of_node, i2c, &clk_src_div);
700 if (ret)
701 return -EINVAL;
702
703 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
704 i2c->base = devm_ioremap_resource(&pdev->dev, res);
705 if (IS_ERR(i2c->base))
706 return PTR_ERR(i2c->base);
707
708 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
709 i2c->pdmabase = devm_ioremap_resource(&pdev->dev, res);
710 if (IS_ERR(i2c->pdmabase))
711 return PTR_ERR(i2c->pdmabase);
712
713 irq = platform_get_irq(pdev, 0);
714 if (irq <= 0)
715 return irq;
716
717 init_completion(&i2c->msg_complete);
718
719 of_id = of_match_node(mtk_i2c_of_match, pdev->dev.of_node);
720 if (!of_id)
721 return -EINVAL;
722
723 i2c->dev_comp = of_id->data;
724 i2c->adap.dev.of_node = pdev->dev.of_node;
725 i2c->dev = &pdev->dev;
726 i2c->adap.dev.parent = &pdev->dev;
727 i2c->adap.owner = THIS_MODULE;
728 i2c->adap.algo = &mtk_i2c_algorithm;
729 i2c->adap.quirks = i2c->dev_comp->quirks;
730 i2c->adap.timeout = 2 * HZ;
731 i2c->adap.retries = 1;
732
733 if (i2c->have_pmic && !i2c->dev_comp->pmic_i2c)
734 return -EINVAL;
735
736 i2c->clk_main = devm_clk_get(&pdev->dev, "main");
737 if (IS_ERR(i2c->clk_main)) {
738 dev_err(&pdev->dev, "cannot get main clock\n");
739 return PTR_ERR(i2c->clk_main);
740 }
741
742 i2c->clk_dma = devm_clk_get(&pdev->dev, "dma");
743 if (IS_ERR(i2c->clk_dma)) {
744 dev_err(&pdev->dev, "cannot get dma clock\n");
745 return PTR_ERR(i2c->clk_dma);
746 }
747
748 clk = i2c->clk_main;
749 if (i2c->have_pmic) {
750 i2c->clk_pmic = devm_clk_get(&pdev->dev, "pmic");
751 if (IS_ERR(i2c->clk_pmic)) {
752 dev_err(&pdev->dev, "cannot get pmic clock\n");
753 return PTR_ERR(i2c->clk_pmic);
754 }
755 clk = i2c->clk_pmic;
756 }
757
758 strlcpy(i2c->adap.name, I2C_DRV_NAME, sizeof(i2c->adap.name));
759
760 ret = mtk_i2c_set_speed(i2c, clk_get_rate(clk), clk_src_div);
761 if (ret) {
762 dev_err(&pdev->dev, "Failed to set the speed.\n");
763 return -EINVAL;
764 }
765
766 if (i2c->dev_comp->support_33bits) {
767 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(33));
768 if (ret) {
769 dev_err(&pdev->dev, "dma_set_mask return error.\n");
770 return ret;
771 }
772 }
773
774 ret = mtk_i2c_clock_enable(i2c);
775 if (ret) {
776 dev_err(&pdev->dev, "clock enable failed!\n");
777 return ret;
778 }
779 mtk_i2c_init_hw(i2c);
780 mtk_i2c_clock_disable(i2c);
781
782 ret = devm_request_irq(&pdev->dev, irq, mtk_i2c_irq,
783 IRQF_TRIGGER_NONE, I2C_DRV_NAME, i2c);
784 if (ret < 0) {
785 dev_err(&pdev->dev,
786 "Request I2C IRQ %d fail\n", irq);
787 return ret;
788 }
789
790 i2c_set_adapdata(&i2c->adap, i2c);
791 ret = i2c_add_adapter(&i2c->adap);
792 if (ret) {
793 dev_err(&pdev->dev, "Failed to add i2c bus to i2c core\n");
794 return ret;
795 }
796
797 platform_set_drvdata(pdev, i2c);
798
799 return 0;
800 }
801
802 static int mtk_i2c_remove(struct platform_device *pdev)
803 {
804 struct mtk_i2c *i2c = platform_get_drvdata(pdev);
805
806 i2c_del_adapter(&i2c->adap);
807
808 return 0;
809 }
810
811 #ifdef CONFIG_PM_SLEEP
812 static int mtk_i2c_resume(struct device *dev)
813 {
814 struct mtk_i2c *i2c = dev_get_drvdata(dev);
815
816 mtk_i2c_init_hw(i2c);
817
818 return 0;
819 }
820 #endif
821
822 static const struct dev_pm_ops mtk_i2c_pm = {
823 SET_SYSTEM_SLEEP_PM_OPS(NULL, mtk_i2c_resume)
824 };
825
826 static struct platform_driver mtk_i2c_driver = {
827 .probe = mtk_i2c_probe,
828 .remove = mtk_i2c_remove,
829 .driver = {
830 .name = I2C_DRV_NAME,
831 .pm = &mtk_i2c_pm,
832 .of_match_table = of_match_ptr(mtk_i2c_of_match),
833 },
834 };
835
836 module_platform_driver(mtk_i2c_driver);
837
838 MODULE_LICENSE("GPL v2");
839 MODULE_DESCRIPTION("MediaTek I2C Bus Driver");
840 MODULE_AUTHOR("Xudong Chen <xudong.chen@mediatek.com>");
Linux with added FPC-III support