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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / media / i2c / ov7670.c
blob56cfb5ca9c953a5ae813c36daff25a3463cea61f
1 /*
2 * A V4L2 driver for OmniVision OV7670 cameras.
3 *
4 * Copyright 2006 One Laptop Per Child Association, Inc. Written
5 * by Jonathan Corbet with substantial inspiration from Mark
6 * McClelland's ovcamchip code.
7 *
8 * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
9 *
10 * This file may be distributed under the terms of the GNU General
11 * Public License, version 2.
12 */
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/slab.h>
16 #include <linux/i2c.h>
17 #include <linux/delay.h>
18 #include <linux/videodev2.h>
19 #include <media/v4l2-device.h>
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-mediabus.h>
22 #include <media/v4l2-image-sizes.h>
23 #include <media/i2c/ov7670.h>
24
25 MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
26 MODULE_DESCRIPTION("A low-level driver for OmniVision ov7670 sensors");
27 MODULE_LICENSE("GPL");
28
29 static bool debug;
30 module_param(debug, bool, 0644);
31 MODULE_PARM_DESC(debug, "Debug level (0-1)");
32
33 /*
34 * The 7670 sits on i2c with ID 0x42
35 */
36 #define OV7670_I2C_ADDR 0x42
37
38 #define PLL_FACTOR 4
39
40 /* Registers */
41 #define REG_GAIN 0x00 /* Gain lower 8 bits (rest in vref) */
42 #define REG_BLUE 0x01 /* blue gain */
43 #define REG_RED 0x02 /* red gain */
44 #define REG_VREF 0x03 /* Pieces of GAIN, VSTART, VSTOP */
45 #define REG_COM1 0x04 /* Control 1 */
46 #define COM1_CCIR656 0x40 /* CCIR656 enable */
47 #define REG_BAVE 0x05 /* U/B Average level */
48 #define REG_GbAVE 0x06 /* Y/Gb Average level */
49 #define REG_AECHH 0x07 /* AEC MS 5 bits */
50 #define REG_RAVE 0x08 /* V/R Average level */
51 #define REG_COM2 0x09 /* Control 2 */
52 #define COM2_SSLEEP 0x10 /* Soft sleep mode */
53 #define REG_PID 0x0a /* Product ID MSB */
54 #define REG_VER 0x0b /* Product ID LSB */
55 #define REG_COM3 0x0c /* Control 3 */
56 #define COM3_SWAP 0x40 /* Byte swap */
57 #define COM3_SCALEEN 0x08 /* Enable scaling */
58 #define COM3_DCWEN 0x04 /* Enable downsamp/crop/window */
59 #define REG_COM4 0x0d /* Control 4 */
60 #define REG_COM5 0x0e /* All "reserved" */
61 #define REG_COM6 0x0f /* Control 6 */
62 #define REG_AECH 0x10 /* More bits of AEC value */
63 #define REG_CLKRC 0x11 /* Clocl control */
64 #define CLK_EXT 0x40 /* Use external clock directly */
65 #define CLK_SCALE 0x3f /* Mask for internal clock scale */
66 #define REG_COM7 0x12 /* Control 7 */
67 #define COM7_RESET 0x80 /* Register reset */
68 #define COM7_FMT_MASK 0x38
69 #define COM7_FMT_VGA 0x00
70 #define COM7_FMT_CIF 0x20 /* CIF format */
71 #define COM7_FMT_QVGA 0x10 /* QVGA format */
72 #define COM7_FMT_QCIF 0x08 /* QCIF format */
73 #define COM7_RGB 0x04 /* bits 0 and 2 - RGB format */
74 #define COM7_YUV 0x00 /* YUV */
75 #define COM7_BAYER 0x01 /* Bayer format */
76 #define COM7_PBAYER 0x05 /* "Processed bayer" */
77 #define REG_COM8 0x13 /* Control 8 */
78 #define COM8_FASTAEC 0x80 /* Enable fast AGC/AEC */
79 #define COM8_AECSTEP 0x40 /* Unlimited AEC step size */
80 #define COM8_BFILT 0x20 /* Band filter enable */
81 #define COM8_AGC 0x04 /* Auto gain enable */
82 #define COM8_AWB 0x02 /* White balance enable */
83 #define COM8_AEC 0x01 /* Auto exposure enable */
84 #define REG_COM9 0x14 /* Control 9 - gain ceiling */
85 #define REG_COM10 0x15 /* Control 10 */
86 #define COM10_HSYNC 0x40 /* HSYNC instead of HREF */
87 #define COM10_PCLK_HB 0x20 /* Suppress PCLK on horiz blank */
88 #define COM10_HREF_REV 0x08 /* Reverse HREF */
89 #define COM10_VS_LEAD 0x04 /* VSYNC on clock leading edge */
90 #define COM10_VS_NEG 0x02 /* VSYNC negative */
91 #define COM10_HS_NEG 0x01 /* HSYNC negative */
92 #define REG_HSTART 0x17 /* Horiz start high bits */
93 #define REG_HSTOP 0x18 /* Horiz stop high bits */
94 #define REG_VSTART 0x19 /* Vert start high bits */
95 #define REG_VSTOP 0x1a /* Vert stop high bits */
96 #define REG_PSHFT 0x1b /* Pixel delay after HREF */
97 #define REG_MIDH 0x1c /* Manuf. ID high */
98 #define REG_MIDL 0x1d /* Manuf. ID low */
99 #define REG_MVFP 0x1e /* Mirror / vflip */
100 #define MVFP_MIRROR 0x20 /* Mirror image */
101 #define MVFP_FLIP 0x10 /* Vertical flip */
102
103 #define REG_AEW 0x24 /* AGC upper limit */
104 #define REG_AEB 0x25 /* AGC lower limit */
105 #define REG_VPT 0x26 /* AGC/AEC fast mode op region */
106 #define REG_HSYST 0x30 /* HSYNC rising edge delay */
107 #define REG_HSYEN 0x31 /* HSYNC falling edge delay */
108 #define REG_HREF 0x32 /* HREF pieces */
109 #define REG_TSLB 0x3a /* lots of stuff */
110 #define TSLB_YLAST 0x04 /* UYVY or VYUY - see com13 */
111 #define REG_COM11 0x3b /* Control 11 */
112 #define COM11_NIGHT 0x80 /* NIght mode enable */
113 #define COM11_NMFR 0x60 /* Two bit NM frame rate */
114 #define COM11_HZAUTO 0x10 /* Auto detect 50/60 Hz */
115 #define COM11_50HZ 0x08 /* Manual 50Hz select */
116 #define COM11_EXP 0x02
117 #define REG_COM12 0x3c /* Control 12 */
118 #define COM12_HREF 0x80 /* HREF always */
119 #define REG_COM13 0x3d /* Control 13 */
120 #define COM13_GAMMA 0x80 /* Gamma enable */
121 #define COM13_UVSAT 0x40 /* UV saturation auto adjustment */
122 #define COM13_UVSWAP 0x01 /* V before U - w/TSLB */
123 #define REG_COM14 0x3e /* Control 14 */
124 #define COM14_DCWEN 0x10 /* DCW/PCLK-scale enable */
125 #define REG_EDGE 0x3f /* Edge enhancement factor */
126 #define REG_COM15 0x40 /* Control 15 */
127 #define COM15_R10F0 0x00 /* Data range 10 to F0 */
128 #define COM15_R01FE 0x80 /* 01 to FE */
129 #define COM15_R00FF 0xc0 /* 00 to FF */
130 #define COM15_RGB565 0x10 /* RGB565 output */
131 #define COM15_RGB555 0x30 /* RGB555 output */
132 #define REG_COM16 0x41 /* Control 16 */
133 #define COM16_AWBGAIN 0x08 /* AWB gain enable */
134 #define REG_COM17 0x42 /* Control 17 */
135 #define COM17_AECWIN 0xc0 /* AEC window - must match COM4 */
136 #define COM17_CBAR 0x08 /* DSP Color bar */
137
138 /*
139 * This matrix defines how the colors are generated, must be
140 * tweaked to adjust hue and saturation.
141 *
142 * Order: v-red, v-green, v-blue, u-red, u-green, u-blue
143 *
144 * They are nine-bit signed quantities, with the sign bit
145 * stored in 0x58. Sign for v-red is bit 0, and up from there.
146 */
147 #define REG_CMATRIX_BASE 0x4f
148 #define CMATRIX_LEN 6
149 #define REG_CMATRIX_SIGN 0x58
150
151
152 #define REG_BRIGHT 0x55 /* Brightness */
153 #define REG_CONTRAS 0x56 /* Contrast control */
154
155 #define REG_GFIX 0x69 /* Fix gain control */
156
157 #define REG_DBLV 0x6b /* PLL control an debugging */
158 #define DBLV_BYPASS 0x00 /* Bypass PLL */
159 #define DBLV_X4 0x01 /* clock x4 */
160 #define DBLV_X6 0x10 /* clock x6 */
161 #define DBLV_X8 0x11 /* clock x8 */
162
163 #define REG_REG76 0x76 /* OV's name */
164 #define R76_BLKPCOR 0x80 /* Black pixel correction enable */
165 #define R76_WHTPCOR 0x40 /* White pixel correction enable */
166
167 #define REG_RGB444 0x8c /* RGB 444 control */
168 #define R444_ENABLE 0x02 /* Turn on RGB444, overrides 5x5 */
169 #define R444_RGBX 0x01 /* Empty nibble at end */
170
171 #define REG_HAECC1 0x9f /* Hist AEC/AGC control 1 */
172 #define REG_HAECC2 0xa0 /* Hist AEC/AGC control 2 */
173
174 #define REG_BD50MAX 0xa5 /* 50hz banding step limit */
175 #define REG_HAECC3 0xa6 /* Hist AEC/AGC control 3 */
176 #define REG_HAECC4 0xa7 /* Hist AEC/AGC control 4 */
177 #define REG_HAECC5 0xa8 /* Hist AEC/AGC control 5 */
178 #define REG_HAECC6 0xa9 /* Hist AEC/AGC control 6 */
179 #define REG_HAECC7 0xaa /* Hist AEC/AGC control 7 */
180 #define REG_BD60MAX 0xab /* 60hz banding step limit */
181
182 enum ov7670_model {
183 MODEL_OV7670 = 0,
184 MODEL_OV7675,
185 };
186
187 struct ov7670_win_size {
188 int width;
189 int height;
190 unsigned char com7_bit;
191 int hstart; /* Start/stop values for the camera. Note */
192 int hstop; /* that they do not always make complete */
193 int vstart; /* sense to humans, but evidently the sensor */
194 int vstop; /* will do the right thing... */
195 struct regval_list *regs; /* Regs to tweak */
196 };
197
198 struct ov7670_devtype {
199 /* formats supported for each model */
200 struct ov7670_win_size *win_sizes;
201 unsigned int n_win_sizes;
202 /* callbacks for frame rate control */
203 int (*set_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
204 void (*get_framerate)(struct v4l2_subdev *, struct v4l2_fract *);
205 };
206
207 /*
208 * Information we maintain about a known sensor.
209 */
210 struct ov7670_format_struct; /* coming later */
211 struct ov7670_info {
212 struct v4l2_subdev sd;
213 struct v4l2_ctrl_handler hdl;
214 struct {
215 /* gain cluster */
216 struct v4l2_ctrl *auto_gain;
217 struct v4l2_ctrl *gain;
218 };
219 struct {
220 /* exposure cluster */
221 struct v4l2_ctrl *auto_exposure;
222 struct v4l2_ctrl *exposure;
223 };
224 struct {
225 /* saturation/hue cluster */
226 struct v4l2_ctrl *saturation;
227 struct v4l2_ctrl *hue;
228 };
229 struct ov7670_format_struct *fmt; /* Current format */
230 int min_width; /* Filter out smaller sizes */
231 int min_height; /* Filter out smaller sizes */
232 int clock_speed; /* External clock speed (MHz) */
233 u8 clkrc; /* Clock divider value */
234 bool use_smbus; /* Use smbus I/O instead of I2C */
235 bool pll_bypass;
236 bool pclk_hb_disable;
237 const struct ov7670_devtype *devtype; /* Device specifics */
238 };
239
240 static inline struct ov7670_info *to_state(struct v4l2_subdev *sd)
241 {
242 return container_of(sd, struct ov7670_info, sd);
243 }
244
245 static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
246 {
247 return &container_of(ctrl->handler, struct ov7670_info, hdl)->sd;
248 }
249
250
251
252 /*
253 * The default register settings, as obtained from OmniVision. There
254 * is really no making sense of most of these - lots of "reserved" values
255 * and such.
256 *
257 * These settings give VGA YUYV.
258 */
259
260 struct regval_list {
261 unsigned char reg_num;
262 unsigned char value;
263 };
264
265 static struct regval_list ov7670_default_regs[] = {
266 { REG_COM7, COM7_RESET },
267 /*
268 * Clock scale: 3 = 15fps
269 * 2 = 20fps
270 * 1 = 30fps
271 */
272 { REG_CLKRC, 0x1 }, /* OV: clock scale (30 fps) */
273 { REG_TSLB, 0x04 }, /* OV */
274 { REG_COM7, 0 }, /* VGA */
275 /*
276 * Set the hardware window. These values from OV don't entirely
277 * make sense - hstop is less than hstart. But they work...
278 */
279 { REG_HSTART, 0x13 }, { REG_HSTOP, 0x01 },
280 { REG_HREF, 0xb6 }, { REG_VSTART, 0x02 },
281 { REG_VSTOP, 0x7a }, { REG_VREF, 0x0a },
282
283 { REG_COM3, 0 }, { REG_COM14, 0 },
284 /* Mystery scaling numbers */
285 { 0x70, 0x3a }, { 0x71, 0x35 },
286 { 0x72, 0x11 }, { 0x73, 0xf0 },
287 { 0xa2, 0x02 }, { REG_COM10, 0x0 },
288
289 /* Gamma curve values */
290 { 0x7a, 0x20 }, { 0x7b, 0x10 },
291 { 0x7c, 0x1e }, { 0x7d, 0x35 },
292 { 0x7e, 0x5a }, { 0x7f, 0x69 },
293 { 0x80, 0x76 }, { 0x81, 0x80 },
294 { 0x82, 0x88 }, { 0x83, 0x8f },
295 { 0x84, 0x96 }, { 0x85, 0xa3 },
296 { 0x86, 0xaf }, { 0x87, 0xc4 },
297 { 0x88, 0xd7 }, { 0x89, 0xe8 },
298
299 /* AGC and AEC parameters. Note we start by disabling those features,
300 then turn them only after tweaking the values. */
301 { REG_COM8, COM8_FASTAEC | COM8_AECSTEP | COM8_BFILT },
302 { REG_GAIN, 0 }, { REG_AECH, 0 },
303 { REG_COM4, 0x40 }, /* magic reserved bit */
304 { REG_COM9, 0x18 }, /* 4x gain + magic rsvd bit */
305 { REG_BD50MAX, 0x05 }, { REG_BD60MAX, 0x07 },
306 { REG_AEW, 0x95 }, { REG_AEB, 0x33 },
307 { REG_VPT, 0xe3 }, { REG_HAECC1, 0x78 },
308 { REG_HAECC2, 0x68 }, { 0xa1, 0x03 }, /* magic */
309 { REG_HAECC3, 0xd8 }, { REG_HAECC4, 0xd8 },
310 { REG_HAECC5, 0xf0 }, { REG_HAECC6, 0x90 },
311 { REG_HAECC7, 0x94 },
312 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC },
313
314 /* Almost all of these are magic "reserved" values. */
315 { REG_COM5, 0x61 }, { REG_COM6, 0x4b },
316 { 0x16, 0x02 }, { REG_MVFP, 0x07 },
317 { 0x21, 0x02 }, { 0x22, 0x91 },
318 { 0x29, 0x07 }, { 0x33, 0x0b },
319 { 0x35, 0x0b }, { 0x37, 0x1d },
320 { 0x38, 0x71 }, { 0x39, 0x2a },
321 { REG_COM12, 0x78 }, { 0x4d, 0x40 },
322 { 0x4e, 0x20 }, { REG_GFIX, 0 },
323 { 0x6b, 0x4a }, { 0x74, 0x10 },
324 { 0x8d, 0x4f }, { 0x8e, 0 },
325 { 0x8f, 0 }, { 0x90, 0 },
326 { 0x91, 0 }, { 0x96, 0 },
327 { 0x9a, 0 }, { 0xb0, 0x84 },
328 { 0xb1, 0x0c }, { 0xb2, 0x0e },
329 { 0xb3, 0x82 }, { 0xb8, 0x0a },
330
331 /* More reserved magic, some of which tweaks white balance */
332 { 0x43, 0x0a }, { 0x44, 0xf0 },
333 { 0x45, 0x34 }, { 0x46, 0x58 },
334 { 0x47, 0x28 }, { 0x48, 0x3a },
335 { 0x59, 0x88 }, { 0x5a, 0x88 },
336 { 0x5b, 0x44 }, { 0x5c, 0x67 },
337 { 0x5d, 0x49 }, { 0x5e, 0x0e },
338 { 0x6c, 0x0a }, { 0x6d, 0x55 },
339 { 0x6e, 0x11 }, { 0x6f, 0x9f }, /* "9e for advance AWB" */
340 { 0x6a, 0x40 }, { REG_BLUE, 0x40 },
341 { REG_RED, 0x60 },
342 { REG_COM8, COM8_FASTAEC|COM8_AECSTEP|COM8_BFILT|COM8_AGC|COM8_AEC|COM8_AWB },
343
344 /* Matrix coefficients */
345 { 0x4f, 0x80 }, { 0x50, 0x80 },
346 { 0x51, 0 }, { 0x52, 0x22 },
347 { 0x53, 0x5e }, { 0x54, 0x80 },
348 { 0x58, 0x9e },
349
350 { REG_COM16, COM16_AWBGAIN }, { REG_EDGE, 0 },
351 { 0x75, 0x05 }, { 0x76, 0xe1 },
352 { 0x4c, 0 }, { 0x77, 0x01 },
353 { REG_COM13, 0xc3 }, { 0x4b, 0x09 },
354 { 0xc9, 0x60 }, { REG_COM16, 0x38 },
355 { 0x56, 0x40 },
356
357 { 0x34, 0x11 }, { REG_COM11, COM11_EXP|COM11_HZAUTO },
358 { 0xa4, 0x88 }, { 0x96, 0 },
359 { 0x97, 0x30 }, { 0x98, 0x20 },
360 { 0x99, 0x30 }, { 0x9a, 0x84 },
361 { 0x9b, 0x29 }, { 0x9c, 0x03 },
362 { 0x9d, 0x4c }, { 0x9e, 0x3f },
363 { 0x78, 0x04 },
364
365 /* Extra-weird stuff. Some sort of multiplexor register */
366 { 0x79, 0x01 }, { 0xc8, 0xf0 },
367 { 0x79, 0x0f }, { 0xc8, 0x00 },
368 { 0x79, 0x10 }, { 0xc8, 0x7e },
369 { 0x79, 0x0a }, { 0xc8, 0x80 },
370 { 0x79, 0x0b }, { 0xc8, 0x01 },
371 { 0x79, 0x0c }, { 0xc8, 0x0f },
372 { 0x79, 0x0d }, { 0xc8, 0x20 },
373 { 0x79, 0x09 }, { 0xc8, 0x80 },
374 { 0x79, 0x02 }, { 0xc8, 0xc0 },
375 { 0x79, 0x03 }, { 0xc8, 0x40 },
376 { 0x79, 0x05 }, { 0xc8, 0x30 },
377 { 0x79, 0x26 },
378
379 { 0xff, 0xff }, /* END MARKER */
380 };
381
382
383 /*
384 * Here we'll try to encapsulate the changes for just the output
385 * video format.
386 *
387 * RGB656 and YUV422 come from OV; RGB444 is homebrewed.
388 *
389 * IMPORTANT RULE: the first entry must be for COM7, see ov7670_s_fmt for why.
390 */
391
392
393 static struct regval_list ov7670_fmt_yuv422[] = {
394 { REG_COM7, 0x0 }, /* Selects YUV mode */
395 { REG_RGB444, 0 }, /* No RGB444 please */
396 { REG_COM1, 0 }, /* CCIR601 */
397 { REG_COM15, COM15_R00FF },
398 { REG_COM9, 0x48 }, /* 32x gain ceiling; 0x8 is reserved bit */
399 { 0x4f, 0x80 }, /* "matrix coefficient 1" */
400 { 0x50, 0x80 }, /* "matrix coefficient 2" */
401 { 0x51, 0 }, /* vb */
402 { 0x52, 0x22 }, /* "matrix coefficient 4" */
403 { 0x53, 0x5e }, /* "matrix coefficient 5" */
404 { 0x54, 0x80 }, /* "matrix coefficient 6" */
405 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
406 { 0xff, 0xff },
407 };
408
409 static struct regval_list ov7670_fmt_rgb565[] = {
410 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
411 { REG_RGB444, 0 }, /* No RGB444 please */
412 { REG_COM1, 0x0 }, /* CCIR601 */
413 { REG_COM15, COM15_RGB565 },
414 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
415 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
416 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
417 { 0x51, 0 }, /* vb */
418 { 0x52, 0x3d }, /* "matrix coefficient 4" */
419 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
420 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
421 { REG_COM13, COM13_GAMMA|COM13_UVSAT },
422 { 0xff, 0xff },
423 };
424
425 static struct regval_list ov7670_fmt_rgb444[] = {
426 { REG_COM7, COM7_RGB }, /* Selects RGB mode */
427 { REG_RGB444, R444_ENABLE }, /* Enable xxxxrrrr ggggbbbb */
428 { REG_COM1, 0x0 }, /* CCIR601 */
429 { REG_COM15, COM15_R01FE|COM15_RGB565 }, /* Data range needed? */
430 { REG_COM9, 0x38 }, /* 16x gain ceiling; 0x8 is reserved bit */
431 { 0x4f, 0xb3 }, /* "matrix coefficient 1" */
432 { 0x50, 0xb3 }, /* "matrix coefficient 2" */
433 { 0x51, 0 }, /* vb */
434 { 0x52, 0x3d }, /* "matrix coefficient 4" */
435 { 0x53, 0xa7 }, /* "matrix coefficient 5" */
436 { 0x54, 0xe4 }, /* "matrix coefficient 6" */
437 { REG_COM13, COM13_GAMMA|COM13_UVSAT|0x2 }, /* Magic rsvd bit */
438 { 0xff, 0xff },
439 };
440
441 static struct regval_list ov7670_fmt_raw[] = {
442 { REG_COM7, COM7_BAYER },
443 { REG_COM13, 0x08 }, /* No gamma, magic rsvd bit */
444 { REG_COM16, 0x3d }, /* Edge enhancement, denoise */
445 { REG_REG76, 0xe1 }, /* Pix correction, magic rsvd */
446 { 0xff, 0xff },
447 };
448
449
450
451 /*
452 * Low-level register I/O.
453 *
454 * Note that there are two versions of these. On the XO 1, the
455 * i2c controller only does SMBUS, so that's what we use. The
456 * ov7670 is not really an SMBUS device, though, so the communication
457 * is not always entirely reliable.
458 */
459 static int ov7670_read_smbus(struct v4l2_subdev *sd, unsigned char reg,
460 unsigned char *value)
461 {
462 struct i2c_client *client = v4l2_get_subdevdata(sd);
463 int ret;
464
465 ret = i2c_smbus_read_byte_data(client, reg);
466 if (ret >= 0) {
467 *value = (unsigned char)ret;
468 ret = 0;
469 }
470 return ret;
471 }
472
473
474 static int ov7670_write_smbus(struct v4l2_subdev *sd, unsigned char reg,
475 unsigned char value)
476 {
477 struct i2c_client *client = v4l2_get_subdevdata(sd);
478 int ret = i2c_smbus_write_byte_data(client, reg, value);
479
480 if (reg == REG_COM7 && (value & COM7_RESET))
481 msleep(5); /* Wait for reset to run */
482 return ret;
483 }
484
485 /*
486 * On most platforms, we'd rather do straight i2c I/O.
487 */
488 static int ov7670_read_i2c(struct v4l2_subdev *sd, unsigned char reg,
489 unsigned char *value)
490 {
491 struct i2c_client *client = v4l2_get_subdevdata(sd);
492 u8 data = reg;
493 struct i2c_msg msg;
494 int ret;
495
496 /*
497 * Send out the register address...
498 */
499 msg.addr = client->addr;
500 msg.flags = 0;
501 msg.len = 1;
502 msg.buf = &data;
503 ret = i2c_transfer(client->adapter, &msg, 1);
504 if (ret < 0) {
505 printk(KERN_ERR "Error %d on register write\n", ret);
506 return ret;
507 }
508 /*
509 * ...then read back the result.
510 */
511 msg.flags = I2C_M_RD;
512 ret = i2c_transfer(client->adapter, &msg, 1);
513 if (ret >= 0) {
514 *value = data;
515 ret = 0;
516 }
517 return ret;
518 }
519
520
521 static int ov7670_write_i2c(struct v4l2_subdev *sd, unsigned char reg,
522 unsigned char value)
523 {
524 struct i2c_client *client = v4l2_get_subdevdata(sd);
525 struct i2c_msg msg;
526 unsigned char data[2] = { reg, value };
527 int ret;
528
529 msg.addr = client->addr;
530 msg.flags = 0;
531 msg.len = 2;
532 msg.buf = data;
533 ret = i2c_transfer(client->adapter, &msg, 1);
534 if (ret > 0)
535 ret = 0;
536 if (reg == REG_COM7 && (value & COM7_RESET))
537 msleep(5); /* Wait for reset to run */
538 return ret;
539 }
540
541 static int ov7670_read(struct v4l2_subdev *sd, unsigned char reg,
542 unsigned char *value)
543 {
544 struct ov7670_info *info = to_state(sd);
545 if (info->use_smbus)
546 return ov7670_read_smbus(sd, reg, value);
547 else
548 return ov7670_read_i2c(sd, reg, value);
549 }
550
551 static int ov7670_write(struct v4l2_subdev *sd, unsigned char reg,
552 unsigned char value)
553 {
554 struct ov7670_info *info = to_state(sd);
555 if (info->use_smbus)
556 return ov7670_write_smbus(sd, reg, value);
557 else
558 return ov7670_write_i2c(sd, reg, value);
559 }
560
561 /*
562 * Write a list of register settings; ff/ff stops the process.
563 */
564 static int ov7670_write_array(struct v4l2_subdev *sd, struct regval_list *vals)
565 {
566 while (vals->reg_num != 0xff || vals->value != 0xff) {
567 int ret = ov7670_write(sd, vals->reg_num, vals->value);
568 if (ret < 0)
569 return ret;
570 vals++;
571 }
572 return 0;
573 }
574
575
576 /*
577 * Stuff that knows about the sensor.
578 */
579 static int ov7670_reset(struct v4l2_subdev *sd, u32 val)
580 {
581 ov7670_write(sd, REG_COM7, COM7_RESET);
582 msleep(1);
583 return 0;
584 }
585
586
587 static int ov7670_init(struct v4l2_subdev *sd, u32 val)
588 {
589 return ov7670_write_array(sd, ov7670_default_regs);
590 }
591
592
593
594 static int ov7670_detect(struct v4l2_subdev *sd)
595 {
596 unsigned char v;
597 int ret;
598
599 ret = ov7670_init(sd, 0);
600 if (ret < 0)
601 return ret;
602 ret = ov7670_read(sd, REG_MIDH, &v);
603 if (ret < 0)
604 return ret;
605 if (v != 0x7f) /* OV manuf. id. */
606 return -ENODEV;
607 ret = ov7670_read(sd, REG_MIDL, &v);
608 if (ret < 0)
609 return ret;
610 if (v != 0xa2)
611 return -ENODEV;
612 /*
613 * OK, we know we have an OmniVision chip...but which one?
614 */
615 ret = ov7670_read(sd, REG_PID, &v);
616 if (ret < 0)
617 return ret;
618 if (v != 0x76) /* PID + VER = 0x76 / 0x73 */
619 return -ENODEV;
620 ret = ov7670_read(sd, REG_VER, &v);
621 if (ret < 0)
622 return ret;
623 if (v != 0x73) /* PID + VER = 0x76 / 0x73 */
624 return -ENODEV;
625 return 0;
626 }
627
628
629 /*
630 * Store information about the video data format. The color matrix
631 * is deeply tied into the format, so keep the relevant values here.
632 * The magic matrix numbers come from OmniVision.
633 */
634 static struct ov7670_format_struct {
635 u32 mbus_code;
636 enum v4l2_colorspace colorspace;
637 struct regval_list *regs;
638 int cmatrix[CMATRIX_LEN];
639 } ov7670_formats[] = {
640 {
641 .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
642 .colorspace = V4L2_COLORSPACE_SRGB,
643 .regs = ov7670_fmt_yuv422,
644 .cmatrix = { 128, -128, 0, -34, -94, 128 },
645 },
646 {
647 .mbus_code = MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE,
648 .colorspace = V4L2_COLORSPACE_SRGB,
649 .regs = ov7670_fmt_rgb444,
650 .cmatrix = { 179, -179, 0, -61, -176, 228 },
651 },
652 {
653 .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
654 .colorspace = V4L2_COLORSPACE_SRGB,
655 .regs = ov7670_fmt_rgb565,
656 .cmatrix = { 179, -179, 0, -61, -176, 228 },
657 },
658 {
659 .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
660 .colorspace = V4L2_COLORSPACE_SRGB,
661 .regs = ov7670_fmt_raw,
662 .cmatrix = { 0, 0, 0, 0, 0, 0 },
663 },
664 };
665 #define N_OV7670_FMTS ARRAY_SIZE(ov7670_formats)
666
667
668 /*
669 * Then there is the issue of window sizes. Try to capture the info here.
670 */
671
672 /*
673 * QCIF mode is done (by OV) in a very strange way - it actually looks like
674 * VGA with weird scaling options - they do *not* use the canned QCIF mode
675 * which is allegedly provided by the sensor. So here's the weird register
676 * settings.
677 */
678 static struct regval_list ov7670_qcif_regs[] = {
679 { REG_COM3, COM3_SCALEEN|COM3_DCWEN },
680 { REG_COM3, COM3_DCWEN },
681 { REG_COM14, COM14_DCWEN | 0x01},
682 { 0x73, 0xf1 },
683 { 0xa2, 0x52 },
684 { 0x7b, 0x1c },
685 { 0x7c, 0x28 },
686 { 0x7d, 0x3c },
687 { 0x7f, 0x69 },
688 { REG_COM9, 0x38 },
689 { 0xa1, 0x0b },
690 { 0x74, 0x19 },
691 { 0x9a, 0x80 },
692 { 0x43, 0x14 },
693 { REG_COM13, 0xc0 },
694 { 0xff, 0xff },
695 };
696
697 static struct ov7670_win_size ov7670_win_sizes[] = {
698 /* VGA */
699 {
700 .width = VGA_WIDTH,
701 .height = VGA_HEIGHT,
702 .com7_bit = COM7_FMT_VGA,
703 .hstart = 158, /* These values from */
704 .hstop = 14, /* Omnivision */
705 .vstart = 10,
706 .vstop = 490,
707 .regs = NULL,
708 },
709 /* CIF */
710 {
711 .width = CIF_WIDTH,
712 .height = CIF_HEIGHT,
713 .com7_bit = COM7_FMT_CIF,
714 .hstart = 170, /* Empirically determined */
715 .hstop = 90,
716 .vstart = 14,
717 .vstop = 494,
718 .regs = NULL,
719 },
720 /* QVGA */
721 {
722 .width = QVGA_WIDTH,
723 .height = QVGA_HEIGHT,
724 .com7_bit = COM7_FMT_QVGA,
725 .hstart = 168, /* Empirically determined */
726 .hstop = 24,
727 .vstart = 12,
728 .vstop = 492,
729 .regs = NULL,
730 },
731 /* QCIF */
732 {
733 .width = QCIF_WIDTH,
734 .height = QCIF_HEIGHT,
735 .com7_bit = COM7_FMT_VGA, /* see comment above */
736 .hstart = 456, /* Empirically determined */
737 .hstop = 24,
738 .vstart = 14,
739 .vstop = 494,
740 .regs = ov7670_qcif_regs,
741 }
742 };
743
744 static struct ov7670_win_size ov7675_win_sizes[] = {
745 /*
746 * Currently, only VGA is supported. Theoretically it could be possible
747 * to support CIF, QVGA and QCIF too. Taking values for ov7670 as a
748 * base and tweak them empirically could be required.
749 */
750 {
751 .width = VGA_WIDTH,
752 .height = VGA_HEIGHT,
753 .com7_bit = COM7_FMT_VGA,
754 .hstart = 158, /* These values from */
755 .hstop = 14, /* Omnivision */
756 .vstart = 14, /* Empirically determined */
757 .vstop = 494,
758 .regs = NULL,
759 }
760 };
761
762 static void ov7675_get_framerate(struct v4l2_subdev *sd,
763 struct v4l2_fract *tpf)
764 {
765 struct ov7670_info *info = to_state(sd);
766 u32 clkrc = info->clkrc;
767 int pll_factor;
768
769 if (info->pll_bypass)
770 pll_factor = 1;
771 else
772 pll_factor = PLL_FACTOR;
773
774 clkrc++;
775 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
776 clkrc = (clkrc >> 1);
777
778 tpf->numerator = 1;
779 tpf->denominator = (5 * pll_factor * info->clock_speed) /
780 (4 * clkrc);
781 }
782
783 static int ov7675_set_framerate(struct v4l2_subdev *sd,
784 struct v4l2_fract *tpf)
785 {
786 struct ov7670_info *info = to_state(sd);
787 u32 clkrc;
788 int pll_factor;
789 int ret;
790
791 /*
792 * The formula is fps = 5/4*pixclk for YUV/RGB and
793 * fps = 5/2*pixclk for RAW.
794 *
795 * pixclk = clock_speed / (clkrc + 1) * PLLfactor
796 *
797 */
798 if (info->pll_bypass) {
799 pll_factor = 1;
800 ret = ov7670_write(sd, REG_DBLV, DBLV_BYPASS);
801 } else {
802 pll_factor = PLL_FACTOR;
803 ret = ov7670_write(sd, REG_DBLV, DBLV_X4);
804 }
805 if (ret < 0)
806 return ret;
807
808 if (tpf->numerator == 0 || tpf->denominator == 0) {
809 clkrc = 0;
810 } else {
811 clkrc = (5 * pll_factor * info->clock_speed * tpf->numerator) /
812 (4 * tpf->denominator);
813 if (info->fmt->mbus_code == MEDIA_BUS_FMT_SBGGR8_1X8)
814 clkrc = (clkrc << 1);
815 clkrc--;
816 }
817
818 /*
819 * The datasheet claims that clkrc = 0 will divide the input clock by 1
820 * but we've checked with an oscilloscope that it divides by 2 instead.
821 * So, if clkrc = 0 just bypass the divider.
822 */
823 if (clkrc <= 0)
824 clkrc = CLK_EXT;
825 else if (clkrc > CLK_SCALE)
826 clkrc = CLK_SCALE;
827 info->clkrc = clkrc;
828
829 /* Recalculate frame rate */
830 ov7675_get_framerate(sd, tpf);
831
832 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
833 if (ret < 0)
834 return ret;
835
836 return ov7670_write(sd, REG_DBLV, DBLV_X4);
837 }
838
839 static void ov7670_get_framerate_legacy(struct v4l2_subdev *sd,
840 struct v4l2_fract *tpf)
841 {
842 struct ov7670_info *info = to_state(sd);
843
844 tpf->numerator = 1;
845 tpf->denominator = info->clock_speed;
846 if ((info->clkrc & CLK_EXT) == 0 && (info->clkrc & CLK_SCALE) > 1)
847 tpf->denominator /= (info->clkrc & CLK_SCALE);
848 }
849
850 static int ov7670_set_framerate_legacy(struct v4l2_subdev *sd,
851 struct v4l2_fract *tpf)
852 {
853 struct ov7670_info *info = to_state(sd);
854 int div;
855
856 if (tpf->numerator == 0 || tpf->denominator == 0)
857 div = 1; /* Reset to full rate */
858 else
859 div = (tpf->numerator * info->clock_speed) / tpf->denominator;
860 if (div == 0)
861 div = 1;
862 else if (div > CLK_SCALE)
863 div = CLK_SCALE;
864 info->clkrc = (info->clkrc & 0x80) | div;
865 tpf->numerator = 1;
866 tpf->denominator = info->clock_speed / div;
867 return ov7670_write(sd, REG_CLKRC, info->clkrc);
868 }
869
870 /*
871 * Store a set of start/stop values into the camera.
872 */
873 static int ov7670_set_hw(struct v4l2_subdev *sd, int hstart, int hstop,
874 int vstart, int vstop)
875 {
876 int ret;
877 unsigned char v;
878 /*
879 * Horizontal: 11 bits, top 8 live in hstart and hstop. Bottom 3 of
880 * hstart are in href[2:0], bottom 3 of hstop in href[5:3]. There is
881 * a mystery "edge offset" value in the top two bits of href.
882 */
883 ret = ov7670_write(sd, REG_HSTART, (hstart >> 3) & 0xff);
884 ret += ov7670_write(sd, REG_HSTOP, (hstop >> 3) & 0xff);
885 ret += ov7670_read(sd, REG_HREF, &v);
886 v = (v & 0xc0) | ((hstop & 0x7) << 3) | (hstart & 0x7);
887 msleep(10);
888 ret += ov7670_write(sd, REG_HREF, v);
889 /*
890 * Vertical: similar arrangement, but only 10 bits.
891 */
892 ret += ov7670_write(sd, REG_VSTART, (vstart >> 2) & 0xff);
893 ret += ov7670_write(sd, REG_VSTOP, (vstop >> 2) & 0xff);
894 ret += ov7670_read(sd, REG_VREF, &v);
895 v = (v & 0xf0) | ((vstop & 0x3) << 2) | (vstart & 0x3);
896 msleep(10);
897 ret += ov7670_write(sd, REG_VREF, v);
898 return ret;
899 }
900
901
902 static int ov7670_enum_mbus_code(struct v4l2_subdev *sd,
903 struct v4l2_subdev_pad_config *cfg,
904 struct v4l2_subdev_mbus_code_enum *code)
905 {
906 if (code->pad || code->index >= N_OV7670_FMTS)
907 return -EINVAL;
908
909 code->code = ov7670_formats[code->index].mbus_code;
910 return 0;
911 }
912
913 static int ov7670_try_fmt_internal(struct v4l2_subdev *sd,
914 struct v4l2_mbus_framefmt *fmt,
915 struct ov7670_format_struct **ret_fmt,
916 struct ov7670_win_size **ret_wsize)
917 {
918 int index, i;
919 struct ov7670_win_size *wsize;
920 struct ov7670_info *info = to_state(sd);
921 unsigned int n_win_sizes = info->devtype->n_win_sizes;
922 unsigned int win_sizes_limit = n_win_sizes;
923
924 for (index = 0; index < N_OV7670_FMTS; index++)
925 if (ov7670_formats[index].mbus_code == fmt->code)
926 break;
927 if (index >= N_OV7670_FMTS) {
928 /* default to first format */
929 index = 0;
930 fmt->code = ov7670_formats[0].mbus_code;
931 }
932 if (ret_fmt != NULL)
933 *ret_fmt = ov7670_formats + index;
934 /*
935 * Fields: the OV devices claim to be progressive.
936 */
937 fmt->field = V4L2_FIELD_NONE;
938
939 /*
940 * Don't consider values that don't match min_height and min_width
941 * constraints.
942 */
943 if (info->min_width || info->min_height)
944 for (i = 0; i < n_win_sizes; i++) {
945 wsize = info->devtype->win_sizes + i;
946
947 if (wsize->width < info->min_width ||
948 wsize->height < info->min_height) {
949 win_sizes_limit = i;
950 break;
951 }
952 }
953 /*
954 * Round requested image size down to the nearest
955 * we support, but not below the smallest.
956 */
957 for (wsize = info->devtype->win_sizes;
958 wsize < info->devtype->win_sizes + win_sizes_limit; wsize++)
959 if (fmt->width >= wsize->width && fmt->height >= wsize->height)
960 break;
961 if (wsize >= info->devtype->win_sizes + win_sizes_limit)
962 wsize--; /* Take the smallest one */
963 if (ret_wsize != NULL)
964 *ret_wsize = wsize;
965 /*
966 * Note the size we'll actually handle.
967 */
968 fmt->width = wsize->width;
969 fmt->height = wsize->height;
970 fmt->colorspace = ov7670_formats[index].colorspace;
971 return 0;
972 }
973
974 /*
975 * Set a format.
976 */
977 static int ov7670_set_fmt(struct v4l2_subdev *sd,
978 struct v4l2_subdev_pad_config *cfg,
979 struct v4l2_subdev_format *format)
980 {
981 struct ov7670_format_struct *ovfmt;
982 struct ov7670_win_size *wsize;
983 struct ov7670_info *info = to_state(sd);
984 unsigned char com7;
985 int ret;
986
987 if (format->pad)
988 return -EINVAL;
989
990 if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
991 ret = ov7670_try_fmt_internal(sd, &format->format, NULL, NULL);
992 if (ret)
993 return ret;
994 cfg->try_fmt = format->format;
995 return 0;
996 }
997
998 ret = ov7670_try_fmt_internal(sd, &format->format, &ovfmt, &wsize);
999
1000 if (ret)
1001 return ret;
1002 /*
1003 * COM7 is a pain in the ass, it doesn't like to be read then
1004 * quickly written afterward. But we have everything we need
1005 * to set it absolutely here, as long as the format-specific
1006 * register sets list it first.
1007 */
1008 com7 = ovfmt->regs[0].value;
1009 com7 |= wsize->com7_bit;
1010 ov7670_write(sd, REG_COM7, com7);
1011 /*
1012 * Now write the rest of the array. Also store start/stops
1013 */
1014 ov7670_write_array(sd, ovfmt->regs + 1);
1015 ov7670_set_hw(sd, wsize->hstart, wsize->hstop, wsize->vstart,
1016 wsize->vstop);
1017 ret = 0;
1018 if (wsize->regs)
1019 ret = ov7670_write_array(sd, wsize->regs);
1020 info->fmt = ovfmt;
1021
1022 /*
1023 * If we're running RGB565, we must rewrite clkrc after setting
1024 * the other parameters or the image looks poor. If we're *not*
1025 * doing RGB565, we must not rewrite clkrc or the image looks
1026 * *really* poor.
1027 *
1028 * (Update) Now that we retain clkrc state, we should be able
1029 * to write it unconditionally, and that will make the frame
1030 * rate persistent too.
1031 */
1032 if (ret == 0)
1033 ret = ov7670_write(sd, REG_CLKRC, info->clkrc);
1034 return 0;
1035 }
1036
1037 /*
1038 * Implement G/S_PARM. There is a "high quality" mode we could try
1039 * to do someday; for now, we just do the frame rate tweak.
1040 */
1041 static int ov7670_g_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
1042 {
1043 struct v4l2_captureparm *cp = &parms->parm.capture;
1044 struct ov7670_info *info = to_state(sd);
1045
1046 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1047 return -EINVAL;
1048
1049 memset(cp, 0, sizeof(struct v4l2_captureparm));
1050 cp->capability = V4L2_CAP_TIMEPERFRAME;
1051 info->devtype->get_framerate(sd, &cp->timeperframe);
1052
1053 return 0;
1054 }
1055
1056 static int ov7670_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *parms)
1057 {
1058 struct v4l2_captureparm *cp = &parms->parm.capture;
1059 struct v4l2_fract *tpf = &cp->timeperframe;
1060 struct ov7670_info *info = to_state(sd);
1061
1062 if (parms->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
1063 return -EINVAL;
1064 if (cp->extendedmode != 0)
1065 return -EINVAL;
1066
1067 return info->devtype->set_framerate(sd, tpf);
1068 }
1069
1070
1071 /*
1072 * Frame intervals. Since frame rates are controlled with the clock
1073 * divider, we can only do 30/n for integer n values. So no continuous
1074 * or stepwise options. Here we just pick a handful of logical values.
1075 */
1076
1077 static int ov7670_frame_rates[] = { 30, 15, 10, 5, 1 };
1078
1079 static int ov7670_enum_frame_interval(struct v4l2_subdev *sd,
1080 struct v4l2_subdev_pad_config *cfg,
1081 struct v4l2_subdev_frame_interval_enum *fie)
1082 {
1083 struct ov7670_info *info = to_state(sd);
1084 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1085 int i;
1086
1087 if (fie->pad)
1088 return -EINVAL;
1089 if (fie->index >= ARRAY_SIZE(ov7670_frame_rates))
1090 return -EINVAL;
1091
1092 /*
1093 * Check if the width/height is valid.
1094 *
1095 * If a minimum width/height was requested, filter out the capture
1096 * windows that fall outside that.
1097 */
1098 for (i = 0; i < n_win_sizes; i++) {
1099 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1100
1101 if (info->min_width && win->width < info->min_width)
1102 continue;
1103 if (info->min_height && win->height < info->min_height)
1104 continue;
1105 if (fie->width == win->width && fie->height == win->height)
1106 break;
1107 }
1108 if (i == n_win_sizes)
1109 return -EINVAL;
1110 fie->interval.numerator = 1;
1111 fie->interval.denominator = ov7670_frame_rates[fie->index];
1112 return 0;
1113 }
1114
1115 /*
1116 * Frame size enumeration
1117 */
1118 static int ov7670_enum_frame_size(struct v4l2_subdev *sd,
1119 struct v4l2_subdev_pad_config *cfg,
1120 struct v4l2_subdev_frame_size_enum *fse)
1121 {
1122 struct ov7670_info *info = to_state(sd);
1123 int i;
1124 int num_valid = -1;
1125 __u32 index = fse->index;
1126 unsigned int n_win_sizes = info->devtype->n_win_sizes;
1127
1128 if (fse->pad)
1129 return -EINVAL;
1130
1131 /*
1132 * If a minimum width/height was requested, filter out the capture
1133 * windows that fall outside that.
1134 */
1135 for (i = 0; i < n_win_sizes; i++) {
1136 struct ov7670_win_size *win = &info->devtype->win_sizes[i];
1137 if (info->min_width && win->width < info->min_width)
1138 continue;
1139 if (info->min_height && win->height < info->min_height)
1140 continue;
1141 if (index == ++num_valid) {
1142 fse->min_width = fse->max_width = win->width;
1143 fse->min_height = fse->max_height = win->height;
1144 return 0;
1145 }
1146 }
1147
1148 return -EINVAL;
1149 }
1150
1151 /*
1152 * Code for dealing with controls.
1153 */
1154
1155 static int ov7670_store_cmatrix(struct v4l2_subdev *sd,
1156 int matrix[CMATRIX_LEN])
1157 {
1158 int i, ret;
1159 unsigned char signbits = 0;
1160
1161 /*
1162 * Weird crap seems to exist in the upper part of
1163 * the sign bits register, so let's preserve it.
1164 */
1165 ret = ov7670_read(sd, REG_CMATRIX_SIGN, &signbits);
1166 signbits &= 0xc0;
1167
1168 for (i = 0; i < CMATRIX_LEN; i++) {
1169 unsigned char raw;
1170
1171 if (matrix[i] < 0) {
1172 signbits |= (1 << i);
1173 if (matrix[i] < -255)
1174 raw = 0xff;
1175 else
1176 raw = (-1 * matrix[i]) & 0xff;
1177 }
1178 else {
1179 if (matrix[i] > 255)
1180 raw = 0xff;
1181 else
1182 raw = matrix[i] & 0xff;
1183 }
1184 ret += ov7670_write(sd, REG_CMATRIX_BASE + i, raw);
1185 }
1186 ret += ov7670_write(sd, REG_CMATRIX_SIGN, signbits);
1187 return ret;
1188 }
1189
1190
1191 /*
1192 * Hue also requires messing with the color matrix. It also requires
1193 * trig functions, which tend not to be well supported in the kernel.
1194 * So here is a simple table of sine values, 0-90 degrees, in steps
1195 * of five degrees. Values are multiplied by 1000.
1196 *
1197 * The following naive approximate trig functions require an argument
1198 * carefully limited to -180 <= theta <= 180.
1199 */
1200 #define SIN_STEP 5
1201 static const int ov7670_sin_table[] = {
1202 0, 87, 173, 258, 342, 422,
1203 499, 573, 642, 707, 766, 819,
1204 866, 906, 939, 965, 984, 996,
1205 1000
1206 };
1207
1208 static int ov7670_sine(int theta)
1209 {
1210 int chs = 1;
1211 int sine;
1212
1213 if (theta < 0) {
1214 theta = -theta;
1215 chs = -1;
1216 }
1217 if (theta <= 90)
1218 sine = ov7670_sin_table[theta/SIN_STEP];
1219 else {
1220 theta -= 90;
1221 sine = 1000 - ov7670_sin_table[theta/SIN_STEP];
1222 }
1223 return sine*chs;
1224 }
1225
1226 static int ov7670_cosine(int theta)
1227 {
1228 theta = 90 - theta;
1229 if (theta > 180)
1230 theta -= 360;
1231 else if (theta < -180)
1232 theta += 360;
1233 return ov7670_sine(theta);
1234 }
1235
1236
1237
1238
1239 static void ov7670_calc_cmatrix(struct ov7670_info *info,
1240 int matrix[CMATRIX_LEN], int sat, int hue)
1241 {
1242 int i;
1243 /*
1244 * Apply the current saturation setting first.
1245 */
1246 for (i = 0; i < CMATRIX_LEN; i++)
1247 matrix[i] = (info->fmt->cmatrix[i] * sat) >> 7;
1248 /*
1249 * Then, if need be, rotate the hue value.
1250 */
1251 if (hue != 0) {
1252 int sinth, costh, tmpmatrix[CMATRIX_LEN];
1253
1254 memcpy(tmpmatrix, matrix, CMATRIX_LEN*sizeof(int));
1255 sinth = ov7670_sine(hue);
1256 costh = ov7670_cosine(hue);
1257
1258 matrix[0] = (matrix[3]*sinth + matrix[0]*costh)/1000;
1259 matrix[1] = (matrix[4]*sinth + matrix[1]*costh)/1000;
1260 matrix[2] = (matrix[5]*sinth + matrix[2]*costh)/1000;
1261 matrix[3] = (matrix[3]*costh - matrix[0]*sinth)/1000;
1262 matrix[4] = (matrix[4]*costh - matrix[1]*sinth)/1000;
1263 matrix[5] = (matrix[5]*costh - matrix[2]*sinth)/1000;
1264 }
1265 }
1266
1267
1268
1269 static int ov7670_s_sat_hue(struct v4l2_subdev *sd, int sat, int hue)
1270 {
1271 struct ov7670_info *info = to_state(sd);
1272 int matrix[CMATRIX_LEN];
1273 int ret;
1274
1275 ov7670_calc_cmatrix(info, matrix, sat, hue);
1276 ret = ov7670_store_cmatrix(sd, matrix);
1277 return ret;
1278 }
1279
1280
1281 /*
1282 * Some weird registers seem to store values in a sign/magnitude format!
1283 */
1284
1285 static unsigned char ov7670_abs_to_sm(unsigned char v)
1286 {
1287 if (v > 127)
1288 return v & 0x7f;
1289 return (128 - v) | 0x80;
1290 }
1291
1292 static int ov7670_s_brightness(struct v4l2_subdev *sd, int value)
1293 {
1294 unsigned char com8 = 0, v;
1295 int ret;
1296
1297 ov7670_read(sd, REG_COM8, &com8);
1298 com8 &= ~COM8_AEC;
1299 ov7670_write(sd, REG_COM8, com8);
1300 v = ov7670_abs_to_sm(value);
1301 ret = ov7670_write(sd, REG_BRIGHT, v);
1302 return ret;
1303 }
1304
1305 static int ov7670_s_contrast(struct v4l2_subdev *sd, int value)
1306 {
1307 return ov7670_write(sd, REG_CONTRAS, (unsigned char) value);
1308 }
1309
1310 static int ov7670_s_hflip(struct v4l2_subdev *sd, int value)
1311 {
1312 unsigned char v = 0;
1313 int ret;
1314
1315 ret = ov7670_read(sd, REG_MVFP, &v);
1316 if (value)
1317 v |= MVFP_MIRROR;
1318 else
1319 v &= ~MVFP_MIRROR;
1320 msleep(10); /* FIXME */
1321 ret += ov7670_write(sd, REG_MVFP, v);
1322 return ret;
1323 }
1324
1325 static int ov7670_s_vflip(struct v4l2_subdev *sd, int value)
1326 {
1327 unsigned char v = 0;
1328 int ret;
1329
1330 ret = ov7670_read(sd, REG_MVFP, &v);
1331 if (value)
1332 v |= MVFP_FLIP;
1333 else
1334 v &= ~MVFP_FLIP;
1335 msleep(10); /* FIXME */
1336 ret += ov7670_write(sd, REG_MVFP, v);
1337 return ret;
1338 }
1339
1340 /*
1341 * GAIN is split between REG_GAIN and REG_VREF[7:6]. If one believes
1342 * the data sheet, the VREF parts should be the most significant, but
1343 * experience shows otherwise. There seems to be little value in
1344 * messing with the VREF bits, so we leave them alone.
1345 */
1346 static int ov7670_g_gain(struct v4l2_subdev *sd, __s32 *value)
1347 {
1348 int ret;
1349 unsigned char gain;
1350
1351 ret = ov7670_read(sd, REG_GAIN, &gain);
1352 *value = gain;
1353 return ret;
1354 }
1355
1356 static int ov7670_s_gain(struct v4l2_subdev *sd, int value)
1357 {
1358 int ret;
1359 unsigned char com8;
1360
1361 ret = ov7670_write(sd, REG_GAIN, value & 0xff);
1362 /* Have to turn off AGC as well */
1363 if (ret == 0) {
1364 ret = ov7670_read(sd, REG_COM8, &com8);
1365 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AGC);
1366 }
1367 return ret;
1368 }
1369
1370 /*
1371 * Tweak autogain.
1372 */
1373 static int ov7670_s_autogain(struct v4l2_subdev *sd, int value)
1374 {
1375 int ret;
1376 unsigned char com8;
1377
1378 ret = ov7670_read(sd, REG_COM8, &com8);
1379 if (ret == 0) {
1380 if (value)
1381 com8 |= COM8_AGC;
1382 else
1383 com8 &= ~COM8_AGC;
1384 ret = ov7670_write(sd, REG_COM8, com8);
1385 }
1386 return ret;
1387 }
1388
1389 static int ov7670_s_exp(struct v4l2_subdev *sd, int value)
1390 {
1391 int ret;
1392 unsigned char com1, com8, aech, aechh;
1393
1394 ret = ov7670_read(sd, REG_COM1, &com1) +
1395 ov7670_read(sd, REG_COM8, &com8) +
1396 ov7670_read(sd, REG_AECHH, &aechh);
1397 if (ret)
1398 return ret;
1399
1400 com1 = (com1 & 0xfc) | (value & 0x03);
1401 aech = (value >> 2) & 0xff;
1402 aechh = (aechh & 0xc0) | ((value >> 10) & 0x3f);
1403 ret = ov7670_write(sd, REG_COM1, com1) +
1404 ov7670_write(sd, REG_AECH, aech) +
1405 ov7670_write(sd, REG_AECHH, aechh);
1406 /* Have to turn off AEC as well */
1407 if (ret == 0)
1408 ret = ov7670_write(sd, REG_COM8, com8 & ~COM8_AEC);
1409 return ret;
1410 }
1411
1412 /*
1413 * Tweak autoexposure.
1414 */
1415 static int ov7670_s_autoexp(struct v4l2_subdev *sd,
1416 enum v4l2_exposure_auto_type value)
1417 {
1418 int ret;
1419 unsigned char com8;
1420
1421 ret = ov7670_read(sd, REG_COM8, &com8);
1422 if (ret == 0) {
1423 if (value == V4L2_EXPOSURE_AUTO)
1424 com8 |= COM8_AEC;
1425 else
1426 com8 &= ~COM8_AEC;
1427 ret = ov7670_write(sd, REG_COM8, com8);
1428 }
1429 return ret;
1430 }
1431
1432
1433 static int ov7670_g_volatile_ctrl(struct v4l2_ctrl *ctrl)
1434 {
1435 struct v4l2_subdev *sd = to_sd(ctrl);
1436 struct ov7670_info *info = to_state(sd);
1437
1438 switch (ctrl->id) {
1439 case V4L2_CID_AUTOGAIN:
1440 return ov7670_g_gain(sd, &info->gain->val);
1441 }
1442 return -EINVAL;
1443 }
1444
1445 static int ov7670_s_ctrl(struct v4l2_ctrl *ctrl)
1446 {
1447 struct v4l2_subdev *sd = to_sd(ctrl);
1448 struct ov7670_info *info = to_state(sd);
1449
1450 switch (ctrl->id) {
1451 case V4L2_CID_BRIGHTNESS:
1452 return ov7670_s_brightness(sd, ctrl->val);
1453 case V4L2_CID_CONTRAST:
1454 return ov7670_s_contrast(sd, ctrl->val);
1455 case V4L2_CID_SATURATION:
1456 return ov7670_s_sat_hue(sd,
1457 info->saturation->val, info->hue->val);
1458 case V4L2_CID_VFLIP:
1459 return ov7670_s_vflip(sd, ctrl->val);
1460 case V4L2_CID_HFLIP:
1461 return ov7670_s_hflip(sd, ctrl->val);
1462 case V4L2_CID_AUTOGAIN:
1463 /* Only set manual gain if auto gain is not explicitly
1464 turned on. */
1465 if (!ctrl->val) {
1466 /* ov7670_s_gain turns off auto gain */
1467 return ov7670_s_gain(sd, info->gain->val);
1468 }
1469 return ov7670_s_autogain(sd, ctrl->val);
1470 case V4L2_CID_EXPOSURE_AUTO:
1471 /* Only set manual exposure if auto exposure is not explicitly
1472 turned on. */
1473 if (ctrl->val == V4L2_EXPOSURE_MANUAL) {
1474 /* ov7670_s_exp turns off auto exposure */
1475 return ov7670_s_exp(sd, info->exposure->val);
1476 }
1477 return ov7670_s_autoexp(sd, ctrl->val);
1478 }
1479 return -EINVAL;
1480 }
1481
1482 static const struct v4l2_ctrl_ops ov7670_ctrl_ops = {
1483 .s_ctrl = ov7670_s_ctrl,
1484 .g_volatile_ctrl = ov7670_g_volatile_ctrl,
1485 };
1486
1487 #ifdef CONFIG_VIDEO_ADV_DEBUG
1488 static int ov7670_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
1489 {
1490 unsigned char val = 0;
1491 int ret;
1492
1493 ret = ov7670_read(sd, reg->reg & 0xff, &val);
1494 reg->val = val;
1495 reg->size = 1;
1496 return ret;
1497 }
1498
1499 static int ov7670_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1500 {
1501 ov7670_write(sd, reg->reg & 0xff, reg->val & 0xff);
1502 return 0;
1503 }
1504 #endif
1505
1506 /* ----------------------------------------------------------------------- */
1507
1508 static const struct v4l2_subdev_core_ops ov7670_core_ops = {
1509 .reset = ov7670_reset,
1510 .init = ov7670_init,
1511 #ifdef CONFIG_VIDEO_ADV_DEBUG
1512 .g_register = ov7670_g_register,
1513 .s_register = ov7670_s_register,
1514 #endif
1515 };
1516
1517 static const struct v4l2_subdev_video_ops ov7670_video_ops = {
1518 .s_parm = ov7670_s_parm,
1519 .g_parm = ov7670_g_parm,
1520 };
1521
1522 static const struct v4l2_subdev_pad_ops ov7670_pad_ops = {
1523 .enum_frame_interval = ov7670_enum_frame_interval,
1524 .enum_frame_size = ov7670_enum_frame_size,
1525 .enum_mbus_code = ov7670_enum_mbus_code,
1526 .set_fmt = ov7670_set_fmt,
1527 };
1528
1529 static const struct v4l2_subdev_ops ov7670_ops = {
1530 .core = &ov7670_core_ops,
1531 .video = &ov7670_video_ops,
1532 .pad = &ov7670_pad_ops,
1533 };
1534
1535 /* ----------------------------------------------------------------------- */
1536
1537 static const struct ov7670_devtype ov7670_devdata[] = {
1538 [MODEL_OV7670] = {
1539 .win_sizes = ov7670_win_sizes,
1540 .n_win_sizes = ARRAY_SIZE(ov7670_win_sizes),
1541 .set_framerate = ov7670_set_framerate_legacy,
1542 .get_framerate = ov7670_get_framerate_legacy,
1543 },
1544 [MODEL_OV7675] = {
1545 .win_sizes = ov7675_win_sizes,
1546 .n_win_sizes = ARRAY_SIZE(ov7675_win_sizes),
1547 .set_framerate = ov7675_set_framerate,
1548 .get_framerate = ov7675_get_framerate,
1549 },
1550 };
1551
1552 static int ov7670_probe(struct i2c_client *client,
1553 const struct i2c_device_id *id)
1554 {
1555 struct v4l2_fract tpf;
1556 struct v4l2_subdev *sd;
1557 struct ov7670_info *info;
1558 int ret;
1559
1560 info = devm_kzalloc(&client->dev, sizeof(*info), GFP_KERNEL);
1561 if (info == NULL)
1562 return -ENOMEM;
1563 sd = &info->sd;
1564 v4l2_i2c_subdev_init(sd, client, &ov7670_ops);
1565
1566 info->clock_speed = 30; /* default: a guess */
1567 if (client->dev.platform_data) {
1568 struct ov7670_config *config = client->dev.platform_data;
1569
1570 /*
1571 * Must apply configuration before initializing device, because it
1572 * selects I/O method.
1573 */
1574 info->min_width = config->min_width;
1575 info->min_height = config->min_height;
1576 info->use_smbus = config->use_smbus;
1577
1578 if (config->clock_speed)
1579 info->clock_speed = config->clock_speed;
1580
1581 /*
1582 * It should be allowed for ov7670 too when it is migrated to
1583 * the new frame rate formula.
1584 */
1585 if (config->pll_bypass && id->driver_data != MODEL_OV7670)
1586 info->pll_bypass = true;
1587
1588 if (config->pclk_hb_disable)
1589 info->pclk_hb_disable = true;
1590 }
1591
1592 /* Make sure it's an ov7670 */
1593 ret = ov7670_detect(sd);
1594 if (ret) {
1595 v4l_dbg(1, debug, client,
1596 "chip found @ 0x%x (%s) is not an ov7670 chip.\n",
1597 client->addr << 1, client->adapter->name);
1598 return ret;
1599 }
1600 v4l_info(client, "chip found @ 0x%02x (%s)\n",
1601 client->addr << 1, client->adapter->name);
1602
1603 info->devtype = &ov7670_devdata[id->driver_data];
1604 info->fmt = &ov7670_formats[0];
1605 info->clkrc = 0;
1606
1607 /* Set default frame rate to 30 fps */
1608 tpf.numerator = 1;
1609 tpf.denominator = 30;
1610 info->devtype->set_framerate(sd, &tpf);
1611
1612 if (info->pclk_hb_disable)
1613 ov7670_write(sd, REG_COM10, COM10_PCLK_HB);
1614
1615 v4l2_ctrl_handler_init(&info->hdl, 10);
1616 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1617 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128);
1618 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1619 V4L2_CID_CONTRAST, 0, 127, 1, 64);
1620 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1621 V4L2_CID_VFLIP, 0, 1, 1, 0);
1622 v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1623 V4L2_CID_HFLIP, 0, 1, 1, 0);
1624 info->saturation = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1625 V4L2_CID_SATURATION, 0, 256, 1, 128);
1626 info->hue = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1627 V4L2_CID_HUE, -180, 180, 5, 0);
1628 info->gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1629 V4L2_CID_GAIN, 0, 255, 1, 128);
1630 info->auto_gain = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1631 V4L2_CID_AUTOGAIN, 0, 1, 1, 1);
1632 info->exposure = v4l2_ctrl_new_std(&info->hdl, &ov7670_ctrl_ops,
1633 V4L2_CID_EXPOSURE, 0, 65535, 1, 500);
1634 info->auto_exposure = v4l2_ctrl_new_std_menu(&info->hdl, &ov7670_ctrl_ops,
1635 V4L2_CID_EXPOSURE_AUTO, V4L2_EXPOSURE_MANUAL, 0,
1636 V4L2_EXPOSURE_AUTO);
1637 sd->ctrl_handler = &info->hdl;
1638 if (info->hdl.error) {
1639 int err = info->hdl.error;
1640
1641 v4l2_ctrl_handler_free(&info->hdl);
1642 return err;
1643 }
1644 /*
1645 * We have checked empirically that hw allows to read back the gain
1646 * value chosen by auto gain but that's not the case for auto exposure.
1647 */
1648 v4l2_ctrl_auto_cluster(2, &info->auto_gain, 0, true);
1649 v4l2_ctrl_auto_cluster(2, &info->auto_exposure,
1650 V4L2_EXPOSURE_MANUAL, false);
1651 v4l2_ctrl_cluster(2, &info->saturation);
1652 v4l2_ctrl_handler_setup(&info->hdl);
1653
1654 return 0;
1655 }
1656
1657
1658 static int ov7670_remove(struct i2c_client *client)
1659 {
1660 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1661 struct ov7670_info *info = to_state(sd);
1662
1663 v4l2_device_unregister_subdev(sd);
1664 v4l2_ctrl_handler_free(&info->hdl);
1665 return 0;
1666 }
1667
1668 static const struct i2c_device_id ov7670_id[] = {
1669 { "ov7670", MODEL_OV7670 },
1670 { "ov7675", MODEL_OV7675 },
1671 { }
1672 };
1673 MODULE_DEVICE_TABLE(i2c, ov7670_id);
1674
1675 static struct i2c_driver ov7670_driver = {
1676 .driver = {
1677 .name = "ov7670",
1678 },
1679 .probe = ov7670_probe,
1680 .remove = ov7670_remove,
1681 .id_table = ov7670_id,
1682 };
1683
1684 module_i2c_driver(ov7670_driver);
Linux with added FPC-III support