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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / media / platform / soc_camera / pxa_camera.c
blob2aaf4a8f71a023992def4c7af9f376c77a4fe327
1 /*
2 * V4L2 Driver for PXA camera host
3 *
4 * Copyright (C) 2006, Sascha Hauer, Pengutronix
5 * Copyright (C) 2008, Guennadi Liakhovetski <kernel@pengutronix.de>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/io.h>
16 #include <linux/delay.h>
17 #include <linux/dma-mapping.h>
18 #include <linux/err.h>
19 #include <linux/errno.h>
20 #include <linux/fs.h>
21 #include <linux/interrupt.h>
22 #include <linux/kernel.h>
23 #include <linux/mm.h>
24 #include <linux/moduleparam.h>
25 #include <linux/time.h>
26 #include <linux/device.h>
27 #include <linux/platform_device.h>
28 #include <linux/clk.h>
29 #include <linux/sched.h>
30 #include <linux/slab.h>
31 #include <linux/dmaengine.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/dma/pxa-dma.h>
34
35 #include <media/v4l2-common.h>
36 #include <media/v4l2-dev.h>
37 #include <media/videobuf-dma-sg.h>
38 #include <media/soc_camera.h>
39 #include <media/drv-intf/soc_mediabus.h>
40 #include <media/v4l2-of.h>
41
42 #include <linux/videodev2.h>
43
44 #include <linux/platform_data/media/camera-pxa.h>
45
46 #define PXA_CAM_VERSION "0.0.6"
47 #define PXA_CAM_DRV_NAME "pxa27x-camera"
48
49 /* Camera Interface */
50 #define CICR0 0x0000
51 #define CICR1 0x0004
52 #define CICR2 0x0008
53 #define CICR3 0x000C
54 #define CICR4 0x0010
55 #define CISR 0x0014
56 #define CIFR 0x0018
57 #define CITOR 0x001C
58 #define CIBR0 0x0028
59 #define CIBR1 0x0030
60 #define CIBR2 0x0038
61
62 #define CICR0_DMAEN (1 << 31) /* DMA request enable */
63 #define CICR0_PAR_EN (1 << 30) /* Parity enable */
64 #define CICR0_SL_CAP_EN (1 << 29) /* Capture enable for slave mode */
65 #define CICR0_ENB (1 << 28) /* Camera interface enable */
66 #define CICR0_DIS (1 << 27) /* Camera interface disable */
67 #define CICR0_SIM (0x7 << 24) /* Sensor interface mode mask */
68 #define CICR0_TOM (1 << 9) /* Time-out mask */
69 #define CICR0_RDAVM (1 << 8) /* Receive-data-available mask */
70 #define CICR0_FEM (1 << 7) /* FIFO-empty mask */
71 #define CICR0_EOLM (1 << 6) /* End-of-line mask */
72 #define CICR0_PERRM (1 << 5) /* Parity-error mask */
73 #define CICR0_QDM (1 << 4) /* Quick-disable mask */
74 #define CICR0_CDM (1 << 3) /* Disable-done mask */
75 #define CICR0_SOFM (1 << 2) /* Start-of-frame mask */
76 #define CICR0_EOFM (1 << 1) /* End-of-frame mask */
77 #define CICR0_FOM (1 << 0) /* FIFO-overrun mask */
78
79 #define CICR1_TBIT (1 << 31) /* Transparency bit */
80 #define CICR1_RGBT_CONV (0x3 << 29) /* RGBT conversion mask */
81 #define CICR1_PPL (0x7ff << 15) /* Pixels per line mask */
82 #define CICR1_RGB_CONV (0x7 << 12) /* RGB conversion mask */
83 #define CICR1_RGB_F (1 << 11) /* RGB format */
84 #define CICR1_YCBCR_F (1 << 10) /* YCbCr format */
85 #define CICR1_RGB_BPP (0x7 << 7) /* RGB bis per pixel mask */
86 #define CICR1_RAW_BPP (0x3 << 5) /* Raw bis per pixel mask */
87 #define CICR1_COLOR_SP (0x3 << 3) /* Color space mask */
88 #define CICR1_DW (0x7 << 0) /* Data width mask */
89
90 #define CICR2_BLW (0xff << 24) /* Beginning-of-line pixel clock
91 wait count mask */
92 #define CICR2_ELW (0xff << 16) /* End-of-line pixel clock
93 wait count mask */
94 #define CICR2_HSW (0x3f << 10) /* Horizontal sync pulse width mask */
95 #define CICR2_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
96 wait count mask */
97 #define CICR2_FSW (0x7 << 0) /* Frame stabilization
98 wait count mask */
99
100 #define CICR3_BFW (0xff << 24) /* Beginning-of-frame line clock
101 wait count mask */
102 #define CICR3_EFW (0xff << 16) /* End-of-frame line clock
103 wait count mask */
104 #define CICR3_VSW (0x3f << 10) /* Vertical sync pulse width mask */
105 #define CICR3_BFPW (0x3f << 3) /* Beginning-of-frame pixel clock
106 wait count mask */
107 #define CICR3_LPF (0x7ff << 0) /* Lines per frame mask */
108
109 #define CICR4_MCLK_DLY (0x3 << 24) /* MCLK Data Capture Delay mask */
110 #define CICR4_PCLK_EN (1 << 23) /* Pixel clock enable */
111 #define CICR4_PCP (1 << 22) /* Pixel clock polarity */
112 #define CICR4_HSP (1 << 21) /* Horizontal sync polarity */
113 #define CICR4_VSP (1 << 20) /* Vertical sync polarity */
114 #define CICR4_MCLK_EN (1 << 19) /* MCLK enable */
115 #define CICR4_FR_RATE (0x7 << 8) /* Frame rate mask */
116 #define CICR4_DIV (0xff << 0) /* Clock divisor mask */
117
118 #define CISR_FTO (1 << 15) /* FIFO time-out */
119 #define CISR_RDAV_2 (1 << 14) /* Channel 2 receive data available */
120 #define CISR_RDAV_1 (1 << 13) /* Channel 1 receive data available */
121 #define CISR_RDAV_0 (1 << 12) /* Channel 0 receive data available */
122 #define CISR_FEMPTY_2 (1 << 11) /* Channel 2 FIFO empty */
123 #define CISR_FEMPTY_1 (1 << 10) /* Channel 1 FIFO empty */
124 #define CISR_FEMPTY_0 (1 << 9) /* Channel 0 FIFO empty */
125 #define CISR_EOL (1 << 8) /* End of line */
126 #define CISR_PAR_ERR (1 << 7) /* Parity error */
127 #define CISR_CQD (1 << 6) /* Camera interface quick disable */
128 #define CISR_CDD (1 << 5) /* Camera interface disable done */
129 #define CISR_SOF (1 << 4) /* Start of frame */
130 #define CISR_EOF (1 << 3) /* End of frame */
131 #define CISR_IFO_2 (1 << 2) /* FIFO overrun for Channel 2 */
132 #define CISR_IFO_1 (1 << 1) /* FIFO overrun for Channel 1 */
133 #define CISR_IFO_0 (1 << 0) /* FIFO overrun for Channel 0 */
134
135 #define CIFR_FLVL2 (0x7f << 23) /* FIFO 2 level mask */
136 #define CIFR_FLVL1 (0x7f << 16) /* FIFO 1 level mask */
137 #define CIFR_FLVL0 (0xff << 8) /* FIFO 0 level mask */
138 #define CIFR_THL_0 (0x3 << 4) /* Threshold Level for Channel 0 FIFO */
139 #define CIFR_RESET_F (1 << 3) /* Reset input FIFOs */
140 #define CIFR_FEN2 (1 << 2) /* FIFO enable for channel 2 */
141 #define CIFR_FEN1 (1 << 1) /* FIFO enable for channel 1 */
142 #define CIFR_FEN0 (1 << 0) /* FIFO enable for channel 0 */
143
144 #define CICR0_SIM_MP (0 << 24)
145 #define CICR0_SIM_SP (1 << 24)
146 #define CICR0_SIM_MS (2 << 24)
147 #define CICR0_SIM_EP (3 << 24)
148 #define CICR0_SIM_ES (4 << 24)
149
150 #define CICR1_DW_VAL(x) ((x) & CICR1_DW) /* Data bus width */
151 #define CICR1_PPL_VAL(x) (((x) << 15) & CICR1_PPL) /* Pixels per line */
152 #define CICR1_COLOR_SP_VAL(x) (((x) << 3) & CICR1_COLOR_SP) /* color space */
153 #define CICR1_RGB_BPP_VAL(x) (((x) << 7) & CICR1_RGB_BPP) /* bpp for rgb */
154 #define CICR1_RGBT_CONV_VAL(x) (((x) << 29) & CICR1_RGBT_CONV) /* rgbt conv */
155
156 #define CICR2_BLW_VAL(x) (((x) << 24) & CICR2_BLW) /* Beginning-of-line pixel clock wait count */
157 #define CICR2_ELW_VAL(x) (((x) << 16) & CICR2_ELW) /* End-of-line pixel clock wait count */
158 #define CICR2_HSW_VAL(x) (((x) << 10) & CICR2_HSW) /* Horizontal sync pulse width */
159 #define CICR2_BFPW_VAL(x) (((x) << 3) & CICR2_BFPW) /* Beginning-of-frame pixel clock wait count */
160 #define CICR2_FSW_VAL(x) (((x) << 0) & CICR2_FSW) /* Frame stabilization wait count */
161
162 #define CICR3_BFW_VAL(x) (((x) << 24) & CICR3_BFW) /* Beginning-of-frame line clock wait count */
163 #define CICR3_EFW_VAL(x) (((x) << 16) & CICR3_EFW) /* End-of-frame line clock wait count */
164 #define CICR3_VSW_VAL(x) (((x) << 11) & CICR3_VSW) /* Vertical sync pulse width */
165 #define CICR3_LPF_VAL(x) (((x) << 0) & CICR3_LPF) /* Lines per frame */
166
167 #define CICR0_IRQ_MASK (CICR0_TOM | CICR0_RDAVM | CICR0_FEM | CICR0_EOLM | \
168 CICR0_PERRM | CICR0_QDM | CICR0_CDM | CICR0_SOFM | \
169 CICR0_EOFM | CICR0_FOM)
170
171 /*
172 * Structures
173 */
174 enum pxa_camera_active_dma {
175 DMA_Y = 0x1,
176 DMA_U = 0x2,
177 DMA_V = 0x4,
178 };
179
180 /* buffer for one video frame */
181 struct pxa_buffer {
182 /* common v4l buffer stuff -- must be first */
183 struct videobuf_buffer vb;
184 u32 code;
185 /* our descriptor lists for Y, U and V channels */
186 struct dma_async_tx_descriptor *descs[3];
187 dma_cookie_t cookie[3];
188 struct scatterlist *sg[3];
189 int sg_len[3];
190 int inwork;
191 enum pxa_camera_active_dma active_dma;
192 };
193
194 struct pxa_camera_dev {
195 struct soc_camera_host soc_host;
196 /*
197 * PXA27x is only supposed to handle one camera on its Quick Capture
198 * interface. If anyone ever builds hardware to enable more than
199 * one camera, they will have to modify this driver too
200 */
201 struct clk *clk;
202
203 unsigned int irq;
204 void __iomem *base;
205
206 int channels;
207 struct dma_chan *dma_chans[3];
208
209 struct pxacamera_platform_data *pdata;
210 struct resource *res;
211 unsigned long platform_flags;
212 unsigned long ciclk;
213 unsigned long mclk;
214 u32 mclk_divisor;
215 u16 width_flags; /* max 10 bits */
216
217 struct list_head capture;
218
219 spinlock_t lock;
220
221 struct pxa_buffer *active;
222 struct tasklet_struct task_eof;
223
224 u32 save_cicr[5];
225 };
226
227 struct pxa_cam {
228 unsigned long flags;
229 };
230
231 static const char *pxa_cam_driver_description = "PXA_Camera";
232
233 static unsigned int vid_limit = 16; /* Video memory limit, in Mb */
234
235 /*
236 * Videobuf operations
237 */
238 static int pxa_videobuf_setup(struct videobuf_queue *vq, unsigned int *count,
239 unsigned int *size)
240 {
241 struct soc_camera_device *icd = vq->priv_data;
242
243 dev_dbg(icd->parent, "count=%d, size=%d\n", *count, *size);
244
245 *size = icd->sizeimage;
246
247 if (0 == *count)
248 *count = 32;
249 if (*size * *count > vid_limit * 1024 * 1024)
250 *count = (vid_limit * 1024 * 1024) / *size;
251
252 return 0;
253 }
254
255 static void free_buffer(struct videobuf_queue *vq, struct pxa_buffer *buf)
256 {
257 struct soc_camera_device *icd = vq->priv_data;
258 struct videobuf_dmabuf *dma = videobuf_to_dma(&buf->vb);
259 int i;
260
261 BUG_ON(in_interrupt());
262
263 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
264 &buf->vb, buf->vb.baddr, buf->vb.bsize);
265
266 /*
267 * This waits until this buffer is out of danger, i.e., until it is no
268 * longer in STATE_QUEUED or STATE_ACTIVE
269 */
270 videobuf_waiton(vq, &buf->vb, 0, 0);
271
272 for (i = 0; i < 3 && buf->descs[i]; i++) {
273 dmaengine_desc_free(buf->descs[i]);
274 kfree(buf->sg[i]);
275 buf->descs[i] = NULL;
276 buf->sg[i] = NULL;
277 buf->sg_len[i] = 0;
278 }
279 videobuf_dma_unmap(vq->dev, dma);
280 videobuf_dma_free(dma);
281
282 buf->vb.state = VIDEOBUF_NEEDS_INIT;
283
284 dev_dbg(icd->parent, "%s end (vb=0x%p) 0x%08lx %d\n", __func__,
285 &buf->vb, buf->vb.baddr, buf->vb.bsize);
286 }
287
288 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
289 enum pxa_camera_active_dma act_dma);
290
291 static void pxa_camera_dma_irq_y(void *data)
292 {
293 struct pxa_camera_dev *pcdev = data;
294
295 pxa_camera_dma_irq(pcdev, DMA_Y);
296 }
297
298 static void pxa_camera_dma_irq_u(void *data)
299 {
300 struct pxa_camera_dev *pcdev = data;
301
302 pxa_camera_dma_irq(pcdev, DMA_U);
303 }
304
305 static void pxa_camera_dma_irq_v(void *data)
306 {
307 struct pxa_camera_dev *pcdev = data;
308
309 pxa_camera_dma_irq(pcdev, DMA_V);
310 }
311
312 /**
313 * pxa_init_dma_channel - init dma descriptors
314 * @pcdev: pxa camera device
315 * @buf: pxa buffer to find pxa dma channel
316 * @dma: dma video buffer
317 * @channel: dma channel (0 => 'Y', 1 => 'U', 2 => 'V')
318 * @cibr: camera Receive Buffer Register
319 * @size: bytes to transfer
320 * @offset: offset in videobuffer of the first byte to transfer
321 *
322 * Prepares the pxa dma descriptors to transfer one camera channel.
323 *
324 * Returns 0 if success or -ENOMEM if no memory is available
325 */
326 static int pxa_init_dma_channel(struct pxa_camera_dev *pcdev,
327 struct pxa_buffer *buf,
328 struct videobuf_dmabuf *dma, int channel,
329 int cibr, int size, int offset)
330 {
331 struct dma_chan *dma_chan = pcdev->dma_chans[channel];
332 struct scatterlist *sg = buf->sg[channel];
333 int sglen = buf->sg_len[channel];
334 struct dma_async_tx_descriptor *tx;
335
336 tx = dmaengine_prep_slave_sg(dma_chan, sg, sglen, DMA_DEV_TO_MEM,
337 DMA_PREP_INTERRUPT | DMA_CTRL_REUSE);
338 if (!tx) {
339 dev_err(pcdev->soc_host.v4l2_dev.dev,
340 "dmaengine_prep_slave_sg failed\n");
341 goto fail;
342 }
343
344 tx->callback_param = pcdev;
345 switch (channel) {
346 case 0:
347 tx->callback = pxa_camera_dma_irq_y;
348 break;
349 case 1:
350 tx->callback = pxa_camera_dma_irq_u;
351 break;
352 case 2:
353 tx->callback = pxa_camera_dma_irq_v;
354 break;
355 }
356
357 buf->descs[channel] = tx;
358 return 0;
359 fail:
360 kfree(sg);
361
362 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
363 "%s (vb=0x%p) dma_tx=%p\n",
364 __func__, &buf->vb, tx);
365
366 return -ENOMEM;
367 }
368
369 static void pxa_videobuf_set_actdma(struct pxa_camera_dev *pcdev,
370 struct pxa_buffer *buf)
371 {
372 buf->active_dma = DMA_Y;
373 if (pcdev->channels == 3)
374 buf->active_dma |= DMA_U | DMA_V;
375 }
376
377 /*
378 * Please check the DMA prepared buffer structure in :
379 * Documentation/video4linux/pxa_camera.txt
380 * Please check also in pxa_camera_check_link_miss() to understand why DMA chain
381 * modification while DMA chain is running will work anyway.
382 */
383 static int pxa_videobuf_prepare(struct videobuf_queue *vq,
384 struct videobuf_buffer *vb, enum v4l2_field field)
385 {
386 struct soc_camera_device *icd = vq->priv_data;
387 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
388 struct pxa_camera_dev *pcdev = ici->priv;
389 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
390 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
391 int ret;
392 int size_y, size_u = 0, size_v = 0;
393 size_t sizes[3];
394
395 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
396 vb, vb->baddr, vb->bsize);
397
398 /* Added list head initialization on alloc */
399 WARN_ON(!list_empty(&vb->queue));
400
401 #ifdef DEBUG
402 /*
403 * This can be useful if you want to see if we actually fill
404 * the buffer with something
405 */
406 memset((void *)vb->baddr, 0xaa, vb->bsize);
407 #endif
408
409 BUG_ON(NULL == icd->current_fmt);
410
411 /*
412 * I think, in buf_prepare you only have to protect global data,
413 * the actual buffer is yours
414 */
415 buf->inwork = 1;
416
417 if (buf->code != icd->current_fmt->code ||
418 vb->width != icd->user_width ||
419 vb->height != icd->user_height ||
420 vb->field != field) {
421 buf->code = icd->current_fmt->code;
422 vb->width = icd->user_width;
423 vb->height = icd->user_height;
424 vb->field = field;
425 vb->state = VIDEOBUF_NEEDS_INIT;
426 }
427
428 vb->size = icd->sizeimage;
429 if (0 != vb->baddr && vb->bsize < vb->size) {
430 ret = -EINVAL;
431 goto out;
432 }
433
434 if (vb->state == VIDEOBUF_NEEDS_INIT) {
435 int size = vb->size;
436 struct videobuf_dmabuf *dma = videobuf_to_dma(vb);
437
438 ret = videobuf_iolock(vq, vb, NULL);
439 if (ret)
440 goto out;
441
442 if (pcdev->channels == 3) {
443 size_y = size / 2;
444 size_u = size_v = size / 4;
445 } else {
446 size_y = size;
447 }
448
449 sizes[0] = size_y;
450 sizes[1] = size_u;
451 sizes[2] = size_v;
452 ret = sg_split(dma->sglist, dma->sglen, 0, pcdev->channels,
453 sizes, buf->sg, buf->sg_len, GFP_KERNEL);
454 if (ret < 0) {
455 dev_err(dev, "sg_split failed: %d\n", ret);
456 goto fail;
457 }
458
459 /* init DMA for Y channel */
460 ret = pxa_init_dma_channel(pcdev, buf, dma, 0, CIBR0,
461 size_y, 0);
462 if (ret) {
463 dev_err(dev, "DMA initialization for Y/RGB failed\n");
464 goto fail;
465 }
466
467 /* init DMA for U channel */
468 if (size_u)
469 ret = pxa_init_dma_channel(pcdev, buf, dma, 1, CIBR1,
470 size_u, size_y);
471 if (ret) {
472 dev_err(dev, "DMA initialization for U failed\n");
473 goto fail;
474 }
475
476 /* init DMA for V channel */
477 if (size_v)
478 ret = pxa_init_dma_channel(pcdev, buf, dma, 2, CIBR2,
479 size_v, size_y + size_u);
480 if (ret) {
481 dev_err(dev, "DMA initialization for V failed\n");
482 goto fail;
483 }
484
485 vb->state = VIDEOBUF_PREPARED;
486 }
487
488 buf->inwork = 0;
489 pxa_videobuf_set_actdma(pcdev, buf);
490
491 return 0;
492
493 fail:
494 free_buffer(vq, buf);
495 out:
496 buf->inwork = 0;
497 return ret;
498 }
499
500 /**
501 * pxa_dma_start_channels - start DMA channel for active buffer
502 * @pcdev: pxa camera device
503 *
504 * Initialize DMA channels to the beginning of the active video buffer, and
505 * start these channels.
506 */
507 static void pxa_dma_start_channels(struct pxa_camera_dev *pcdev)
508 {
509 int i;
510 struct pxa_buffer *active;
511
512 active = pcdev->active;
513
514 for (i = 0; i < pcdev->channels; i++) {
515 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
516 "%s (channel=%d)\n", __func__, i);
517 dma_async_issue_pending(pcdev->dma_chans[i]);
518 }
519 }
520
521 static void pxa_dma_stop_channels(struct pxa_camera_dev *pcdev)
522 {
523 int i;
524
525 for (i = 0; i < pcdev->channels; i++) {
526 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
527 "%s (channel=%d)\n", __func__, i);
528 dmaengine_terminate_all(pcdev->dma_chans[i]);
529 }
530 }
531
532 static void pxa_dma_add_tail_buf(struct pxa_camera_dev *pcdev,
533 struct pxa_buffer *buf)
534 {
535 int i;
536
537 for (i = 0; i < pcdev->channels; i++) {
538 buf->cookie[i] = dmaengine_submit(buf->descs[i]);
539 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
540 "%s (channel=%d) : submit vb=%p cookie=%d\n",
541 __func__, i, buf, buf->descs[i]->cookie);
542 }
543 }
544
545 /**
546 * pxa_camera_start_capture - start video capturing
547 * @pcdev: camera device
548 *
549 * Launch capturing. DMA channels should not be active yet. They should get
550 * activated at the end of frame interrupt, to capture only whole frames, and
551 * never begin the capture of a partial frame.
552 */
553 static void pxa_camera_start_capture(struct pxa_camera_dev *pcdev)
554 {
555 unsigned long cicr0;
556
557 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
558 __raw_writel(__raw_readl(pcdev->base + CISR), pcdev->base + CISR);
559 /* Enable End-Of-Frame Interrupt */
560 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_ENB;
561 cicr0 &= ~CICR0_EOFM;
562 __raw_writel(cicr0, pcdev->base + CICR0);
563 }
564
565 static void pxa_camera_stop_capture(struct pxa_camera_dev *pcdev)
566 {
567 unsigned long cicr0;
568
569 pxa_dma_stop_channels(pcdev);
570
571 cicr0 = __raw_readl(pcdev->base + CICR0) & ~CICR0_ENB;
572 __raw_writel(cicr0, pcdev->base + CICR0);
573
574 pcdev->active = NULL;
575 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s\n", __func__);
576 }
577
578 /* Called under spinlock_irqsave(&pcdev->lock, ...) */
579 static void pxa_videobuf_queue(struct videobuf_queue *vq,
580 struct videobuf_buffer *vb)
581 {
582 struct soc_camera_device *icd = vq->priv_data;
583 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
584 struct pxa_camera_dev *pcdev = ici->priv;
585 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
586
587 dev_dbg(icd->parent, "%s (vb=0x%p) 0x%08lx %d active=%p\n",
588 __func__, vb, vb->baddr, vb->bsize, pcdev->active);
589
590 list_add_tail(&vb->queue, &pcdev->capture);
591
592 vb->state = VIDEOBUF_ACTIVE;
593 pxa_dma_add_tail_buf(pcdev, buf);
594
595 if (!pcdev->active)
596 pxa_camera_start_capture(pcdev);
597 }
598
599 static void pxa_videobuf_release(struct videobuf_queue *vq,
600 struct videobuf_buffer *vb)
601 {
602 struct pxa_buffer *buf = container_of(vb, struct pxa_buffer, vb);
603 #ifdef DEBUG
604 struct soc_camera_device *icd = vq->priv_data;
605 struct device *dev = icd->parent;
606
607 dev_dbg(dev, "%s (vb=0x%p) 0x%08lx %d\n", __func__,
608 vb, vb->baddr, vb->bsize);
609
610 switch (vb->state) {
611 case VIDEOBUF_ACTIVE:
612 dev_dbg(dev, "%s (active)\n", __func__);
613 break;
614 case VIDEOBUF_QUEUED:
615 dev_dbg(dev, "%s (queued)\n", __func__);
616 break;
617 case VIDEOBUF_PREPARED:
618 dev_dbg(dev, "%s (prepared)\n", __func__);
619 break;
620 default:
621 dev_dbg(dev, "%s (unknown)\n", __func__);
622 break;
623 }
624 #endif
625
626 free_buffer(vq, buf);
627 }
628
629 static void pxa_camera_wakeup(struct pxa_camera_dev *pcdev,
630 struct videobuf_buffer *vb,
631 struct pxa_buffer *buf)
632 {
633 /* _init is used to debug races, see comment in pxa_camera_reqbufs() */
634 list_del_init(&vb->queue);
635 vb->state = VIDEOBUF_DONE;
636 v4l2_get_timestamp(&vb->ts);
637 vb->field_count++;
638 wake_up(&vb->done);
639 dev_dbg(pcdev->soc_host.v4l2_dev.dev, "%s dequeud buffer (vb=0x%p)\n",
640 __func__, vb);
641
642 if (list_empty(&pcdev->capture)) {
643 pxa_camera_stop_capture(pcdev);
644 return;
645 }
646
647 pcdev->active = list_entry(pcdev->capture.next,
648 struct pxa_buffer, vb.queue);
649 }
650
651 /**
652 * pxa_camera_check_link_miss - check missed DMA linking
653 * @pcdev: camera device
654 *
655 * The DMA chaining is done with DMA running. This means a tiny temporal window
656 * remains, where a buffer is queued on the chain, while the chain is already
657 * stopped. This means the tailed buffer would never be transferred by DMA.
658 * This function restarts the capture for this corner case, where :
659 * - DADR() == DADDR_STOP
660 * - a videobuffer is queued on the pcdev->capture list
661 *
662 * Please check the "DMA hot chaining timeslice issue" in
663 * Documentation/video4linux/pxa_camera.txt
664 *
665 * Context: should only be called within the dma irq handler
666 */
667 static void pxa_camera_check_link_miss(struct pxa_camera_dev *pcdev,
668 dma_cookie_t last_submitted,
669 dma_cookie_t last_issued)
670 {
671 bool is_dma_stopped = last_submitted != last_issued;
672
673 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
674 "%s : top queued buffer=%p, is_dma_stopped=%d\n",
675 __func__, pcdev->active, is_dma_stopped);
676
677 if (pcdev->active && is_dma_stopped)
678 pxa_camera_start_capture(pcdev);
679 }
680
681 static void pxa_camera_dma_irq(struct pxa_camera_dev *pcdev,
682 enum pxa_camera_active_dma act_dma)
683 {
684 struct device *dev = pcdev->soc_host.v4l2_dev.dev;
685 struct pxa_buffer *buf, *last_buf;
686 unsigned long flags;
687 u32 camera_status, overrun;
688 int chan;
689 struct videobuf_buffer *vb;
690 enum dma_status last_status;
691 dma_cookie_t last_issued;
692
693 spin_lock_irqsave(&pcdev->lock, flags);
694
695 camera_status = __raw_readl(pcdev->base + CISR);
696 dev_dbg(dev, "camera dma irq, cisr=0x%x dma=%d\n",
697 camera_status, act_dma);
698 overrun = CISR_IFO_0;
699 if (pcdev->channels == 3)
700 overrun |= CISR_IFO_1 | CISR_IFO_2;
701
702 /*
703 * pcdev->active should not be NULL in DMA irq handler.
704 *
705 * But there is one corner case : if capture was stopped due to an
706 * overrun of channel 1, and at that same channel 2 was completed.
707 *
708 * When handling the overrun in DMA irq for channel 1, we'll stop the
709 * capture and restart it (and thus set pcdev->active to NULL). But the
710 * DMA irq handler will already be pending for channel 2. So on entering
711 * the DMA irq handler for channel 2 there will be no active buffer, yet
712 * that is normal.
713 */
714 if (!pcdev->active)
715 goto out;
716
717 vb = &pcdev->active->vb;
718 buf = container_of(vb, struct pxa_buffer, vb);
719 WARN_ON(buf->inwork || list_empty(&vb->queue));
720
721 /*
722 * It's normal if the last frame creates an overrun, as there
723 * are no more DMA descriptors to fetch from QCI fifos
724 */
725 switch (act_dma) {
726 case DMA_U:
727 chan = 1;
728 break;
729 case DMA_V:
730 chan = 2;
731 break;
732 default:
733 chan = 0;
734 break;
735 }
736 last_buf = list_entry(pcdev->capture.prev,
737 struct pxa_buffer, vb.queue);
738 last_status = dma_async_is_tx_complete(pcdev->dma_chans[chan],
739 last_buf->cookie[chan],
740 NULL, &last_issued);
741 if (camera_status & overrun &&
742 last_status != DMA_COMPLETE) {
743 dev_dbg(dev, "FIFO overrun! CISR: %x\n",
744 camera_status);
745 pxa_camera_stop_capture(pcdev);
746 list_for_each_entry(buf, &pcdev->capture, vb.queue)
747 pxa_dma_add_tail_buf(pcdev, buf);
748 pxa_camera_start_capture(pcdev);
749 goto out;
750 }
751 buf->active_dma &= ~act_dma;
752 if (!buf->active_dma) {
753 pxa_camera_wakeup(pcdev, vb, buf);
754 pxa_camera_check_link_miss(pcdev, last_buf->cookie[chan],
755 last_issued);
756 }
757
758 out:
759 spin_unlock_irqrestore(&pcdev->lock, flags);
760 }
761
762 static struct videobuf_queue_ops pxa_videobuf_ops = {
763 .buf_setup = pxa_videobuf_setup,
764 .buf_prepare = pxa_videobuf_prepare,
765 .buf_queue = pxa_videobuf_queue,
766 .buf_release = pxa_videobuf_release,
767 };
768
769 static void pxa_camera_init_videobuf(struct videobuf_queue *q,
770 struct soc_camera_device *icd)
771 {
772 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
773 struct pxa_camera_dev *pcdev = ici->priv;
774
775 /*
776 * We must pass NULL as dev pointer, then all pci_* dma operations
777 * transform to normal dma_* ones.
778 */
779 videobuf_queue_sg_init(q, &pxa_videobuf_ops, NULL, &pcdev->lock,
780 V4L2_BUF_TYPE_VIDEO_CAPTURE, V4L2_FIELD_NONE,
781 sizeof(struct pxa_buffer), icd, &ici->host_lock);
782 }
783
784 static u32 mclk_get_divisor(struct platform_device *pdev,
785 struct pxa_camera_dev *pcdev)
786 {
787 unsigned long mclk = pcdev->mclk;
788 struct device *dev = &pdev->dev;
789 u32 div;
790 unsigned long lcdclk;
791
792 lcdclk = clk_get_rate(pcdev->clk);
793 pcdev->ciclk = lcdclk;
794
795 /* mclk <= ciclk / 4 (27.4.2) */
796 if (mclk > lcdclk / 4) {
797 mclk = lcdclk / 4;
798 dev_warn(dev, "Limiting master clock to %lu\n", mclk);
799 }
800
801 /* We verify mclk != 0, so if anyone breaks it, here comes their Oops */
802 div = (lcdclk + 2 * mclk - 1) / (2 * mclk) - 1;
803
804 /* If we're not supplying MCLK, leave it at 0 */
805 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
806 pcdev->mclk = lcdclk / (2 * (div + 1));
807
808 dev_dbg(dev, "LCD clock %luHz, target freq %luHz, divisor %u\n",
809 lcdclk, mclk, div);
810
811 return div;
812 }
813
814 static void recalculate_fifo_timeout(struct pxa_camera_dev *pcdev,
815 unsigned long pclk)
816 {
817 /* We want a timeout > 1 pixel time, not ">=" */
818 u32 ciclk_per_pixel = pcdev->ciclk / pclk + 1;
819
820 __raw_writel(ciclk_per_pixel, pcdev->base + CITOR);
821 }
822
823 static void pxa_camera_activate(struct pxa_camera_dev *pcdev)
824 {
825 u32 cicr4 = 0;
826
827 /* disable all interrupts */
828 __raw_writel(0x3ff, pcdev->base + CICR0);
829
830 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
831 cicr4 |= CICR4_PCLK_EN;
832 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
833 cicr4 |= CICR4_MCLK_EN;
834 if (pcdev->platform_flags & PXA_CAMERA_PCP)
835 cicr4 |= CICR4_PCP;
836 if (pcdev->platform_flags & PXA_CAMERA_HSP)
837 cicr4 |= CICR4_HSP;
838 if (pcdev->platform_flags & PXA_CAMERA_VSP)
839 cicr4 |= CICR4_VSP;
840
841 __raw_writel(pcdev->mclk_divisor | cicr4, pcdev->base + CICR4);
842
843 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
844 /* Initialise the timeout under the assumption pclk = mclk */
845 recalculate_fifo_timeout(pcdev, pcdev->mclk);
846 else
847 /* "Safe default" - 13MHz */
848 recalculate_fifo_timeout(pcdev, 13000000);
849
850 clk_prepare_enable(pcdev->clk);
851 }
852
853 static void pxa_camera_deactivate(struct pxa_camera_dev *pcdev)
854 {
855 clk_disable_unprepare(pcdev->clk);
856 }
857
858 static void pxa_camera_eof(unsigned long arg)
859 {
860 struct pxa_camera_dev *pcdev = (struct pxa_camera_dev *)arg;
861 unsigned long cifr;
862 struct pxa_buffer *buf;
863 struct videobuf_buffer *vb;
864
865 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
866 "Camera interrupt status 0x%x\n",
867 __raw_readl(pcdev->base + CISR));
868
869 /* Reset the FIFOs */
870 cifr = __raw_readl(pcdev->base + CIFR) | CIFR_RESET_F;
871 __raw_writel(cifr, pcdev->base + CIFR);
872
873 pcdev->active = list_first_entry(&pcdev->capture,
874 struct pxa_buffer, vb.queue);
875 vb = &pcdev->active->vb;
876 buf = container_of(vb, struct pxa_buffer, vb);
877 pxa_videobuf_set_actdma(pcdev, buf);
878
879 pxa_dma_start_channels(pcdev);
880 }
881
882 static irqreturn_t pxa_camera_irq(int irq, void *data)
883 {
884 struct pxa_camera_dev *pcdev = data;
885 unsigned long status, cicr0;
886
887 status = __raw_readl(pcdev->base + CISR);
888 dev_dbg(pcdev->soc_host.v4l2_dev.dev,
889 "Camera interrupt status 0x%lx\n", status);
890
891 if (!status)
892 return IRQ_NONE;
893
894 __raw_writel(status, pcdev->base + CISR);
895
896 if (status & CISR_EOF) {
897 cicr0 = __raw_readl(pcdev->base + CICR0) | CICR0_EOFM;
898 __raw_writel(cicr0, pcdev->base + CICR0);
899 tasklet_schedule(&pcdev->task_eof);
900 }
901
902 return IRQ_HANDLED;
903 }
904
905 static int pxa_camera_add_device(struct soc_camera_device *icd)
906 {
907 dev_info(icd->parent, "PXA Camera driver attached to camera %d\n",
908 icd->devnum);
909
910 return 0;
911 }
912
913 static void pxa_camera_remove_device(struct soc_camera_device *icd)
914 {
915 dev_info(icd->parent, "PXA Camera driver detached from camera %d\n",
916 icd->devnum);
917 }
918
919 /*
920 * The following two functions absolutely depend on the fact, that
921 * there can be only one camera on PXA quick capture interface
922 * Called with .host_lock held
923 */
924 static int pxa_camera_clock_start(struct soc_camera_host *ici)
925 {
926 struct pxa_camera_dev *pcdev = ici->priv;
927
928 pxa_camera_activate(pcdev);
929
930 return 0;
931 }
932
933 /* Called with .host_lock held */
934 static void pxa_camera_clock_stop(struct soc_camera_host *ici)
935 {
936 struct pxa_camera_dev *pcdev = ici->priv;
937
938 /* disable capture, disable interrupts */
939 __raw_writel(0x3ff, pcdev->base + CICR0);
940
941 /* Stop DMA engine */
942 pxa_dma_stop_channels(pcdev);
943 pxa_camera_deactivate(pcdev);
944 }
945
946 static int test_platform_param(struct pxa_camera_dev *pcdev,
947 unsigned char buswidth, unsigned long *flags)
948 {
949 /*
950 * Platform specified synchronization and pixel clock polarities are
951 * only a recommendation and are only used during probing. The PXA270
952 * quick capture interface supports both.
953 */
954 *flags = (pcdev->platform_flags & PXA_CAMERA_MASTER ?
955 V4L2_MBUS_MASTER : V4L2_MBUS_SLAVE) |
956 V4L2_MBUS_HSYNC_ACTIVE_HIGH |
957 V4L2_MBUS_HSYNC_ACTIVE_LOW |
958 V4L2_MBUS_VSYNC_ACTIVE_HIGH |
959 V4L2_MBUS_VSYNC_ACTIVE_LOW |
960 V4L2_MBUS_DATA_ACTIVE_HIGH |
961 V4L2_MBUS_PCLK_SAMPLE_RISING |
962 V4L2_MBUS_PCLK_SAMPLE_FALLING;
963
964 /* If requested data width is supported by the platform, use it */
965 if ((1 << (buswidth - 1)) & pcdev->width_flags)
966 return 0;
967
968 return -EINVAL;
969 }
970
971 static void pxa_camera_setup_cicr(struct soc_camera_device *icd,
972 unsigned long flags, __u32 pixfmt)
973 {
974 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
975 struct pxa_camera_dev *pcdev = ici->priv;
976 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
977 unsigned long dw, bpp;
978 u32 cicr0, cicr1, cicr2, cicr3, cicr4 = 0, y_skip_top;
979 int ret = v4l2_subdev_call(sd, sensor, g_skip_top_lines, &y_skip_top);
980
981 if (ret < 0)
982 y_skip_top = 0;
983
984 /*
985 * Datawidth is now guaranteed to be equal to one of the three values.
986 * We fix bit-per-pixel equal to data-width...
987 */
988 switch (icd->current_fmt->host_fmt->bits_per_sample) {
989 case 10:
990 dw = 4;
991 bpp = 0x40;
992 break;
993 case 9:
994 dw = 3;
995 bpp = 0x20;
996 break;
997 default:
998 /*
999 * Actually it can only be 8 now,
1000 * default is just to silence compiler warnings
1001 */
1002 case 8:
1003 dw = 2;
1004 bpp = 0;
1005 }
1006
1007 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1008 cicr4 |= CICR4_PCLK_EN;
1009 if (pcdev->platform_flags & PXA_CAMERA_MCLK_EN)
1010 cicr4 |= CICR4_MCLK_EN;
1011 if (flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1012 cicr4 |= CICR4_PCP;
1013 if (flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)
1014 cicr4 |= CICR4_HSP;
1015 if (flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)
1016 cicr4 |= CICR4_VSP;
1017
1018 cicr0 = __raw_readl(pcdev->base + CICR0);
1019 if (cicr0 & CICR0_ENB)
1020 __raw_writel(cicr0 & ~CICR0_ENB, pcdev->base + CICR0);
1021
1022 cicr1 = CICR1_PPL_VAL(icd->user_width - 1) | bpp | dw;
1023
1024 switch (pixfmt) {
1025 case V4L2_PIX_FMT_YUV422P:
1026 pcdev->channels = 3;
1027 cicr1 |= CICR1_YCBCR_F;
1028 /*
1029 * Normally, pxa bus wants as input UYVY format. We allow all
1030 * reorderings of the YUV422 format, as no processing is done,
1031 * and the YUV stream is just passed through without any
1032 * transformation. Note that UYVY is the only format that
1033 * should be used if pxa framebuffer Overlay2 is used.
1034 */
1035 case V4L2_PIX_FMT_UYVY:
1036 case V4L2_PIX_FMT_VYUY:
1037 case V4L2_PIX_FMT_YUYV:
1038 case V4L2_PIX_FMT_YVYU:
1039 cicr1 |= CICR1_COLOR_SP_VAL(2);
1040 break;
1041 case V4L2_PIX_FMT_RGB555:
1042 cicr1 |= CICR1_RGB_BPP_VAL(1) | CICR1_RGBT_CONV_VAL(2) |
1043 CICR1_TBIT | CICR1_COLOR_SP_VAL(1);
1044 break;
1045 case V4L2_PIX_FMT_RGB565:
1046 cicr1 |= CICR1_COLOR_SP_VAL(1) | CICR1_RGB_BPP_VAL(2);
1047 break;
1048 }
1049
1050 cicr2 = 0;
1051 cicr3 = CICR3_LPF_VAL(icd->user_height - 1) |
1052 CICR3_BFW_VAL(min((u32)255, y_skip_top));
1053 cicr4 |= pcdev->mclk_divisor;
1054
1055 __raw_writel(cicr1, pcdev->base + CICR1);
1056 __raw_writel(cicr2, pcdev->base + CICR2);
1057 __raw_writel(cicr3, pcdev->base + CICR3);
1058 __raw_writel(cicr4, pcdev->base + CICR4);
1059
1060 /* CIF interrupts are not used, only DMA */
1061 cicr0 = (cicr0 & CICR0_ENB) | (pcdev->platform_flags & PXA_CAMERA_MASTER ?
1062 CICR0_SIM_MP : (CICR0_SL_CAP_EN | CICR0_SIM_SP));
1063 cicr0 |= CICR0_DMAEN | CICR0_IRQ_MASK;
1064 __raw_writel(cicr0, pcdev->base + CICR0);
1065 }
1066
1067 static int pxa_camera_set_bus_param(struct soc_camera_device *icd)
1068 {
1069 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1070 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1071 struct pxa_camera_dev *pcdev = ici->priv;
1072 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1073 u32 pixfmt = icd->current_fmt->host_fmt->fourcc;
1074 unsigned long bus_flags, common_flags;
1075 int ret;
1076 struct pxa_cam *cam = icd->host_priv;
1077
1078 ret = test_platform_param(pcdev, icd->current_fmt->host_fmt->bits_per_sample,
1079 &bus_flags);
1080 if (ret < 0)
1081 return ret;
1082
1083 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1084 if (!ret) {
1085 common_flags = soc_mbus_config_compatible(&cfg,
1086 bus_flags);
1087 if (!common_flags) {
1088 dev_warn(icd->parent,
1089 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1090 cfg.flags, bus_flags);
1091 return -EINVAL;
1092 }
1093 } else if (ret != -ENOIOCTLCMD) {
1094 return ret;
1095 } else {
1096 common_flags = bus_flags;
1097 }
1098
1099 pcdev->channels = 1;
1100
1101 /* Make choises, based on platform preferences */
1102 if ((common_flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH) &&
1103 (common_flags & V4L2_MBUS_HSYNC_ACTIVE_LOW)) {
1104 if (pcdev->platform_flags & PXA_CAMERA_HSP)
1105 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_HIGH;
1106 else
1107 common_flags &= ~V4L2_MBUS_HSYNC_ACTIVE_LOW;
1108 }
1109
1110 if ((common_flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH) &&
1111 (common_flags & V4L2_MBUS_VSYNC_ACTIVE_LOW)) {
1112 if (pcdev->platform_flags & PXA_CAMERA_VSP)
1113 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_HIGH;
1114 else
1115 common_flags &= ~V4L2_MBUS_VSYNC_ACTIVE_LOW;
1116 }
1117
1118 if ((common_flags & V4L2_MBUS_PCLK_SAMPLE_RISING) &&
1119 (common_flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)) {
1120 if (pcdev->platform_flags & PXA_CAMERA_PCP)
1121 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_RISING;
1122 else
1123 common_flags &= ~V4L2_MBUS_PCLK_SAMPLE_FALLING;
1124 }
1125
1126 cfg.flags = common_flags;
1127 ret = v4l2_subdev_call(sd, video, s_mbus_config, &cfg);
1128 if (ret < 0 && ret != -ENOIOCTLCMD) {
1129 dev_dbg(icd->parent, "camera s_mbus_config(0x%lx) returned %d\n",
1130 common_flags, ret);
1131 return ret;
1132 }
1133
1134 cam->flags = common_flags;
1135
1136 pxa_camera_setup_cicr(icd, common_flags, pixfmt);
1137
1138 return 0;
1139 }
1140
1141 static int pxa_camera_try_bus_param(struct soc_camera_device *icd,
1142 unsigned char buswidth)
1143 {
1144 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1145 struct soc_camera_host *ici = to_soc_camera_host(icd->parent);
1146 struct pxa_camera_dev *pcdev = ici->priv;
1147 struct v4l2_mbus_config cfg = {.type = V4L2_MBUS_PARALLEL,};
1148 unsigned long bus_flags, common_flags;
1149 int ret = test_platform_param(pcdev, buswidth, &bus_flags);
1150
1151 if (ret < 0)
1152 return ret;
1153
1154 ret = v4l2_subdev_call(sd, video, g_mbus_config, &cfg);
1155 if (!ret) {
1156 common_flags = soc_mbus_config_compatible(&cfg,
1157 bus_flags);
1158 if (!common_flags) {
1159 dev_warn(icd->parent,
1160 "Flags incompatible: camera 0x%x, host 0x%lx\n",
1161 cfg.flags, bus_flags);
1162 return -EINVAL;
1163 }
1164 } else if (ret == -ENOIOCTLCMD) {
1165 ret = 0;
1166 }
1167
1168 return ret;
1169 }
1170
1171 static const struct soc_mbus_pixelfmt pxa_camera_formats[] = {
1172 {
1173 .fourcc = V4L2_PIX_FMT_YUV422P,
1174 .name = "Planar YUV422 16 bit",
1175 .bits_per_sample = 8,
1176 .packing = SOC_MBUS_PACKING_2X8_PADHI,
1177 .order = SOC_MBUS_ORDER_LE,
1178 .layout = SOC_MBUS_LAYOUT_PLANAR_2Y_U_V,
1179 },
1180 };
1181
1182 /* This will be corrected as we get more formats */
1183 static bool pxa_camera_packing_supported(const struct soc_mbus_pixelfmt *fmt)
1184 {
1185 return fmt->packing == SOC_MBUS_PACKING_NONE ||
1186 (fmt->bits_per_sample == 8 &&
1187 fmt->packing == SOC_MBUS_PACKING_2X8_PADHI) ||
1188 (fmt->bits_per_sample > 8 &&
1189 fmt->packing == SOC_MBUS_PACKING_EXTEND16);
1190 }
1191
1192 static int pxa_camera_get_formats(struct soc_camera_device *icd, unsigned int idx,
1193 struct soc_camera_format_xlate *xlate)
1194 {
1195 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1196 struct device *dev = icd->parent;
1197 int formats = 0, ret;
1198 struct pxa_cam *cam;
1199 struct v4l2_subdev_mbus_code_enum code = {
1200 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1201 .index = idx,
1202 };
1203 const struct soc_mbus_pixelfmt *fmt;
1204
1205 ret = v4l2_subdev_call(sd, pad, enum_mbus_code, NULL, &code);
1206 if (ret < 0)
1207 /* No more formats */
1208 return 0;
1209
1210 fmt = soc_mbus_get_fmtdesc(code.code);
1211 if (!fmt) {
1212 dev_err(dev, "Invalid format code #%u: %d\n", idx, code.code);
1213 return 0;
1214 }
1215
1216 /* This also checks support for the requested bits-per-sample */
1217 ret = pxa_camera_try_bus_param(icd, fmt->bits_per_sample);
1218 if (ret < 0)
1219 return 0;
1220
1221 if (!icd->host_priv) {
1222 cam = kzalloc(sizeof(*cam), GFP_KERNEL);
1223 if (!cam)
1224 return -ENOMEM;
1225
1226 icd->host_priv = cam;
1227 } else {
1228 cam = icd->host_priv;
1229 }
1230
1231 switch (code.code) {
1232 case MEDIA_BUS_FMT_UYVY8_2X8:
1233 formats++;
1234 if (xlate) {
1235 xlate->host_fmt = &pxa_camera_formats[0];
1236 xlate->code = code.code;
1237 xlate++;
1238 dev_dbg(dev, "Providing format %s using code %d\n",
1239 pxa_camera_formats[0].name, code.code);
1240 }
1241 case MEDIA_BUS_FMT_VYUY8_2X8:
1242 case MEDIA_BUS_FMT_YUYV8_2X8:
1243 case MEDIA_BUS_FMT_YVYU8_2X8:
1244 case MEDIA_BUS_FMT_RGB565_2X8_LE:
1245 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
1246 if (xlate)
1247 dev_dbg(dev, "Providing format %s packed\n",
1248 fmt->name);
1249 break;
1250 default:
1251 if (!pxa_camera_packing_supported(fmt))
1252 return 0;
1253 if (xlate)
1254 dev_dbg(dev,
1255 "Providing format %s in pass-through mode\n",
1256 fmt->name);
1257 }
1258
1259 /* Generic pass-through */
1260 formats++;
1261 if (xlate) {
1262 xlate->host_fmt = fmt;
1263 xlate->code = code.code;
1264 xlate++;
1265 }
1266
1267 return formats;
1268 }
1269
1270 static void pxa_camera_put_formats(struct soc_camera_device *icd)
1271 {
1272 kfree(icd->host_priv);
1273 icd->host_priv = NULL;
1274 }
1275
1276 static int pxa_camera_check_frame(u32 width, u32 height)
1277 {
1278 /* limit to pxa hardware capabilities */
1279 return height < 32 || height > 2048 || width < 48 || width > 2048 ||
1280 (width & 0x01);
1281 }
1282
1283 static int pxa_camera_set_crop(struct soc_camera_device *icd,
1284 const struct v4l2_crop *a)
1285 {
1286 const struct v4l2_rect *rect = &a->c;
1287 struct device *dev = icd->parent;
1288 struct soc_camera_host *ici = to_soc_camera_host(dev);
1289 struct pxa_camera_dev *pcdev = ici->priv;
1290 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1291 struct soc_camera_sense sense = {
1292 .master_clock = pcdev->mclk,
1293 .pixel_clock_max = pcdev->ciclk / 4,
1294 };
1295 struct v4l2_subdev_format fmt = {
1296 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1297 };
1298 struct v4l2_mbus_framefmt *mf = &fmt.format;
1299 struct pxa_cam *cam = icd->host_priv;
1300 u32 fourcc = icd->current_fmt->host_fmt->fourcc;
1301 int ret;
1302
1303 /* If PCLK is used to latch data from the sensor, check sense */
1304 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1305 icd->sense = &sense;
1306
1307 ret = v4l2_subdev_call(sd, video, s_crop, a);
1308
1309 icd->sense = NULL;
1310
1311 if (ret < 0) {
1312 dev_warn(dev, "Failed to crop to %ux%u@%u:%u\n",
1313 rect->width, rect->height, rect->left, rect->top);
1314 return ret;
1315 }
1316
1317 ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &fmt);
1318 if (ret < 0)
1319 return ret;
1320
1321 if (pxa_camera_check_frame(mf->width, mf->height)) {
1322 /*
1323 * Camera cropping produced a frame beyond our capabilities.
1324 * FIXME: just extract a subframe, that we can process.
1325 */
1326 v4l_bound_align_image(&mf->width, 48, 2048, 1,
1327 &mf->height, 32, 2048, 0,
1328 fourcc == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1329 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &fmt);
1330 if (ret < 0)
1331 return ret;
1332
1333 if (pxa_camera_check_frame(mf->width, mf->height)) {
1334 dev_warn(icd->parent,
1335 "Inconsistent state. Use S_FMT to repair\n");
1336 return -EINVAL;
1337 }
1338 }
1339
1340 if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1341 if (sense.pixel_clock > sense.pixel_clock_max) {
1342 dev_err(dev,
1343 "pixel clock %lu set by the camera too high!",
1344 sense.pixel_clock);
1345 return -EIO;
1346 }
1347 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1348 }
1349
1350 icd->user_width = mf->width;
1351 icd->user_height = mf->height;
1352
1353 pxa_camera_setup_cicr(icd, cam->flags, fourcc);
1354
1355 return ret;
1356 }
1357
1358 static int pxa_camera_set_fmt(struct soc_camera_device *icd,
1359 struct v4l2_format *f)
1360 {
1361 struct device *dev = icd->parent;
1362 struct soc_camera_host *ici = to_soc_camera_host(dev);
1363 struct pxa_camera_dev *pcdev = ici->priv;
1364 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1365 const struct soc_camera_format_xlate *xlate = NULL;
1366 struct soc_camera_sense sense = {
1367 .master_clock = pcdev->mclk,
1368 .pixel_clock_max = pcdev->ciclk / 4,
1369 };
1370 struct v4l2_pix_format *pix = &f->fmt.pix;
1371 struct v4l2_subdev_format format = {
1372 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
1373 };
1374 struct v4l2_mbus_framefmt *mf = &format.format;
1375 int ret;
1376
1377 xlate = soc_camera_xlate_by_fourcc(icd, pix->pixelformat);
1378 if (!xlate) {
1379 dev_warn(dev, "Format %x not found\n", pix->pixelformat);
1380 return -EINVAL;
1381 }
1382
1383 /* If PCLK is used to latch data from the sensor, check sense */
1384 if (pcdev->platform_flags & PXA_CAMERA_PCLK_EN)
1385 /* The caller holds a mutex. */
1386 icd->sense = &sense;
1387
1388 mf->width = pix->width;
1389 mf->height = pix->height;
1390 mf->field = pix->field;
1391 mf->colorspace = pix->colorspace;
1392 mf->code = xlate->code;
1393
1394 ret = v4l2_subdev_call(sd, pad, set_fmt, NULL, &format);
1395
1396 if (mf->code != xlate->code)
1397 return -EINVAL;
1398
1399 icd->sense = NULL;
1400
1401 if (ret < 0) {
1402 dev_warn(dev, "Failed to configure for format %x\n",
1403 pix->pixelformat);
1404 } else if (pxa_camera_check_frame(mf->width, mf->height)) {
1405 dev_warn(dev,
1406 "Camera driver produced an unsupported frame %dx%d\n",
1407 mf->width, mf->height);
1408 ret = -EINVAL;
1409 } else if (sense.flags & SOCAM_SENSE_PCLK_CHANGED) {
1410 if (sense.pixel_clock > sense.pixel_clock_max) {
1411 dev_err(dev,
1412 "pixel clock %lu set by the camera too high!",
1413 sense.pixel_clock);
1414 return -EIO;
1415 }
1416 recalculate_fifo_timeout(pcdev, sense.pixel_clock);
1417 }
1418
1419 if (ret < 0)
1420 return ret;
1421
1422 pix->width = mf->width;
1423 pix->height = mf->height;
1424 pix->field = mf->field;
1425 pix->colorspace = mf->colorspace;
1426 icd->current_fmt = xlate;
1427
1428 return ret;
1429 }
1430
1431 static int pxa_camera_try_fmt(struct soc_camera_device *icd,
1432 struct v4l2_format *f)
1433 {
1434 struct v4l2_subdev *sd = soc_camera_to_subdev(icd);
1435 const struct soc_camera_format_xlate *xlate;
1436 struct v4l2_pix_format *pix = &f->fmt.pix;
1437 struct v4l2_subdev_pad_config pad_cfg;
1438 struct v4l2_subdev_format format = {
1439 .which = V4L2_SUBDEV_FORMAT_TRY,
1440 };
1441 struct v4l2_mbus_framefmt *mf = &format.format;
1442 __u32 pixfmt = pix->pixelformat;
1443 int ret;
1444
1445 xlate = soc_camera_xlate_by_fourcc(icd, pixfmt);
1446 if (!xlate) {
1447 dev_warn(icd->parent, "Format %x not found\n", pixfmt);
1448 return -EINVAL;
1449 }
1450
1451 /*
1452 * Limit to pxa hardware capabilities. YUV422P planar format requires
1453 * images size to be a multiple of 16 bytes. If not, zeros will be
1454 * inserted between Y and U planes, and U and V planes, which violates
1455 * the YUV422P standard.
1456 */
1457 v4l_bound_align_image(&pix->width, 48, 2048, 1,
1458 &pix->height, 32, 2048, 0,
1459 pixfmt == V4L2_PIX_FMT_YUV422P ? 4 : 0);
1460
1461 /* limit to sensor capabilities */
1462 mf->width = pix->width;
1463 mf->height = pix->height;
1464 /* Only progressive video supported so far */
1465 mf->field = V4L2_FIELD_NONE;
1466 mf->colorspace = pix->colorspace;
1467 mf->code = xlate->code;
1468
1469 ret = v4l2_subdev_call(sd, pad, set_fmt, &pad_cfg, &format);
1470 if (ret < 0)
1471 return ret;
1472
1473 pix->width = mf->width;
1474 pix->height = mf->height;
1475 pix->colorspace = mf->colorspace;
1476
1477 switch (mf->field) {
1478 case V4L2_FIELD_ANY:
1479 case V4L2_FIELD_NONE:
1480 pix->field = V4L2_FIELD_NONE;
1481 break;
1482 default:
1483 /* TODO: support interlaced at least in pass-through mode */
1484 dev_err(icd->parent, "Field type %d unsupported.\n",
1485 mf->field);
1486 return -EINVAL;
1487 }
1488
1489 return ret;
1490 }
1491
1492 static int pxa_camera_reqbufs(struct soc_camera_device *icd,
1493 struct v4l2_requestbuffers *p)
1494 {
1495 int i;
1496
1497 /*
1498 * This is for locking debugging only. I removed spinlocks and now I
1499 * check whether .prepare is ever called on a linked buffer, or whether
1500 * a dma IRQ can occur for an in-work or unlinked buffer. Until now
1501 * it hadn't triggered
1502 */
1503 for (i = 0; i < p->count; i++) {
1504 struct pxa_buffer *buf = container_of(icd->vb_vidq.bufs[i],
1505 struct pxa_buffer, vb);
1506 buf->inwork = 0;
1507 INIT_LIST_HEAD(&buf->vb.queue);
1508 }
1509
1510 return 0;
1511 }
1512
1513 static unsigned int pxa_camera_poll(struct file *file, poll_table *pt)
1514 {
1515 struct soc_camera_device *icd = file->private_data;
1516 struct pxa_buffer *buf;
1517
1518 buf = list_entry(icd->vb_vidq.stream.next, struct pxa_buffer,
1519 vb.stream);
1520
1521 poll_wait(file, &buf->vb.done, pt);
1522
1523 if (buf->vb.state == VIDEOBUF_DONE ||
1524 buf->vb.state == VIDEOBUF_ERROR)
1525 return POLLIN|POLLRDNORM;
1526
1527 return 0;
1528 }
1529
1530 static int pxa_camera_querycap(struct soc_camera_host *ici,
1531 struct v4l2_capability *cap)
1532 {
1533 /* cap->name is set by the firendly caller:-> */
1534 strlcpy(cap->card, pxa_cam_driver_description, sizeof(cap->card));
1535 cap->device_caps = V4L2_CAP_VIDEO_CAPTURE | V4L2_CAP_STREAMING;
1536 cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
1537
1538 return 0;
1539 }
1540
1541 static int pxa_camera_suspend(struct device *dev)
1542 {
1543 struct soc_camera_host *ici = to_soc_camera_host(dev);
1544 struct pxa_camera_dev *pcdev = ici->priv;
1545 int i = 0, ret = 0;
1546
1547 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR0);
1548 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR1);
1549 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR2);
1550 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR3);
1551 pcdev->save_cicr[i++] = __raw_readl(pcdev->base + CICR4);
1552
1553 if (pcdev->soc_host.icd) {
1554 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd);
1555 ret = v4l2_subdev_call(sd, core, s_power, 0);
1556 if (ret == -ENOIOCTLCMD)
1557 ret = 0;
1558 }
1559
1560 return ret;
1561 }
1562
1563 static int pxa_camera_resume(struct device *dev)
1564 {
1565 struct soc_camera_host *ici = to_soc_camera_host(dev);
1566 struct pxa_camera_dev *pcdev = ici->priv;
1567 int i = 0, ret = 0;
1568
1569 __raw_writel(pcdev->save_cicr[i++] & ~CICR0_ENB, pcdev->base + CICR0);
1570 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR1);
1571 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR2);
1572 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR3);
1573 __raw_writel(pcdev->save_cicr[i++], pcdev->base + CICR4);
1574
1575 if (pcdev->soc_host.icd) {
1576 struct v4l2_subdev *sd = soc_camera_to_subdev(pcdev->soc_host.icd);
1577 ret = v4l2_subdev_call(sd, core, s_power, 1);
1578 if (ret == -ENOIOCTLCMD)
1579 ret = 0;
1580 }
1581
1582 /* Restart frame capture if active buffer exists */
1583 if (!ret && pcdev->active)
1584 pxa_camera_start_capture(pcdev);
1585
1586 return ret;
1587 }
1588
1589 static struct soc_camera_host_ops pxa_soc_camera_host_ops = {
1590 .owner = THIS_MODULE,
1591 .add = pxa_camera_add_device,
1592 .remove = pxa_camera_remove_device,
1593 .clock_start = pxa_camera_clock_start,
1594 .clock_stop = pxa_camera_clock_stop,
1595 .set_crop = pxa_camera_set_crop,
1596 .get_formats = pxa_camera_get_formats,
1597 .put_formats = pxa_camera_put_formats,
1598 .set_fmt = pxa_camera_set_fmt,
1599 .try_fmt = pxa_camera_try_fmt,
1600 .init_videobuf = pxa_camera_init_videobuf,
1601 .reqbufs = pxa_camera_reqbufs,
1602 .poll = pxa_camera_poll,
1603 .querycap = pxa_camera_querycap,
1604 .set_bus_param = pxa_camera_set_bus_param,
1605 };
1606
1607 static int pxa_camera_pdata_from_dt(struct device *dev,
1608 struct pxa_camera_dev *pcdev)
1609 {
1610 u32 mclk_rate;
1611 struct device_node *np = dev->of_node;
1612 struct v4l2_of_endpoint ep;
1613 int err = of_property_read_u32(np, "clock-frequency",
1614 &mclk_rate);
1615 if (!err) {
1616 pcdev->platform_flags |= PXA_CAMERA_MCLK_EN;
1617 pcdev->mclk = mclk_rate;
1618 }
1619
1620 np = of_graph_get_next_endpoint(np, NULL);
1621 if (!np) {
1622 dev_err(dev, "could not find endpoint\n");
1623 return -EINVAL;
1624 }
1625
1626 err = v4l2_of_parse_endpoint(np, &ep);
1627 if (err) {
1628 dev_err(dev, "could not parse endpoint\n");
1629 goto out;
1630 }
1631
1632 switch (ep.bus.parallel.bus_width) {
1633 case 4:
1634 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_4;
1635 break;
1636 case 5:
1637 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_5;
1638 break;
1639 case 8:
1640 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_8;
1641 break;
1642 case 9:
1643 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_9;
1644 break;
1645 case 10:
1646 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1647 break;
1648 default:
1649 break;
1650 }
1651
1652 if (ep.bus.parallel.flags & V4L2_MBUS_MASTER)
1653 pcdev->platform_flags |= PXA_CAMERA_MASTER;
1654 if (ep.bus.parallel.flags & V4L2_MBUS_HSYNC_ACTIVE_HIGH)
1655 pcdev->platform_flags |= PXA_CAMERA_HSP;
1656 if (ep.bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
1657 pcdev->platform_flags |= PXA_CAMERA_VSP;
1658 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
1659 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN | PXA_CAMERA_PCP;
1660 if (ep.bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_FALLING)
1661 pcdev->platform_flags |= PXA_CAMERA_PCLK_EN;
1662
1663 out:
1664 of_node_put(np);
1665
1666 return err;
1667 }
1668
1669 static int pxa_camera_probe(struct platform_device *pdev)
1670 {
1671 struct pxa_camera_dev *pcdev;
1672 struct resource *res;
1673 void __iomem *base;
1674 struct dma_slave_config config = {
1675 .src_addr_width = 0,
1676 .src_maxburst = 8,
1677 .direction = DMA_DEV_TO_MEM,
1678 };
1679 dma_cap_mask_t mask;
1680 struct pxad_param params;
1681 int irq;
1682 int err = 0, i;
1683
1684 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1685 irq = platform_get_irq(pdev, 0);
1686 if (!res || irq < 0)
1687 return -ENODEV;
1688
1689 pcdev = devm_kzalloc(&pdev->dev, sizeof(*pcdev), GFP_KERNEL);
1690 if (!pcdev) {
1691 dev_err(&pdev->dev, "Could not allocate pcdev\n");
1692 return -ENOMEM;
1693 }
1694
1695 pcdev->clk = devm_clk_get(&pdev->dev, NULL);
1696 if (IS_ERR(pcdev->clk))
1697 return PTR_ERR(pcdev->clk);
1698
1699 pcdev->res = res;
1700
1701 pcdev->pdata = pdev->dev.platform_data;
1702 if (&pdev->dev.of_node && !pcdev->pdata) {
1703 err = pxa_camera_pdata_from_dt(&pdev->dev, pcdev);
1704 } else {
1705 pcdev->platform_flags = pcdev->pdata->flags;
1706 pcdev->mclk = pcdev->pdata->mclk_10khz * 10000;
1707 }
1708 if (err < 0)
1709 return err;
1710
1711 if (!(pcdev->platform_flags & (PXA_CAMERA_DATAWIDTH_8 |
1712 PXA_CAMERA_DATAWIDTH_9 | PXA_CAMERA_DATAWIDTH_10))) {
1713 /*
1714 * Platform hasn't set available data widths. This is bad.
1715 * Warn and use a default.
1716 */
1717 dev_warn(&pdev->dev, "WARNING! Platform hasn't set available "
1718 "data widths, using default 10 bit\n");
1719 pcdev->platform_flags |= PXA_CAMERA_DATAWIDTH_10;
1720 }
1721 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_8)
1722 pcdev->width_flags = 1 << 7;
1723 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_9)
1724 pcdev->width_flags |= 1 << 8;
1725 if (pcdev->platform_flags & PXA_CAMERA_DATAWIDTH_10)
1726 pcdev->width_flags |= 1 << 9;
1727 if (!pcdev->mclk) {
1728 dev_warn(&pdev->dev,
1729 "mclk == 0! Please, fix your platform data. "
1730 "Using default 20MHz\n");
1731 pcdev->mclk = 20000000;
1732 }
1733
1734 pcdev->mclk_divisor = mclk_get_divisor(pdev, pcdev);
1735
1736 INIT_LIST_HEAD(&pcdev->capture);
1737 spin_lock_init(&pcdev->lock);
1738
1739 /*
1740 * Request the regions.
1741 */
1742 base = devm_ioremap_resource(&pdev->dev, res);
1743 if (IS_ERR(base))
1744 return PTR_ERR(base);
1745
1746 pcdev->irq = irq;
1747 pcdev->base = base;
1748
1749 /* request dma */
1750 dma_cap_zero(mask);
1751 dma_cap_set(DMA_SLAVE, mask);
1752 dma_cap_set(DMA_PRIVATE, mask);
1753
1754 params.prio = 0;
1755 params.drcmr = 68;
1756 pcdev->dma_chans[0] =
1757 dma_request_slave_channel_compat(mask, pxad_filter_fn,
1758 &params, &pdev->dev, "CI_Y");
1759 if (!pcdev->dma_chans[0]) {
1760 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1761 return -ENODEV;
1762 }
1763
1764 params.drcmr = 69;
1765 pcdev->dma_chans[1] =
1766 dma_request_slave_channel_compat(mask, pxad_filter_fn,
1767 &params, &pdev->dev, "CI_U");
1768 if (!pcdev->dma_chans[1]) {
1769 dev_err(&pdev->dev, "Can't request DMA for Y\n");
1770 goto exit_free_dma_y;
1771 }
1772
1773 params.drcmr = 70;
1774 pcdev->dma_chans[2] =
1775 dma_request_slave_channel_compat(mask, pxad_filter_fn,
1776 &params, &pdev->dev, "CI_V");
1777 if (!pcdev->dma_chans[2]) {
1778 dev_err(&pdev->dev, "Can't request DMA for V\n");
1779 goto exit_free_dma_u;
1780 }
1781
1782 for (i = 0; i < 3; i++) {
1783 config.src_addr = pcdev->res->start + CIBR0 + i * 8;
1784 err = dmaengine_slave_config(pcdev->dma_chans[i], &config);
1785 if (err < 0) {
1786 dev_err(&pdev->dev, "dma slave config failed: %d\n",
1787 err);
1788 goto exit_free_dma;
1789 }
1790 }
1791
1792 /* request irq */
1793 err = devm_request_irq(&pdev->dev, pcdev->irq, pxa_camera_irq, 0,
1794 PXA_CAM_DRV_NAME, pcdev);
1795 if (err) {
1796 dev_err(&pdev->dev, "Camera interrupt register failed\n");
1797 goto exit_free_dma;
1798 }
1799
1800 pcdev->soc_host.drv_name = PXA_CAM_DRV_NAME;
1801 pcdev->soc_host.ops = &pxa_soc_camera_host_ops;
1802 pcdev->soc_host.priv = pcdev;
1803 pcdev->soc_host.v4l2_dev.dev = &pdev->dev;
1804 pcdev->soc_host.nr = pdev->id;
1805 tasklet_init(&pcdev->task_eof, pxa_camera_eof, (unsigned long)pcdev);
1806
1807 err = soc_camera_host_register(&pcdev->soc_host);
1808 if (err)
1809 goto exit_free_dma;
1810
1811 return 0;
1812
1813 exit_free_dma:
1814 dma_release_channel(pcdev->dma_chans[2]);
1815 exit_free_dma_u:
1816 dma_release_channel(pcdev->dma_chans[1]);
1817 exit_free_dma_y:
1818 dma_release_channel(pcdev->dma_chans[0]);
1819 return err;
1820 }
1821
1822 static int pxa_camera_remove(struct platform_device *pdev)
1823 {
1824 struct soc_camera_host *soc_host = to_soc_camera_host(&pdev->dev);
1825 struct pxa_camera_dev *pcdev = container_of(soc_host,
1826 struct pxa_camera_dev, soc_host);
1827
1828 dma_release_channel(pcdev->dma_chans[0]);
1829 dma_release_channel(pcdev->dma_chans[1]);
1830 dma_release_channel(pcdev->dma_chans[2]);
1831
1832 soc_camera_host_unregister(soc_host);
1833
1834 dev_info(&pdev->dev, "PXA Camera driver unloaded\n");
1835
1836 return 0;
1837 }
1838
1839 static const struct dev_pm_ops pxa_camera_pm = {
1840 .suspend = pxa_camera_suspend,
1841 .resume = pxa_camera_resume,
1842 };
1843
1844 static const struct of_device_id pxa_camera_of_match[] = {
1845 { .compatible = "marvell,pxa270-qci", },
1846 {},
1847 };
1848 MODULE_DEVICE_TABLE(of, pxa_camera_of_match);
1849
1850 static struct platform_driver pxa_camera_driver = {
1851 .driver = {
1852 .name = PXA_CAM_DRV_NAME,
1853 .pm = &pxa_camera_pm,
1854 .of_match_table = of_match_ptr(pxa_camera_of_match),
1855 },
1856 .probe = pxa_camera_probe,
1857 .remove = pxa_camera_remove,
1858 };
1859
1860 module_platform_driver(pxa_camera_driver);
1861
1862 MODULE_DESCRIPTION("PXA27x SoC Camera Host driver");
1863 MODULE_AUTHOR("Guennadi Liakhovetski <kernel@pengutronix.de>");
1864 MODULE_LICENSE("GPL");
1865 MODULE_VERSION(PXA_CAM_VERSION);
1866 MODULE_ALIAS("platform:" PXA_CAM_DRV_NAME);
Linux with added FPC-III support