drivers/media/platform/vsp1/vsp1_pipe.c

   1 /*
   2  * vsp1_pipe.c  --  R-Car VSP1 Pipeline
   3  *
   4  * Copyright (C) 2013-2015 Renesas Electronics Corporation
   5  *
   6  * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  */
  13
  14 #include <linux/delay.h>
  15 #include <linux/list.h>
  16 #include <linux/sched.h>
  17 #include <linux/wait.h>
  18
  19 #include <media/media-entity.h>
  20 #include <media/v4l2-subdev.h>
  21
  22 #include "vsp1.h"
  23 #include "vsp1_bru.h"
  24 #include "vsp1_dl.h"
  25 #include "vsp1_entity.h"
  26 #include "vsp1_pipe.h"
  27 #include "vsp1_rwpf.h"
  28 #include "vsp1_uds.h"
  29
  30 /* -----------------------------------------------------------------------------
  31  * Helper Functions
  32  */
  33
  34 static const struct vsp1_format_info vsp1_video_formats[] = {
  35         { V4L2_PIX_FMT_RGB332, MEDIA_BUS_FMT_ARGB8888_1X32,
  36           VI6_FMT_RGB_332, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  37           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  38           1, { 8, 0, 0 }, false, false, 1, 1, false },
  39         { V4L2_PIX_FMT_ARGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  40           VI6_FMT_ARGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  41           VI6_RPF_DSWAP_P_WDS,
  42           1, { 16, 0, 0 }, false, false, 1, 1, true },
  43         { V4L2_PIX_FMT_XRGB444, MEDIA_BUS_FMT_ARGB8888_1X32,
  44           VI6_FMT_XRGB_4444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  45           VI6_RPF_DSWAP_P_WDS,
  46           1, { 16, 0, 0 }, false, false, 1, 1, true },
  47         { V4L2_PIX_FMT_ARGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  48           VI6_FMT_ARGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  49           VI6_RPF_DSWAP_P_WDS,
  50           1, { 16, 0, 0 }, false, false, 1, 1, true },
  51         { V4L2_PIX_FMT_XRGB555, MEDIA_BUS_FMT_ARGB8888_1X32,
  52           VI6_FMT_XRGB_1555, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  53           VI6_RPF_DSWAP_P_WDS,
  54           1, { 16, 0, 0 }, false, false, 1, 1, false },
  55         { V4L2_PIX_FMT_RGB565, MEDIA_BUS_FMT_ARGB8888_1X32,
  56           VI6_FMT_RGB_565, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  57           VI6_RPF_DSWAP_P_WDS,
  58           1, { 16, 0, 0 }, false, false, 1, 1, false },
  59         { V4L2_PIX_FMT_BGR24, MEDIA_BUS_FMT_ARGB8888_1X32,
  60           VI6_FMT_BGR_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  61           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  62           1, { 24, 0, 0 }, false, false, 1, 1, false },
  63         { V4L2_PIX_FMT_RGB24, MEDIA_BUS_FMT_ARGB8888_1X32,
  64           VI6_FMT_RGB_888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  65           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  66           1, { 24, 0, 0 }, false, false, 1, 1, false },
  67         { V4L2_PIX_FMT_ABGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  68           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  69           1, { 32, 0, 0 }, false, false, 1, 1, true },
  70         { V4L2_PIX_FMT_XBGR32, MEDIA_BUS_FMT_ARGB8888_1X32,
  71           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS,
  72           1, { 32, 0, 0 }, false, false, 1, 1, false },
  73         { V4L2_PIX_FMT_ARGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  74           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  75           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  76           1, { 32, 0, 0 }, false, false, 1, 1, true },
  77         { V4L2_PIX_FMT_XRGB32, MEDIA_BUS_FMT_ARGB8888_1X32,
  78           VI6_FMT_ARGB_8888, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  79           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  80           1, { 32, 0, 0 }, false, false, 1, 1, false },
  81         { V4L2_PIX_FMT_UYVY, MEDIA_BUS_FMT_AYUV8_1X32,
  82           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  83           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  84           1, { 16, 0, 0 }, false, false, 2, 1, false },
  85         { V4L2_PIX_FMT_VYUY, MEDIA_BUS_FMT_AYUV8_1X32,
  86           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  87           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  88           1, { 16, 0, 0 }, false, true, 2, 1, false },
  89         { V4L2_PIX_FMT_YUYV, MEDIA_BUS_FMT_AYUV8_1X32,
  90           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  91           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  92           1, { 16, 0, 0 }, true, false, 2, 1, false },
  93         { V4L2_PIX_FMT_YVYU, MEDIA_BUS_FMT_AYUV8_1X32,
  94           VI6_FMT_YUYV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  95           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
  96           1, { 16, 0, 0 }, true, true, 2, 1, false },
  97         { V4L2_PIX_FMT_NV12M, MEDIA_BUS_FMT_AYUV8_1X32,
  98           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
  99           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 100           2, { 8, 16, 0 }, false, false, 2, 2, false },
 101         { V4L2_PIX_FMT_NV21M, MEDIA_BUS_FMT_AYUV8_1X32,
 102           VI6_FMT_Y_UV_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 103           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 104           2, { 8, 16, 0 }, false, true, 2, 2, false },
 105         { V4L2_PIX_FMT_NV16M, MEDIA_BUS_FMT_AYUV8_1X32,
 106           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 107           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 108           2, { 8, 16, 0 }, false, false, 2, 1, false },
 109         { V4L2_PIX_FMT_NV61M, MEDIA_BUS_FMT_AYUV8_1X32,
 110           VI6_FMT_Y_UV_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 111           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 112           2, { 8, 16, 0 }, false, true, 2, 1, false },
 113         { V4L2_PIX_FMT_YUV420M, MEDIA_BUS_FMT_AYUV8_1X32,
 114           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 115           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 116           3, { 8, 8, 8 }, false, false, 2, 2, false },
 117         { V4L2_PIX_FMT_YVU420M, MEDIA_BUS_FMT_AYUV8_1X32,
 118           VI6_FMT_Y_U_V_420, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 119           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 120           3, { 8, 8, 8 }, false, true, 2, 2, false },
 121         { V4L2_PIX_FMT_YUV422M, MEDIA_BUS_FMT_AYUV8_1X32,
 122           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 123           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 124           3, { 8, 8, 8 }, false, false, 2, 1, false },
 125         { V4L2_PIX_FMT_YVU422M, MEDIA_BUS_FMT_AYUV8_1X32,
 126           VI6_FMT_Y_U_V_422, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 127           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 128           3, { 8, 8, 8 }, false, true, 2, 1, false },
 129         { V4L2_PIX_FMT_YUV444M, MEDIA_BUS_FMT_AYUV8_1X32,
 130           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 131           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 132           3, { 8, 8, 8 }, false, false, 1, 1, false },
 133         { V4L2_PIX_FMT_YVU444M, MEDIA_BUS_FMT_AYUV8_1X32,
 134           VI6_FMT_Y_U_V_444, VI6_RPF_DSWAP_P_LLS | VI6_RPF_DSWAP_P_LWS |
 135           VI6_RPF_DSWAP_P_WDS | VI6_RPF_DSWAP_P_BTS,
 136           3, { 8, 8, 8 }, false, true, 1, 1, false },
 137 };
 138
 139 /*
 140  * vsp1_get_format_info - Retrieve format information for a 4CC
 141  * @fourcc: the format 4CC
 142  *
 143  * Return a pointer to the format information structure corresponding to the
 144  * given V4L2 format 4CC, or NULL if no corresponding format can be found.
 145  */
 146 const struct vsp1_format_info *vsp1_get_format_info(u32 fourcc)
 147 {
 148         unsigned int i;
 149
 150         for (i = 0; i < ARRAY_SIZE(vsp1_video_formats); ++i) {
 151                 const struct vsp1_format_info *info = &vsp1_video_formats[i];
 152
 153                 if (info->fourcc == fourcc)
 154                         return info;
 155         }
 156
 157         return NULL;
 158 }
 159
 160 /* -----------------------------------------------------------------------------
 161  * Pipeline Management
 162  */
 163
 164 void vsp1_pipeline_reset(struct vsp1_pipeline *pipe)
 165 {
 166         unsigned int i;
 167
 168         if (pipe->bru) {
 169                 struct vsp1_bru *bru = to_bru(&pipe->bru->subdev);
 170
 171                 for (i = 0; i < ARRAY_SIZE(bru->inputs); ++i)
 172                         bru->inputs[i].rpf = NULL;
 173         }
 174
 175         for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i)
 176                 pipe->inputs[i] = NULL;
 177
 178         INIT_LIST_HEAD(&pipe->entities);
 179         pipe->state = VSP1_PIPELINE_STOPPED;
 180         pipe->buffers_ready = 0;
 181         pipe->num_inputs = 0;
 182         pipe->output = NULL;
 183         pipe->bru = NULL;
 184         pipe->lif = NULL;
 185         pipe->uds = NULL;
 186 }
 187
 188 void vsp1_pipeline_init(struct vsp1_pipeline *pipe)
 189 {
 190         mutex_init(&pipe->lock);
 191         spin_lock_init(&pipe->irqlock);
 192         init_waitqueue_head(&pipe->wq);
 193
 194         INIT_LIST_HEAD(&pipe->entities);
 195         pipe->state = VSP1_PIPELINE_STOPPED;
 196 }
 197
 198 void vsp1_pipeline_run(struct vsp1_pipeline *pipe)
 199 {
 200         struct vsp1_device *vsp1 = pipe->output->entity.vsp1;
 201
 202         if (pipe->state == VSP1_PIPELINE_STOPPED) {
 203                 vsp1_write(vsp1, VI6_CMD(pipe->output->entity.index),
 204                            VI6_CMD_STRCMD);
 205                 pipe->state = VSP1_PIPELINE_RUNNING;
 206         }
 207
 208         pipe->buffers_ready = 0;
 209 }
 210
 211 bool vsp1_pipeline_stopped(struct vsp1_pipeline *pipe)
 212 {
 213         unsigned long flags;
 214         bool stopped;
 215
 216         spin_lock_irqsave(&pipe->irqlock, flags);
 217         stopped = pipe->state == VSP1_PIPELINE_STOPPED;
 218         spin_unlock_irqrestore(&pipe->irqlock, flags);
 219
 220         return stopped;
 221 }
 222
 223 int vsp1_pipeline_stop(struct vsp1_pipeline *pipe)
 224 {
 225         struct vsp1_entity *entity;
 226         unsigned long flags;
 227         int ret;
 228
 229         if (pipe->dl) {
 230                 /* When using display lists in continuous frame mode the only
 231                  * way to stop the pipeline is to reset the hardware.
 232                  */
 233                 ret = vsp1_reset_wpf(pipe->output->entity.vsp1,
 234                                      pipe->output->entity.index);
 235                 if (ret == 0) {
 236                         spin_lock_irqsave(&pipe->irqlock, flags);
 237                         pipe->state = VSP1_PIPELINE_STOPPED;
 238                         spin_unlock_irqrestore(&pipe->irqlock, flags);
 239                 }
 240         } else {
 241                 /* Otherwise just request a stop and wait. */
 242                 spin_lock_irqsave(&pipe->irqlock, flags);
 243                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 244                         pipe->state = VSP1_PIPELINE_STOPPING;
 245                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 246
 247                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 248                                          msecs_to_jiffies(500));
 249                 ret = ret == 0 ? -ETIMEDOUT : 0;
 250         }
 251
 252         list_for_each_entry(entity, &pipe->entities, list_pipe) {
 253                 if (entity->route && entity->route->reg)
 254                         vsp1_write(entity->vsp1, entity->route->reg,
 255                                    VI6_DPR_NODE_UNUSED);
 256
 257                 v4l2_subdev_call(&entity->subdev, video, s_stream, 0);
 258         }
 259
 260         return ret;
 261 }
 262
 263 bool vsp1_pipeline_ready(struct vsp1_pipeline *pipe)
 264 {
 265         unsigned int mask;
 266
 267         mask = ((1 << pipe->num_inputs) - 1) << 1;
 268         if (!pipe->lif)
 269                 mask |= 1 << 0;
 270
 271         return pipe->buffers_ready == mask;
 272 }
 273
 274 void vsp1_pipeline_display_start(struct vsp1_pipeline *pipe)
 275 {
 276         if (pipe->dl)
 277                 vsp1_dl_irq_display_start(pipe->dl);
 278 }
 279
 280 void vsp1_pipeline_frame_end(struct vsp1_pipeline *pipe)
 281 {
 282         enum vsp1_pipeline_state state;
 283         unsigned long flags;
 284
 285         if (pipe == NULL)
 286                 return;
 287
 288         if (pipe->dl)
 289                 vsp1_dl_irq_frame_end(pipe->dl);
 290
 291         /* Signal frame end to the pipeline handler. */
 292         pipe->frame_end(pipe);
 293
 294         spin_lock_irqsave(&pipe->irqlock, flags);
 295
 296         state = pipe->state;
 297
 298         /* When using display lists in continuous frame mode the pipeline is
 299          * automatically restarted by the hardware.
 300          */
 301         if (!pipe->dl)
 302                 pipe->state = VSP1_PIPELINE_STOPPED;
 303
 304         /* If a stop has been requested, mark the pipeline as stopped and
 305          * return.
 306          */
 307         if (state == VSP1_PIPELINE_STOPPING) {
 308                 wake_up(&pipe->wq);
 309                 goto done;
 310         }
 311
 312         /* Restart the pipeline if ready. */
 313         if (vsp1_pipeline_ready(pipe))
 314                 vsp1_pipeline_run(pipe);
 315
 316 done:
 317         spin_unlock_irqrestore(&pipe->irqlock, flags);
 318 }
 319
 320 /*
 321  * Propagate the alpha value through the pipeline.
 322  *
 323  * As the UDS has restricted scaling capabilities when the alpha component needs
 324  * to be scaled, we disable alpha scaling when the UDS input has a fixed alpha
 325  * value. The UDS then outputs a fixed alpha value which needs to be programmed
 326  * from the input RPF alpha.
 327  */
 328 void vsp1_pipeline_propagate_alpha(struct vsp1_pipeline *pipe,
 329                                    struct vsp1_entity *input,
 330                                    unsigned int alpha)
 331 {
 332         struct vsp1_entity *entity;
 333         struct media_pad *pad;
 334
 335         pad = media_entity_remote_pad(&input->pads[RWPF_PAD_SOURCE]);
 336
 337         while (pad) {
 338                 if (!is_media_entity_v4l2_subdev(pad->entity))
 339                         break;
 340
 341                 entity = to_vsp1_entity(media_entity_to_v4l2_subdev(pad->entity));
 342
 343                 /* The BRU background color has a fixed alpha value set to 255,
 344                  * the output alpha value is thus always equal to 255.
 345                  */
 346                 if (entity->type == VSP1_ENTITY_BRU)
 347                         alpha = 255;
 348
 349                 if (entity->type == VSP1_ENTITY_UDS) {
 350                         struct vsp1_uds *uds = to_uds(&entity->subdev);
 351
 352                         vsp1_uds_set_alpha(uds, alpha);
 353                         break;
 354                 }
 355
 356                 pad = &entity->pads[entity->source_pad];
 357                 pad = media_entity_remote_pad(pad);
 358         }
 359 }
 360
 361 void vsp1_pipelines_suspend(struct vsp1_device *vsp1)
 362 {
 363         unsigned long flags;
 364         unsigned int i;
 365         int ret;
 366
 367         /* To avoid increasing the system suspend time needlessly, loop over the
 368          * pipelines twice, first to set them all to the stopping state, and
 369          * then to wait for the stop to complete.
 370          */
 371         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 372                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 373                 struct vsp1_pipeline *pipe;
 374
 375                 if (wpf == NULL)
 376                         continue;
 377
 378                 pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity);
 379                 if (pipe == NULL)
 380                         continue;
 381
 382                 spin_lock_irqsave(&pipe->irqlock, flags);
 383                 if (pipe->state == VSP1_PIPELINE_RUNNING)
 384                         pipe->state = VSP1_PIPELINE_STOPPING;
 385                 spin_unlock_irqrestore(&pipe->irqlock, flags);
 386         }
 387
 388         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 389                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 390                 struct vsp1_pipeline *pipe;
 391
 392                 if (wpf == NULL)
 393                         continue;
 394
 395                 pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity);
 396                 if (pipe == NULL)
 397                         continue;
 398
 399                 ret = wait_event_timeout(pipe->wq, vsp1_pipeline_stopped(pipe),
 400                                          msecs_to_jiffies(500));
 401                 if (ret == 0)
 402                         dev_warn(vsp1->dev, "pipeline %u stop timeout\n",
 403                                  wpf->entity.index);
 404         }
 405 }
 406
 407 void vsp1_pipelines_resume(struct vsp1_device *vsp1)
 408 {
 409         unsigned int i;
 410
 411         /* Resume pipeline all running pipelines. */
 412         for (i = 0; i < vsp1->info->wpf_count; ++i) {
 413                 struct vsp1_rwpf *wpf = vsp1->wpf[i];
 414                 struct vsp1_pipeline *pipe;
 415
 416                 if (wpf == NULL)
 417                         continue;
 418
 419                 pipe = to_vsp1_pipeline(&wpf->entity.subdev.entity);
 420                 if (pipe == NULL)
 421                         continue;
 422
 423                 if (vsp1_pipeline_ready(pipe))
 424                         vsp1_pipeline_run(pipe);
 425         }
 426 }