Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / media / platform / vsp1 / vsp1_rpf.c
blob5bc1d1574a432872baa8f169fbd7017a2ddc11c7
1 /*
2 * vsp1_rpf.c -- R-Car VSP1 Read Pixel Formatter
4 * Copyright (C) 2013-2014 Renesas Electronics Corporation
6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
14 #include <linux/device.h>
16 #include <media/v4l2-subdev.h>
18 #include "vsp1.h"
19 #include "vsp1_rwpf.h"
20 #include "vsp1_video.h"
22 #define RPF_MAX_WIDTH 8190
23 #define RPF_MAX_HEIGHT 8190
25 /* -----------------------------------------------------------------------------
26 * Device Access
29 static inline void vsp1_rpf_write(struct vsp1_rwpf *rpf, u32 reg, u32 data)
31 vsp1_mod_write(&rpf->entity, reg + rpf->entity.index * VI6_RPF_OFFSET,
32 data);
35 /* -----------------------------------------------------------------------------
36 * Controls
39 static int rpf_s_ctrl(struct v4l2_ctrl *ctrl)
41 struct vsp1_rwpf *rpf =
42 container_of(ctrl->handler, struct vsp1_rwpf, ctrls);
43 struct vsp1_pipeline *pipe;
45 if (!vsp1_entity_is_streaming(&rpf->entity))
46 return 0;
48 switch (ctrl->id) {
49 case V4L2_CID_ALPHA_COMPONENT:
50 vsp1_rpf_write(rpf, VI6_RPF_VRTCOL_SET,
51 ctrl->val << VI6_RPF_VRTCOL_SET_LAYA_SHIFT);
53 pipe = to_vsp1_pipeline(&rpf->entity.subdev.entity);
54 vsp1_pipeline_propagate_alpha(pipe, &rpf->entity, ctrl->val);
55 break;
58 return 0;
61 static const struct v4l2_ctrl_ops rpf_ctrl_ops = {
62 .s_ctrl = rpf_s_ctrl,
65 /* -----------------------------------------------------------------------------
66 * V4L2 Subdevice Core Operations
69 static int rpf_s_stream(struct v4l2_subdev *subdev, int enable)
71 struct vsp1_pipeline *pipe = to_vsp1_pipeline(&subdev->entity);
72 struct vsp1_rwpf *rpf = to_rwpf(subdev);
73 struct vsp1_device *vsp1 = rpf->entity.vsp1;
74 const struct vsp1_format_info *fmtinfo = rpf->fmtinfo;
75 const struct v4l2_pix_format_mplane *format = &rpf->format;
76 const struct v4l2_rect *crop = &rpf->crop;
77 u32 pstride;
78 u32 infmt;
79 int ret;
81 ret = vsp1_entity_set_streaming(&rpf->entity, enable);
82 if (ret < 0)
83 return ret;
85 if (!enable)
86 return 0;
88 /* Source size, stride and crop offsets.
90 * The crop offsets correspond to the location of the crop rectangle top
91 * left corner in the plane buffer. Only two offsets are needed, as
92 * planes 2 and 3 always have identical strides.
94 vsp1_rpf_write(rpf, VI6_RPF_SRC_BSIZE,
95 (crop->width << VI6_RPF_SRC_BSIZE_BHSIZE_SHIFT) |
96 (crop->height << VI6_RPF_SRC_BSIZE_BVSIZE_SHIFT));
97 vsp1_rpf_write(rpf, VI6_RPF_SRC_ESIZE,
98 (crop->width << VI6_RPF_SRC_ESIZE_EHSIZE_SHIFT) |
99 (crop->height << VI6_RPF_SRC_ESIZE_EVSIZE_SHIFT));
101 rpf->offsets[0] = crop->top * format->plane_fmt[0].bytesperline
102 + crop->left * fmtinfo->bpp[0] / 8;
103 pstride = format->plane_fmt[0].bytesperline
104 << VI6_RPF_SRCM_PSTRIDE_Y_SHIFT;
106 vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_Y,
107 rpf->buf_addr[0] + rpf->offsets[0]);
109 if (format->num_planes > 1) {
110 rpf->offsets[1] = crop->top * format->plane_fmt[1].bytesperline
111 + crop->left * fmtinfo->bpp[1] / 8;
112 pstride |= format->plane_fmt[1].bytesperline
113 << VI6_RPF_SRCM_PSTRIDE_C_SHIFT;
115 vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C0,
116 rpf->buf_addr[1] + rpf->offsets[1]);
118 if (format->num_planes > 2)
119 vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C1,
120 rpf->buf_addr[2] + rpf->offsets[1]);
123 vsp1_rpf_write(rpf, VI6_RPF_SRCM_PSTRIDE, pstride);
125 /* Format */
126 infmt = VI6_RPF_INFMT_CIPM
127 | (fmtinfo->hwfmt << VI6_RPF_INFMT_RDFMT_SHIFT);
129 if (fmtinfo->swap_yc)
130 infmt |= VI6_RPF_INFMT_SPYCS;
131 if (fmtinfo->swap_uv)
132 infmt |= VI6_RPF_INFMT_SPUVS;
134 if (rpf->entity.formats[RWPF_PAD_SINK].code !=
135 rpf->entity.formats[RWPF_PAD_SOURCE].code)
136 infmt |= VI6_RPF_INFMT_CSC;
138 vsp1_rpf_write(rpf, VI6_RPF_INFMT, infmt);
139 vsp1_rpf_write(rpf, VI6_RPF_DSWAP, fmtinfo->swap);
141 /* Output location */
142 vsp1_rpf_write(rpf, VI6_RPF_LOC,
143 (rpf->location.left << VI6_RPF_LOC_HCOORD_SHIFT) |
144 (rpf->location.top << VI6_RPF_LOC_VCOORD_SHIFT));
146 /* Use the alpha channel (extended to 8 bits) when available or an
147 * alpha value set through the V4L2_CID_ALPHA_COMPONENT control
148 * otherwise. Disable color keying.
150 vsp1_rpf_write(rpf, VI6_RPF_ALPH_SEL, VI6_RPF_ALPH_SEL_AEXT_EXT |
151 (fmtinfo->alpha ? VI6_RPF_ALPH_SEL_ASEL_PACKED
152 : VI6_RPF_ALPH_SEL_ASEL_FIXED));
154 if (vsp1->info->uapi)
155 mutex_lock(rpf->ctrls.lock);
156 vsp1_rpf_write(rpf, VI6_RPF_VRTCOL_SET,
157 rpf->alpha->cur.val << VI6_RPF_VRTCOL_SET_LAYA_SHIFT);
158 vsp1_pipeline_propagate_alpha(pipe, &rpf->entity, rpf->alpha->cur.val);
159 if (vsp1->info->uapi)
160 mutex_unlock(rpf->ctrls.lock);
162 vsp1_rpf_write(rpf, VI6_RPF_MSK_CTRL, 0);
163 vsp1_rpf_write(rpf, VI6_RPF_CKEY_CTRL, 0);
165 return 0;
168 /* -----------------------------------------------------------------------------
169 * V4L2 Subdevice Operations
172 static struct v4l2_subdev_video_ops rpf_video_ops = {
173 .s_stream = rpf_s_stream,
176 static struct v4l2_subdev_pad_ops rpf_pad_ops = {
177 .enum_mbus_code = vsp1_rwpf_enum_mbus_code,
178 .enum_frame_size = vsp1_rwpf_enum_frame_size,
179 .get_fmt = vsp1_rwpf_get_format,
180 .set_fmt = vsp1_rwpf_set_format,
181 .get_selection = vsp1_rwpf_get_selection,
182 .set_selection = vsp1_rwpf_set_selection,
185 static struct v4l2_subdev_ops rpf_ops = {
186 .video = &rpf_video_ops,
187 .pad = &rpf_pad_ops,
190 /* -----------------------------------------------------------------------------
191 * Video Device Operations
194 static void rpf_set_memory(struct vsp1_rwpf *rpf, struct vsp1_rwpf_memory *mem)
196 unsigned int i;
198 for (i = 0; i < 3; ++i)
199 rpf->buf_addr[i] = mem->addr[i];
201 if (!vsp1_entity_is_streaming(&rpf->entity))
202 return;
204 vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_Y,
205 mem->addr[0] + rpf->offsets[0]);
206 if (mem->num_planes > 1)
207 vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C0,
208 mem->addr[1] + rpf->offsets[1]);
209 if (mem->num_planes > 2)
210 vsp1_rpf_write(rpf, VI6_RPF_SRCM_ADDR_C1,
211 mem->addr[2] + rpf->offsets[1]);
214 static const struct vsp1_rwpf_operations rpf_vdev_ops = {
215 .set_memory = rpf_set_memory,
218 /* -----------------------------------------------------------------------------
219 * Initialization and Cleanup
222 struct vsp1_rwpf *vsp1_rpf_create(struct vsp1_device *vsp1, unsigned int index)
224 struct v4l2_subdev *subdev;
225 struct vsp1_rwpf *rpf;
226 int ret;
228 rpf = devm_kzalloc(vsp1->dev, sizeof(*rpf), GFP_KERNEL);
229 if (rpf == NULL)
230 return ERR_PTR(-ENOMEM);
232 rpf->ops = &rpf_vdev_ops;
234 rpf->max_width = RPF_MAX_WIDTH;
235 rpf->max_height = RPF_MAX_HEIGHT;
237 rpf->entity.type = VSP1_ENTITY_RPF;
238 rpf->entity.index = index;
240 ret = vsp1_entity_init(vsp1, &rpf->entity, 2);
241 if (ret < 0)
242 return ERR_PTR(ret);
244 /* Initialize the V4L2 subdev. */
245 subdev = &rpf->entity.subdev;
246 v4l2_subdev_init(subdev, &rpf_ops);
248 subdev->entity.ops = &vsp1->media_ops;
249 subdev->internal_ops = &vsp1_subdev_internal_ops;
250 snprintf(subdev->name, sizeof(subdev->name), "%s rpf.%u",
251 dev_name(vsp1->dev), index);
252 v4l2_set_subdevdata(subdev, rpf);
253 subdev->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
255 vsp1_entity_init_formats(subdev, NULL);
257 /* Initialize the control handler. */
258 v4l2_ctrl_handler_init(&rpf->ctrls, 1);
259 rpf->alpha = v4l2_ctrl_new_std(&rpf->ctrls, &rpf_ctrl_ops,
260 V4L2_CID_ALPHA_COMPONENT,
261 0, 255, 1, 255);
263 rpf->entity.subdev.ctrl_handler = &rpf->ctrls;
265 if (rpf->ctrls.error) {
266 dev_err(vsp1->dev, "rpf%u: failed to initialize controls\n",
267 index);
268 ret = rpf->ctrls.error;
269 goto error;
272 return rpf;
274 error:
275 vsp1_entity_destroy(&rpf->entity);
276 return ERR_PTR(ret);