2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
4 * The data sheet for this device can be found at:
5 * http://wiki.laptop.org/go/Datasheets
7 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
13 #include <linux/device.h>
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/nand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/rslib.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
27 #define CAFE_NAND_CTRL1 0x00
28 #define CAFE_NAND_CTRL2 0x04
29 #define CAFE_NAND_CTRL3 0x08
30 #define CAFE_NAND_STATUS 0x0c
31 #define CAFE_NAND_IRQ 0x10
32 #define CAFE_NAND_IRQ_MASK 0x14
33 #define CAFE_NAND_DATA_LEN 0x18
34 #define CAFE_NAND_ADDR1 0x1c
35 #define CAFE_NAND_ADDR2 0x20
36 #define CAFE_NAND_TIMING1 0x24
37 #define CAFE_NAND_TIMING2 0x28
38 #define CAFE_NAND_TIMING3 0x2c
39 #define CAFE_NAND_NONMEM 0x30
40 #define CAFE_NAND_ECC_RESULT 0x3C
41 #define CAFE_NAND_DMA_CTRL 0x40
42 #define CAFE_NAND_DMA_ADDR0 0x44
43 #define CAFE_NAND_DMA_ADDR1 0x48
44 #define CAFE_NAND_ECC_SYN01 0x50
45 #define CAFE_NAND_ECC_SYN23 0x54
46 #define CAFE_NAND_ECC_SYN45 0x58
47 #define CAFE_NAND_ECC_SYN67 0x5c
48 #define CAFE_NAND_READ_DATA 0x1000
49 #define CAFE_NAND_WRITE_DATA 0x2000
51 #define CAFE_GLOBAL_CTRL 0x3004
52 #define CAFE_GLOBAL_IRQ 0x3008
53 #define CAFE_GLOBAL_IRQ_MASK 0x300c
54 #define CAFE_NAND_RESET 0x3034
56 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
57 #define CTRL1_CHIPSELECT (1<<19)
60 struct nand_chip nand
;
63 struct rs_control
*rs
;
71 unsigned char *dmabuf
;
74 static int usedma
= 1;
75 module_param(usedma
, int, 0644);
77 static int skipbbt
= 0;
78 module_param(skipbbt
, int, 0644);
81 module_param(debug
, int, 0644);
83 static int regdebug
= 0;
84 module_param(regdebug
, int, 0644);
86 static int checkecc
= 1;
87 module_param(checkecc
, int, 0644);
89 static unsigned int numtimings
;
91 module_param_array(timing
, int, &numtimings
, 0644);
93 static const char *part_probes
[] = { "cmdlinepart", "RedBoot", NULL
};
95 /* Hrm. Why isn't this already conditional on something in the struct device? */
96 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
98 /* Make it easier to switch to PIO if we need to */
99 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
100 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
102 static int cafe_device_ready(struct mtd_info
*mtd
)
104 struct nand_chip
*chip
= mtd_to_nand(mtd
);
105 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
106 int result
= !!(cafe_readl(cafe
, NAND_STATUS
) & 0x40000000);
107 uint32_t irqs
= cafe_readl(cafe
, NAND_IRQ
);
109 cafe_writel(cafe
, irqs
, NAND_IRQ
);
111 cafe_dev_dbg(&cafe
->pdev
->dev
, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
112 result
?"":" not", irqs
, cafe_readl(cafe
, NAND_IRQ
),
113 cafe_readl(cafe
, GLOBAL_IRQ
), cafe_readl(cafe
, GLOBAL_IRQ_MASK
));
119 static void cafe_write_buf(struct mtd_info
*mtd
, const uint8_t *buf
, int len
)
121 struct nand_chip
*chip
= mtd_to_nand(mtd
);
122 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
125 memcpy(cafe
->dmabuf
+ cafe
->datalen
, buf
, len
);
127 memcpy_toio(cafe
->mmio
+ CAFE_NAND_WRITE_DATA
+ cafe
->datalen
, buf
, len
);
129 cafe
->datalen
+= len
;
131 cafe_dev_dbg(&cafe
->pdev
->dev
, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
135 static void cafe_read_buf(struct mtd_info
*mtd
, uint8_t *buf
, int len
)
137 struct nand_chip
*chip
= mtd_to_nand(mtd
);
138 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
141 memcpy(buf
, cafe
->dmabuf
+ cafe
->datalen
, len
);
143 memcpy_fromio(buf
, cafe
->mmio
+ CAFE_NAND_READ_DATA
+ cafe
->datalen
, len
);
145 cafe_dev_dbg(&cafe
->pdev
->dev
, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
147 cafe
->datalen
+= len
;
150 static uint8_t cafe_read_byte(struct mtd_info
*mtd
)
152 struct nand_chip
*chip
= mtd_to_nand(mtd
);
153 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
156 cafe_read_buf(mtd
, &d
, 1);
157 cafe_dev_dbg(&cafe
->pdev
->dev
, "Read %02x\n", d
);
162 static void cafe_nand_cmdfunc(struct mtd_info
*mtd
, unsigned command
,
163 int column
, int page_addr
)
165 struct nand_chip
*chip
= mtd_to_nand(mtd
);
166 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
169 uint32_t doneint
= 0x80000000;
171 cafe_dev_dbg(&cafe
->pdev
->dev
, "cmdfunc %02x, 0x%x, 0x%x\n",
172 command
, column
, page_addr
);
174 if (command
== NAND_CMD_ERASE2
|| command
== NAND_CMD_PAGEPROG
) {
175 /* Second half of a command we already calculated */
176 cafe_writel(cafe
, cafe
->ctl2
| 0x100 | command
, NAND_CTRL2
);
178 cafe
->ctl2
&= ~(1<<30);
179 cafe_dev_dbg(&cafe
->pdev
->dev
, "Continue command, ctl1 %08x, #data %d\n",
180 cafe
->ctl1
, cafe
->nr_data
);
183 /* Reset ECC engine */
184 cafe_writel(cafe
, 0, NAND_CTRL2
);
186 /* Emulate NAND_CMD_READOOB on large-page chips */
187 if (mtd
->writesize
> 512 &&
188 command
== NAND_CMD_READOOB
) {
189 column
+= mtd
->writesize
;
190 command
= NAND_CMD_READ0
;
193 /* FIXME: Do we need to send read command before sending data
194 for small-page chips, to position the buffer correctly? */
197 cafe_writel(cafe
, column
, NAND_ADDR1
);
201 } else if (page_addr
!= -1) {
202 cafe_writel(cafe
, page_addr
& 0xffff, NAND_ADDR1
);
205 cafe_writel(cafe
, page_addr
, NAND_ADDR2
);
207 if (mtd
->size
> mtd
->writesize
<< 16)
211 cafe
->data_pos
= cafe
->datalen
= 0;
213 /* Set command valid bit, mask in the chip select bit */
214 ctl1
= 0x80000000 | command
| (cafe
->ctl1
& CTRL1_CHIPSELECT
);
216 /* Set RD or WR bits as appropriate */
217 if (command
== NAND_CMD_READID
|| command
== NAND_CMD_STATUS
) {
218 ctl1
|= (1<<26); /* rd */
219 /* Always 5 bytes, for now */
221 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
223 } else if (command
== NAND_CMD_READ0
|| command
== NAND_CMD_READ1
||
224 command
== NAND_CMD_READOOB
|| command
== NAND_CMD_RNDOUT
) {
225 ctl1
|= 1<<26; /* rd */
226 /* For now, assume just read to end of page */
227 cafe
->datalen
= mtd
->writesize
+ mtd
->oobsize
- column
;
228 } else if (command
== NAND_CMD_SEQIN
)
229 ctl1
|= 1<<25; /* wr */
231 /* Set number of address bytes */
233 ctl1
|= ((adrbytes
-1)|8) << 27;
235 if (command
== NAND_CMD_SEQIN
|| command
== NAND_CMD_ERASE1
) {
236 /* Ignore the first command of a pair; the hardware
237 deals with them both at once, later */
239 cafe_dev_dbg(&cafe
->pdev
->dev
, "Setup for delayed command, ctl1 %08x, dlen %x\n",
240 cafe
->ctl1
, cafe
->datalen
);
243 /* RNDOUT and READ0 commands need a following byte */
244 if (command
== NAND_CMD_RNDOUT
)
245 cafe_writel(cafe
, cafe
->ctl2
| 0x100 | NAND_CMD_RNDOUTSTART
, NAND_CTRL2
);
246 else if (command
== NAND_CMD_READ0
&& mtd
->writesize
> 512)
247 cafe_writel(cafe
, cafe
->ctl2
| 0x100 | NAND_CMD_READSTART
, NAND_CTRL2
);
250 cafe_dev_dbg(&cafe
->pdev
->dev
, "dlen %x, ctl1 %x, ctl2 %x\n",
251 cafe
->datalen
, ctl1
, cafe_readl(cafe
, NAND_CTRL2
));
253 /* NB: The datasheet lies -- we really should be subtracting 1 here */
254 cafe_writel(cafe
, cafe
->datalen
, NAND_DATA_LEN
);
255 cafe_writel(cafe
, 0x90000000, NAND_IRQ
);
256 if (usedma
&& (ctl1
& (3<<25))) {
257 uint32_t dmactl
= 0xc0000000 + cafe
->datalen
;
258 /* If WR or RD bits set, set up DMA */
259 if (ctl1
& (1<<26)) {
262 /* ... so it's done when the DMA is done, not just
264 doneint
= 0x10000000;
266 cafe_writel(cafe
, dmactl
, NAND_DMA_CTRL
);
270 if (unlikely(regdebug
)) {
272 printk("About to write command %08x to register 0\n", ctl1
);
273 for (i
=4; i
< 0x5c; i
+=4)
274 printk("Register %x: %08x\n", i
, readl(cafe
->mmio
+ i
));
277 cafe_writel(cafe
, ctl1
, NAND_CTRL1
);
278 /* Apply this short delay always to ensure that we do wait tWB in
279 * any case on any machine. */
286 for (c
= 500000; c
!= 0; c
--) {
287 irqs
= cafe_readl(cafe
, NAND_IRQ
);
292 cafe_dev_dbg(&cafe
->pdev
->dev
, "Wait for ready, IRQ %x\n", irqs
);
295 cafe_writel(cafe
, doneint
, NAND_IRQ
);
296 cafe_dev_dbg(&cafe
->pdev
->dev
, "Command %x completed after %d usec, irqs %x (%x)\n",
297 command
, 500000-c
, irqs
, cafe_readl(cafe
, NAND_IRQ
));
300 WARN_ON(cafe
->ctl2
& (1<<30));
304 case NAND_CMD_CACHEDPROG
:
305 case NAND_CMD_PAGEPROG
:
306 case NAND_CMD_ERASE1
:
307 case NAND_CMD_ERASE2
:
310 case NAND_CMD_STATUS
:
311 case NAND_CMD_RNDOUT
:
312 cafe_writel(cafe
, cafe
->ctl2
, NAND_CTRL2
);
315 nand_wait_ready(mtd
);
316 cafe_writel(cafe
, cafe
->ctl2
, NAND_CTRL2
);
319 static void cafe_select_chip(struct mtd_info
*mtd
, int chipnr
)
321 struct nand_chip
*chip
= mtd_to_nand(mtd
);
322 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
324 cafe_dev_dbg(&cafe
->pdev
->dev
, "select_chip %d\n", chipnr
);
326 /* Mask the appropriate bit into the stored value of ctl1
327 which will be used by cafe_nand_cmdfunc() */
329 cafe
->ctl1
|= CTRL1_CHIPSELECT
;
331 cafe
->ctl1
&= ~CTRL1_CHIPSELECT
;
334 static irqreturn_t
cafe_nand_interrupt(int irq
, void *id
)
336 struct mtd_info
*mtd
= id
;
337 struct nand_chip
*chip
= mtd_to_nand(mtd
);
338 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
339 uint32_t irqs
= cafe_readl(cafe
, NAND_IRQ
);
340 cafe_writel(cafe
, irqs
& ~0x90000000, NAND_IRQ
);
344 cafe_dev_dbg(&cafe
->pdev
->dev
, "irq, bits %x (%x)\n", irqs
, cafe_readl(cafe
, NAND_IRQ
));
348 static void cafe_nand_bug(struct mtd_info
*mtd
)
353 static int cafe_nand_write_oob(struct mtd_info
*mtd
,
354 struct nand_chip
*chip
, int page
)
358 chip
->cmdfunc(mtd
, NAND_CMD_SEQIN
, mtd
->writesize
, page
);
359 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
360 chip
->cmdfunc(mtd
, NAND_CMD_PAGEPROG
, -1, -1);
361 status
= chip
->waitfunc(mtd
, chip
);
363 return status
& NAND_STATUS_FAIL
? -EIO
: 0;
366 /* Don't use -- use nand_read_oob_std for now */
367 static int cafe_nand_read_oob(struct mtd_info
*mtd
, struct nand_chip
*chip
,
370 chip
->cmdfunc(mtd
, NAND_CMD_READOOB
, 0, page
);
371 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
375 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
376 * @mtd: mtd info structure
377 * @chip: nand chip info structure
378 * @buf: buffer to store read data
379 * @oob_required: caller expects OOB data read to chip->oob_poi
381 * The hw generator calculates the error syndrome automatically. Therefore
382 * we need a special oob layout and handling.
384 static int cafe_nand_read_page(struct mtd_info
*mtd
, struct nand_chip
*chip
,
385 uint8_t *buf
, int oob_required
, int page
)
387 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
388 unsigned int max_bitflips
= 0;
390 cafe_dev_dbg(&cafe
->pdev
->dev
, "ECC result %08x SYN1,2 %08x\n",
391 cafe_readl(cafe
, NAND_ECC_RESULT
),
392 cafe_readl(cafe
, NAND_ECC_SYN01
));
394 chip
->read_buf(mtd
, buf
, mtd
->writesize
);
395 chip
->read_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
397 if (checkecc
&& cafe_readl(cafe
, NAND_ECC_RESULT
) & (1<<18)) {
398 unsigned short syn
[8], pat
[4];
400 u8
*oob
= chip
->oob_poi
;
403 for (i
=0; i
<8; i
+=2) {
404 uint32_t tmp
= cafe_readl(cafe
, NAND_ECC_SYN01
+ (i
*2));
405 syn
[i
] = cafe
->rs
->index_of
[tmp
& 0xfff];
406 syn
[i
+1] = cafe
->rs
->index_of
[(tmp
>> 16) & 0xfff];
409 n
= decode_rs16(cafe
->rs
, NULL
, NULL
, 1367, syn
, 0, pos
, 0,
412 for (i
= 0; i
< n
; i
++) {
415 /* The 12-bit symbols are mapped to bytes here */
421 /* high four bits do not correspond to data */
426 } else if (p
== 1365) {
427 buf
[2047] ^= pat
[i
] >> 4;
428 oob
[0] ^= pat
[i
] << 4;
429 } else if (p
> 1365) {
431 oob
[3*p
/2 - 2048] ^= pat
[i
] >> 4;
432 oob
[3*p
/2 - 2047] ^= pat
[i
] << 4;
434 oob
[3*p
/2 - 2049] ^= pat
[i
] >> 8;
435 oob
[3*p
/2 - 2048] ^= pat
[i
];
437 } else if ((p
& 1) == 1) {
438 buf
[3*p
/2] ^= pat
[i
] >> 4;
439 buf
[3*p
/2 + 1] ^= pat
[i
] << 4;
441 buf
[3*p
/2 - 1] ^= pat
[i
] >> 8;
442 buf
[3*p
/2] ^= pat
[i
];
447 dev_dbg(&cafe
->pdev
->dev
, "Failed to correct ECC at %08x\n",
448 cafe_readl(cafe
, NAND_ADDR2
) * 2048);
449 for (i
= 0; i
< 0x5c; i
+= 4)
450 printk("Register %x: %08x\n", i
, readl(cafe
->mmio
+ i
));
451 mtd
->ecc_stats
.failed
++;
453 dev_dbg(&cafe
->pdev
->dev
, "Corrected %d symbol errors\n", n
);
454 mtd
->ecc_stats
.corrected
+= n
;
455 max_bitflips
= max_t(unsigned int, max_bitflips
, n
);
462 static struct nand_ecclayout cafe_oobinfo_2048
= {
464 .eccpos
= { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
465 .oobfree
= {{14, 50}}
468 /* Ick. The BBT code really ought to be able to work this bit out
469 for itself from the above, at least for the 2KiB case */
470 static uint8_t cafe_bbt_pattern_2048
[] = { 'B', 'b', 't', '0' };
471 static uint8_t cafe_mirror_pattern_2048
[] = { '1', 't', 'b', 'B' };
473 static uint8_t cafe_bbt_pattern_512
[] = { 0xBB };
474 static uint8_t cafe_mirror_pattern_512
[] = { 0xBC };
477 static struct nand_bbt_descr cafe_bbt_main_descr_2048
= {
478 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
479 | NAND_BBT_2BIT
| NAND_BBT_VERSION
,
484 .pattern
= cafe_bbt_pattern_2048
487 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048
= {
488 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
489 | NAND_BBT_2BIT
| NAND_BBT_VERSION
,
494 .pattern
= cafe_mirror_pattern_2048
497 static struct nand_ecclayout cafe_oobinfo_512
= {
499 .eccpos
= { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13},
503 static struct nand_bbt_descr cafe_bbt_main_descr_512
= {
504 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
505 | NAND_BBT_2BIT
| NAND_BBT_VERSION
,
510 .pattern
= cafe_bbt_pattern_512
513 static struct nand_bbt_descr cafe_bbt_mirror_descr_512
= {
514 .options
= NAND_BBT_LASTBLOCK
| NAND_BBT_CREATE
| NAND_BBT_WRITE
515 | NAND_BBT_2BIT
| NAND_BBT_VERSION
,
520 .pattern
= cafe_mirror_pattern_512
524 static int cafe_nand_write_page_lowlevel(struct mtd_info
*mtd
,
525 struct nand_chip
*chip
,
526 const uint8_t *buf
, int oob_required
,
529 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
531 chip
->write_buf(mtd
, buf
, mtd
->writesize
);
532 chip
->write_buf(mtd
, chip
->oob_poi
, mtd
->oobsize
);
534 /* Set up ECC autogeneration */
535 cafe
->ctl2
|= (1<<30);
540 static int cafe_nand_block_bad(struct mtd_info
*mtd
, loff_t ofs
)
545 /* F_2[X]/(X**6+X+1) */
546 static unsigned short gf64_mul(u8 a
, u8 b
)
552 for (i
= 0; i
< 6; i
++) {
564 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
565 static u16
gf4096_mul(u16 a
, u16 b
)
567 u8 ah
, al
, bh
, bl
, ch
, cl
;
574 ch
= gf64_mul(ah
^ al
, bh
^ bl
) ^ gf64_mul(al
, bl
);
575 cl
= gf64_mul(gf64_mul(ah
, bh
), 0x21) ^ gf64_mul(al
, bl
);
577 return (ch
<< 6) ^ cl
;
580 static int cafe_mul(int x
)
584 return gf4096_mul(x
, 0xe01);
587 static int cafe_nand_probe(struct pci_dev
*pdev
,
588 const struct pci_device_id
*ent
)
590 struct mtd_info
*mtd
;
591 struct cafe_priv
*cafe
;
595 struct nand_buffers
*nbuf
;
597 /* Very old versions shared the same PCI ident for all three
598 functions on the chip. Verify the class too... */
599 if ((pdev
->class >> 8) != PCI_CLASS_MEMORY_FLASH
)
602 err
= pci_enable_device(pdev
);
606 pci_set_master(pdev
);
608 cafe
= kzalloc(sizeof(*cafe
), GFP_KERNEL
);
612 mtd
= nand_to_mtd(&cafe
->nand
);
613 mtd
->dev
.parent
= &pdev
->dev
;
614 nand_set_controller_data(&cafe
->nand
, cafe
);
617 cafe
->mmio
= pci_iomap(pdev
, 0, 0);
619 dev_warn(&pdev
->dev
, "failed to iomap\n");
624 cafe
->rs
= init_rs_non_canonical(12, &cafe_mul
, 0, 1, 8);
630 cafe
->nand
.cmdfunc
= cafe_nand_cmdfunc
;
631 cafe
->nand
.dev_ready
= cafe_device_ready
;
632 cafe
->nand
.read_byte
= cafe_read_byte
;
633 cafe
->nand
.read_buf
= cafe_read_buf
;
634 cafe
->nand
.write_buf
= cafe_write_buf
;
635 cafe
->nand
.select_chip
= cafe_select_chip
;
637 cafe
->nand
.chip_delay
= 0;
639 /* Enable the following for a flash based bad block table */
640 cafe
->nand
.bbt_options
= NAND_BBT_USE_FLASH
;
641 cafe
->nand
.options
= NAND_OWN_BUFFERS
;
644 cafe
->nand
.options
|= NAND_SKIP_BBTSCAN
;
645 cafe
->nand
.block_bad
= cafe_nand_block_bad
;
648 if (numtimings
&& numtimings
!= 3) {
649 dev_warn(&cafe
->pdev
->dev
, "%d timing register values ignored; precisely three are required\n", numtimings
);
652 if (numtimings
== 3) {
653 cafe_dev_dbg(&cafe
->pdev
->dev
, "Using provided timings (%08x %08x %08x)\n",
654 timing
[0], timing
[1], timing
[2]);
656 timing
[0] = cafe_readl(cafe
, NAND_TIMING1
);
657 timing
[1] = cafe_readl(cafe
, NAND_TIMING2
);
658 timing
[2] = cafe_readl(cafe
, NAND_TIMING3
);
660 if (timing
[0] | timing
[1] | timing
[2]) {
661 cafe_dev_dbg(&cafe
->pdev
->dev
, "Timing registers already set (%08x %08x %08x)\n",
662 timing
[0], timing
[1], timing
[2]);
664 dev_warn(&cafe
->pdev
->dev
, "Timing registers unset; using most conservative defaults\n");
665 timing
[0] = timing
[1] = timing
[2] = 0xffffffff;
669 /* Start off by resetting the NAND controller completely */
670 cafe_writel(cafe
, 1, NAND_RESET
);
671 cafe_writel(cafe
, 0, NAND_RESET
);
673 cafe_writel(cafe
, timing
[0], NAND_TIMING1
);
674 cafe_writel(cafe
, timing
[1], NAND_TIMING2
);
675 cafe_writel(cafe
, timing
[2], NAND_TIMING3
);
677 cafe_writel(cafe
, 0xffffffff, NAND_IRQ_MASK
);
678 err
= request_irq(pdev
->irq
, &cafe_nand_interrupt
, IRQF_SHARED
,
681 dev_warn(&pdev
->dev
, "Could not register IRQ %d\n", pdev
->irq
);
685 /* Disable master reset, enable NAND clock */
686 ctrl
= cafe_readl(cafe
, GLOBAL_CTRL
);
689 cafe_writel(cafe
, ctrl
| 0x05, GLOBAL_CTRL
);
690 cafe_writel(cafe
, ctrl
| 0x0a, GLOBAL_CTRL
);
691 cafe_writel(cafe
, 0, NAND_DMA_CTRL
);
693 cafe_writel(cafe
, 0x7006, GLOBAL_CTRL
);
694 cafe_writel(cafe
, 0x700a, GLOBAL_CTRL
);
696 /* Enable NAND IRQ in global IRQ mask register */
697 cafe_writel(cafe
, 0x80000007, GLOBAL_IRQ_MASK
);
698 cafe_dev_dbg(&cafe
->pdev
->dev
, "Control %x, IRQ mask %x\n",
699 cafe_readl(cafe
, GLOBAL_CTRL
),
700 cafe_readl(cafe
, GLOBAL_IRQ_MASK
));
702 /* Do not use the DMA for the nand_scan_ident() */
706 /* Scan to find existence of the device */
707 if (nand_scan_ident(mtd
, 2, NULL
)) {
712 cafe
->dmabuf
= dma_alloc_coherent(&cafe
->pdev
->dev
,
713 2112 + sizeof(struct nand_buffers
) +
714 mtd
->writesize
+ mtd
->oobsize
,
715 &cafe
->dmaaddr
, GFP_KERNEL
);
720 cafe
->nand
.buffers
= nbuf
= (void *)cafe
->dmabuf
+ 2112;
722 /* Set up DMA address */
723 cafe_writel(cafe
, cafe
->dmaaddr
& 0xffffffff, NAND_DMA_ADDR0
);
724 if (sizeof(cafe
->dmaaddr
) > 4)
725 /* Shift in two parts to shut the compiler up */
726 cafe_writel(cafe
, (cafe
->dmaaddr
>> 16) >> 16, NAND_DMA_ADDR1
);
728 cafe_writel(cafe
, 0, NAND_DMA_ADDR1
);
730 cafe_dev_dbg(&cafe
->pdev
->dev
, "Set DMA address to %x (virt %p)\n",
731 cafe_readl(cafe
, NAND_DMA_ADDR0
), cafe
->dmabuf
);
733 /* this driver does not need the @ecccalc and @ecccode */
734 nbuf
->ecccalc
= NULL
;
735 nbuf
->ecccode
= NULL
;
736 nbuf
->databuf
= (uint8_t *)(nbuf
+ 1);
738 /* Restore the DMA flag */
741 cafe
->ctl2
= 1<<27; /* Reed-Solomon ECC */
742 if (mtd
->writesize
== 2048)
743 cafe
->ctl2
|= 1<<29; /* 2KiB page size */
745 /* Set up ECC according to the type of chip we found */
746 if (mtd
->writesize
== 2048) {
747 cafe
->nand
.ecc
.layout
= &cafe_oobinfo_2048
;
748 cafe
->nand
.bbt_td
= &cafe_bbt_main_descr_2048
;
749 cafe
->nand
.bbt_md
= &cafe_bbt_mirror_descr_2048
;
750 } else if (mtd
->writesize
== 512) {
751 cafe
->nand
.ecc
.layout
= &cafe_oobinfo_512
;
752 cafe
->nand
.bbt_td
= &cafe_bbt_main_descr_512
;
753 cafe
->nand
.bbt_md
= &cafe_bbt_mirror_descr_512
;
755 printk(KERN_WARNING
"Unexpected NAND flash writesize %d. Aborting\n",
759 cafe
->nand
.ecc
.mode
= NAND_ECC_HW_SYNDROME
;
760 cafe
->nand
.ecc
.size
= mtd
->writesize
;
761 cafe
->nand
.ecc
.bytes
= 14;
762 cafe
->nand
.ecc
.strength
= 4;
763 cafe
->nand
.ecc
.hwctl
= (void *)cafe_nand_bug
;
764 cafe
->nand
.ecc
.calculate
= (void *)cafe_nand_bug
;
765 cafe
->nand
.ecc
.correct
= (void *)cafe_nand_bug
;
766 cafe
->nand
.ecc
.write_page
= cafe_nand_write_page_lowlevel
;
767 cafe
->nand
.ecc
.write_oob
= cafe_nand_write_oob
;
768 cafe
->nand
.ecc
.read_page
= cafe_nand_read_page
;
769 cafe
->nand
.ecc
.read_oob
= cafe_nand_read_oob
;
771 err
= nand_scan_tail(mtd
);
775 pci_set_drvdata(pdev
, mtd
);
777 mtd
->name
= "cafe_nand";
778 mtd_device_parse_register(mtd
, part_probes
, NULL
, NULL
, 0);
783 dma_free_coherent(&cafe
->pdev
->dev
,
784 2112 + sizeof(struct nand_buffers
) +
785 mtd
->writesize
+ mtd
->oobsize
,
786 cafe
->dmabuf
, cafe
->dmaaddr
);
788 /* Disable NAND IRQ in global IRQ mask register */
789 cafe_writel(cafe
, ~1 & cafe_readl(cafe
, GLOBAL_IRQ_MASK
), GLOBAL_IRQ_MASK
);
790 free_irq(pdev
->irq
, mtd
);
792 pci_iounmap(pdev
, cafe
->mmio
);
799 static void cafe_nand_remove(struct pci_dev
*pdev
)
801 struct mtd_info
*mtd
= pci_get_drvdata(pdev
);
802 struct nand_chip
*chip
= mtd_to_nand(mtd
);
803 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
805 /* Disable NAND IRQ in global IRQ mask register */
806 cafe_writel(cafe
, ~1 & cafe_readl(cafe
, GLOBAL_IRQ_MASK
), GLOBAL_IRQ_MASK
);
807 free_irq(pdev
->irq
, mtd
);
810 pci_iounmap(pdev
, cafe
->mmio
);
811 dma_free_coherent(&cafe
->pdev
->dev
,
812 2112 + sizeof(struct nand_buffers
) +
813 mtd
->writesize
+ mtd
->oobsize
,
814 cafe
->dmabuf
, cafe
->dmaaddr
);
818 static const struct pci_device_id cafe_nand_tbl
[] = {
819 { PCI_VENDOR_ID_MARVELL
, PCI_DEVICE_ID_MARVELL_88ALP01_NAND
,
820 PCI_ANY_ID
, PCI_ANY_ID
},
824 MODULE_DEVICE_TABLE(pci
, cafe_nand_tbl
);
826 static int cafe_nand_resume(struct pci_dev
*pdev
)
829 struct mtd_info
*mtd
= pci_get_drvdata(pdev
);
830 struct nand_chip
*chip
= mtd_to_nand(mtd
);
831 struct cafe_priv
*cafe
= nand_get_controller_data(chip
);
833 /* Start off by resetting the NAND controller completely */
834 cafe_writel(cafe
, 1, NAND_RESET
);
835 cafe_writel(cafe
, 0, NAND_RESET
);
836 cafe_writel(cafe
, 0xffffffff, NAND_IRQ_MASK
);
838 /* Restore timing configuration */
839 cafe_writel(cafe
, timing
[0], NAND_TIMING1
);
840 cafe_writel(cafe
, timing
[1], NAND_TIMING2
);
841 cafe_writel(cafe
, timing
[2], NAND_TIMING3
);
843 /* Disable master reset, enable NAND clock */
844 ctrl
= cafe_readl(cafe
, GLOBAL_CTRL
);
847 cafe_writel(cafe
, ctrl
| 0x05, GLOBAL_CTRL
);
848 cafe_writel(cafe
, ctrl
| 0x0a, GLOBAL_CTRL
);
849 cafe_writel(cafe
, 0, NAND_DMA_CTRL
);
850 cafe_writel(cafe
, 0x7006, GLOBAL_CTRL
);
851 cafe_writel(cafe
, 0x700a, GLOBAL_CTRL
);
853 /* Set up DMA address */
854 cafe_writel(cafe
, cafe
->dmaaddr
& 0xffffffff, NAND_DMA_ADDR0
);
855 if (sizeof(cafe
->dmaaddr
) > 4)
856 /* Shift in two parts to shut the compiler up */
857 cafe_writel(cafe
, (cafe
->dmaaddr
>> 16) >> 16, NAND_DMA_ADDR1
);
859 cafe_writel(cafe
, 0, NAND_DMA_ADDR1
);
861 /* Enable NAND IRQ in global IRQ mask register */
862 cafe_writel(cafe
, 0x80000007, GLOBAL_IRQ_MASK
);
866 static struct pci_driver cafe_nand_pci_driver
= {
868 .id_table
= cafe_nand_tbl
,
869 .probe
= cafe_nand_probe
,
870 .remove
= cafe_nand_remove
,
871 .resume
= cafe_nand_resume
,
874 module_pci_driver(cafe_nand_pci_driver
);
876 MODULE_LICENSE("GPL");
877 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
878 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");