drivers/net/ethernet/amd/xgbe/xgbe.h

   1 /*
   2  * AMD 10Gb Ethernet driver
   3  *
   4  * This file is available to you under your choice of the following two
   5  * licenses:
   6  *
   7  * License 1: GPLv2
   8  *
   9  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  10  *
  11  * This file is free software; you may copy, redistribute and/or modify
  12  * it under the terms of the GNU General Public License as published by
  13  * the Free Software Foundation, either version 2 of the License, or (at
  14  * your option) any later version.
  15  *
  16  * This file is distributed in the hope that it will be useful, but
  17  * WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19  * General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
  23  *
  24  * This file incorporates work covered by the following copyright and
  25  * permission notice:
  26  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  27  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  28  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  29  *     and you.
  30  *
  31  *     The Software IS NOT an item of Licensed Software or Licensed Product
  32  *     under any End User Software License Agreement or Agreement for Licensed
  33  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  34  *     granted, free of charge, to any person obtaining a copy of this software
  35  *     annotated with this license and the Software, to deal in the Software
  36  *     without restriction, including without limitation the rights to use,
  37  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  38  *     of the Software, and to permit persons to whom the Software is furnished
  39  *     to do so, subject to the following conditions:
  40  *
  41  *     The above copyright notice and this permission notice shall be included
  42  *     in all copies or substantial portions of the Software.
  43  *
  44  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
  45  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
  46  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
  47  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
  48  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  49  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  50  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  51  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  52  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  53  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  54  *     THE POSSIBILITY OF SUCH DAMAGE.
  55  *
  56  *
  57  * License 2: Modified BSD
  58  *
  59  * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
  60  * All rights reserved.
  61  *
  62  * Redistribution and use in source and binary forms, with or without
  63  * modification, are permitted provided that the following conditions are met:
  64  *     * Redistributions of source code must retain the above copyright
  65  *       notice, this list of conditions and the following disclaimer.
  66  *     * Redistributions in binary form must reproduce the above copyright
  67  *       notice, this list of conditions and the following disclaimer in the
  68  *       documentation and/or other materials provided with the distribution.
  69  *     * Neither the name of Advanced Micro Devices, Inc. nor the
  70  *       names of its contributors may be used to endorse or promote products
  71  *       derived from this software without specific prior written permission.
  72  *
  73  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  74  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  75  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  76  * ARE DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  77  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  78  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  79  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  80  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  81  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
  82  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  83  *
  84  * This file incorporates work covered by the following copyright and
  85  * permission notice:
  86  *     The Synopsys DWC ETHER XGMAC Software Driver and documentation
  87  *     (hereinafter "Software") is an unsupported proprietary work of Synopsys,
  88  *     Inc. unless otherwise expressly agreed to in writing between Synopsys
  89  *     and you.
  90  *
  91  *     The Software IS NOT an item of Licensed Software or Licensed Product
  92  *     under any End User Software License Agreement or Agreement for Licensed
  93  *     Product with Synopsys or any supplement thereto.  Permission is hereby
  94  *     granted, free of charge, to any person obtaining a copy of this software
  95  *     annotated with this license and the Software, to deal in the Software
  96  *     without restriction, including without limitation the rights to use,
  97  *     copy, modify, merge, publish, distribute, sublicense, and/or sell copies
  98  *     of the Software, and to permit persons to whom the Software is furnished
  99  *     to do so, subject to the following conditions:
 100  *
 101  *     The above copyright notice and this permission notice shall be included
 102  *     in all copies or substantial portions of the Software.
 103  *
 104  *     THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS"
 105  *     BASIS AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
 106  *     TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
 107  *     PARTICULAR PURPOSE ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS
 108  *     BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
 109  *     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
 110  *     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
 111  *     INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
 112  *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
 113  *     ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
 114  *     THE POSSIBILITY OF SUCH DAMAGE.
 115  */
 116
 117 #ifndef __XGBE_H__
 118 #define __XGBE_H__
 119
 120 #include <linux/dma-mapping.h>
 121 #include <linux/netdevice.h>
 122 #include <linux/workqueue.h>
 123 #include <linux/phy.h>
 124 #include <linux/if_vlan.h>
 125 #include <linux/bitops.h>
 126 #include <linux/ptp_clock_kernel.h>
 127 #include <linux/timecounter.h>
 128 #include <linux/net_tstamp.h>
 129 #include <net/dcbnl.h>
 130
 131 #define XGBE_DRV_NAME           "amd-xgbe"
 132 #define XGBE_DRV_VERSION        "1.0.2"
 133 #define XGBE_DRV_DESC           "AMD 10 Gigabit Ethernet Driver"
 134
 135 /* Descriptor related defines */
 136 #define XGBE_TX_DESC_CNT        512
 137 #define XGBE_TX_DESC_MIN_FREE   (XGBE_TX_DESC_CNT >> 3)
 138 #define XGBE_TX_DESC_MAX_PROC   (XGBE_TX_DESC_CNT >> 1)
 139 #define XGBE_RX_DESC_CNT        512
 140
 141 #define XGBE_TX_MAX_BUF_SIZE    (0x3fff & ~(64 - 1))
 142
 143 /* Descriptors required for maximum contiguous TSO/GSO packet */
 144 #define XGBE_TX_MAX_SPLIT       ((GSO_MAX_SIZE / XGBE_TX_MAX_BUF_SIZE) + 1)
 145
 146 /* Maximum possible descriptors needed for an SKB:
 147  * - Maximum number of SKB frags
 148  * - Maximum descriptors for contiguous TSO/GSO packet
 149  * - Possible context descriptor
 150  * - Possible TSO header descriptor
 151  */
 152 #define XGBE_TX_MAX_DESCS       (MAX_SKB_FRAGS + XGBE_TX_MAX_SPLIT + 2)
 153
 154 #define XGBE_RX_MIN_BUF_SIZE    (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
 155 #define XGBE_RX_BUF_ALIGN       64
 156 #define XGBE_SKB_ALLOC_SIZE     256
 157 #define XGBE_SPH_HDSMS_SIZE     2       /* Keep in sync with SKB_ALLOC_SIZE */
 158
 159 #define XGBE_MAX_DMA_CHANNELS   16
 160 #define XGBE_MAX_QUEUES         16
 161 #define XGBE_DMA_STOP_TIMEOUT   5
 162
 163 /* DMA cache settings - Outer sharable, write-back, write-allocate */
 164 #define XGBE_DMA_OS_AXDOMAIN    0x2
 165 #define XGBE_DMA_OS_ARCACHE     0xb
 166 #define XGBE_DMA_OS_AWCACHE     0xf
 167
 168 /* DMA cache settings - System, no caches used */
 169 #define XGBE_DMA_SYS_AXDOMAIN   0x3
 170 #define XGBE_DMA_SYS_ARCACHE    0x0
 171 #define XGBE_DMA_SYS_AWCACHE    0x0
 172
 173 #define XGBE_DMA_INTERRUPT_MASK 0x31c7
 174
 175 #define XGMAC_MIN_PACKET        60
 176 #define XGMAC_STD_PACKET_MTU    1500
 177 #define XGMAC_MAX_STD_PACKET    1518
 178 #define XGMAC_JUMBO_PACKET_MTU  9000
 179 #define XGMAC_MAX_JUMBO_PACKET  9018
 180
 181 /* Common property names */
 182 #define XGBE_MAC_ADDR_PROPERTY  "mac-address"
 183 #define XGBE_PHY_MODE_PROPERTY  "phy-mode"
 184 #define XGBE_DMA_IRQS_PROPERTY  "amd,per-channel-interrupt"
 185 #define XGBE_SPEEDSET_PROPERTY  "amd,speed-set"
 186 #define XGBE_BLWC_PROPERTY      "amd,serdes-blwc"
 187 #define XGBE_CDR_RATE_PROPERTY  "amd,serdes-cdr-rate"
 188 #define XGBE_PQ_SKEW_PROPERTY   "amd,serdes-pq-skew"
 189 #define XGBE_TX_AMP_PROPERTY    "amd,serdes-tx-amp"
 190 #define XGBE_DFE_CFG_PROPERTY   "amd,serdes-dfe-tap-config"
 191 #define XGBE_DFE_ENA_PROPERTY   "amd,serdes-dfe-tap-enable"
 192
 193 /* Device-tree clock names */
 194 #define XGBE_DMA_CLOCK          "dma_clk"
 195 #define XGBE_PTP_CLOCK          "ptp_clk"
 196
 197 /* ACPI property names */
 198 #define XGBE_ACPI_DMA_FREQ      "amd,dma-freq"
 199 #define XGBE_ACPI_PTP_FREQ      "amd,ptp-freq"
 200
 201 /* Timestamp support - values based on 50MHz PTP clock
 202  *   50MHz => 20 nsec
 203  */
 204 #define XGBE_TSTAMP_SSINC       20
 205 #define XGBE_TSTAMP_SNSINC      0
 206
 207 /* Driver PMT macros */
 208 #define XGMAC_DRIVER_CONTEXT    1
 209 #define XGMAC_IOCTL_CONTEXT     2
 210
 211 #define XGBE_FIFO_MAX           81920
 212
 213 #define XGBE_TC_MIN_QUANTUM     10
 214
 215 /* Helper macro for descriptor handling
 216  *  Always use XGBE_GET_DESC_DATA to access the descriptor data
 217  *  since the index is free-running and needs to be and-ed
 218  *  with the descriptor count value of the ring to index to
 219  *  the proper descriptor data.
 220  */
 221 #define XGBE_GET_DESC_DATA(_ring, _idx)                         \
 222         ((_ring)->rdata +                                       \
 223          ((_idx) & ((_ring)->rdesc_count - 1)))
 224
 225 /* Default coalescing parameters */
 226 #define XGMAC_INIT_DMA_TX_USECS         1000
 227 #define XGMAC_INIT_DMA_TX_FRAMES        25
 228
 229 #define XGMAC_MAX_DMA_RIWT              0xff
 230 #define XGMAC_INIT_DMA_RX_USECS         30
 231 #define XGMAC_INIT_DMA_RX_FRAMES        25
 232
 233 /* Flow control queue count */
 234 #define XGMAC_MAX_FLOW_CONTROL_QUEUES   8
 235
 236 /* Maximum MAC address hash table size (256 bits = 8 bytes) */
 237 #define XGBE_MAC_HASH_TABLE_SIZE        8
 238
 239 /* Receive Side Scaling */
 240 #define XGBE_RSS_HASH_KEY_SIZE          40
 241 #define XGBE_RSS_MAX_TABLE_SIZE         256
 242 #define XGBE_RSS_LOOKUP_TABLE_TYPE      0
 243 #define XGBE_RSS_HASH_KEY_TYPE          1
 244
 245 /* Auto-negotiation */
 246 #define XGBE_AN_MS_TIMEOUT              500
 247 #define XGBE_LINK_TIMEOUT               10
 248
 249 #define XGBE_AN_INT_CMPLT               0x01
 250 #define XGBE_AN_INC_LINK                0x02
 251 #define XGBE_AN_PG_RCV                  0x04
 252 #define XGBE_AN_INT_MASK                0x07
 253
 254 /* Rate-change complete wait/retry count */
 255 #define XGBE_RATECHANGE_COUNT           500
 256
 257 /* Default SerDes settings */
 258 #define XGBE_SPEED_10000_BLWC           0
 259 #define XGBE_SPEED_10000_CDR            0x7
 260 #define XGBE_SPEED_10000_PLL            0x1
 261 #define XGBE_SPEED_10000_PQ             0x12
 262 #define XGBE_SPEED_10000_RATE           0x0
 263 #define XGBE_SPEED_10000_TXAMP          0xa
 264 #define XGBE_SPEED_10000_WORD           0x7
 265 #define XGBE_SPEED_10000_DFE_TAP_CONFIG 0x1
 266 #define XGBE_SPEED_10000_DFE_TAP_ENABLE 0x7f
 267
 268 #define XGBE_SPEED_2500_BLWC            1
 269 #define XGBE_SPEED_2500_CDR             0x2
 270 #define XGBE_SPEED_2500_PLL             0x0
 271 #define XGBE_SPEED_2500_PQ              0xa
 272 #define XGBE_SPEED_2500_RATE            0x1
 273 #define XGBE_SPEED_2500_TXAMP           0xf
 274 #define XGBE_SPEED_2500_WORD            0x1
 275 #define XGBE_SPEED_2500_DFE_TAP_CONFIG  0x3
 276 #define XGBE_SPEED_2500_DFE_TAP_ENABLE  0x0
 277
 278 #define XGBE_SPEED_1000_BLWC            1
 279 #define XGBE_SPEED_1000_CDR             0x2
 280 #define XGBE_SPEED_1000_PLL             0x0
 281 #define XGBE_SPEED_1000_PQ              0xa
 282 #define XGBE_SPEED_1000_RATE            0x3
 283 #define XGBE_SPEED_1000_TXAMP           0xf
 284 #define XGBE_SPEED_1000_WORD            0x1
 285 #define XGBE_SPEED_1000_DFE_TAP_CONFIG  0x3
 286 #define XGBE_SPEED_1000_DFE_TAP_ENABLE  0x0
 287
 288 struct xgbe_prv_data;
 289
 290 struct xgbe_packet_data {
 291         struct sk_buff *skb;
 292
 293         unsigned int attributes;
 294
 295         unsigned int errors;
 296
 297         unsigned int rdesc_count;
 298         unsigned int length;
 299
 300         unsigned int header_len;
 301         unsigned int tcp_header_len;
 302         unsigned int tcp_payload_len;
 303         unsigned short mss;
 304
 305         unsigned short vlan_ctag;
 306
 307         u64 rx_tstamp;
 308
 309         u32 rss_hash;
 310         enum pkt_hash_types rss_hash_type;
 311
 312         unsigned int tx_packets;
 313         unsigned int tx_bytes;
 314 };
 315
 316 /* Common Rx and Tx descriptor mapping */
 317 struct xgbe_ring_desc {
 318         __le32 desc0;
 319         __le32 desc1;
 320         __le32 desc2;
 321         __le32 desc3;
 322 };
 323
 324 /* Page allocation related values */
 325 struct xgbe_page_alloc {
 326         struct page *pages;
 327         unsigned int pages_len;
 328         unsigned int pages_offset;
 329
 330         dma_addr_t pages_dma;
 331 };
 332
 333 /* Ring entry buffer data */
 334 struct xgbe_buffer_data {
 335         struct xgbe_page_alloc pa;
 336         struct xgbe_page_alloc pa_unmap;
 337
 338         dma_addr_t dma_base;
 339         unsigned long dma_off;
 340         unsigned int dma_len;
 341 };
 342
 343 /* Tx-related ring data */
 344 struct xgbe_tx_ring_data {
 345         unsigned int packets;           /* BQL packet count */
 346         unsigned int bytes;             /* BQL byte count */
 347 };
 348
 349 /* Rx-related ring data */
 350 struct xgbe_rx_ring_data {
 351         struct xgbe_buffer_data hdr;    /* Header locations */
 352         struct xgbe_buffer_data buf;    /* Payload locations */
 353
 354         unsigned short hdr_len;         /* Length of received header */
 355         unsigned short len;             /* Length of received packet */
 356 };
 357
 358 /* Structure used to hold information related to the descriptor
 359  * and the packet associated with the descriptor (always use
 360  * use the XGBE_GET_DESC_DATA macro to access this data from the ring)
 361  */
 362 struct xgbe_ring_data {
 363         struct xgbe_ring_desc *rdesc;   /* Virtual address of descriptor */
 364         dma_addr_t rdesc_dma;           /* DMA address of descriptor */
 365
 366         struct sk_buff *skb;            /* Virtual address of SKB */
 367         dma_addr_t skb_dma;             /* DMA address of SKB data */
 368         unsigned int skb_dma_len;       /* Length of SKB DMA area */
 369
 370         struct xgbe_tx_ring_data tx;    /* Tx-related data */
 371         struct xgbe_rx_ring_data rx;    /* Rx-related data */
 372
 373         unsigned int mapped_as_page;
 374
 375         /* Incomplete receive save location.  If the budget is exhausted
 376          * or the last descriptor (last normal descriptor or a following
 377          * context descriptor) has not been DMA'd yet the current state
 378          * of the receive processing needs to be saved.
 379          */
 380         unsigned int state_saved;
 381         struct {
 382                 struct sk_buff *skb;
 383                 unsigned int len;
 384                 unsigned int error;
 385         } state;
 386 };
 387
 388 struct xgbe_ring {
 389         /* Ring lock - used just for TX rings at the moment */
 390         spinlock_t lock;
 391
 392         /* Per packet related information */
 393         struct xgbe_packet_data packet_data;
 394
 395         /* Virtual/DMA addresses and count of allocated descriptor memory */
 396         struct xgbe_ring_desc *rdesc;
 397         dma_addr_t rdesc_dma;
 398         unsigned int rdesc_count;
 399
 400         /* Array of descriptor data corresponding the descriptor memory
 401          * (always use the XGBE_GET_DESC_DATA macro to access this data)
 402          */
 403         struct xgbe_ring_data *rdata;
 404
 405         /* Page allocation for RX buffers */
 406         struct xgbe_page_alloc rx_hdr_pa;
 407         struct xgbe_page_alloc rx_buf_pa;
 408
 409         /* Ring index values
 410          *  cur   - Tx: index of descriptor to be used for current transfer
 411          *          Rx: index of descriptor to check for packet availability
 412          *  dirty - Tx: index of descriptor to check for transfer complete
 413          *          Rx: index of descriptor to check for buffer reallocation
 414          */
 415         unsigned int cur;
 416         unsigned int dirty;
 417
 418         /* Coalesce frame count used for interrupt bit setting */
 419         unsigned int coalesce_count;
 420
 421         union {
 422                 struct {
 423                         unsigned int queue_stopped;
 424                         unsigned int xmit_more;
 425                         unsigned short cur_mss;
 426                         unsigned short cur_vlan_ctag;
 427                 } tx;
 428         };
 429 } ____cacheline_aligned;
 430
 431 /* Structure used to describe the descriptor rings associated with
 432  * a DMA channel.
 433  */
 434 struct xgbe_channel {
 435         char name[16];
 436
 437         /* Address of private data area for device */
 438         struct xgbe_prv_data *pdata;
 439
 440         /* Queue index and base address of queue's DMA registers */
 441         unsigned int queue_index;
 442         void __iomem *dma_regs;
 443
 444         /* Per channel interrupt irq number */
 445         int dma_irq;
 446         char dma_irq_name[IFNAMSIZ + 32];
 447
 448         /* Netdev related settings */
 449         struct napi_struct napi;
 450
 451         unsigned int saved_ier;
 452
 453         unsigned int tx_timer_active;
 454         struct timer_list tx_timer;
 455
 456         struct xgbe_ring *tx_ring;
 457         struct xgbe_ring *rx_ring;
 458 } ____cacheline_aligned;
 459
 460 enum xgbe_state {
 461         XGBE_DOWN,
 462         XGBE_LINK_INIT,
 463         XGBE_LINK_ERR,
 464 };
 465
 466 enum xgbe_int {
 467         XGMAC_INT_DMA_CH_SR_TI,
 468         XGMAC_INT_DMA_CH_SR_TPS,
 469         XGMAC_INT_DMA_CH_SR_TBU,
 470         XGMAC_INT_DMA_CH_SR_RI,
 471         XGMAC_INT_DMA_CH_SR_RBU,
 472         XGMAC_INT_DMA_CH_SR_RPS,
 473         XGMAC_INT_DMA_CH_SR_TI_RI,
 474         XGMAC_INT_DMA_CH_SR_FBE,
 475         XGMAC_INT_DMA_ALL,
 476 };
 477
 478 enum xgbe_int_state {
 479         XGMAC_INT_STATE_SAVE,
 480         XGMAC_INT_STATE_RESTORE,
 481 };
 482
 483 enum xgbe_speed {
 484         XGBE_SPEED_1000 = 0,
 485         XGBE_SPEED_2500,
 486         XGBE_SPEED_10000,
 487         XGBE_SPEEDS,
 488 };
 489
 490 enum xgbe_an {
 491         XGBE_AN_READY = 0,
 492         XGBE_AN_PAGE_RECEIVED,
 493         XGBE_AN_INCOMPAT_LINK,
 494         XGBE_AN_COMPLETE,
 495         XGBE_AN_NO_LINK,
 496         XGBE_AN_ERROR,
 497 };
 498
 499 enum xgbe_rx {
 500         XGBE_RX_BPA = 0,
 501         XGBE_RX_XNP,
 502         XGBE_RX_COMPLETE,
 503         XGBE_RX_ERROR,
 504 };
 505
 506 enum xgbe_mode {
 507         XGBE_MODE_KR = 0,
 508         XGBE_MODE_KX,
 509 };
 510
 511 enum xgbe_speedset {
 512         XGBE_SPEEDSET_1000_10000 = 0,
 513         XGBE_SPEEDSET_2500_10000,
 514 };
 515
 516 struct xgbe_phy {
 517         u32 supported;
 518         u32 advertising;
 519         u32 lp_advertising;
 520
 521         int address;
 522
 523         int autoneg;
 524         int speed;
 525         int duplex;
 526
 527         int link;
 528
 529         int pause_autoneg;
 530         int tx_pause;
 531         int rx_pause;
 532 };
 533
 534 struct xgbe_mmc_stats {
 535         /* Tx Stats */
 536         u64 txoctetcount_gb;
 537         u64 txframecount_gb;
 538         u64 txbroadcastframes_g;
 539         u64 txmulticastframes_g;
 540         u64 tx64octets_gb;
 541         u64 tx65to127octets_gb;
 542         u64 tx128to255octets_gb;
 543         u64 tx256to511octets_gb;
 544         u64 tx512to1023octets_gb;
 545         u64 tx1024tomaxoctets_gb;
 546         u64 txunicastframes_gb;
 547         u64 txmulticastframes_gb;
 548         u64 txbroadcastframes_gb;
 549         u64 txunderflowerror;
 550         u64 txoctetcount_g;
 551         u64 txframecount_g;
 552         u64 txpauseframes;
 553         u64 txvlanframes_g;
 554
 555         /* Rx Stats */
 556         u64 rxframecount_gb;
 557         u64 rxoctetcount_gb;
 558         u64 rxoctetcount_g;
 559         u64 rxbroadcastframes_g;
 560         u64 rxmulticastframes_g;
 561         u64 rxcrcerror;
 562         u64 rxrunterror;
 563         u64 rxjabbererror;
 564         u64 rxundersize_g;
 565         u64 rxoversize_g;
 566         u64 rx64octets_gb;
 567         u64 rx65to127octets_gb;
 568         u64 rx128to255octets_gb;
 569         u64 rx256to511octets_gb;
 570         u64 rx512to1023octets_gb;
 571         u64 rx1024tomaxoctets_gb;
 572         u64 rxunicastframes_g;
 573         u64 rxlengtherror;
 574         u64 rxoutofrangetype;
 575         u64 rxpauseframes;
 576         u64 rxfifooverflow;
 577         u64 rxvlanframes_gb;
 578         u64 rxwatchdogerror;
 579 };
 580
 581 struct xgbe_ext_stats {
 582         u64 tx_tso_packets;
 583         u64 rx_split_header_packets;
 584         u64 rx_buffer_unavailable;
 585 };
 586
 587 struct xgbe_hw_if {
 588         int (*tx_complete)(struct xgbe_ring_desc *);
 589
 590         int (*set_mac_address)(struct xgbe_prv_data *, u8 *addr);
 591         int (*config_rx_mode)(struct xgbe_prv_data *);
 592
 593         int (*enable_rx_csum)(struct xgbe_prv_data *);
 594         int (*disable_rx_csum)(struct xgbe_prv_data *);
 595
 596         int (*enable_rx_vlan_stripping)(struct xgbe_prv_data *);
 597         int (*disable_rx_vlan_stripping)(struct xgbe_prv_data *);
 598         int (*enable_rx_vlan_filtering)(struct xgbe_prv_data *);
 599         int (*disable_rx_vlan_filtering)(struct xgbe_prv_data *);
 600         int (*update_vlan_hash_table)(struct xgbe_prv_data *);
 601
 602         int (*read_mmd_regs)(struct xgbe_prv_data *, int, int);
 603         void (*write_mmd_regs)(struct xgbe_prv_data *, int, int, int);
 604         int (*set_gmii_speed)(struct xgbe_prv_data *);
 605         int (*set_gmii_2500_speed)(struct xgbe_prv_data *);
 606         int (*set_xgmii_speed)(struct xgbe_prv_data *);
 607
 608         void (*enable_tx)(struct xgbe_prv_data *);
 609         void (*disable_tx)(struct xgbe_prv_data *);
 610         void (*enable_rx)(struct xgbe_prv_data *);
 611         void (*disable_rx)(struct xgbe_prv_data *);
 612
 613         void (*powerup_tx)(struct xgbe_prv_data *);
 614         void (*powerdown_tx)(struct xgbe_prv_data *);
 615         void (*powerup_rx)(struct xgbe_prv_data *);
 616         void (*powerdown_rx)(struct xgbe_prv_data *);
 617
 618         int (*init)(struct xgbe_prv_data *);
 619         int (*exit)(struct xgbe_prv_data *);
 620
 621         int (*enable_int)(struct xgbe_channel *, enum xgbe_int);
 622         int (*disable_int)(struct xgbe_channel *, enum xgbe_int);
 623         void (*dev_xmit)(struct xgbe_channel *);
 624         int (*dev_read)(struct xgbe_channel *);
 625         void (*tx_desc_init)(struct xgbe_channel *);
 626         void (*rx_desc_init)(struct xgbe_channel *);
 627         void (*tx_desc_reset)(struct xgbe_ring_data *);
 628         void (*rx_desc_reset)(struct xgbe_prv_data *, struct xgbe_ring_data *,
 629                               unsigned int);
 630         int (*is_last_desc)(struct xgbe_ring_desc *);
 631         int (*is_context_desc)(struct xgbe_ring_desc *);
 632         void (*tx_start_xmit)(struct xgbe_channel *, struct xgbe_ring *);
 633
 634         /* For FLOW ctrl */
 635         int (*config_tx_flow_control)(struct xgbe_prv_data *);
 636         int (*config_rx_flow_control)(struct xgbe_prv_data *);
 637
 638         /* For RX coalescing */
 639         int (*config_rx_coalesce)(struct xgbe_prv_data *);
 640         int (*config_tx_coalesce)(struct xgbe_prv_data *);
 641         unsigned int (*usec_to_riwt)(struct xgbe_prv_data *, unsigned int);
 642         unsigned int (*riwt_to_usec)(struct xgbe_prv_data *, unsigned int);
 643
 644         /* For RX and TX threshold config */
 645         int (*config_rx_threshold)(struct xgbe_prv_data *, unsigned int);
 646         int (*config_tx_threshold)(struct xgbe_prv_data *, unsigned int);
 647
 648         /* For RX and TX Store and Forward Mode config */
 649         int (*config_rsf_mode)(struct xgbe_prv_data *, unsigned int);
 650         int (*config_tsf_mode)(struct xgbe_prv_data *, unsigned int);
 651
 652         /* For TX DMA Operate on Second Frame config */
 653         int (*config_osp_mode)(struct xgbe_prv_data *);
 654
 655         /* For RX and TX PBL config */
 656         int (*config_rx_pbl_val)(struct xgbe_prv_data *);
 657         int (*get_rx_pbl_val)(struct xgbe_prv_data *);
 658         int (*config_tx_pbl_val)(struct xgbe_prv_data *);
 659         int (*get_tx_pbl_val)(struct xgbe_prv_data *);
 660         int (*config_pblx8)(struct xgbe_prv_data *);
 661
 662         /* For MMC statistics */
 663         void (*rx_mmc_int)(struct xgbe_prv_data *);
 664         void (*tx_mmc_int)(struct xgbe_prv_data *);
 665         void (*read_mmc_stats)(struct xgbe_prv_data *);
 666
 667         /* For Timestamp config */
 668         int (*config_tstamp)(struct xgbe_prv_data *, unsigned int);
 669         void (*update_tstamp_addend)(struct xgbe_prv_data *, unsigned int);
 670         void (*set_tstamp_time)(struct xgbe_prv_data *, unsigned int sec,
 671                                 unsigned int nsec);
 672         u64 (*get_tstamp_time)(struct xgbe_prv_data *);
 673         u64 (*get_tx_tstamp)(struct xgbe_prv_data *);
 674
 675         /* For Data Center Bridging config */
 676         void (*config_tc)(struct xgbe_prv_data *);
 677         void (*config_dcb_tc)(struct xgbe_prv_data *);
 678         void (*config_dcb_pfc)(struct xgbe_prv_data *);
 679
 680         /* For Receive Side Scaling */
 681         int (*enable_rss)(struct xgbe_prv_data *);
 682         int (*disable_rss)(struct xgbe_prv_data *);
 683         int (*set_rss_hash_key)(struct xgbe_prv_data *, const u8 *);
 684         int (*set_rss_lookup_table)(struct xgbe_prv_data *, const u32 *);
 685 };
 686
 687 struct xgbe_phy_if {
 688         /* For initial PHY setup */
 689         void (*phy_init)(struct xgbe_prv_data *);
 690
 691         /* For PHY support when setting device up/down */
 692         int (*phy_reset)(struct xgbe_prv_data *);
 693         int (*phy_start)(struct xgbe_prv_data *);
 694         void (*phy_stop)(struct xgbe_prv_data *);
 695
 696         /* For PHY support while device is up */
 697         void (*phy_status)(struct xgbe_prv_data *);
 698         int (*phy_config_aneg)(struct xgbe_prv_data *);
 699 };
 700
 701 struct xgbe_desc_if {
 702         int (*alloc_ring_resources)(struct xgbe_prv_data *);
 703         void (*free_ring_resources)(struct xgbe_prv_data *);
 704         int (*map_tx_skb)(struct xgbe_channel *, struct sk_buff *);
 705         int (*map_rx_buffer)(struct xgbe_prv_data *, struct xgbe_ring *,
 706                              struct xgbe_ring_data *);
 707         void (*unmap_rdata)(struct xgbe_prv_data *, struct xgbe_ring_data *);
 708         void (*wrapper_tx_desc_init)(struct xgbe_prv_data *);
 709         void (*wrapper_rx_desc_init)(struct xgbe_prv_data *);
 710 };
 711
 712 /* This structure contains flags that indicate what hardware features
 713  * or configurations are present in the device.
 714  */
 715 struct xgbe_hw_features {
 716         /* HW Version */
 717         unsigned int version;
 718
 719         /* HW Feature Register0 */
 720         unsigned int gmii;              /* 1000 Mbps support */
 721         unsigned int vlhash;            /* VLAN Hash Filter */
 722         unsigned int sma;               /* SMA(MDIO) Interface */
 723         unsigned int rwk;               /* PMT remote wake-up packet */
 724         unsigned int mgk;               /* PMT magic packet */
 725         unsigned int mmc;               /* RMON module */
 726         unsigned int aoe;               /* ARP Offload */
 727         unsigned int ts;                /* IEEE 1588-2008 Advanced Timestamp */
 728         unsigned int eee;               /* Energy Efficient Ethernet */
 729         unsigned int tx_coe;            /* Tx Checksum Offload */
 730         unsigned int rx_coe;            /* Rx Checksum Offload */
 731         unsigned int addn_mac;          /* Additional MAC Addresses */
 732         unsigned int ts_src;            /* Timestamp Source */
 733         unsigned int sa_vlan_ins;       /* Source Address or VLAN Insertion */
 734
 735         /* HW Feature Register1 */
 736         unsigned int rx_fifo_size;      /* MTL Receive FIFO Size */
 737         unsigned int tx_fifo_size;      /* MTL Transmit FIFO Size */
 738         unsigned int adv_ts_hi;         /* Advance Timestamping High Word */
 739         unsigned int dma_width;         /* DMA width */
 740         unsigned int dcb;               /* DCB Feature */
 741         unsigned int sph;               /* Split Header Feature */
 742         unsigned int tso;               /* TCP Segmentation Offload */
 743         unsigned int dma_debug;         /* DMA Debug Registers */
 744         unsigned int rss;               /* Receive Side Scaling */
 745         unsigned int tc_cnt;            /* Number of Traffic Classes */
 746         unsigned int hash_table_size;   /* Hash Table Size */
 747         unsigned int l3l4_filter_num;   /* Number of L3-L4 Filters */
 748
 749         /* HW Feature Register2 */
 750         unsigned int rx_q_cnt;          /* Number of MTL Receive Queues */
 751         unsigned int tx_q_cnt;          /* Number of MTL Transmit Queues */
 752         unsigned int rx_ch_cnt;         /* Number of DMA Receive Channels */
 753         unsigned int tx_ch_cnt;         /* Number of DMA Transmit Channels */
 754         unsigned int pps_out_num;       /* Number of PPS outputs */
 755         unsigned int aux_snap_num;      /* Number of Aux snapshot inputs */
 756 };
 757
 758 struct xgbe_prv_data {
 759         struct net_device *netdev;
 760         struct platform_device *pdev;
 761         struct acpi_device *adev;
 762         struct device *dev;
 763
 764         /* ACPI or DT flag */
 765         unsigned int use_acpi;
 766
 767         /* XGMAC/XPCS related mmio registers */
 768         void __iomem *xgmac_regs;       /* XGMAC CSRs */
 769         void __iomem *xpcs_regs;        /* XPCS MMD registers */
 770         void __iomem *rxtx_regs;        /* SerDes Rx/Tx CSRs */
 771         void __iomem *sir0_regs;        /* SerDes integration registers (1/2) */
 772         void __iomem *sir1_regs;        /* SerDes integration registers (2/2) */
 773
 774         /* Overall device lock */
 775         spinlock_t lock;
 776
 777         /* XPCS indirect addressing lock */
 778         spinlock_t xpcs_lock;
 779
 780         /* RSS addressing mutex */
 781         struct mutex rss_mutex;
 782
 783         /* Flags representing xgbe_state */
 784         unsigned long dev_state;
 785
 786         int dev_irq;
 787         unsigned int per_channel_irq;
 788
 789         struct xgbe_hw_if hw_if;
 790         struct xgbe_phy_if phy_if;
 791         struct xgbe_desc_if desc_if;
 792
 793         /* AXI DMA settings */
 794         unsigned int coherent;
 795         unsigned int axdomain;
 796         unsigned int arcache;
 797         unsigned int awcache;
 798
 799         /* Service routine support */
 800         struct workqueue_struct *dev_workqueue;
 801         struct work_struct service_work;
 802         struct timer_list service_timer;
 803
 804         /* Rings for Tx/Rx on a DMA channel */
 805         struct xgbe_channel *channel;
 806         unsigned int channel_count;
 807         unsigned int tx_ring_count;
 808         unsigned int tx_desc_count;
 809         unsigned int rx_ring_count;
 810         unsigned int rx_desc_count;
 811
 812         unsigned int tx_q_count;
 813         unsigned int rx_q_count;
 814
 815         /* Tx/Rx common settings */
 816         unsigned int pblx8;
 817
 818         /* Tx settings */
 819         unsigned int tx_sf_mode;
 820         unsigned int tx_threshold;
 821         unsigned int tx_pbl;
 822         unsigned int tx_osp_mode;
 823
 824         /* Rx settings */
 825         unsigned int rx_sf_mode;
 826         unsigned int rx_threshold;
 827         unsigned int rx_pbl;
 828
 829         /* Tx coalescing settings */
 830         unsigned int tx_usecs;
 831         unsigned int tx_frames;
 832
 833         /* Rx coalescing settings */
 834         unsigned int rx_riwt;
 835         unsigned int rx_usecs;
 836         unsigned int rx_frames;
 837
 838         /* Current Rx buffer size */
 839         unsigned int rx_buf_size;
 840
 841         /* Flow control settings */
 842         unsigned int pause_autoneg;
 843         unsigned int tx_pause;
 844         unsigned int rx_pause;
 845
 846         /* Receive Side Scaling settings */
 847         u8 rss_key[XGBE_RSS_HASH_KEY_SIZE];
 848         u32 rss_table[XGBE_RSS_MAX_TABLE_SIZE];
 849         u32 rss_options;
 850
 851         /* Netdev related settings */
 852         unsigned char mac_addr[ETH_ALEN];
 853         netdev_features_t netdev_features;
 854         struct napi_struct napi;
 855         struct xgbe_mmc_stats mmc_stats;
 856         struct xgbe_ext_stats ext_stats;
 857
 858         /* Filtering support */
 859         unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
 860
 861         /* Device clocks */
 862         struct clk *sysclk;
 863         unsigned long sysclk_rate;
 864         struct clk *ptpclk;
 865         unsigned long ptpclk_rate;
 866
 867         /* Timestamp support */
 868         spinlock_t tstamp_lock;
 869         struct ptp_clock_info ptp_clock_info;
 870         struct ptp_clock *ptp_clock;
 871         struct hwtstamp_config tstamp_config;
 872         struct cyclecounter tstamp_cc;
 873         struct timecounter tstamp_tc;
 874         unsigned int tstamp_addend;
 875         struct work_struct tx_tstamp_work;
 876         struct sk_buff *tx_tstamp_skb;
 877         u64 tx_tstamp;
 878
 879         /* DCB support */
 880         struct ieee_ets *ets;
 881         struct ieee_pfc *pfc;
 882         unsigned int q2tc_map[XGBE_MAX_QUEUES];
 883         unsigned int prio2q_map[IEEE_8021QAZ_MAX_TCS];
 884         u8 num_tcs;
 885
 886         /* Hardware features of the device */
 887         struct xgbe_hw_features hw_feat;
 888
 889         /* Device restart work structure */
 890         struct work_struct restart_work;
 891
 892         /* Keeps track of power mode */
 893         unsigned int power_down;
 894
 895         /* Network interface message level setting */
 896         u32 msg_enable;
 897
 898         /* Current PHY settings */
 899         phy_interface_t phy_mode;
 900         int phy_link;
 901         int phy_speed;
 902
 903         /* MDIO/PHY related settings */
 904         struct xgbe_phy phy;
 905         int mdio_mmd;
 906         unsigned long link_check;
 907
 908         char an_name[IFNAMSIZ + 32];
 909         struct workqueue_struct *an_workqueue;
 910
 911         int an_irq;
 912         struct work_struct an_irq_work;
 913
 914         unsigned int speed_set;
 915
 916         /* SerDes UEFI configurable settings.
 917          *   Switching between modes/speeds requires new values for some
 918          *   SerDes settings.  The values can be supplied as device
 919          *   properties in array format.  The first array entry is for
 920          *   1GbE, second for 2.5GbE and third for 10GbE
 921          */
 922         u32 serdes_blwc[XGBE_SPEEDS];
 923         u32 serdes_cdr_rate[XGBE_SPEEDS];
 924         u32 serdes_pq_skew[XGBE_SPEEDS];
 925         u32 serdes_tx_amp[XGBE_SPEEDS];
 926         u32 serdes_dfe_tap_cfg[XGBE_SPEEDS];
 927         u32 serdes_dfe_tap_ena[XGBE_SPEEDS];
 928
 929         /* Auto-negotiation state machine support */
 930         unsigned int an_int;
 931         struct mutex an_mutex;
 932         enum xgbe_an an_result;
 933         enum xgbe_an an_state;
 934         enum xgbe_rx kr_state;
 935         enum xgbe_rx kx_state;
 936         struct work_struct an_work;
 937         unsigned int an_supported;
 938         unsigned int parallel_detect;
 939         unsigned int fec_ability;
 940         unsigned long an_start;
 941
 942         unsigned int lpm_ctrl;          /* CTRL1 for resume */
 943
 944 #ifdef CONFIG_DEBUG_FS
 945         struct dentry *xgbe_debugfs;
 946
 947         unsigned int debugfs_xgmac_reg;
 948
 949         unsigned int debugfs_xpcs_mmd;
 950         unsigned int debugfs_xpcs_reg;
 951 #endif
 952 };
 953
 954 /* Function prototypes*/
 955
 956 void xgbe_init_function_ptrs_dev(struct xgbe_hw_if *);
 957 void xgbe_init_function_ptrs_phy(struct xgbe_phy_if *);
 958 void xgbe_init_function_ptrs_desc(struct xgbe_desc_if *);
 959 struct net_device_ops *xgbe_get_netdev_ops(void);
 960 struct ethtool_ops *xgbe_get_ethtool_ops(void);
 961 #ifdef CONFIG_AMD_XGBE_DCB
 962 const struct dcbnl_rtnl_ops *xgbe_get_dcbnl_ops(void);
 963 #endif
 964
 965 void xgbe_ptp_register(struct xgbe_prv_data *);
 966 void xgbe_ptp_unregister(struct xgbe_prv_data *);
 967 void xgbe_dump_tx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
 968                        unsigned int, unsigned int, unsigned int);
 969 void xgbe_dump_rx_desc(struct xgbe_prv_data *, struct xgbe_ring *,
 970                        unsigned int);
 971 void xgbe_print_pkt(struct net_device *, struct sk_buff *, bool);
 972 void xgbe_get_all_hw_features(struct xgbe_prv_data *);
 973 int xgbe_powerup(struct net_device *, unsigned int);
 974 int xgbe_powerdown(struct net_device *, unsigned int);
 975 void xgbe_init_rx_coalesce(struct xgbe_prv_data *);
 976 void xgbe_init_tx_coalesce(struct xgbe_prv_data *);
 977
 978 #ifdef CONFIG_DEBUG_FS
 979 void xgbe_debugfs_init(struct xgbe_prv_data *);
 980 void xgbe_debugfs_exit(struct xgbe_prv_data *);
 981 #else
 982 static inline void xgbe_debugfs_init(struct xgbe_prv_data *pdata) {}
 983 static inline void xgbe_debugfs_exit(struct xgbe_prv_data *pdata) {}
 984 #endif /* CONFIG_DEBUG_FS */
 985
 986 /* NOTE: Uncomment for function trace log messages in KERNEL LOG */
 987 #if 0
 988 #define YDEBUG
 989 #define YDEBUG_MDIO
 990 #endif
 991
 992 /* For debug prints */
 993 #ifdef YDEBUG
 994 #define DBGPR(x...) pr_alert(x)
 995 #else
 996 #define DBGPR(x...) do { } while (0)
 997 #endif
 998
 999 #ifdef YDEBUG_MDIO
1000 #define DBGPR_MDIO(x...) pr_alert(x)
1001 #else
1002 #define DBGPR_MDIO(x...) do { } while (0)
1003 #endif
1004
1005 #endif