drivers/net/ethernet/ezchip/nps_enet.c

   1 /*
   2  * Copyright(c) 2015 EZchip Technologies.
   3  *
   4  * This program is free software; you can redistribute it and/or modify it
   5  * under the terms and conditions of the GNU General Public License,
   6  * version 2, as published by the Free Software Foundation.
   7  *
   8  * This program is distributed in the hope it will be useful, but WITHOUT
   9  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  11  * more details.
  12  *
  13  * The full GNU General Public License is included in this distribution in
  14  * the file called "COPYING".
  15  */
  16
  17 #include <linux/module.h>
  18 #include <linux/etherdevice.h>
  19 #include <linux/of_address.h>
  20 #include <linux/of_irq.h>
  21 #include <linux/of_net.h>
  22 #include <linux/of_platform.h>
  23 #include "nps_enet.h"
  24
  25 #define DRV_NAME                        "nps_mgt_enet"
  26
  27 static void nps_enet_clean_rx_fifo(struct net_device *ndev, u32 frame_len)
  28 {
  29         struct nps_enet_priv *priv = netdev_priv(ndev);
  30         u32 i, len = DIV_ROUND_UP(frame_len, sizeof(u32));
  31
  32         /* Empty Rx FIFO buffer by reading all words */
  33         for (i = 0; i < len; i++)
  34                 nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
  35 }
  36
  37 static void nps_enet_read_rx_fifo(struct net_device *ndev,
  38                                   unsigned char *dst, u32 length)
  39 {
  40         struct nps_enet_priv *priv = netdev_priv(ndev);
  41         s32 i, last = length & (sizeof(u32) - 1);
  42         u32 *reg = (u32 *)dst, len = length / sizeof(u32);
  43         bool dst_is_aligned = IS_ALIGNED((unsigned long)dst, sizeof(u32));
  44
  45         /* In case dst is not aligned we need an intermediate buffer */
  46         if (dst_is_aligned) {
  47                 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, reg, len);
  48                 reg += len;
  49         }
  50         else { /* !dst_is_aligned */
  51                 for (i = 0; i < len; i++, reg++) {
  52                         u32 buf = nps_enet_reg_get(priv, NPS_ENET_REG_RX_BUF);
  53                         put_unaligned_be32(buf, reg);
  54                 }
  55         }
  56         /* copy last bytes (if any) */
  57         if (last) {
  58                 u32 buf;
  59                 ioread32_rep(priv->regs_base + NPS_ENET_REG_RX_BUF, &buf, 1);
  60                 memcpy((u8 *)reg, &buf, last);
  61         }
  62 }
  63
  64 static u32 nps_enet_rx_handler(struct net_device *ndev)
  65 {
  66         u32 frame_len, err = 0;
  67         u32 work_done = 0;
  68         struct nps_enet_priv *priv = netdev_priv(ndev);
  69         struct sk_buff *skb;
  70         u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
  71         u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
  72         u32 rx_ctrl_er = (rx_ctrl_value & RX_CTL_ER_MASK) >> RX_CTL_ER_SHIFT;
  73         u32 rx_ctrl_crc = (rx_ctrl_value & RX_CTL_CRC_MASK) >> RX_CTL_CRC_SHIFT;
  74
  75         frame_len = (rx_ctrl_value & RX_CTL_NR_MASK) >> RX_CTL_NR_SHIFT;
  76
  77         /* Check if we got RX */
  78         if (!rx_ctrl_cr)
  79                 return work_done;
  80
  81         /* If we got here there is a work for us */
  82         work_done++;
  83
  84         /* Check Rx error */
  85         if (rx_ctrl_er) {
  86                 ndev->stats.rx_errors++;
  87                 err = 1;
  88         }
  89
  90         /* Check Rx CRC error */
  91         if (rx_ctrl_crc) {
  92                 ndev->stats.rx_crc_errors++;
  93                 ndev->stats.rx_dropped++;
  94                 err = 1;
  95         }
  96
  97         /* Check Frame length Min 64b */
  98         if (unlikely(frame_len < ETH_ZLEN)) {
  99                 ndev->stats.rx_length_errors++;
 100                 ndev->stats.rx_dropped++;
 101                 err = 1;
 102         }
 103
 104         if (err)
 105                 goto rx_irq_clean;
 106
 107         /* Skb allocation */
 108         skb = netdev_alloc_skb_ip_align(ndev, frame_len);
 109         if (unlikely(!skb)) {
 110                 ndev->stats.rx_errors++;
 111                 ndev->stats.rx_dropped++;
 112                 goto rx_irq_clean;
 113         }
 114
 115         /* Copy frame from Rx fifo into the skb */
 116         nps_enet_read_rx_fifo(ndev, skb->data, frame_len);
 117
 118         skb_put(skb, frame_len);
 119         skb->protocol = eth_type_trans(skb, ndev);
 120         skb->ip_summed = CHECKSUM_UNNECESSARY;
 121
 122         ndev->stats.rx_packets++;
 123         ndev->stats.rx_bytes += frame_len;
 124         netif_receive_skb(skb);
 125
 126         goto rx_irq_frame_done;
 127
 128 rx_irq_clean:
 129         /* Clean Rx fifo */
 130         nps_enet_clean_rx_fifo(ndev, frame_len);
 131
 132 rx_irq_frame_done:
 133         /* Ack Rx ctrl register */
 134         nps_enet_reg_set(priv, NPS_ENET_REG_RX_CTL, 0);
 135
 136         return work_done;
 137 }
 138
 139 static void nps_enet_tx_handler(struct net_device *ndev)
 140 {
 141         struct nps_enet_priv *priv = netdev_priv(ndev);
 142         u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
 143         u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
 144         u32 tx_ctrl_et = (tx_ctrl_value & TX_CTL_ET_MASK) >> TX_CTL_ET_SHIFT;
 145         u32 tx_ctrl_nt = (tx_ctrl_value & TX_CTL_NT_MASK) >> TX_CTL_NT_SHIFT;
 146
 147         /* Check if we got TX */
 148         if (!priv->tx_packet_sent || tx_ctrl_ct)
 149                 return;
 150
 151         /* Ack Tx ctrl register */
 152         nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, 0);
 153
 154         /* Check Tx transmit error */
 155         if (unlikely(tx_ctrl_et)) {
 156                 ndev->stats.tx_errors++;
 157         } else {
 158                 ndev->stats.tx_packets++;
 159                 ndev->stats.tx_bytes += tx_ctrl_nt;
 160         }
 161
 162         dev_kfree_skb(priv->tx_skb);
 163         priv->tx_packet_sent = false;
 164
 165         if (netif_queue_stopped(ndev))
 166                 netif_wake_queue(ndev);
 167 }
 168
 169 /**
 170  * nps_enet_poll - NAPI poll handler.
 171  * @napi:       Pointer to napi_struct structure.
 172  * @budget:     How many frames to process on one call.
 173  *
 174  * returns:     Number of processed frames
 175  */
 176 static int nps_enet_poll(struct napi_struct *napi, int budget)
 177 {
 178         struct net_device *ndev = napi->dev;
 179         struct nps_enet_priv *priv = netdev_priv(ndev);
 180         u32 work_done;
 181
 182         nps_enet_tx_handler(ndev);
 183         work_done = nps_enet_rx_handler(ndev);
 184         if (work_done < budget) {
 185                 u32 buf_int_enable_value = 0;
 186
 187                 napi_complete(napi);
 188
 189                 /* set tx_done and rx_rdy bits */
 190                 buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
 191                 buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
 192
 193                 nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
 194                                  buf_int_enable_value);
 195         }
 196
 197         return work_done;
 198 }
 199
 200 /**
 201  * nps_enet_irq_handler - Global interrupt handler for ENET.
 202  * @irq:                irq number.
 203  * @dev_instance:       device instance.
 204  *
 205  * returns: IRQ_HANDLED for all cases.
 206  *
 207  * EZchip ENET has 2 interrupt causes, and depending on bits raised in
 208  * CTRL registers we may tell what is a reason for interrupt to fire up.
 209  * We got one for RX and the other for TX (completion).
 210  */
 211 static irqreturn_t nps_enet_irq_handler(s32 irq, void *dev_instance)
 212 {
 213         struct net_device *ndev = dev_instance;
 214         struct nps_enet_priv *priv = netdev_priv(ndev);
 215         u32 rx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_RX_CTL);
 216         u32 tx_ctrl_value = nps_enet_reg_get(priv, NPS_ENET_REG_TX_CTL);
 217         u32 tx_ctrl_ct = (tx_ctrl_value & TX_CTL_CT_MASK) >> TX_CTL_CT_SHIFT;
 218         u32 rx_ctrl_cr = (rx_ctrl_value & RX_CTL_CR_MASK) >> RX_CTL_CR_SHIFT;
 219
 220         if ((!tx_ctrl_ct && priv->tx_packet_sent) || rx_ctrl_cr)
 221                 if (likely(napi_schedule_prep(&priv->napi))) {
 222                         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
 223                         __napi_schedule(&priv->napi);
 224                 }
 225
 226         return IRQ_HANDLED;
 227 }
 228
 229 static void nps_enet_set_hw_mac_address(struct net_device *ndev)
 230 {
 231         struct nps_enet_priv *priv = netdev_priv(ndev);
 232         u32 ge_mac_cfg_1_value = 0;
 233         u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
 234
 235         /* set MAC address in HW */
 236         ge_mac_cfg_1_value |= ndev->dev_addr[0] << CFG_1_OCTET_0_SHIFT;
 237         ge_mac_cfg_1_value |= ndev->dev_addr[1] << CFG_1_OCTET_1_SHIFT;
 238         ge_mac_cfg_1_value |= ndev->dev_addr[2] << CFG_1_OCTET_2_SHIFT;
 239         ge_mac_cfg_1_value |= ndev->dev_addr[3] << CFG_1_OCTET_3_SHIFT;
 240         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_4_MASK)
 241                  | ndev->dev_addr[4] << CFG_2_OCTET_4_SHIFT;
 242         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_OCTET_5_MASK)
 243                  | ndev->dev_addr[5] << CFG_2_OCTET_5_SHIFT;
 244
 245         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_1,
 246                          ge_mac_cfg_1_value);
 247
 248         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
 249                          *ge_mac_cfg_2_value);
 250 }
 251
 252 /**
 253  * nps_enet_hw_reset - Reset the network device.
 254  * @ndev:       Pointer to the network device.
 255  *
 256  * This function reset the PCS and TX fifo.
 257  * The programming model is to set the relevant reset bits
 258  * wait for some time for this to propagate and then unset
 259  * the reset bits. This way we ensure that reset procedure
 260  * is done successfully by device.
 261  */
 262 static void nps_enet_hw_reset(struct net_device *ndev)
 263 {
 264         struct nps_enet_priv *priv = netdev_priv(ndev);
 265         u32 ge_rst_value = 0, phase_fifo_ctl_value = 0;
 266
 267         /* Pcs reset sequence*/
 268         ge_rst_value |= NPS_ENET_ENABLE << RST_GMAC_0_SHIFT;
 269         nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
 270         usleep_range(10, 20);
 271         nps_enet_reg_set(priv, NPS_ENET_REG_GE_RST, ge_rst_value);
 272
 273         /* Tx fifo reset sequence */
 274         phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_RST_SHIFT;
 275         phase_fifo_ctl_value |= NPS_ENET_ENABLE << PHASE_FIFO_CTL_INIT_SHIFT;
 276         nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
 277                          phase_fifo_ctl_value);
 278         usleep_range(10, 20);
 279         phase_fifo_ctl_value = 0;
 280         nps_enet_reg_set(priv, NPS_ENET_REG_PHASE_FIFO_CTL,
 281                          phase_fifo_ctl_value);
 282 }
 283
 284 static void nps_enet_hw_enable_control(struct net_device *ndev)
 285 {
 286         struct nps_enet_priv *priv = netdev_priv(ndev);
 287         u32 ge_mac_cfg_0_value = 0, buf_int_enable_value = 0;
 288         u32 *ge_mac_cfg_2_value = &priv->ge_mac_cfg_2_value;
 289         u32 *ge_mac_cfg_3_value = &priv->ge_mac_cfg_3_value;
 290         s32 max_frame_length;
 291
 292         /* Enable Rx and Tx statistics */
 293         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_STAT_EN_MASK)
 294                  | NPS_ENET_GE_MAC_CFG_2_STAT_EN << CFG_2_STAT_EN_SHIFT;
 295
 296         /* Discard packets with different MAC address */
 297         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
 298                  | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
 299
 300         /* Discard multicast packets */
 301         *ge_mac_cfg_2_value = (*ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
 302                  | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
 303
 304         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2,
 305                          *ge_mac_cfg_2_value);
 306
 307         /* Discard Packets bigger than max frame length */
 308         max_frame_length = ETH_HLEN + ndev->mtu + ETH_FCS_LEN;
 309         if (max_frame_length <= NPS_ENET_MAX_FRAME_LENGTH) {
 310                 *ge_mac_cfg_3_value =
 311                          (*ge_mac_cfg_3_value & ~CFG_3_MAX_LEN_MASK)
 312                          | max_frame_length << CFG_3_MAX_LEN_SHIFT;
 313         }
 314
 315         /* Enable interrupts */
 316         buf_int_enable_value |= NPS_ENET_ENABLE << RX_RDY_SHIFT;
 317         buf_int_enable_value |= NPS_ENET_ENABLE << TX_DONE_SHIFT;
 318         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE,
 319                          buf_int_enable_value);
 320
 321         /* Write device MAC address to HW */
 322         nps_enet_set_hw_mac_address(ndev);
 323
 324         /* Rx and Tx HW features */
 325         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_PAD_EN_SHIFT;
 326         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_CRC_EN_SHIFT;
 327         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_CRC_STRIP_SHIFT;
 328
 329         /* IFG configuration */
 330         ge_mac_cfg_0_value |=
 331                  NPS_ENET_GE_MAC_CFG_0_RX_IFG << CFG_0_RX_IFG_SHIFT;
 332         ge_mac_cfg_0_value |=
 333                  NPS_ENET_GE_MAC_CFG_0_TX_IFG << CFG_0_TX_IFG_SHIFT;
 334
 335         /* preamble configuration */
 336         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_PR_CHECK_EN_SHIFT;
 337         ge_mac_cfg_0_value |=
 338                  NPS_ENET_GE_MAC_CFG_0_TX_PR_LEN << CFG_0_TX_PR_LEN_SHIFT;
 339
 340         /* enable flow control frames */
 341         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_FC_EN_SHIFT;
 342         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_FC_EN_SHIFT;
 343         ge_mac_cfg_0_value |=
 344                  NPS_ENET_GE_MAC_CFG_0_TX_FC_RETR << CFG_0_TX_FC_RETR_SHIFT;
 345         *ge_mac_cfg_3_value = (*ge_mac_cfg_3_value & ~CFG_3_CF_DROP_MASK)
 346                  | NPS_ENET_ENABLE << CFG_3_CF_DROP_SHIFT;
 347
 348         /* Enable Rx and Tx */
 349         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_RX_EN_SHIFT;
 350         ge_mac_cfg_0_value |= NPS_ENET_ENABLE << CFG_0_TX_EN_SHIFT;
 351
 352         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_3,
 353                          *ge_mac_cfg_3_value);
 354         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0,
 355                          ge_mac_cfg_0_value);
 356 }
 357
 358 static void nps_enet_hw_disable_control(struct net_device *ndev)
 359 {
 360         struct nps_enet_priv *priv = netdev_priv(ndev);
 361
 362         /* Disable interrupts */
 363         nps_enet_reg_set(priv, NPS_ENET_REG_BUF_INT_ENABLE, 0);
 364
 365         /* Disable Rx and Tx */
 366         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_0, 0);
 367 }
 368
 369 static void nps_enet_send_frame(struct net_device *ndev,
 370                                 struct sk_buff *skb)
 371 {
 372         struct nps_enet_priv *priv = netdev_priv(ndev);
 373         u32 tx_ctrl_value = 0;
 374         short length = skb->len;
 375         u32 i, len = DIV_ROUND_UP(length, sizeof(u32));
 376         u32 *src = (void *)skb->data;
 377         bool src_is_aligned = IS_ALIGNED((unsigned long)src, sizeof(u32));
 378
 379         /* In case src is not aligned we need an intermediate buffer */
 380         if (src_is_aligned)
 381                 iowrite32_rep(priv->regs_base + NPS_ENET_REG_TX_BUF, src, len);
 382         else /* !src_is_aligned */
 383                 for (i = 0; i < len; i++, src++)
 384                         nps_enet_reg_set(priv, NPS_ENET_REG_TX_BUF,
 385                                          get_unaligned_be32(src));
 386
 387         /* Write the length of the Frame */
 388         tx_ctrl_value |= length << TX_CTL_NT_SHIFT;
 389
 390         /* Indicate SW is done */
 391         priv->tx_packet_sent = true;
 392         tx_ctrl_value |= NPS_ENET_ENABLE << TX_CTL_CT_SHIFT;
 393         /* Send Frame */
 394         nps_enet_reg_set(priv, NPS_ENET_REG_TX_CTL, tx_ctrl_value);
 395 }
 396
 397 /**
 398  * nps_enet_set_mac_address - Set the MAC address for this device.
 399  * @ndev:       Pointer to net_device structure.
 400  * @p:          6 byte Address to be written as MAC address.
 401  *
 402  * This function copies the HW address from the sockaddr structure to the
 403  * net_device structure and updates the address in HW.
 404  *
 405  * returns:     -EBUSY if the net device is busy or 0 if the address is set
 406  *              successfully.
 407  */
 408 static s32 nps_enet_set_mac_address(struct net_device *ndev, void *p)
 409 {
 410         struct sockaddr *addr = p;
 411         s32 res;
 412
 413         if (netif_running(ndev))
 414                 return -EBUSY;
 415
 416         res = eth_mac_addr(ndev, p);
 417         if (!res) {
 418                 ether_addr_copy(ndev->dev_addr, addr->sa_data);
 419                 nps_enet_set_hw_mac_address(ndev);
 420         }
 421
 422         return res;
 423 }
 424
 425 /**
 426  * nps_enet_set_rx_mode - Change the receive filtering mode.
 427  * @ndev:       Pointer to the network device.
 428  *
 429  * This function enables/disables promiscuous mode
 430  */
 431 static void nps_enet_set_rx_mode(struct net_device *ndev)
 432 {
 433         struct nps_enet_priv *priv = netdev_priv(ndev);
 434         u32 ge_mac_cfg_2_value = priv->ge_mac_cfg_2_value;
 435
 436         if (ndev->flags & IFF_PROMISC) {
 437                 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
 438                          | NPS_ENET_DISABLE << CFG_2_DISK_DA_SHIFT;
 439                 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
 440                          | NPS_ENET_DISABLE << CFG_2_DISK_MC_SHIFT;
 441
 442         } else {
 443                 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_DA_MASK)
 444                          | NPS_ENET_ENABLE << CFG_2_DISK_DA_SHIFT;
 445                 ge_mac_cfg_2_value = (ge_mac_cfg_2_value & ~CFG_2_DISK_MC_MASK)
 446                          | NPS_ENET_ENABLE << CFG_2_DISK_MC_SHIFT;
 447
 448         }
 449
 450         nps_enet_reg_set(priv, NPS_ENET_REG_GE_MAC_CFG_2, ge_mac_cfg_2_value);
 451 }
 452
 453 /**
 454  * nps_enet_open - Open the network device.
 455  * @ndev:       Pointer to the network device.
 456  *
 457  * returns: 0, on success or non-zero error value on failure.
 458  *
 459  * This function sets the MAC address, requests and enables an IRQ
 460  * for the ENET device and starts the Tx queue.
 461  */
 462 static s32 nps_enet_open(struct net_device *ndev)
 463 {
 464         struct nps_enet_priv *priv = netdev_priv(ndev);
 465         s32 err;
 466
 467         /* Reset private variables */
 468         priv->tx_packet_sent = false;
 469         priv->ge_mac_cfg_2_value = 0;
 470         priv->ge_mac_cfg_3_value = 0;
 471
 472         /* ge_mac_cfg_3 default values */
 473         priv->ge_mac_cfg_3_value |=
 474                  NPS_ENET_GE_MAC_CFG_3_RX_IFG_TH << CFG_3_RX_IFG_TH_SHIFT;
 475
 476         priv->ge_mac_cfg_3_value |=
 477                  NPS_ENET_GE_MAC_CFG_3_MAX_LEN << CFG_3_MAX_LEN_SHIFT;
 478
 479         /* Disable HW device */
 480         nps_enet_hw_disable_control(ndev);
 481
 482         /* irq Rx allocation */
 483         err = request_irq(priv->irq, nps_enet_irq_handler,
 484                           0, "enet-rx-tx", ndev);
 485         if (err)
 486                 return err;
 487
 488         napi_enable(&priv->napi);
 489
 490         /* Enable HW device */
 491         nps_enet_hw_reset(ndev);
 492         nps_enet_hw_enable_control(ndev);
 493
 494         netif_start_queue(ndev);
 495
 496         return 0;
 497 }
 498
 499 /**
 500  * nps_enet_stop - Close the network device.
 501  * @ndev:       Pointer to the network device.
 502  *
 503  * This function stops the Tx queue, disables interrupts for the ENET device.
 504  */
 505 static s32 nps_enet_stop(struct net_device *ndev)
 506 {
 507         struct nps_enet_priv *priv = netdev_priv(ndev);
 508
 509         napi_disable(&priv->napi);
 510         netif_stop_queue(ndev);
 511         nps_enet_hw_disable_control(ndev);
 512         free_irq(priv->irq, ndev);
 513
 514         return 0;
 515 }
 516
 517 /**
 518  * nps_enet_start_xmit - Starts the data transmission.
 519  * @skb:        sk_buff pointer that contains data to be Transmitted.
 520  * @ndev:       Pointer to net_device structure.
 521  *
 522  * returns: NETDEV_TX_OK, on success
 523  *              NETDEV_TX_BUSY, if any of the descriptors are not free.
 524  *
 525  * This function is invoked from upper layers to initiate transmission.
 526  */
 527 static netdev_tx_t nps_enet_start_xmit(struct sk_buff *skb,
 528                                        struct net_device *ndev)
 529 {
 530         struct nps_enet_priv *priv = netdev_priv(ndev);
 531
 532         /* This driver handles one frame at a time  */
 533         netif_stop_queue(ndev);
 534
 535         priv->tx_skb = skb;
 536
 537         nps_enet_send_frame(ndev, skb);
 538
 539         return NETDEV_TX_OK;
 540 }
 541
 542 #ifdef CONFIG_NET_POLL_CONTROLLER
 543 static void nps_enet_poll_controller(struct net_device *ndev)
 544 {
 545         disable_irq(ndev->irq);
 546         nps_enet_irq_handler(ndev->irq, ndev);
 547         enable_irq(ndev->irq);
 548 }
 549 #endif
 550
 551 static const struct net_device_ops nps_netdev_ops = {
 552         .ndo_open               = nps_enet_open,
 553         .ndo_stop               = nps_enet_stop,
 554         .ndo_start_xmit         = nps_enet_start_xmit,
 555         .ndo_set_mac_address    = nps_enet_set_mac_address,
 556         .ndo_set_rx_mode        = nps_enet_set_rx_mode,
 557 #ifdef CONFIG_NET_POLL_CONTROLLER
 558         .ndo_poll_controller    = nps_enet_poll_controller,
 559 #endif
 560 };
 561
 562 static s32 nps_enet_probe(struct platform_device *pdev)
 563 {
 564         struct device *dev = &pdev->dev;
 565         struct net_device *ndev;
 566         struct nps_enet_priv *priv;
 567         s32 err = 0;
 568         const char *mac_addr;
 569         struct resource *res_regs;
 570
 571         if (!dev->of_node)
 572                 return -ENODEV;
 573
 574         ndev = alloc_etherdev(sizeof(struct nps_enet_priv));
 575         if (!ndev)
 576                 return -ENOMEM;
 577
 578         platform_set_drvdata(pdev, ndev);
 579         SET_NETDEV_DEV(ndev, dev);
 580         priv = netdev_priv(ndev);
 581
 582         /* The EZ NET specific entries in the device structure. */
 583         ndev->netdev_ops = &nps_netdev_ops;
 584         ndev->watchdog_timeo = (400 * HZ / 1000);
 585         /* FIXME :: no multicast support yet */
 586         ndev->flags &= ~IFF_MULTICAST;
 587
 588         res_regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 589         priv->regs_base = devm_ioremap_resource(dev, res_regs);
 590         if (IS_ERR(priv->regs_base)) {
 591                 err = PTR_ERR(priv->regs_base);
 592                 goto out_netdev;
 593         }
 594         dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs_base);
 595
 596         /* set kernel MAC address to dev */
 597         mac_addr = of_get_mac_address(dev->of_node);
 598         if (mac_addr)
 599                 ether_addr_copy(ndev->dev_addr, mac_addr);
 600         else
 601                 eth_hw_addr_random(ndev);
 602
 603         /* Get IRQ number */
 604         priv->irq = platform_get_irq(pdev, 0);
 605         if (!priv->irq) {
 606                 dev_err(dev, "failed to retrieve <irq Rx-Tx> value from device tree\n");
 607                 err = -ENODEV;
 608                 goto out_netdev;
 609         }
 610
 611         netif_napi_add(ndev, &priv->napi, nps_enet_poll,
 612                        NPS_ENET_NAPI_POLL_WEIGHT);
 613
 614         /* Register the driver. Should be the last thing in probe */
 615         err = register_netdev(ndev);
 616         if (err) {
 617                 dev_err(dev, "Failed to register ndev for %s, err = 0x%08x\n",
 618                         ndev->name, (s32)err);
 619                 goto out_netif_api;
 620         }
 621
 622         dev_info(dev, "(rx/tx=%d)\n", priv->irq);
 623         return 0;
 624
 625 out_netif_api:
 626         netif_napi_del(&priv->napi);
 627 out_netdev:
 628         if (err)
 629                 free_netdev(ndev);
 630
 631         return err;
 632 }
 633
 634 static s32 nps_enet_remove(struct platform_device *pdev)
 635 {
 636         struct net_device *ndev = platform_get_drvdata(pdev);
 637         struct nps_enet_priv *priv = netdev_priv(ndev);
 638
 639         unregister_netdev(ndev);
 640         free_netdev(ndev);
 641         netif_napi_del(&priv->napi);
 642
 643         return 0;
 644 }
 645
 646 static const struct of_device_id nps_enet_dt_ids[] = {
 647         { .compatible = "ezchip,nps-mgt-enet" },
 648         { /* Sentinel */ }
 649 };
 650
 651 static struct platform_driver nps_enet_driver = {
 652         .probe = nps_enet_probe,
 653         .remove = nps_enet_remove,
 654         .driver = {
 655                 .name = DRV_NAME,
 656                 .of_match_table  = nps_enet_dt_ids,
 657         },
 658 };
 659
 660 module_platform_driver(nps_enet_driver);
 661
 662 MODULE_AUTHOR("EZchip Semiconductor");
 663 MODULE_LICENSE("GPL v2");