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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / net / ethernet / intel / i40evf / i40e_adminq_cmd.h
blobaad8d62771102e090fcdf22fae68722306c4f2d7
1 /*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
4 * Copyright(c) 2013 - 2016 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
15 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
18 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27 #ifndef _I40E_ADMINQ_CMD_H_
28 #define _I40E_ADMINQ_CMD_H_
29
30 /* This header file defines the i40e Admin Queue commands and is shared between
31 * i40e Firmware and Software.
32 *
33 * This file needs to comply with the Linux Kernel coding style.
34 */
35
36 #define I40E_FW_API_VERSION_MAJOR 0x0001
37 #define I40E_FW_API_VERSION_MINOR 0x0005
38
39 struct i40e_aq_desc {
40 __le16 flags;
41 __le16 opcode;
42 __le16 datalen;
43 __le16 retval;
44 __le32 cookie_high;
45 __le32 cookie_low;
46 union {
47 struct {
48 __le32 param0;
49 __le32 param1;
50 __le32 param2;
51 __le32 param3;
52 } internal;
53 struct {
54 __le32 param0;
55 __le32 param1;
56 __le32 addr_high;
57 __le32 addr_low;
58 } external;
59 u8 raw[16];
60 } params;
61 };
62
63 /* Flags sub-structure
64 * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 |
65 * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
66 */
67
68 /* command flags and offsets*/
69 #define I40E_AQ_FLAG_DD_SHIFT 0
70 #define I40E_AQ_FLAG_CMP_SHIFT 1
71 #define I40E_AQ_FLAG_ERR_SHIFT 2
72 #define I40E_AQ_FLAG_VFE_SHIFT 3
73 #define I40E_AQ_FLAG_LB_SHIFT 9
74 #define I40E_AQ_FLAG_RD_SHIFT 10
75 #define I40E_AQ_FLAG_VFC_SHIFT 11
76 #define I40E_AQ_FLAG_BUF_SHIFT 12
77 #define I40E_AQ_FLAG_SI_SHIFT 13
78 #define I40E_AQ_FLAG_EI_SHIFT 14
79 #define I40E_AQ_FLAG_FE_SHIFT 15
80
81 #define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */
82 #define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */
83 #define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */
84 #define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */
85 #define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */
86 #define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */
87 #define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */
88 #define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
89 #define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */
90 #define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */
91 #define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */
92
93 /* error codes */
94 enum i40e_admin_queue_err {
95 I40E_AQ_RC_OK = 0, /* success */
96 I40E_AQ_RC_EPERM = 1, /* Operation not permitted */
97 I40E_AQ_RC_ENOENT = 2, /* No such element */
98 I40E_AQ_RC_ESRCH = 3, /* Bad opcode */
99 I40E_AQ_RC_EINTR = 4, /* operation interrupted */
100 I40E_AQ_RC_EIO = 5, /* I/O error */
101 I40E_AQ_RC_ENXIO = 6, /* No such resource */
102 I40E_AQ_RC_E2BIG = 7, /* Arg too long */
103 I40E_AQ_RC_EAGAIN = 8, /* Try again */
104 I40E_AQ_RC_ENOMEM = 9, /* Out of memory */
105 I40E_AQ_RC_EACCES = 10, /* Permission denied */
106 I40E_AQ_RC_EFAULT = 11, /* Bad address */
107 I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */
108 I40E_AQ_RC_EEXIST = 13, /* object already exists */
109 I40E_AQ_RC_EINVAL = 14, /* Invalid argument */
110 I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */
111 I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */
112 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */
113 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */
114 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */
115 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */
116 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */
117 I40E_AQ_RC_EFBIG = 22, /* File too large */
118 };
119
120 /* Admin Queue command opcodes */
121 enum i40e_admin_queue_opc {
122 /* aq commands */
123 i40e_aqc_opc_get_version = 0x0001,
124 i40e_aqc_opc_driver_version = 0x0002,
125 i40e_aqc_opc_queue_shutdown = 0x0003,
126 i40e_aqc_opc_set_pf_context = 0x0004,
127
128 /* resource ownership */
129 i40e_aqc_opc_request_resource = 0x0008,
130 i40e_aqc_opc_release_resource = 0x0009,
131
132 i40e_aqc_opc_list_func_capabilities = 0x000A,
133 i40e_aqc_opc_list_dev_capabilities = 0x000B,
134
135 /* LAA */
136 i40e_aqc_opc_mac_address_read = 0x0107,
137 i40e_aqc_opc_mac_address_write = 0x0108,
138
139 /* PXE */
140 i40e_aqc_opc_clear_pxe_mode = 0x0110,
141
142 /* internal switch commands */
143 i40e_aqc_opc_get_switch_config = 0x0200,
144 i40e_aqc_opc_add_statistics = 0x0201,
145 i40e_aqc_opc_remove_statistics = 0x0202,
146 i40e_aqc_opc_set_port_parameters = 0x0203,
147 i40e_aqc_opc_get_switch_resource_alloc = 0x0204,
148 i40e_aqc_opc_set_switch_config = 0x0205,
149 i40e_aqc_opc_rx_ctl_reg_read = 0x0206,
150 i40e_aqc_opc_rx_ctl_reg_write = 0x0207,
151
152 i40e_aqc_opc_add_vsi = 0x0210,
153 i40e_aqc_opc_update_vsi_parameters = 0x0211,
154 i40e_aqc_opc_get_vsi_parameters = 0x0212,
155
156 i40e_aqc_opc_add_pv = 0x0220,
157 i40e_aqc_opc_update_pv_parameters = 0x0221,
158 i40e_aqc_opc_get_pv_parameters = 0x0222,
159
160 i40e_aqc_opc_add_veb = 0x0230,
161 i40e_aqc_opc_update_veb_parameters = 0x0231,
162 i40e_aqc_opc_get_veb_parameters = 0x0232,
163
164 i40e_aqc_opc_delete_element = 0x0243,
165
166 i40e_aqc_opc_add_macvlan = 0x0250,
167 i40e_aqc_opc_remove_macvlan = 0x0251,
168 i40e_aqc_opc_add_vlan = 0x0252,
169 i40e_aqc_opc_remove_vlan = 0x0253,
170 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254,
171 i40e_aqc_opc_add_tag = 0x0255,
172 i40e_aqc_opc_remove_tag = 0x0256,
173 i40e_aqc_opc_add_multicast_etag = 0x0257,
174 i40e_aqc_opc_remove_multicast_etag = 0x0258,
175 i40e_aqc_opc_update_tag = 0x0259,
176 i40e_aqc_opc_add_control_packet_filter = 0x025A,
177 i40e_aqc_opc_remove_control_packet_filter = 0x025B,
178 i40e_aqc_opc_add_cloud_filters = 0x025C,
179 i40e_aqc_opc_remove_cloud_filters = 0x025D,
180
181 i40e_aqc_opc_add_mirror_rule = 0x0260,
182 i40e_aqc_opc_delete_mirror_rule = 0x0261,
183
184 /* DCB commands */
185 i40e_aqc_opc_dcb_ignore_pfc = 0x0301,
186 i40e_aqc_opc_dcb_updated = 0x0302,
187
188 /* TX scheduler */
189 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400,
190 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406,
191 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407,
192 i40e_aqc_opc_query_vsi_bw_config = 0x0408,
193 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A,
194 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410,
195
196 i40e_aqc_opc_enable_switching_comp_ets = 0x0413,
197 i40e_aqc_opc_modify_switching_comp_ets = 0x0414,
198 i40e_aqc_opc_disable_switching_comp_ets = 0x0415,
199 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416,
200 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417,
201 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418,
202 i40e_aqc_opc_query_port_ets_config = 0x0419,
203 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A,
204 i40e_aqc_opc_suspend_port_tx = 0x041B,
205 i40e_aqc_opc_resume_port_tx = 0x041C,
206 i40e_aqc_opc_configure_partition_bw = 0x041D,
207
208 /* hmc */
209 i40e_aqc_opc_query_hmc_resource_profile = 0x0500,
210 i40e_aqc_opc_set_hmc_resource_profile = 0x0501,
211
212 /* phy commands*/
213 i40e_aqc_opc_get_phy_abilities = 0x0600,
214 i40e_aqc_opc_set_phy_config = 0x0601,
215 i40e_aqc_opc_set_mac_config = 0x0603,
216 i40e_aqc_opc_set_link_restart_an = 0x0605,
217 i40e_aqc_opc_get_link_status = 0x0607,
218 i40e_aqc_opc_set_phy_int_mask = 0x0613,
219 i40e_aqc_opc_get_local_advt_reg = 0x0614,
220 i40e_aqc_opc_set_local_advt_reg = 0x0615,
221 i40e_aqc_opc_get_partner_advt = 0x0616,
222 i40e_aqc_opc_set_lb_modes = 0x0618,
223 i40e_aqc_opc_get_phy_wol_caps = 0x0621,
224 i40e_aqc_opc_set_phy_debug = 0x0622,
225 i40e_aqc_opc_upload_ext_phy_fm = 0x0625,
226 i40e_aqc_opc_run_phy_activity = 0x0626,
227
228 /* NVM commands */
229 i40e_aqc_opc_nvm_read = 0x0701,
230 i40e_aqc_opc_nvm_erase = 0x0702,
231 i40e_aqc_opc_nvm_update = 0x0703,
232 i40e_aqc_opc_nvm_config_read = 0x0704,
233 i40e_aqc_opc_nvm_config_write = 0x0705,
234 i40e_aqc_opc_oem_post_update = 0x0720,
235 i40e_aqc_opc_thermal_sensor = 0x0721,
236
237 /* virtualization commands */
238 i40e_aqc_opc_send_msg_to_pf = 0x0801,
239 i40e_aqc_opc_send_msg_to_vf = 0x0802,
240 i40e_aqc_opc_send_msg_to_peer = 0x0803,
241
242 /* alternate structure */
243 i40e_aqc_opc_alternate_write = 0x0900,
244 i40e_aqc_opc_alternate_write_indirect = 0x0901,
245 i40e_aqc_opc_alternate_read = 0x0902,
246 i40e_aqc_opc_alternate_read_indirect = 0x0903,
247 i40e_aqc_opc_alternate_write_done = 0x0904,
248 i40e_aqc_opc_alternate_set_mode = 0x0905,
249 i40e_aqc_opc_alternate_clear_port = 0x0906,
250
251 /* LLDP commands */
252 i40e_aqc_opc_lldp_get_mib = 0x0A00,
253 i40e_aqc_opc_lldp_update_mib = 0x0A01,
254 i40e_aqc_opc_lldp_add_tlv = 0x0A02,
255 i40e_aqc_opc_lldp_update_tlv = 0x0A03,
256 i40e_aqc_opc_lldp_delete_tlv = 0x0A04,
257 i40e_aqc_opc_lldp_stop = 0x0A05,
258 i40e_aqc_opc_lldp_start = 0x0A06,
259
260 /* Tunnel commands */
261 i40e_aqc_opc_add_udp_tunnel = 0x0B00,
262 i40e_aqc_opc_del_udp_tunnel = 0x0B01,
263 i40e_aqc_opc_set_rss_key = 0x0B02,
264 i40e_aqc_opc_set_rss_lut = 0x0B03,
265 i40e_aqc_opc_get_rss_key = 0x0B04,
266 i40e_aqc_opc_get_rss_lut = 0x0B05,
267
268 /* Async Events */
269 i40e_aqc_opc_event_lan_overflow = 0x1001,
270
271 /* OEM commands */
272 i40e_aqc_opc_oem_parameter_change = 0xFE00,
273 i40e_aqc_opc_oem_device_status_change = 0xFE01,
274 i40e_aqc_opc_oem_ocsd_initialize = 0xFE02,
275 i40e_aqc_opc_oem_ocbb_initialize = 0xFE03,
276
277 /* debug commands */
278 i40e_aqc_opc_debug_read_reg = 0xFF03,
279 i40e_aqc_opc_debug_write_reg = 0xFF04,
280 i40e_aqc_opc_debug_modify_reg = 0xFF07,
281 i40e_aqc_opc_debug_dump_internals = 0xFF08,
282 };
283
284 /* command structures and indirect data structures */
285
286 /* Structure naming conventions:
287 * - no suffix for direct command descriptor structures
288 * - _data for indirect sent data
289 * - _resp for indirect return data (data which is both will use _data)
290 * - _completion for direct return data
291 * - _element_ for repeated elements (may also be _data or _resp)
292 *
293 * Command structures are expected to overlay the params.raw member of the basic
294 * descriptor, and as such cannot exceed 16 bytes in length.
295 */
296
297 /* This macro is used to generate a compilation error if a structure
298 * is not exactly the correct length. It gives a divide by zero error if the
299 * structure is not of the correct size, otherwise it creates an enum that is
300 * never used.
301 */
302 #define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \
303 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
304
305 /* This macro is used extensively to ensure that command structures are 16
306 * bytes in length as they have to map to the raw array of that size.
307 */
308 #define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X)
309
310 /* internal (0x00XX) commands */
311
312 /* Get version (direct 0x0001) */
313 struct i40e_aqc_get_version {
314 __le32 rom_ver;
315 __le32 fw_build;
316 __le16 fw_major;
317 __le16 fw_minor;
318 __le16 api_major;
319 __le16 api_minor;
320 };
321
322 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version);
323
324 /* Send driver version (indirect 0x0002) */
325 struct i40e_aqc_driver_version {
326 u8 driver_major_ver;
327 u8 driver_minor_ver;
328 u8 driver_build_ver;
329 u8 driver_subbuild_ver;
330 u8 reserved[4];
331 __le32 address_high;
332 __le32 address_low;
333 };
334
335 I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version);
336
337 /* Queue Shutdown (direct 0x0003) */
338 struct i40e_aqc_queue_shutdown {
339 __le32 driver_unloading;
340 #define I40E_AQ_DRIVER_UNLOADING 0x1
341 u8 reserved[12];
342 };
343
344 I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown);
345
346 /* Set PF context (0x0004, direct) */
347 struct i40e_aqc_set_pf_context {
348 u8 pf_id;
349 u8 reserved[15];
350 };
351
352 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context);
353
354 /* Request resource ownership (direct 0x0008)
355 * Release resource ownership (direct 0x0009)
356 */
357 #define I40E_AQ_RESOURCE_NVM 1
358 #define I40E_AQ_RESOURCE_SDP 2
359 #define I40E_AQ_RESOURCE_ACCESS_READ 1
360 #define I40E_AQ_RESOURCE_ACCESS_WRITE 2
361 #define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000
362 #define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000
363
364 struct i40e_aqc_request_resource {
365 __le16 resource_id;
366 __le16 access_type;
367 __le32 timeout;
368 __le32 resource_number;
369 u8 reserved[4];
370 };
371
372 I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource);
373
374 /* Get function capabilities (indirect 0x000A)
375 * Get device capabilities (indirect 0x000B)
376 */
377 struct i40e_aqc_list_capabilites {
378 u8 command_flags;
379 #define I40E_AQ_LIST_CAP_PF_INDEX_EN 1
380 u8 pf_index;
381 u8 reserved[2];
382 __le32 count;
383 __le32 addr_high;
384 __le32 addr_low;
385 };
386
387 I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites);
388
389 struct i40e_aqc_list_capabilities_element_resp {
390 __le16 id;
391 u8 major_rev;
392 u8 minor_rev;
393 __le32 number;
394 __le32 logical_id;
395 __le32 phys_id;
396 u8 reserved[16];
397 };
398
399 /* list of caps */
400
401 #define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001
402 #define I40E_AQ_CAP_ID_MNG_MODE 0x0002
403 #define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003
404 #define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004
405 #define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005
406 #define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006
407 #define I40E_AQ_CAP_ID_WOL_AND_PROXY 0x0008
408 #define I40E_AQ_CAP_ID_SRIOV 0x0012
409 #define I40E_AQ_CAP_ID_VF 0x0013
410 #define I40E_AQ_CAP_ID_VMDQ 0x0014
411 #define I40E_AQ_CAP_ID_8021QBG 0x0015
412 #define I40E_AQ_CAP_ID_8021QBR 0x0016
413 #define I40E_AQ_CAP_ID_VSI 0x0017
414 #define I40E_AQ_CAP_ID_DCB 0x0018
415 #define I40E_AQ_CAP_ID_FCOE 0x0021
416 #define I40E_AQ_CAP_ID_ISCSI 0x0022
417 #define I40E_AQ_CAP_ID_RSS 0x0040
418 #define I40E_AQ_CAP_ID_RXQ 0x0041
419 #define I40E_AQ_CAP_ID_TXQ 0x0042
420 #define I40E_AQ_CAP_ID_MSIX 0x0043
421 #define I40E_AQ_CAP_ID_VF_MSIX 0x0044
422 #define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045
423 #define I40E_AQ_CAP_ID_1588 0x0046
424 #define I40E_AQ_CAP_ID_IWARP 0x0051
425 #define I40E_AQ_CAP_ID_LED 0x0061
426 #define I40E_AQ_CAP_ID_SDP 0x0062
427 #define I40E_AQ_CAP_ID_MDIO 0x0063
428 #define I40E_AQ_CAP_ID_WSR_PROT 0x0064
429 #define I40E_AQ_CAP_ID_FLEX10 0x00F1
430 #define I40E_AQ_CAP_ID_CEM 0x00F2
431
432 /* Set CPPM Configuration (direct 0x0103) */
433 struct i40e_aqc_cppm_configuration {
434 __le16 command_flags;
435 #define I40E_AQ_CPPM_EN_LTRC 0x0800
436 #define I40E_AQ_CPPM_EN_DMCTH 0x1000
437 #define I40E_AQ_CPPM_EN_DMCTLX 0x2000
438 #define I40E_AQ_CPPM_EN_HPTC 0x4000
439 #define I40E_AQ_CPPM_EN_DMARC 0x8000
440 __le16 ttlx;
441 __le32 dmacr;
442 __le16 dmcth;
443 u8 hptc;
444 u8 reserved;
445 __le32 pfltrc;
446 };
447
448 I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration);
449
450 /* Set ARP Proxy command / response (indirect 0x0104) */
451 struct i40e_aqc_arp_proxy_data {
452 __le16 command_flags;
453 #define I40E_AQ_ARP_INIT_IPV4 0x0008
454 #define I40E_AQ_ARP_UNSUP_CTL 0x0010
455 #define I40E_AQ_ARP_ENA 0x0020
456 #define I40E_AQ_ARP_ADD_IPV4 0x0040
457 #define I40E_AQ_ARP_DEL_IPV4 0x0080
458 __le16 table_id;
459 __le32 pfpm_proxyfc;
460 __le32 ip_addr;
461 u8 mac_addr[6];
462 u8 reserved[2];
463 };
464
465 I40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data);
466
467 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
468 struct i40e_aqc_ns_proxy_data {
469 __le16 table_idx_mac_addr_0;
470 __le16 table_idx_mac_addr_1;
471 __le16 table_idx_ipv6_0;
472 __le16 table_idx_ipv6_1;
473 __le16 control;
474 #define I40E_AQ_NS_PROXY_ADD_0 0x0100
475 #define I40E_AQ_NS_PROXY_DEL_0 0x0200
476 #define I40E_AQ_NS_PROXY_ADD_1 0x0400
477 #define I40E_AQ_NS_PROXY_DEL_1 0x0800
478 #define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000
479 #define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000
480 #define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000
481 #define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000
482 #define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001
483 #define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002
484 #define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004
485 u8 mac_addr_0[6];
486 u8 mac_addr_1[6];
487 u8 local_mac_addr[6];
488 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
489 u8 ipv6_addr_1[16];
490 };
491
492 I40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data);
493
494 /* Manage LAA Command (0x0106) - obsolete */
495 struct i40e_aqc_mng_laa {
496 __le16 command_flags;
497 #define I40E_AQ_LAA_FLAG_WR 0x8000
498 u8 reserved[2];
499 __le32 sal;
500 __le16 sah;
501 u8 reserved2[6];
502 };
503
504 I40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa);
505
506 /* Manage MAC Address Read Command (indirect 0x0107) */
507 struct i40e_aqc_mac_address_read {
508 __le16 command_flags;
509 #define I40E_AQC_LAN_ADDR_VALID 0x10
510 #define I40E_AQC_SAN_ADDR_VALID 0x20
511 #define I40E_AQC_PORT_ADDR_VALID 0x40
512 #define I40E_AQC_WOL_ADDR_VALID 0x80
513 #define I40E_AQC_MC_MAG_EN_VALID 0x100
514 #define I40E_AQC_ADDR_VALID_MASK 0x1F0
515 u8 reserved[6];
516 __le32 addr_high;
517 __le32 addr_low;
518 };
519
520 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read);
521
522 struct i40e_aqc_mac_address_read_data {
523 u8 pf_lan_mac[6];
524 u8 pf_san_mac[6];
525 u8 port_mac[6];
526 u8 pf_wol_mac[6];
527 };
528
529 I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data);
530
531 /* Manage MAC Address Write Command (0x0108) */
532 struct i40e_aqc_mac_address_write {
533 __le16 command_flags;
534 #define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000
535 #define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000
536 #define I40E_AQC_WRITE_TYPE_PORT 0x8000
537 #define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000
538 #define I40E_AQC_WRITE_TYPE_MASK 0xC000
539
540 __le16 mac_sah;
541 __le32 mac_sal;
542 u8 reserved[8];
543 };
544
545 I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write);
546
547 /* PXE commands (0x011x) */
548
549 /* Clear PXE Command and response (direct 0x0110) */
550 struct i40e_aqc_clear_pxe {
551 u8 rx_cnt;
552 u8 reserved[15];
553 };
554
555 I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe);
556
557 /* Switch configuration commands (0x02xx) */
558
559 /* Used by many indirect commands that only pass an seid and a buffer in the
560 * command
561 */
562 struct i40e_aqc_switch_seid {
563 __le16 seid;
564 u8 reserved[6];
565 __le32 addr_high;
566 __le32 addr_low;
567 };
568
569 I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid);
570
571 /* Get Switch Configuration command (indirect 0x0200)
572 * uses i40e_aqc_switch_seid for the descriptor
573 */
574 struct i40e_aqc_get_switch_config_header_resp {
575 __le16 num_reported;
576 __le16 num_total;
577 u8 reserved[12];
578 };
579
580 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp);
581
582 struct i40e_aqc_switch_config_element_resp {
583 u8 element_type;
584 #define I40E_AQ_SW_ELEM_TYPE_MAC 1
585 #define I40E_AQ_SW_ELEM_TYPE_PF 2
586 #define I40E_AQ_SW_ELEM_TYPE_VF 3
587 #define I40E_AQ_SW_ELEM_TYPE_EMP 4
588 #define I40E_AQ_SW_ELEM_TYPE_BMC 5
589 #define I40E_AQ_SW_ELEM_TYPE_PV 16
590 #define I40E_AQ_SW_ELEM_TYPE_VEB 17
591 #define I40E_AQ_SW_ELEM_TYPE_PA 18
592 #define I40E_AQ_SW_ELEM_TYPE_VSI 19
593 u8 revision;
594 #define I40E_AQ_SW_ELEM_REV_1 1
595 __le16 seid;
596 __le16 uplink_seid;
597 __le16 downlink_seid;
598 u8 reserved[3];
599 u8 connection_type;
600 #define I40E_AQ_CONN_TYPE_REGULAR 0x1
601 #define I40E_AQ_CONN_TYPE_DEFAULT 0x2
602 #define I40E_AQ_CONN_TYPE_CASCADED 0x3
603 __le16 scheduler_id;
604 __le16 element_info;
605 };
606
607 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp);
608
609 /* Get Switch Configuration (indirect 0x0200)
610 * an array of elements are returned in the response buffer
611 * the first in the array is the header, remainder are elements
612 */
613 struct i40e_aqc_get_switch_config_resp {
614 struct i40e_aqc_get_switch_config_header_resp header;
615 struct i40e_aqc_switch_config_element_resp element[1];
616 };
617
618 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp);
619
620 /* Add Statistics (direct 0x0201)
621 * Remove Statistics (direct 0x0202)
622 */
623 struct i40e_aqc_add_remove_statistics {
624 __le16 seid;
625 __le16 vlan;
626 __le16 stat_index;
627 u8 reserved[10];
628 };
629
630 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics);
631
632 /* Set Port Parameters command (direct 0x0203) */
633 struct i40e_aqc_set_port_parameters {
634 __le16 command_flags;
635 #define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1
636 #define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */
637 #define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4
638 __le16 bad_frame_vsi;
639 __le16 default_seid; /* reserved for command */
640 u8 reserved[10];
641 };
642
643 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters);
644
645 /* Get Switch Resource Allocation (indirect 0x0204) */
646 struct i40e_aqc_get_switch_resource_alloc {
647 u8 num_entries; /* reserved for command */
648 u8 reserved[7];
649 __le32 addr_high;
650 __le32 addr_low;
651 };
652
653 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc);
654
655 /* expect an array of these structs in the response buffer */
656 struct i40e_aqc_switch_resource_alloc_element_resp {
657 u8 resource_type;
658 #define I40E_AQ_RESOURCE_TYPE_VEB 0x0
659 #define I40E_AQ_RESOURCE_TYPE_VSI 0x1
660 #define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2
661 #define I40E_AQ_RESOURCE_TYPE_STAG 0x3
662 #define I40E_AQ_RESOURCE_TYPE_ETAG 0x4
663 #define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5
664 #define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6
665 #define I40E_AQ_RESOURCE_TYPE_VLAN 0x7
666 #define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8
667 #define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9
668 #define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA
669 #define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB
670 #define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC
671 #define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD
672 #define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
673 #define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10
674 #define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11
675 #define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12
676 #define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13
677 u8 reserved1;
678 __le16 guaranteed;
679 __le16 total;
680 __le16 used;
681 __le16 total_unalloced;
682 u8 reserved2[6];
683 };
684
685 I40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp);
686
687 /* Set Switch Configuration (direct 0x0205) */
688 struct i40e_aqc_set_switch_config {
689 __le16 flags;
690 #define I40E_AQ_SET_SWITCH_CFG_PROMISC 0x0001
691 #define I40E_AQ_SET_SWITCH_CFG_L2_FILTER 0x0002
692 __le16 valid_flags;
693 u8 reserved[12];
694 };
695
696 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_switch_config);
697
698 /* Read Receive control registers (direct 0x0206)
699 * Write Receive control registers (direct 0x0207)
700 * used for accessing Rx control registers that can be
701 * slow and need special handling when under high Rx load
702 */
703 struct i40e_aqc_rx_ctl_reg_read_write {
704 __le32 reserved1;
705 __le32 address;
706 __le32 reserved2;
707 __le32 value;
708 };
709
710 I40E_CHECK_CMD_LENGTH(i40e_aqc_rx_ctl_reg_read_write);
711
712 /* Add VSI (indirect 0x0210)
713 * this indirect command uses struct i40e_aqc_vsi_properties_data
714 * as the indirect buffer (128 bytes)
715 *
716 * Update VSI (indirect 0x211)
717 * uses the same data structure as Add VSI
718 *
719 * Get VSI (indirect 0x0212)
720 * uses the same completion and data structure as Add VSI
721 */
722 struct i40e_aqc_add_get_update_vsi {
723 __le16 uplink_seid;
724 u8 connection_type;
725 #define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1
726 #define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2
727 #define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3
728 u8 reserved1;
729 u8 vf_id;
730 u8 reserved2;
731 __le16 vsi_flags;
732 #define I40E_AQ_VSI_TYPE_SHIFT 0x0
733 #define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT)
734 #define I40E_AQ_VSI_TYPE_VF 0x0
735 #define I40E_AQ_VSI_TYPE_VMDQ2 0x1
736 #define I40E_AQ_VSI_TYPE_PF 0x2
737 #define I40E_AQ_VSI_TYPE_EMP_MNG 0x3
738 #define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4
739 __le32 addr_high;
740 __le32 addr_low;
741 };
742
743 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi);
744
745 struct i40e_aqc_add_get_update_vsi_completion {
746 __le16 seid;
747 __le16 vsi_number;
748 __le16 vsi_used;
749 __le16 vsi_free;
750 __le32 addr_high;
751 __le32 addr_low;
752 };
753
754 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion);
755
756 struct i40e_aqc_vsi_properties_data {
757 /* first 96 byte are written by SW */
758 __le16 valid_sections;
759 #define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001
760 #define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002
761 #define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004
762 #define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008
763 #define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010
764 #define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020
765 #define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040
766 #define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080
767 #define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100
768 #define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200
769 /* switch section */
770 __le16 switch_id; /* 12bit id combined with flags below */
771 #define I40E_AQ_VSI_SW_ID_SHIFT 0x0000
772 #define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT)
773 #define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
774 #define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
775 #define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
776 u8 sw_reserved[2];
777 /* security section */
778 u8 sec_flags;
779 #define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01
780 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02
781 #define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04
782 u8 sec_reserved;
783 /* VLAN section */
784 __le16 pvid; /* VLANS include priority bits */
785 __le16 fcoe_pvid;
786 u8 port_vlan_flags;
787 #define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00
788 #define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \
789 I40E_AQ_VSI_PVLAN_MODE_SHIFT)
790 #define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01
791 #define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
792 #define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03
793 #define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04
794 #define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03
795 #define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \
796 I40E_AQ_VSI_PVLAN_EMOD_SHIFT)
797 #define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
798 #define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08
799 #define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10
800 #define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18
801 u8 pvlan_reserved[3];
802 /* ingress egress up sections */
803 __le32 ingress_table; /* bitmap, 3 bits per up */
804 #define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0
805 #define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \
806 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT)
807 #define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3
808 #define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \
809 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT)
810 #define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6
811 #define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \
812 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT)
813 #define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9
814 #define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \
815 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT)
816 #define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12
817 #define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \
818 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT)
819 #define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15
820 #define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \
821 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT)
822 #define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18
823 #define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \
824 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT)
825 #define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21
826 #define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \
827 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT)
828 __le32 egress_table; /* same defines as for ingress table */
829 /* cascaded PV section */
830 __le16 cas_pv_tag;
831 u8 cas_pv_flags;
832 #define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00
833 #define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \
834 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT)
835 #define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00
836 #define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01
837 #define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02
838 #define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10
839 #define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20
840 #define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40
841 u8 cas_pv_reserved;
842 /* queue mapping section */
843 __le16 mapping_flags;
844 #define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0
845 #define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1
846 __le16 queue_mapping[16];
847 #define I40E_AQ_VSI_QUEUE_SHIFT 0x0
848 #define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT)
849 __le16 tc_mapping[8];
850 #define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
851 #define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \
852 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT)
853 #define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
854 #define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \
855 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT)
856 /* queueing option section */
857 u8 queueing_opt_flags;
858 #define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04
859 #define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08
860 #define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10
861 #define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20
862 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00
863 #define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
864 u8 queueing_opt_reserved[3];
865 /* scheduler section */
866 u8 up_enable_bits;
867 u8 sched_reserved;
868 /* outer up section */
869 __le32 outer_up_table; /* same structure and defines as ingress tbl */
870 u8 cmd_reserved[8];
871 /* last 32 bytes are written by FW */
872 __le16 qs_handle[8];
873 #define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF
874 __le16 stat_counter_idx;
875 __le16 sched_id;
876 u8 resp_reserved[12];
877 };
878
879 I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data);
880
881 /* Add Port Virtualizer (direct 0x0220)
882 * also used for update PV (direct 0x0221) but only flags are used
883 * (IS_CTRL_PORT only works on add PV)
884 */
885 struct i40e_aqc_add_update_pv {
886 __le16 command_flags;
887 #define I40E_AQC_PV_FLAG_PV_TYPE 0x1
888 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2
889 #define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4
890 #define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8
891 __le16 uplink_seid;
892 __le16 connected_seid;
893 u8 reserved[10];
894 };
895
896 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv);
897
898 struct i40e_aqc_add_update_pv_completion {
899 /* reserved for update; for add also encodes error if rc == ENOSPC */
900 __le16 pv_seid;
901 #define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1
902 #define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2
903 #define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
904 #define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8
905 u8 reserved[14];
906 };
907
908 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion);
909
910 /* Get PV Params (direct 0x0222)
911 * uses i40e_aqc_switch_seid for the descriptor
912 */
913
914 struct i40e_aqc_get_pv_params_completion {
915 __le16 seid;
916 __le16 default_stag;
917 __le16 pv_flags; /* same flags as add_pv */
918 #define I40E_AQC_GET_PV_PV_TYPE 0x1
919 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2
920 #define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4
921 u8 reserved[8];
922 __le16 default_port_seid;
923 };
924
925 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion);
926
927 /* Add VEB (direct 0x0230) */
928 struct i40e_aqc_add_veb {
929 __le16 uplink_seid;
930 __le16 downlink_seid;
931 __le16 veb_flags;
932 #define I40E_AQC_ADD_VEB_FLOATING 0x1
933 #define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1
934 #define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \
935 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT)
936 #define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2
937 #define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4
938 #define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 /* deprecated */
939 #define I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS 0x10
940 u8 enable_tcs;
941 u8 reserved[9];
942 };
943
944 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb);
945
946 struct i40e_aqc_add_veb_completion {
947 u8 reserved[6];
948 __le16 switch_seid;
949 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
950 __le16 veb_seid;
951 #define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1
952 #define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2
953 #define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4
954 #define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8
955 __le16 statistic_index;
956 __le16 vebs_used;
957 __le16 vebs_free;
958 };
959
960 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion);
961
962 /* Get VEB Parameters (direct 0x0232)
963 * uses i40e_aqc_switch_seid for the descriptor
964 */
965 struct i40e_aqc_get_veb_parameters_completion {
966 __le16 seid;
967 __le16 switch_id;
968 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */
969 __le16 statistic_index;
970 __le16 vebs_used;
971 __le16 vebs_free;
972 u8 reserved[4];
973 };
974
975 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion);
976
977 /* Delete Element (direct 0x0243)
978 * uses the generic i40e_aqc_switch_seid
979 */
980
981 /* Add MAC-VLAN (indirect 0x0250) */
982
983 /* used for the command for most vlan commands */
984 struct i40e_aqc_macvlan {
985 __le16 num_addresses;
986 __le16 seid[3];
987 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0
988 #define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \
989 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
990 #define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000
991 __le32 addr_high;
992 __le32 addr_low;
993 };
994
995 I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan);
996
997 /* indirect data for command and response */
998 struct i40e_aqc_add_macvlan_element_data {
999 u8 mac_addr[6];
1000 __le16 vlan_tag;
1001 __le16 flags;
1002 #define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001
1003 #define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002
1004 #define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004
1005 #define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008
1006 #define I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC 0x0010
1007 __le16 queue_number;
1008 #define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0
1009 #define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \
1010 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1011 /* response section */
1012 u8 match_method;
1013 #define I40E_AQC_MM_PERFECT_MATCH 0x01
1014 #define I40E_AQC_MM_HASH_MATCH 0x02
1015 #define I40E_AQC_MM_ERR_NO_RES 0xFF
1016 u8 reserved1[3];
1017 };
1018
1019 struct i40e_aqc_add_remove_macvlan_completion {
1020 __le16 perfect_mac_used;
1021 __le16 perfect_mac_free;
1022 __le16 unicast_hash_free;
1023 __le16 multicast_hash_free;
1024 __le32 addr_high;
1025 __le32 addr_low;
1026 };
1027
1028 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion);
1029
1030 /* Remove MAC-VLAN (indirect 0x0251)
1031 * uses i40e_aqc_macvlan for the descriptor
1032 * data points to an array of num_addresses of elements
1033 */
1034
1035 struct i40e_aqc_remove_macvlan_element_data {
1036 u8 mac_addr[6];
1037 __le16 vlan_tag;
1038 u8 flags;
1039 #define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01
1040 #define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02
1041 #define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08
1042 #define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10
1043 u8 reserved[3];
1044 /* reply section */
1045 u8 error_code;
1046 #define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0
1047 #define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF
1048 u8 reply_reserved[3];
1049 };
1050
1051 /* Add VLAN (indirect 0x0252)
1052 * Remove VLAN (indirect 0x0253)
1053 * use the generic i40e_aqc_macvlan for the command
1054 */
1055 struct i40e_aqc_add_remove_vlan_element_data {
1056 __le16 vlan_tag;
1057 u8 vlan_flags;
1058 /* flags for add VLAN */
1059 #define I40E_AQC_ADD_VLAN_LOCAL 0x1
1060 #define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1
1061 #define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT)
1062 #define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0
1063 #define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2
1064 #define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4
1065 #define I40E_AQC_VLAN_PTYPE_SHIFT 3
1066 #define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT)
1067 #define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0
1068 #define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8
1069 #define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10
1070 #define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18
1071 /* flags for remove VLAN */
1072 #define I40E_AQC_REMOVE_VLAN_ALL 0x1
1073 u8 reserved;
1074 u8 result;
1075 /* flags for add VLAN */
1076 #define I40E_AQC_ADD_VLAN_SUCCESS 0x0
1077 #define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE
1078 #define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1079 /* flags for remove VLAN */
1080 #define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0
1081 #define I40E_AQC_REMOVE_VLAN_FAIL 0xFF
1082 u8 reserved1[3];
1083 };
1084
1085 struct i40e_aqc_add_remove_vlan_completion {
1086 u8 reserved[4];
1087 __le16 vlans_used;
1088 __le16 vlans_free;
1089 __le32 addr_high;
1090 __le32 addr_low;
1091 };
1092
1093 /* Set VSI Promiscuous Modes (direct 0x0254) */
1094 struct i40e_aqc_set_vsi_promiscuous_modes {
1095 __le16 promiscuous_flags;
1096 __le16 valid_flags;
1097 /* flags used for both fields above */
1098 #define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01
1099 #define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02
1100 #define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04
1101 #define I40E_AQC_SET_VSI_DEFAULT 0x08
1102 #define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10
1103 #define I40E_AQC_SET_VSI_PROMISC_TX 0x8000
1104 __le16 seid;
1105 #define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF
1106 __le16 vlan_tag;
1107 #define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF
1108 #define I40E_AQC_SET_VSI_VLAN_VALID 0x8000
1109 u8 reserved[8];
1110 };
1111
1112 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes);
1113
1114 /* Add S/E-tag command (direct 0x0255)
1115 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1116 */
1117 struct i40e_aqc_add_tag {
1118 __le16 flags;
1119 #define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001
1120 __le16 seid;
1121 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0
1122 #define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1123 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1124 __le16 tag;
1125 __le16 queue_number;
1126 u8 reserved[8];
1127 };
1128
1129 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag);
1130
1131 struct i40e_aqc_add_remove_tag_completion {
1132 u8 reserved[12];
1133 __le16 tags_used;
1134 __le16 tags_free;
1135 };
1136
1137 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion);
1138
1139 /* Remove S/E-tag command (direct 0x0256)
1140 * Uses generic i40e_aqc_add_remove_tag_completion for completion
1141 */
1142 struct i40e_aqc_remove_tag {
1143 __le16 seid;
1144 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0
1145 #define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1146 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1147 __le16 tag;
1148 u8 reserved[12];
1149 };
1150
1151 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag);
1152
1153 /* Add multicast E-Tag (direct 0x0257)
1154 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1155 * and no external data
1156 */
1157 struct i40e_aqc_add_remove_mcast_etag {
1158 __le16 pv_seid;
1159 __le16 etag;
1160 u8 num_unicast_etags;
1161 u8 reserved[3];
1162 __le32 addr_high; /* address of array of 2-byte s-tags */
1163 __le32 addr_low;
1164 };
1165
1166 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag);
1167
1168 struct i40e_aqc_add_remove_mcast_etag_completion {
1169 u8 reserved[4];
1170 __le16 mcast_etags_used;
1171 __le16 mcast_etags_free;
1172 __le32 addr_high;
1173 __le32 addr_low;
1174
1175 };
1176
1177 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion);
1178
1179 /* Update S/E-Tag (direct 0x0259) */
1180 struct i40e_aqc_update_tag {
1181 __le16 seid;
1182 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0
1183 #define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \
1184 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1185 __le16 old_tag;
1186 __le16 new_tag;
1187 u8 reserved[10];
1188 };
1189
1190 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag);
1191
1192 struct i40e_aqc_update_tag_completion {
1193 u8 reserved[12];
1194 __le16 tags_used;
1195 __le16 tags_free;
1196 };
1197
1198 I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion);
1199
1200 /* Add Control Packet filter (direct 0x025A)
1201 * Remove Control Packet filter (direct 0x025B)
1202 * uses the i40e_aqc_add_oveb_cloud,
1203 * and the generic direct completion structure
1204 */
1205 struct i40e_aqc_add_remove_control_packet_filter {
1206 u8 mac[6];
1207 __le16 etype;
1208 __le16 flags;
1209 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001
1210 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002
1211 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004
1212 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008
1213 #define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000
1214 __le16 seid;
1215 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0
1216 #define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \
1217 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1218 __le16 queue;
1219 u8 reserved[2];
1220 };
1221
1222 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter);
1223
1224 struct i40e_aqc_add_remove_control_packet_filter_completion {
1225 __le16 mac_etype_used;
1226 __le16 etype_used;
1227 __le16 mac_etype_free;
1228 __le16 etype_free;
1229 u8 reserved[8];
1230 };
1231
1232 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion);
1233
1234 /* Add Cloud filters (indirect 0x025C)
1235 * Remove Cloud filters (indirect 0x025D)
1236 * uses the i40e_aqc_add_remove_cloud_filters,
1237 * and the generic indirect completion structure
1238 */
1239 struct i40e_aqc_add_remove_cloud_filters {
1240 u8 num_filters;
1241 u8 reserved;
1242 __le16 seid;
1243 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0
1244 #define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \
1245 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1246 u8 reserved2[4];
1247 __le32 addr_high;
1248 __le32 addr_low;
1249 };
1250
1251 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters);
1252
1253 struct i40e_aqc_add_remove_cloud_filters_element_data {
1254 u8 outer_mac[6];
1255 u8 inner_mac[6];
1256 __le16 inner_vlan;
1257 union {
1258 struct {
1259 u8 reserved[12];
1260 u8 data[4];
1261 } v4;
1262 struct {
1263 u8 data[16];
1264 } v6;
1265 } ipaddr;
1266 __le16 flags;
1267 #define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0
1268 #define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \
1269 I40E_AQC_ADD_CLOUD_FILTER_SHIFT)
1270 /* 0x0000 reserved */
1271 #define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001
1272 /* 0x0002 reserved */
1273 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003
1274 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004
1275 /* 0x0005 reserved */
1276 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006
1277 /* 0x0007 reserved */
1278 /* 0x0008 reserved */
1279 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009
1280 #define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A
1281 #define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B
1282 #define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C
1283
1284 #define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080
1285 #define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6
1286 #define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0
1287 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0
1288 #define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100
1289
1290 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9
1291 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00
1292 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN 0
1293 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1
1294 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE 2
1295 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3
1296 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_RESERVED 4
1297 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE 5
1298
1299 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC 0x2000
1300 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC 0x4000
1301 #define I40E_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP 0x8000
1302
1303 __le32 tenant_id;
1304 u8 reserved[4];
1305 __le16 queue_number;
1306 #define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0
1307 #define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \
1308 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT)
1309 u8 reserved2[14];
1310 /* response section */
1311 u8 allocation_result;
1312 #define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0
1313 #define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF
1314 u8 response_reserved[7];
1315 };
1316
1317 struct i40e_aqc_remove_cloud_filters_completion {
1318 __le16 perfect_ovlan_used;
1319 __le16 perfect_ovlan_free;
1320 __le16 vlan_used;
1321 __le16 vlan_free;
1322 __le32 addr_high;
1323 __le32 addr_low;
1324 };
1325
1326 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion);
1327
1328 /* Add Mirror Rule (indirect or direct 0x0260)
1329 * Delete Mirror Rule (indirect or direct 0x0261)
1330 * note: some rule types (4,5) do not use an external buffer.
1331 * take care to set the flags correctly.
1332 */
1333 struct i40e_aqc_add_delete_mirror_rule {
1334 __le16 seid;
1335 __le16 rule_type;
1336 #define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0
1337 #define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \
1338 I40E_AQC_MIRROR_RULE_TYPE_SHIFT)
1339 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1340 #define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2
1341 #define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3
1342 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4
1343 #define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5
1344 __le16 num_entries;
1345 __le16 destination; /* VSI for add, rule id for delete */
1346 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */
1347 __le32 addr_low;
1348 };
1349
1350 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule);
1351
1352 struct i40e_aqc_add_delete_mirror_rule_completion {
1353 u8 reserved[2];
1354 __le16 rule_id; /* only used on add */
1355 __le16 mirror_rules_used;
1356 __le16 mirror_rules_free;
1357 __le32 addr_high;
1358 __le32 addr_low;
1359 };
1360
1361 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion);
1362
1363 /* DCB 0x03xx*/
1364
1365 /* PFC Ignore (direct 0x0301)
1366 * the command and response use the same descriptor structure
1367 */
1368 struct i40e_aqc_pfc_ignore {
1369 u8 tc_bitmap;
1370 u8 command_flags; /* unused on response */
1371 #define I40E_AQC_PFC_IGNORE_SET 0x80
1372 #define I40E_AQC_PFC_IGNORE_CLEAR 0x0
1373 u8 reserved[14];
1374 };
1375
1376 I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore);
1377
1378 /* DCB Update (direct 0x0302) uses the i40e_aq_desc structure
1379 * with no parameters
1380 */
1381
1382 /* TX scheduler 0x04xx */
1383
1384 /* Almost all the indirect commands use
1385 * this generic struct to pass the SEID in param0
1386 */
1387 struct i40e_aqc_tx_sched_ind {
1388 __le16 vsi_seid;
1389 u8 reserved[6];
1390 __le32 addr_high;
1391 __le32 addr_low;
1392 };
1393
1394 I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind);
1395
1396 /* Several commands respond with a set of queue set handles */
1397 struct i40e_aqc_qs_handles_resp {
1398 __le16 qs_handles[8];
1399 };
1400
1401 /* Configure VSI BW limits (direct 0x0400) */
1402 struct i40e_aqc_configure_vsi_bw_limit {
1403 __le16 vsi_seid;
1404 u8 reserved[2];
1405 __le16 credit;
1406 u8 reserved1[2];
1407 u8 max_credit; /* 0-3, limit = 2^max */
1408 u8 reserved2[7];
1409 };
1410
1411 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit);
1412
1413 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1414 * responds with i40e_aqc_qs_handles_resp
1415 */
1416 struct i40e_aqc_configure_vsi_ets_sla_bw_data {
1417 u8 tc_valid_bits;
1418 u8 reserved[15];
1419 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */
1420
1421 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1422 __le16 tc_bw_max[2];
1423 u8 reserved1[28];
1424 };
1425
1426 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data);
1427
1428 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1429 * responds with i40e_aqc_qs_handles_resp
1430 */
1431 struct i40e_aqc_configure_vsi_tc_bw_data {
1432 u8 tc_valid_bits;
1433 u8 reserved[3];
1434 u8 tc_bw_credits[8];
1435 u8 reserved1[4];
1436 __le16 qs_handles[8];
1437 };
1438
1439 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data);
1440
1441 /* Query vsi bw configuration (indirect 0x0408) */
1442 struct i40e_aqc_query_vsi_bw_config_resp {
1443 u8 tc_valid_bits;
1444 u8 tc_suspended_bits;
1445 u8 reserved[14];
1446 __le16 qs_handles[8];
1447 u8 reserved1[4];
1448 __le16 port_bw_limit;
1449 u8 reserved2[2];
1450 u8 max_bw; /* 0-3, limit = 2^max */
1451 u8 reserved3[23];
1452 };
1453
1454 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp);
1455
1456 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1457 struct i40e_aqc_query_vsi_ets_sla_config_resp {
1458 u8 tc_valid_bits;
1459 u8 reserved[3];
1460 u8 share_credits[8];
1461 __le16 credits[8];
1462
1463 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1464 __le16 tc_bw_max[2];
1465 };
1466
1467 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp);
1468
1469 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1470 struct i40e_aqc_configure_switching_comp_bw_limit {
1471 __le16 seid;
1472 u8 reserved[2];
1473 __le16 credit;
1474 u8 reserved1[2];
1475 u8 max_bw; /* 0-3, limit = 2^max */
1476 u8 reserved2[7];
1477 };
1478
1479 I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit);
1480
1481 /* Enable Physical Port ETS (indirect 0x0413)
1482 * Modify Physical Port ETS (indirect 0x0414)
1483 * Disable Physical Port ETS (indirect 0x0415)
1484 */
1485 struct i40e_aqc_configure_switching_comp_ets_data {
1486 u8 reserved[4];
1487 u8 tc_valid_bits;
1488 u8 seepage;
1489 #define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1
1490 u8 tc_strict_priority_flags;
1491 u8 reserved1[17];
1492 u8 tc_bw_share_credits[8];
1493 u8 reserved2[96];
1494 };
1495
1496 I40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data);
1497
1498 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1499 struct i40e_aqc_configure_switching_comp_ets_bw_limit_data {
1500 u8 tc_valid_bits;
1501 u8 reserved[15];
1502 __le16 tc_bw_credit[8];
1503
1504 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1505 __le16 tc_bw_max[2];
1506 u8 reserved1[28];
1507 };
1508
1509 I40E_CHECK_STRUCT_LEN(0x40,
1510 i40e_aqc_configure_switching_comp_ets_bw_limit_data);
1511
1512 /* Configure Switching Component Bandwidth Allocation per Tc
1513 * (indirect 0x0417)
1514 */
1515 struct i40e_aqc_configure_switching_comp_bw_config_data {
1516 u8 tc_valid_bits;
1517 u8 reserved[2];
1518 u8 absolute_credits; /* bool */
1519 u8 tc_bw_share_credits[8];
1520 u8 reserved1[20];
1521 };
1522
1523 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data);
1524
1525 /* Query Switching Component Configuration (indirect 0x0418) */
1526 struct i40e_aqc_query_switching_comp_ets_config_resp {
1527 u8 tc_valid_bits;
1528 u8 reserved[35];
1529 __le16 port_bw_limit;
1530 u8 reserved1[2];
1531 u8 tc_bw_max; /* 0-3, limit = 2^max */
1532 u8 reserved2[23];
1533 };
1534
1535 I40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp);
1536
1537 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1538 struct i40e_aqc_query_port_ets_config_resp {
1539 u8 reserved[4];
1540 u8 tc_valid_bits;
1541 u8 reserved1;
1542 u8 tc_strict_priority_bits;
1543 u8 reserved2;
1544 u8 tc_bw_share_credits[8];
1545 __le16 tc_bw_limits[8];
1546
1547 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1548 __le16 tc_bw_max[2];
1549 u8 reserved3[32];
1550 };
1551
1552 I40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp);
1553
1554 /* Query Switching Component Bandwidth Allocation per Traffic Type
1555 * (indirect 0x041A)
1556 */
1557 struct i40e_aqc_query_switching_comp_bw_config_resp {
1558 u8 tc_valid_bits;
1559 u8 reserved[2];
1560 u8 absolute_credits_enable; /* bool */
1561 u8 tc_bw_share_credits[8];
1562 __le16 tc_bw_limits[8];
1563
1564 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1565 __le16 tc_bw_max[2];
1566 };
1567
1568 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp);
1569
1570 /* Suspend/resume port TX traffic
1571 * (direct 0x041B and 0x041C) uses the generic SEID struct
1572 */
1573
1574 /* Configure partition BW
1575 * (indirect 0x041D)
1576 */
1577 struct i40e_aqc_configure_partition_bw_data {
1578 __le16 pf_valid_bits;
1579 u8 min_bw[16]; /* guaranteed bandwidth */
1580 u8 max_bw[16]; /* bandwidth limit */
1581 };
1582
1583 I40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data);
1584
1585 /* Get and set the active HMC resource profile and status.
1586 * (direct 0x0500) and (direct 0x0501)
1587 */
1588 struct i40e_aq_get_set_hmc_resource_profile {
1589 u8 pm_profile;
1590 u8 pe_vf_enabled;
1591 u8 reserved[14];
1592 };
1593
1594 I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile);
1595
1596 enum i40e_aq_hmc_profile {
1597 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */
1598 I40E_HMC_PROFILE_DEFAULT = 1,
1599 I40E_HMC_PROFILE_FAVOR_VF = 2,
1600 I40E_HMC_PROFILE_EQUAL = 3,
1601 };
1602
1603 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF
1604 #define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F
1605
1606 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1607
1608 /* set in param0 for get phy abilities to report qualified modules */
1609 #define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001
1610 #define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002
1611
1612 enum i40e_aq_phy_type {
1613 I40E_PHY_TYPE_SGMII = 0x0,
1614 I40E_PHY_TYPE_1000BASE_KX = 0x1,
1615 I40E_PHY_TYPE_10GBASE_KX4 = 0x2,
1616 I40E_PHY_TYPE_10GBASE_KR = 0x3,
1617 I40E_PHY_TYPE_40GBASE_KR4 = 0x4,
1618 I40E_PHY_TYPE_XAUI = 0x5,
1619 I40E_PHY_TYPE_XFI = 0x6,
1620 I40E_PHY_TYPE_SFI = 0x7,
1621 I40E_PHY_TYPE_XLAUI = 0x8,
1622 I40E_PHY_TYPE_XLPPI = 0x9,
1623 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA,
1624 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB,
1625 I40E_PHY_TYPE_10GBASE_AOC = 0xC,
1626 I40E_PHY_TYPE_40GBASE_AOC = 0xD,
1627 I40E_PHY_TYPE_100BASE_TX = 0x11,
1628 I40E_PHY_TYPE_1000BASE_T = 0x12,
1629 I40E_PHY_TYPE_10GBASE_T = 0x13,
1630 I40E_PHY_TYPE_10GBASE_SR = 0x14,
1631 I40E_PHY_TYPE_10GBASE_LR = 0x15,
1632 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16,
1633 I40E_PHY_TYPE_10GBASE_CR1 = 0x17,
1634 I40E_PHY_TYPE_40GBASE_CR4 = 0x18,
1635 I40E_PHY_TYPE_40GBASE_SR4 = 0x19,
1636 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A,
1637 I40E_PHY_TYPE_1000BASE_SX = 0x1B,
1638 I40E_PHY_TYPE_1000BASE_LX = 0x1C,
1639 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D,
1640 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E,
1641 I40E_PHY_TYPE_MAX
1642 };
1643
1644 #define I40E_LINK_SPEED_100MB_SHIFT 0x1
1645 #define I40E_LINK_SPEED_1000MB_SHIFT 0x2
1646 #define I40E_LINK_SPEED_10GB_SHIFT 0x3
1647 #define I40E_LINK_SPEED_40GB_SHIFT 0x4
1648 #define I40E_LINK_SPEED_20GB_SHIFT 0x5
1649
1650 enum i40e_aq_link_speed {
1651 I40E_LINK_SPEED_UNKNOWN = 0,
1652 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT),
1653 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT),
1654 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT),
1655 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT),
1656 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT)
1657 };
1658
1659 struct i40e_aqc_module_desc {
1660 u8 oui[3];
1661 u8 reserved1;
1662 u8 part_number[16];
1663 u8 revision[4];
1664 u8 reserved2[8];
1665 };
1666
1667 I40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc);
1668
1669 struct i40e_aq_get_phy_abilities_resp {
1670 __le32 phy_type; /* bitmap using the above enum for offsets */
1671 u8 link_speed; /* bitmap using the above enum bit patterns */
1672 u8 abilities;
1673 #define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01
1674 #define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02
1675 #define I40E_AQ_PHY_FLAG_LOW_POWER 0x04
1676 #define I40E_AQ_PHY_LINK_ENABLED 0x08
1677 #define I40E_AQ_PHY_AN_ENABLED 0x10
1678 #define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20
1679 __le16 eee_capability;
1680 #define I40E_AQ_EEE_100BASE_TX 0x0002
1681 #define I40E_AQ_EEE_1000BASE_T 0x0004
1682 #define I40E_AQ_EEE_10GBASE_T 0x0008
1683 #define I40E_AQ_EEE_1000BASE_KX 0x0010
1684 #define I40E_AQ_EEE_10GBASE_KX4 0x0020
1685 #define I40E_AQ_EEE_10GBASE_KR 0x0040
1686 __le32 eeer_val;
1687 u8 d3_lpan;
1688 #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01
1689 u8 reserved[3];
1690 u8 phy_id[4];
1691 u8 module_type[3];
1692 u8 qualified_module_count;
1693 #define I40E_AQ_PHY_MAX_QMS 16
1694 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS];
1695 };
1696
1697 I40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp);
1698
1699 /* Set PHY Config (direct 0x0601) */
1700 struct i40e_aq_set_phy_config { /* same bits as above in all */
1701 __le32 phy_type;
1702 u8 link_speed;
1703 u8 abilities;
1704 /* bits 0-2 use the values from get_phy_abilities_resp */
1705 #define I40E_AQ_PHY_ENABLE_LINK 0x08
1706 #define I40E_AQ_PHY_ENABLE_AN 0x10
1707 #define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20
1708 __le16 eee_capability;
1709 __le32 eeer;
1710 u8 low_power_ctrl;
1711 u8 reserved[3];
1712 };
1713
1714 I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config);
1715
1716 /* Set MAC Config command data structure (direct 0x0603) */
1717 struct i40e_aq_set_mac_config {
1718 __le16 max_frame_size;
1719 u8 params;
1720 #define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04
1721 #define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78
1722 #define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3
1723 #define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0
1724 #define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF
1725 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9
1726 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8
1727 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7
1728 #define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6
1729 #define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5
1730 #define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4
1731 #define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3
1732 #define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2
1733 #define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1
1734 u8 tx_timer_priority; /* bitmap */
1735 __le16 tx_timer_value;
1736 __le16 fc_refresh_threshold;
1737 u8 reserved[8];
1738 };
1739
1740 I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config);
1741
1742 /* Restart Auto-Negotiation (direct 0x605) */
1743 struct i40e_aqc_set_link_restart_an {
1744 u8 command;
1745 #define I40E_AQ_PHY_RESTART_AN 0x02
1746 #define I40E_AQ_PHY_LINK_ENABLE 0x04
1747 u8 reserved[15];
1748 };
1749
1750 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an);
1751
1752 /* Get Link Status cmd & response data structure (direct 0x0607) */
1753 struct i40e_aqc_get_link_status {
1754 __le16 command_flags; /* only field set on command */
1755 #define I40E_AQ_LSE_MASK 0x3
1756 #define I40E_AQ_LSE_NOP 0x0
1757 #define I40E_AQ_LSE_DISABLE 0x2
1758 #define I40E_AQ_LSE_ENABLE 0x3
1759 /* only response uses this flag */
1760 #define I40E_AQ_LSE_IS_ENABLED 0x1
1761 u8 phy_type; /* i40e_aq_phy_type */
1762 u8 link_speed; /* i40e_aq_link_speed */
1763 u8 link_info;
1764 #define I40E_AQ_LINK_UP 0x01 /* obsolete */
1765 #define I40E_AQ_LINK_UP_FUNCTION 0x01
1766 #define I40E_AQ_LINK_FAULT 0x02
1767 #define I40E_AQ_LINK_FAULT_TX 0x04
1768 #define I40E_AQ_LINK_FAULT_RX 0x08
1769 #define I40E_AQ_LINK_FAULT_REMOTE 0x10
1770 #define I40E_AQ_LINK_UP_PORT 0x20
1771 #define I40E_AQ_MEDIA_AVAILABLE 0x40
1772 #define I40E_AQ_SIGNAL_DETECT 0x80
1773 u8 an_info;
1774 #define I40E_AQ_AN_COMPLETED 0x01
1775 #define I40E_AQ_LP_AN_ABILITY 0x02
1776 #define I40E_AQ_PD_FAULT 0x04
1777 #define I40E_AQ_FEC_EN 0x08
1778 #define I40E_AQ_PHY_LOW_POWER 0x10
1779 #define I40E_AQ_LINK_PAUSE_TX 0x20
1780 #define I40E_AQ_LINK_PAUSE_RX 0x40
1781 #define I40E_AQ_QUALIFIED_MODULE 0x80
1782 u8 ext_info;
1783 #define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01
1784 #define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02
1785 #define I40E_AQ_LINK_TX_SHIFT 0x02
1786 #define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT)
1787 #define I40E_AQ_LINK_TX_ACTIVE 0x00
1788 #define I40E_AQ_LINK_TX_DRAINED 0x01
1789 #define I40E_AQ_LINK_TX_FLUSHED 0x03
1790 #define I40E_AQ_LINK_FORCED_40G 0x10
1791 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */
1792 __le16 max_frame_size;
1793 u8 config;
1794 #define I40E_AQ_CONFIG_CRC_ENA 0x04
1795 #define I40E_AQ_CONFIG_PACING_MASK 0x78
1796 u8 external_power_ability;
1797 #define I40E_AQ_LINK_POWER_CLASS_1 0x00
1798 #define I40E_AQ_LINK_POWER_CLASS_2 0x01
1799 #define I40E_AQ_LINK_POWER_CLASS_3 0x02
1800 #define I40E_AQ_LINK_POWER_CLASS_4 0x03
1801 u8 reserved[4];
1802 };
1803
1804 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status);
1805
1806 /* Set event mask command (direct 0x613) */
1807 struct i40e_aqc_set_phy_int_mask {
1808 u8 reserved[8];
1809 __le16 event_mask;
1810 #define I40E_AQ_EVENT_LINK_UPDOWN 0x0002
1811 #define I40E_AQ_EVENT_MEDIA_NA 0x0004
1812 #define I40E_AQ_EVENT_LINK_FAULT 0x0008
1813 #define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010
1814 #define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020
1815 #define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040
1816 #define I40E_AQ_EVENT_AN_COMPLETED 0x0080
1817 #define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100
1818 #define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
1819 u8 reserved1[6];
1820 };
1821
1822 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask);
1823
1824 /* Get Local AN advt register (direct 0x0614)
1825 * Set Local AN advt register (direct 0x0615)
1826 * Get Link Partner AN advt register (direct 0x0616)
1827 */
1828 struct i40e_aqc_an_advt_reg {
1829 __le32 local_an_reg0;
1830 __le16 local_an_reg1;
1831 u8 reserved[10];
1832 };
1833
1834 I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg);
1835
1836 /* Set Loopback mode (0x0618) */
1837 struct i40e_aqc_set_lb_mode {
1838 __le16 lb_mode;
1839 #define I40E_AQ_LB_PHY_LOCAL 0x01
1840 #define I40E_AQ_LB_PHY_REMOTE 0x02
1841 #define I40E_AQ_LB_MAC_LOCAL 0x04
1842 u8 reserved[14];
1843 };
1844
1845 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode);
1846
1847 /* Set PHY Debug command (0x0622) */
1848 struct i40e_aqc_set_phy_debug {
1849 u8 command_flags;
1850 #define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02
1851 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2
1852 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \
1853 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
1854 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00
1855 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01
1856 #define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02
1857 #define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10
1858 u8 reserved[15];
1859 };
1860
1861 I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug);
1862
1863 enum i40e_aq_phy_reg_type {
1864 I40E_AQC_PHY_REG_INTERNAL = 0x1,
1865 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2,
1866 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3
1867 };
1868
1869 /* Run PHY Activity (0x0626) */
1870 struct i40e_aqc_run_phy_activity {
1871 __le16 activity_id;
1872 u8 flags;
1873 u8 reserved1;
1874 __le32 control;
1875 __le32 data;
1876 u8 reserved2[4];
1877 };
1878
1879 I40E_CHECK_CMD_LENGTH(i40e_aqc_run_phy_activity);
1880
1881 /* NVM Read command (indirect 0x0701)
1882 * NVM Erase commands (direct 0x0702)
1883 * NVM Update commands (indirect 0x0703)
1884 */
1885 struct i40e_aqc_nvm_update {
1886 u8 command_flags;
1887 #define I40E_AQ_NVM_LAST_CMD 0x01
1888 #define I40E_AQ_NVM_FLASH_ONLY 0x80
1889 u8 module_pointer;
1890 __le16 length;
1891 __le32 offset;
1892 __le32 addr_high;
1893 __le32 addr_low;
1894 };
1895
1896 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update);
1897
1898 /* NVM Config Read (indirect 0x0704) */
1899 struct i40e_aqc_nvm_config_read {
1900 __le16 cmd_flags;
1901 #define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1
1902 #define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0
1903 #define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1
1904 __le16 element_count;
1905 __le16 element_id; /* Feature/field ID */
1906 __le16 element_id_msw; /* MSWord of field ID */
1907 __le32 address_high;
1908 __le32 address_low;
1909 };
1910
1911 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read);
1912
1913 /* NVM Config Write (indirect 0x0705) */
1914 struct i40e_aqc_nvm_config_write {
1915 __le16 cmd_flags;
1916 __le16 element_count;
1917 u8 reserved[4];
1918 __le32 address_high;
1919 __le32 address_low;
1920 };
1921
1922 I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write);
1923
1924 /* Used for 0x0704 as well as for 0x0705 commands */
1925 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1
1926 #define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
1927 (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
1928 #define I40E_AQ_ANVM_FEATURE 0
1929 #define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT)
1930 struct i40e_aqc_nvm_config_data_feature {
1931 __le16 feature_id;
1932 #define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01
1933 #define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08
1934 #define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10
1935 __le16 feature_options;
1936 __le16 feature_selection;
1937 };
1938
1939 I40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature);
1940
1941 struct i40e_aqc_nvm_config_data_immediate_field {
1942 __le32 field_id;
1943 __le32 field_value;
1944 __le16 field_options;
1945 __le16 reserved;
1946 };
1947
1948 I40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field);
1949
1950 /* OEM Post Update (indirect 0x0720)
1951 * no command data struct used
1952 */
1953 struct i40e_aqc_nvm_oem_post_update {
1954 #define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01
1955 u8 sel_data;
1956 u8 reserved[7];
1957 };
1958
1959 I40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update);
1960
1961 struct i40e_aqc_nvm_oem_post_update_buffer {
1962 u8 str_len;
1963 u8 dev_addr;
1964 __le16 eeprom_addr;
1965 u8 data[36];
1966 };
1967
1968 I40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer);
1969
1970 /* Thermal Sensor (indirect 0x0721)
1971 * read or set thermal sensor configs and values
1972 * takes a sensor and command specific data buffer, not detailed here
1973 */
1974 struct i40e_aqc_thermal_sensor {
1975 u8 sensor_action;
1976 #define I40E_AQ_THERMAL_SENSOR_READ_CONFIG 0
1977 #define I40E_AQ_THERMAL_SENSOR_SET_CONFIG 1
1978 #define I40E_AQ_THERMAL_SENSOR_READ_TEMP 2
1979 u8 reserved[7];
1980 __le32 addr_high;
1981 __le32 addr_low;
1982 };
1983
1984 I40E_CHECK_CMD_LENGTH(i40e_aqc_thermal_sensor);
1985
1986 /* Send to PF command (indirect 0x0801) id is only used by PF
1987 * Send to VF command (indirect 0x0802) id is only used by PF
1988 * Send to Peer PF command (indirect 0x0803)
1989 */
1990 struct i40e_aqc_pf_vf_message {
1991 __le32 id;
1992 u8 reserved[4];
1993 __le32 addr_high;
1994 __le32 addr_low;
1995 };
1996
1997 I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message);
1998
1999 /* Alternate structure */
2000
2001 /* Direct write (direct 0x0900)
2002 * Direct read (direct 0x0902)
2003 */
2004 struct i40e_aqc_alternate_write {
2005 __le32 address0;
2006 __le32 data0;
2007 __le32 address1;
2008 __le32 data1;
2009 };
2010
2011 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write);
2012
2013 /* Indirect write (indirect 0x0901)
2014 * Indirect read (indirect 0x0903)
2015 */
2016
2017 struct i40e_aqc_alternate_ind_write {
2018 __le32 address;
2019 __le32 length;
2020 __le32 addr_high;
2021 __le32 addr_low;
2022 };
2023
2024 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write);
2025
2026 /* Done alternate write (direct 0x0904)
2027 * uses i40e_aq_desc
2028 */
2029 struct i40e_aqc_alternate_write_done {
2030 __le16 cmd_flags;
2031 #define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1
2032 #define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0
2033 #define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1
2034 #define I40E_AQ_ALTERNATE_RESET_NEEDED 2
2035 u8 reserved[14];
2036 };
2037
2038 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done);
2039
2040 /* Set OEM mode (direct 0x0905) */
2041 struct i40e_aqc_alternate_set_mode {
2042 __le32 mode;
2043 #define I40E_AQ_ALTERNATE_MODE_NONE 0
2044 #define I40E_AQ_ALTERNATE_MODE_OEM 1
2045 u8 reserved[12];
2046 };
2047
2048 I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode);
2049
2050 /* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */
2051
2052 /* async events 0x10xx */
2053
2054 /* Lan Queue Overflow Event (direct, 0x1001) */
2055 struct i40e_aqc_lan_overflow {
2056 __le32 prtdcb_rupto;
2057 __le32 otx_ctl;
2058 u8 reserved[8];
2059 };
2060
2061 I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow);
2062
2063 /* Get LLDP MIB (indirect 0x0A00) */
2064 struct i40e_aqc_lldp_get_mib {
2065 u8 type;
2066 u8 reserved1;
2067 #define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3
2068 #define I40E_AQ_LLDP_MIB_LOCAL 0x0
2069 #define I40E_AQ_LLDP_MIB_REMOTE 0x1
2070 #define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2
2071 #define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC
2072 #define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2
2073 #define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2074 #define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1
2075 #define I40E_AQ_LLDP_TX_SHIFT 0x4
2076 #define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT)
2077 /* TX pause flags use I40E_AQ_LINK_TX_* above */
2078 __le16 local_len;
2079 __le16 remote_len;
2080 u8 reserved2[2];
2081 __le32 addr_high;
2082 __le32 addr_low;
2083 };
2084
2085 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib);
2086
2087 /* Configure LLDP MIB Change Event (direct 0x0A01)
2088 * also used for the event (with type in the command field)
2089 */
2090 struct i40e_aqc_lldp_update_mib {
2091 u8 command;
2092 #define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0
2093 #define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2094 u8 reserved[7];
2095 __le32 addr_high;
2096 __le32 addr_low;
2097 };
2098
2099 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib);
2100
2101 /* Add LLDP TLV (indirect 0x0A02)
2102 * Delete LLDP TLV (indirect 0x0A04)
2103 */
2104 struct i40e_aqc_lldp_add_tlv {
2105 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2106 u8 reserved1[1];
2107 __le16 len;
2108 u8 reserved2[4];
2109 __le32 addr_high;
2110 __le32 addr_low;
2111 };
2112
2113 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv);
2114
2115 /* Update LLDP TLV (indirect 0x0A03) */
2116 struct i40e_aqc_lldp_update_tlv {
2117 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */
2118 u8 reserved;
2119 __le16 old_len;
2120 __le16 new_offset;
2121 __le16 new_len;
2122 __le32 addr_high;
2123 __le32 addr_low;
2124 };
2125
2126 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv);
2127
2128 /* Stop LLDP (direct 0x0A05) */
2129 struct i40e_aqc_lldp_stop {
2130 u8 command;
2131 #define I40E_AQ_LLDP_AGENT_STOP 0x0
2132 #define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1
2133 u8 reserved[15];
2134 };
2135
2136 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop);
2137
2138 /* Start LLDP (direct 0x0A06) */
2139
2140 struct i40e_aqc_lldp_start {
2141 u8 command;
2142 #define I40E_AQ_LLDP_AGENT_START 0x1
2143 u8 reserved[15];
2144 };
2145
2146 I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start);
2147
2148 /* Apply MIB changes (0x0A07)
2149 * uses the generic struc as it contains no data
2150 */
2151
2152 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2153 struct i40e_aqc_add_udp_tunnel {
2154 __le16 udp_port;
2155 u8 reserved0[3];
2156 u8 protocol_type;
2157 #define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00
2158 #define I40E_AQC_TUNNEL_TYPE_NGE 0x01
2159 #define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10
2160 #define I40E_AQC_TUNNEL_TYPE_VXLAN_GPE 0x11
2161 u8 reserved1[10];
2162 };
2163
2164 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel);
2165
2166 struct i40e_aqc_add_udp_tunnel_completion {
2167 __le16 udp_port;
2168 u8 filter_entry_index;
2169 u8 multiple_pfs;
2170 #define I40E_AQC_SINGLE_PF 0x0
2171 #define I40E_AQC_MULTIPLE_PFS 0x1
2172 u8 total_filters;
2173 u8 reserved[11];
2174 };
2175
2176 I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion);
2177
2178 /* remove UDP Tunnel command (0x0B01) */
2179 struct i40e_aqc_remove_udp_tunnel {
2180 u8 reserved[2];
2181 u8 index; /* 0 to 15 */
2182 u8 reserved2[13];
2183 };
2184
2185 I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel);
2186
2187 struct i40e_aqc_del_udp_tunnel_completion {
2188 __le16 udp_port;
2189 u8 index; /* 0 to 15 */
2190 u8 multiple_pfs;
2191 u8 total_filters_used;
2192 u8 reserved1[11];
2193 };
2194
2195 I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion);
2196
2197 struct i40e_aqc_get_set_rss_key {
2198 #define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15)
2199 #define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0
2200 #define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \
2201 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2202 __le16 vsi_id;
2203 u8 reserved[6];
2204 __le32 addr_high;
2205 __le32 addr_low;
2206 };
2207
2208 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key);
2209
2210 struct i40e_aqc_get_set_rss_key_data {
2211 u8 standard_rss_key[0x28];
2212 u8 extended_hash_key[0xc];
2213 };
2214
2215 I40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data);
2216
2217 struct i40e_aqc_get_set_rss_lut {
2218 #define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15)
2219 #define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0
2220 #define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \
2221 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2222 __le16 vsi_id;
2223 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0
2224 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \
2225 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2226
2227 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0
2228 #define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1
2229 __le16 flags;
2230 u8 reserved[4];
2231 __le32 addr_high;
2232 __le32 addr_low;
2233 };
2234
2235 I40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut);
2236
2237 /* tunnel key structure 0x0B10 */
2238
2239 struct i40e_aqc_tunnel_key_structure_A0 {
2240 __le16 key1_off;
2241 __le16 key1_len;
2242 __le16 key2_off;
2243 __le16 key2_len;
2244 __le16 flags;
2245 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2246 /* response flags */
2247 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2248 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2249 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2250 u8 resreved[6];
2251 };
2252
2253 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure_A0);
2254
2255 struct i40e_aqc_tunnel_key_structure {
2256 u8 key1_off;
2257 u8 key2_off;
2258 u8 key1_len; /* 0 to 15 */
2259 u8 key2_len; /* 0 to 15 */
2260 u8 flags;
2261 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01
2262 /* response flags */
2263 #define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01
2264 #define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02
2265 #define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03
2266 u8 network_key_index;
2267 #define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0
2268 #define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1
2269 #define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2
2270 #define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3
2271 u8 reserved[10];
2272 };
2273
2274 I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure);
2275
2276 /* OEM mode commands (direct 0xFE0x) */
2277 struct i40e_aqc_oem_param_change {
2278 __le32 param_type;
2279 #define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0
2280 #define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1
2281 #define I40E_AQ_OEM_PARAM_MAC 2
2282 __le32 param_value1;
2283 __le16 param_value2;
2284 u8 reserved[6];
2285 };
2286
2287 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change);
2288
2289 struct i40e_aqc_oem_state_change {
2290 __le32 state;
2291 #define I40E_AQ_OEM_STATE_LINK_DOWN 0x0
2292 #define I40E_AQ_OEM_STATE_LINK_UP 0x1
2293 u8 reserved[12];
2294 };
2295
2296 I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change);
2297
2298 /* Initialize OCSD (0xFE02, direct) */
2299 struct i40e_aqc_opc_oem_ocsd_initialize {
2300 u8 type_status;
2301 u8 reserved1[3];
2302 __le32 ocsd_memory_block_addr_high;
2303 __le32 ocsd_memory_block_addr_low;
2304 __le32 requested_update_interval;
2305 };
2306
2307 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize);
2308
2309 /* Initialize OCBB (0xFE03, direct) */
2310 struct i40e_aqc_opc_oem_ocbb_initialize {
2311 u8 type_status;
2312 u8 reserved1[3];
2313 __le32 ocbb_memory_block_addr_high;
2314 __le32 ocbb_memory_block_addr_low;
2315 u8 reserved2[4];
2316 };
2317
2318 I40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize);
2319
2320 /* debug commands */
2321
2322 /* get device id (0xFF00) uses the generic structure */
2323
2324 /* set test more (0xFF01, internal) */
2325
2326 struct i40e_acq_set_test_mode {
2327 u8 mode;
2328 #define I40E_AQ_TEST_PARTIAL 0
2329 #define I40E_AQ_TEST_FULL 1
2330 #define I40E_AQ_TEST_NVM 2
2331 u8 reserved[3];
2332 u8 command;
2333 #define I40E_AQ_TEST_OPEN 0
2334 #define I40E_AQ_TEST_CLOSE 1
2335 #define I40E_AQ_TEST_INC 2
2336 u8 reserved2[3];
2337 __le32 address_high;
2338 __le32 address_low;
2339 };
2340
2341 I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode);
2342
2343 /* Debug Read Register command (0xFF03)
2344 * Debug Write Register command (0xFF04)
2345 */
2346 struct i40e_aqc_debug_reg_read_write {
2347 __le32 reserved;
2348 __le32 address;
2349 __le32 value_high;
2350 __le32 value_low;
2351 };
2352
2353 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write);
2354
2355 /* Scatter/gather Reg Read (indirect 0xFF05)
2356 * Scatter/gather Reg Write (indirect 0xFF06)
2357 */
2358
2359 /* i40e_aq_desc is used for the command */
2360 struct i40e_aqc_debug_reg_sg_element_data {
2361 __le32 address;
2362 __le32 value;
2363 };
2364
2365 /* Debug Modify register (direct 0xFF07) */
2366 struct i40e_aqc_debug_modify_reg {
2367 __le32 address;
2368 __le32 value;
2369 __le32 clear_mask;
2370 __le32 set_mask;
2371 };
2372
2373 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg);
2374
2375 /* dump internal data (0xFF08, indirect) */
2376
2377 #define I40E_AQ_CLUSTER_ID_AUX 0
2378 #define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1
2379 #define I40E_AQ_CLUSTER_ID_TXSCHED 2
2380 #define I40E_AQ_CLUSTER_ID_HMC 3
2381 #define I40E_AQ_CLUSTER_ID_MAC0 4
2382 #define I40E_AQ_CLUSTER_ID_MAC1 5
2383 #define I40E_AQ_CLUSTER_ID_MAC2 6
2384 #define I40E_AQ_CLUSTER_ID_MAC3 7
2385 #define I40E_AQ_CLUSTER_ID_DCB 8
2386 #define I40E_AQ_CLUSTER_ID_EMP_MEM 9
2387 #define I40E_AQ_CLUSTER_ID_PKT_BUF 10
2388 #define I40E_AQ_CLUSTER_ID_ALTRAM 11
2389
2390 struct i40e_aqc_debug_dump_internals {
2391 u8 cluster_id;
2392 u8 table_id;
2393 __le16 data_size;
2394 __le32 idx;
2395 __le32 address_high;
2396 __le32 address_low;
2397 };
2398
2399 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals);
2400
2401 struct i40e_aqc_debug_modify_internals {
2402 u8 cluster_id;
2403 u8 cluster_specific_params[7];
2404 __le32 address_high;
2405 __le32 address_low;
2406 };
2407
2408 I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals);
2409
2410 #endif /* _I40E_ADMINQ_CMD_H_ */
Linux with added FPC-III support