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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / net / ethernet / mediatek / mtk_eth_soc.c
blobe0b68afea56e7695ed0de5122cc027c683aefb46
1 /* This program is free software; you can redistribute it and/or modify
2 * it under the terms of the GNU General Public License as published by
3 * the Free Software Foundation; version 2 of the License
4 *
5 * This program is distributed in the hope that it will be useful,
6 * but WITHOUT ANY WARRANTY; without even the implied warranty of
7 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
8 * GNU General Public License for more details.
9 *
10 * Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
11 * Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
12 * Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
13 */
14
15 #include <linux/of_device.h>
16 #include <linux/of_mdio.h>
17 #include <linux/of_net.h>
18 #include <linux/mfd/syscon.h>
19 #include <linux/regmap.h>
20 #include <linux/clk.h>
21 #include <linux/if_vlan.h>
22 #include <linux/reset.h>
23 #include <linux/tcp.h>
24
25 #include "mtk_eth_soc.h"
26
27 static int mtk_msg_level = -1;
28 module_param_named(msg_level, mtk_msg_level, int, 0);
29 MODULE_PARM_DESC(msg_level, "Message level (-1=defaults,0=none,...,16=all)");
30
31 #define MTK_ETHTOOL_STAT(x) { #x, \
32 offsetof(struct mtk_hw_stats, x) / sizeof(u64) }
33
34 /* strings used by ethtool */
35 static const struct mtk_ethtool_stats {
36 char str[ETH_GSTRING_LEN];
37 u32 offset;
38 } mtk_ethtool_stats[] = {
39 MTK_ETHTOOL_STAT(tx_bytes),
40 MTK_ETHTOOL_STAT(tx_packets),
41 MTK_ETHTOOL_STAT(tx_skip),
42 MTK_ETHTOOL_STAT(tx_collisions),
43 MTK_ETHTOOL_STAT(rx_bytes),
44 MTK_ETHTOOL_STAT(rx_packets),
45 MTK_ETHTOOL_STAT(rx_overflow),
46 MTK_ETHTOOL_STAT(rx_fcs_errors),
47 MTK_ETHTOOL_STAT(rx_short_errors),
48 MTK_ETHTOOL_STAT(rx_long_errors),
49 MTK_ETHTOOL_STAT(rx_checksum_errors),
50 MTK_ETHTOOL_STAT(rx_flow_control_packets),
51 };
52
53 void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg)
54 {
55 __raw_writel(val, eth->base + reg);
56 }
57
58 u32 mtk_r32(struct mtk_eth *eth, unsigned reg)
59 {
60 return __raw_readl(eth->base + reg);
61 }
62
63 static int mtk_mdio_busy_wait(struct mtk_eth *eth)
64 {
65 unsigned long t_start = jiffies;
66
67 while (1) {
68 if (!(mtk_r32(eth, MTK_PHY_IAC) & PHY_IAC_ACCESS))
69 return 0;
70 if (time_after(jiffies, t_start + PHY_IAC_TIMEOUT))
71 break;
72 usleep_range(10, 20);
73 }
74
75 dev_err(eth->dev, "mdio: MDIO timeout\n");
76 return -1;
77 }
78
79 u32 _mtk_mdio_write(struct mtk_eth *eth, u32 phy_addr,
80 u32 phy_register, u32 write_data)
81 {
82 if (mtk_mdio_busy_wait(eth))
83 return -1;
84
85 write_data &= 0xffff;
86
87 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_WRITE |
88 (phy_register << PHY_IAC_REG_SHIFT) |
89 (phy_addr << PHY_IAC_ADDR_SHIFT) | write_data,
90 MTK_PHY_IAC);
91
92 if (mtk_mdio_busy_wait(eth))
93 return -1;
94
95 return 0;
96 }
97
98 u32 _mtk_mdio_read(struct mtk_eth *eth, int phy_addr, int phy_reg)
99 {
100 u32 d;
101
102 if (mtk_mdio_busy_wait(eth))
103 return 0xffff;
104
105 mtk_w32(eth, PHY_IAC_ACCESS | PHY_IAC_START | PHY_IAC_READ |
106 (phy_reg << PHY_IAC_REG_SHIFT) |
107 (phy_addr << PHY_IAC_ADDR_SHIFT),
108 MTK_PHY_IAC);
109
110 if (mtk_mdio_busy_wait(eth))
111 return 0xffff;
112
113 d = mtk_r32(eth, MTK_PHY_IAC) & 0xffff;
114
115 return d;
116 }
117
118 static int mtk_mdio_write(struct mii_bus *bus, int phy_addr,
119 int phy_reg, u16 val)
120 {
121 struct mtk_eth *eth = bus->priv;
122
123 return _mtk_mdio_write(eth, phy_addr, phy_reg, val);
124 }
125
126 static int mtk_mdio_read(struct mii_bus *bus, int phy_addr, int phy_reg)
127 {
128 struct mtk_eth *eth = bus->priv;
129
130 return _mtk_mdio_read(eth, phy_addr, phy_reg);
131 }
132
133 static void mtk_phy_link_adjust(struct net_device *dev)
134 {
135 struct mtk_mac *mac = netdev_priv(dev);
136 u32 mcr = MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG |
137 MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN |
138 MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN |
139 MAC_MCR_BACKPR_EN;
140
141 switch (mac->phy_dev->speed) {
142 case SPEED_1000:
143 mcr |= MAC_MCR_SPEED_1000;
144 break;
145 case SPEED_100:
146 mcr |= MAC_MCR_SPEED_100;
147 break;
148 };
149
150 if (mac->phy_dev->link)
151 mcr |= MAC_MCR_FORCE_LINK;
152
153 if (mac->phy_dev->duplex)
154 mcr |= MAC_MCR_FORCE_DPX;
155
156 if (mac->phy_dev->pause)
157 mcr |= MAC_MCR_FORCE_RX_FC | MAC_MCR_FORCE_TX_FC;
158
159 mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
160
161 if (mac->phy_dev->link)
162 netif_carrier_on(dev);
163 else
164 netif_carrier_off(dev);
165 }
166
167 static int mtk_phy_connect_node(struct mtk_eth *eth, struct mtk_mac *mac,
168 struct device_node *phy_node)
169 {
170 const __be32 *_addr = NULL;
171 struct phy_device *phydev;
172 int phy_mode, addr;
173
174 _addr = of_get_property(phy_node, "reg", NULL);
175
176 if (!_addr || (be32_to_cpu(*_addr) >= 0x20)) {
177 pr_err("%s: invalid phy address\n", phy_node->name);
178 return -EINVAL;
179 }
180 addr = be32_to_cpu(*_addr);
181 phy_mode = of_get_phy_mode(phy_node);
182 if (phy_mode < 0) {
183 dev_err(eth->dev, "incorrect phy-mode %d\n", phy_mode);
184 return -EINVAL;
185 }
186
187 phydev = of_phy_connect(eth->netdev[mac->id], phy_node,
188 mtk_phy_link_adjust, 0, phy_mode);
189 if (!phydev) {
190 dev_err(eth->dev, "could not connect to PHY\n");
191 return -ENODEV;
192 }
193
194 dev_info(eth->dev,
195 "connected mac %d to PHY at %s [uid=%08x, driver=%s]\n",
196 mac->id, phydev_name(phydev), phydev->phy_id,
197 phydev->drv->name);
198
199 mac->phy_dev = phydev;
200
201 return 0;
202 }
203
204 static int mtk_phy_connect(struct mtk_mac *mac)
205 {
206 struct mtk_eth *eth = mac->hw;
207 struct device_node *np;
208 u32 val, ge_mode;
209
210 np = of_parse_phandle(mac->of_node, "phy-handle", 0);
211 if (!np)
212 return -ENODEV;
213
214 switch (of_get_phy_mode(np)) {
215 case PHY_INTERFACE_MODE_RGMII:
216 ge_mode = 0;
217 break;
218 case PHY_INTERFACE_MODE_MII:
219 ge_mode = 1;
220 break;
221 case PHY_INTERFACE_MODE_RMII:
222 ge_mode = 2;
223 break;
224 default:
225 dev_err(eth->dev, "invalid phy_mode\n");
226 return -1;
227 }
228
229 /* put the gmac into the right mode */
230 regmap_read(eth->ethsys, ETHSYS_SYSCFG0, &val);
231 val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
232 val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
233 regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
234
235 mtk_phy_connect_node(eth, mac, np);
236 mac->phy_dev->autoneg = AUTONEG_ENABLE;
237 mac->phy_dev->speed = 0;
238 mac->phy_dev->duplex = 0;
239 mac->phy_dev->supported &= PHY_BASIC_FEATURES;
240 mac->phy_dev->advertising = mac->phy_dev->supported |
241 ADVERTISED_Autoneg;
242 phy_start_aneg(mac->phy_dev);
243
244 return 0;
245 }
246
247 static int mtk_mdio_init(struct mtk_eth *eth)
248 {
249 struct device_node *mii_np;
250 int err;
251
252 mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
253 if (!mii_np) {
254 dev_err(eth->dev, "no %s child node found", "mdio-bus");
255 return -ENODEV;
256 }
257
258 if (!of_device_is_available(mii_np)) {
259 err = 0;
260 goto err_put_node;
261 }
262
263 eth->mii_bus = mdiobus_alloc();
264 if (!eth->mii_bus) {
265 err = -ENOMEM;
266 goto err_put_node;
267 }
268
269 eth->mii_bus->name = "mdio";
270 eth->mii_bus->read = mtk_mdio_read;
271 eth->mii_bus->write = mtk_mdio_write;
272 eth->mii_bus->priv = eth;
273 eth->mii_bus->parent = eth->dev;
274
275 snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%s", mii_np->name);
276 err = of_mdiobus_register(eth->mii_bus, mii_np);
277 if (err)
278 goto err_free_bus;
279
280 return 0;
281
282 err_free_bus:
283 kfree(eth->mii_bus);
284
285 err_put_node:
286 of_node_put(mii_np);
287 eth->mii_bus = NULL;
288 return err;
289 }
290
291 static void mtk_mdio_cleanup(struct mtk_eth *eth)
292 {
293 if (!eth->mii_bus)
294 return;
295
296 mdiobus_unregister(eth->mii_bus);
297 of_node_put(eth->mii_bus->dev.of_node);
298 kfree(eth->mii_bus);
299 }
300
301 static inline void mtk_irq_disable(struct mtk_eth *eth, u32 mask)
302 {
303 u32 val;
304
305 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
306 mtk_w32(eth, val & ~mask, MTK_QDMA_INT_MASK);
307 /* flush write */
308 mtk_r32(eth, MTK_QDMA_INT_MASK);
309 }
310
311 static inline void mtk_irq_enable(struct mtk_eth *eth, u32 mask)
312 {
313 u32 val;
314
315 val = mtk_r32(eth, MTK_QDMA_INT_MASK);
316 mtk_w32(eth, val | mask, MTK_QDMA_INT_MASK);
317 /* flush write */
318 mtk_r32(eth, MTK_QDMA_INT_MASK);
319 }
320
321 static int mtk_set_mac_address(struct net_device *dev, void *p)
322 {
323 int ret = eth_mac_addr(dev, p);
324 struct mtk_mac *mac = netdev_priv(dev);
325 const char *macaddr = dev->dev_addr;
326 unsigned long flags;
327
328 if (ret)
329 return ret;
330
331 spin_lock_irqsave(&mac->hw->page_lock, flags);
332 mtk_w32(mac->hw, (macaddr[0] << 8) | macaddr[1],
333 MTK_GDMA_MAC_ADRH(mac->id));
334 mtk_w32(mac->hw, (macaddr[2] << 24) | (macaddr[3] << 16) |
335 (macaddr[4] << 8) | macaddr[5],
336 MTK_GDMA_MAC_ADRL(mac->id));
337 spin_unlock_irqrestore(&mac->hw->page_lock, flags);
338
339 return 0;
340 }
341
342 void mtk_stats_update_mac(struct mtk_mac *mac)
343 {
344 struct mtk_hw_stats *hw_stats = mac->hw_stats;
345 unsigned int base = MTK_GDM1_TX_GBCNT;
346 u64 stats;
347
348 base += hw_stats->reg_offset;
349
350 u64_stats_update_begin(&hw_stats->syncp);
351
352 hw_stats->rx_bytes += mtk_r32(mac->hw, base);
353 stats = mtk_r32(mac->hw, base + 0x04);
354 if (stats)
355 hw_stats->rx_bytes += (stats << 32);
356 hw_stats->rx_packets += mtk_r32(mac->hw, base + 0x08);
357 hw_stats->rx_overflow += mtk_r32(mac->hw, base + 0x10);
358 hw_stats->rx_fcs_errors += mtk_r32(mac->hw, base + 0x14);
359 hw_stats->rx_short_errors += mtk_r32(mac->hw, base + 0x18);
360 hw_stats->rx_long_errors += mtk_r32(mac->hw, base + 0x1c);
361 hw_stats->rx_checksum_errors += mtk_r32(mac->hw, base + 0x20);
362 hw_stats->rx_flow_control_packets +=
363 mtk_r32(mac->hw, base + 0x24);
364 hw_stats->tx_skip += mtk_r32(mac->hw, base + 0x28);
365 hw_stats->tx_collisions += mtk_r32(mac->hw, base + 0x2c);
366 hw_stats->tx_bytes += mtk_r32(mac->hw, base + 0x30);
367 stats = mtk_r32(mac->hw, base + 0x34);
368 if (stats)
369 hw_stats->tx_bytes += (stats << 32);
370 hw_stats->tx_packets += mtk_r32(mac->hw, base + 0x38);
371 u64_stats_update_end(&hw_stats->syncp);
372 }
373
374 static void mtk_stats_update(struct mtk_eth *eth)
375 {
376 int i;
377
378 for (i = 0; i < MTK_MAC_COUNT; i++) {
379 if (!eth->mac[i] || !eth->mac[i]->hw_stats)
380 continue;
381 if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
382 mtk_stats_update_mac(eth->mac[i]);
383 spin_unlock(&eth->mac[i]->hw_stats->stats_lock);
384 }
385 }
386 }
387
388 static struct rtnl_link_stats64 *mtk_get_stats64(struct net_device *dev,
389 struct rtnl_link_stats64 *storage)
390 {
391 struct mtk_mac *mac = netdev_priv(dev);
392 struct mtk_hw_stats *hw_stats = mac->hw_stats;
393 unsigned int start;
394
395 if (netif_running(dev) && netif_device_present(dev)) {
396 if (spin_trylock(&hw_stats->stats_lock)) {
397 mtk_stats_update_mac(mac);
398 spin_unlock(&hw_stats->stats_lock);
399 }
400 }
401
402 do {
403 start = u64_stats_fetch_begin_irq(&hw_stats->syncp);
404 storage->rx_packets = hw_stats->rx_packets;
405 storage->tx_packets = hw_stats->tx_packets;
406 storage->rx_bytes = hw_stats->rx_bytes;
407 storage->tx_bytes = hw_stats->tx_bytes;
408 storage->collisions = hw_stats->tx_collisions;
409 storage->rx_length_errors = hw_stats->rx_short_errors +
410 hw_stats->rx_long_errors;
411 storage->rx_over_errors = hw_stats->rx_overflow;
412 storage->rx_crc_errors = hw_stats->rx_fcs_errors;
413 storage->rx_errors = hw_stats->rx_checksum_errors;
414 storage->tx_aborted_errors = hw_stats->tx_skip;
415 } while (u64_stats_fetch_retry_irq(&hw_stats->syncp, start));
416
417 storage->tx_errors = dev->stats.tx_errors;
418 storage->rx_dropped = dev->stats.rx_dropped;
419 storage->tx_dropped = dev->stats.tx_dropped;
420
421 return storage;
422 }
423
424 static inline int mtk_max_frag_size(int mtu)
425 {
426 /* make sure buf_size will be at least MTK_MAX_RX_LENGTH */
427 if (mtu + MTK_RX_ETH_HLEN < MTK_MAX_RX_LENGTH)
428 mtu = MTK_MAX_RX_LENGTH - MTK_RX_ETH_HLEN;
429
430 return SKB_DATA_ALIGN(MTK_RX_HLEN + mtu) +
431 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
432 }
433
434 static inline int mtk_max_buf_size(int frag_size)
435 {
436 int buf_size = frag_size - NET_SKB_PAD - NET_IP_ALIGN -
437 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
438
439 WARN_ON(buf_size < MTK_MAX_RX_LENGTH);
440
441 return buf_size;
442 }
443
444 static inline void mtk_rx_get_desc(struct mtk_rx_dma *rxd,
445 struct mtk_rx_dma *dma_rxd)
446 {
447 rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
448 rxd->rxd2 = READ_ONCE(dma_rxd->rxd2);
449 rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
450 rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
451 }
452
453 /* the qdma core needs scratch memory to be setup */
454 static int mtk_init_fq_dma(struct mtk_eth *eth)
455 {
456 dma_addr_t phy_ring_head, phy_ring_tail;
457 int cnt = MTK_DMA_SIZE;
458 dma_addr_t dma_addr;
459 int i;
460
461 eth->scratch_ring = dma_alloc_coherent(eth->dev,
462 cnt * sizeof(struct mtk_tx_dma),
463 &phy_ring_head,
464 GFP_ATOMIC | __GFP_ZERO);
465 if (unlikely(!eth->scratch_ring))
466 return -ENOMEM;
467
468 eth->scratch_head = kcalloc(cnt, MTK_QDMA_PAGE_SIZE,
469 GFP_KERNEL);
470 dma_addr = dma_map_single(eth->dev,
471 eth->scratch_head, cnt * MTK_QDMA_PAGE_SIZE,
472 DMA_FROM_DEVICE);
473 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
474 return -ENOMEM;
475
476 memset(eth->scratch_ring, 0x0, sizeof(struct mtk_tx_dma) * cnt);
477 phy_ring_tail = phy_ring_head +
478 (sizeof(struct mtk_tx_dma) * (cnt - 1));
479
480 for (i = 0; i < cnt; i++) {
481 eth->scratch_ring[i].txd1 =
482 (dma_addr + (i * MTK_QDMA_PAGE_SIZE));
483 if (i < cnt - 1)
484 eth->scratch_ring[i].txd2 = (phy_ring_head +
485 ((i + 1) * sizeof(struct mtk_tx_dma)));
486 eth->scratch_ring[i].txd3 = TX_DMA_SDL(MTK_QDMA_PAGE_SIZE);
487 }
488
489 mtk_w32(eth, phy_ring_head, MTK_QDMA_FQ_HEAD);
490 mtk_w32(eth, phy_ring_tail, MTK_QDMA_FQ_TAIL);
491 mtk_w32(eth, (cnt << 16) | cnt, MTK_QDMA_FQ_CNT);
492 mtk_w32(eth, MTK_QDMA_PAGE_SIZE << 16, MTK_QDMA_FQ_BLEN);
493
494 return 0;
495 }
496
497 static inline void *mtk_qdma_phys_to_virt(struct mtk_tx_ring *ring, u32 desc)
498 {
499 void *ret = ring->dma;
500
501 return ret + (desc - ring->phys);
502 }
503
504 static inline struct mtk_tx_buf *mtk_desc_to_tx_buf(struct mtk_tx_ring *ring,
505 struct mtk_tx_dma *txd)
506 {
507 int idx = txd - ring->dma;
508
509 return &ring->buf[idx];
510 }
511
512 static void mtk_tx_unmap(struct device *dev, struct mtk_tx_buf *tx_buf)
513 {
514 if (tx_buf->flags & MTK_TX_FLAGS_SINGLE0) {
515 dma_unmap_single(dev,
516 dma_unmap_addr(tx_buf, dma_addr0),
517 dma_unmap_len(tx_buf, dma_len0),
518 DMA_TO_DEVICE);
519 } else if (tx_buf->flags & MTK_TX_FLAGS_PAGE0) {
520 dma_unmap_page(dev,
521 dma_unmap_addr(tx_buf, dma_addr0),
522 dma_unmap_len(tx_buf, dma_len0),
523 DMA_TO_DEVICE);
524 }
525 tx_buf->flags = 0;
526 if (tx_buf->skb &&
527 (tx_buf->skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC))
528 dev_kfree_skb_any(tx_buf->skb);
529 tx_buf->skb = NULL;
530 }
531
532 static int mtk_tx_map(struct sk_buff *skb, struct net_device *dev,
533 int tx_num, struct mtk_tx_ring *ring, bool gso)
534 {
535 struct mtk_mac *mac = netdev_priv(dev);
536 struct mtk_eth *eth = mac->hw;
537 struct mtk_tx_dma *itxd, *txd;
538 struct mtk_tx_buf *tx_buf;
539 unsigned long flags;
540 dma_addr_t mapped_addr;
541 unsigned int nr_frags;
542 int i, n_desc = 1;
543 u32 txd4 = 0;
544
545 itxd = ring->next_free;
546 if (itxd == ring->last_free)
547 return -ENOMEM;
548
549 /* set the forward port */
550 txd4 |= (mac->id + 1) << TX_DMA_FPORT_SHIFT;
551
552 tx_buf = mtk_desc_to_tx_buf(ring, itxd);
553 memset(tx_buf, 0, sizeof(*tx_buf));
554
555 if (gso)
556 txd4 |= TX_DMA_TSO;
557
558 /* TX Checksum offload */
559 if (skb->ip_summed == CHECKSUM_PARTIAL)
560 txd4 |= TX_DMA_CHKSUM;
561
562 /* VLAN header offload */
563 if (skb_vlan_tag_present(skb))
564 txd4 |= TX_DMA_INS_VLAN | skb_vlan_tag_get(skb);
565
566 mapped_addr = dma_map_single(&dev->dev, skb->data,
567 skb_headlen(skb), DMA_TO_DEVICE);
568 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
569 return -ENOMEM;
570
571 /* normally we can rely on the stack not calling this more than once,
572 * however we have 2 queues running ont he same ring so we need to lock
573 * the ring access
574 */
575 spin_lock_irqsave(&eth->page_lock, flags);
576 WRITE_ONCE(itxd->txd1, mapped_addr);
577 tx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
578 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
579 dma_unmap_len_set(tx_buf, dma_len0, skb_headlen(skb));
580
581 /* TX SG offload */
582 txd = itxd;
583 nr_frags = skb_shinfo(skb)->nr_frags;
584 for (i = 0; i < nr_frags; i++) {
585 struct skb_frag_struct *frag = &skb_shinfo(skb)->frags[i];
586 unsigned int offset = 0;
587 int frag_size = skb_frag_size(frag);
588
589 while (frag_size) {
590 bool last_frag = false;
591 unsigned int frag_map_size;
592
593 txd = mtk_qdma_phys_to_virt(ring, txd->txd2);
594 if (txd == ring->last_free)
595 goto err_dma;
596
597 n_desc++;
598 frag_map_size = min(frag_size, MTK_TX_DMA_BUF_LEN);
599 mapped_addr = skb_frag_dma_map(&dev->dev, frag, offset,
600 frag_map_size,
601 DMA_TO_DEVICE);
602 if (unlikely(dma_mapping_error(&dev->dev, mapped_addr)))
603 goto err_dma;
604
605 if (i == nr_frags - 1 &&
606 (frag_size - frag_map_size) == 0)
607 last_frag = true;
608
609 WRITE_ONCE(txd->txd1, mapped_addr);
610 WRITE_ONCE(txd->txd3, (TX_DMA_SWC |
611 TX_DMA_PLEN0(frag_map_size) |
612 last_frag * TX_DMA_LS0) |
613 mac->id);
614 WRITE_ONCE(txd->txd4, 0);
615
616 tx_buf->skb = (struct sk_buff *)MTK_DMA_DUMMY_DESC;
617 tx_buf = mtk_desc_to_tx_buf(ring, txd);
618 memset(tx_buf, 0, sizeof(*tx_buf));
619
620 tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
621 dma_unmap_addr_set(tx_buf, dma_addr0, mapped_addr);
622 dma_unmap_len_set(tx_buf, dma_len0, frag_map_size);
623 frag_size -= frag_map_size;
624 offset += frag_map_size;
625 }
626 }
627
628 /* store skb to cleanup */
629 tx_buf->skb = skb;
630
631 WRITE_ONCE(itxd->txd4, txd4);
632 WRITE_ONCE(itxd->txd3, (TX_DMA_SWC | TX_DMA_PLEN0(skb_headlen(skb)) |
633 (!nr_frags * TX_DMA_LS0)));
634
635 spin_unlock_irqrestore(&eth->page_lock, flags);
636
637 netdev_sent_queue(dev, skb->len);
638 skb_tx_timestamp(skb);
639
640 ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
641 atomic_sub(n_desc, &ring->free_count);
642
643 /* make sure that all changes to the dma ring are flushed before we
644 * continue
645 */
646 wmb();
647
648 if (netif_xmit_stopped(netdev_get_tx_queue(dev, 0)) || !skb->xmit_more)
649 mtk_w32(eth, txd->txd2, MTK_QTX_CTX_PTR);
650
651 return 0;
652
653 err_dma:
654 do {
655 tx_buf = mtk_desc_to_tx_buf(ring, txd);
656
657 /* unmap dma */
658 mtk_tx_unmap(&dev->dev, tx_buf);
659
660 itxd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
661 itxd = mtk_qdma_phys_to_virt(ring, itxd->txd2);
662 } while (itxd != txd);
663
664 spin_unlock_irqrestore(&eth->page_lock, flags);
665
666 return -ENOMEM;
667 }
668
669 static inline int mtk_cal_txd_req(struct sk_buff *skb)
670 {
671 int i, nfrags;
672 struct skb_frag_struct *frag;
673
674 nfrags = 1;
675 if (skb_is_gso(skb)) {
676 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
677 frag = &skb_shinfo(skb)->frags[i];
678 nfrags += DIV_ROUND_UP(frag->size, MTK_TX_DMA_BUF_LEN);
679 }
680 } else {
681 nfrags += skb_shinfo(skb)->nr_frags;
682 }
683
684 return DIV_ROUND_UP(nfrags, 2);
685 }
686
687 static int mtk_start_xmit(struct sk_buff *skb, struct net_device *dev)
688 {
689 struct mtk_mac *mac = netdev_priv(dev);
690 struct mtk_eth *eth = mac->hw;
691 struct mtk_tx_ring *ring = &eth->tx_ring;
692 struct net_device_stats *stats = &dev->stats;
693 bool gso = false;
694 int tx_num;
695
696 tx_num = mtk_cal_txd_req(skb);
697 if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
698 netif_stop_queue(dev);
699 netif_err(eth, tx_queued, dev,
700 "Tx Ring full when queue awake!\n");
701 return NETDEV_TX_BUSY;
702 }
703
704 /* TSO: fill MSS info in tcp checksum field */
705 if (skb_is_gso(skb)) {
706 if (skb_cow_head(skb, 0)) {
707 netif_warn(eth, tx_err, dev,
708 "GSO expand head fail.\n");
709 goto drop;
710 }
711
712 if (skb_shinfo(skb)->gso_type &
713 (SKB_GSO_TCPV4 | SKB_GSO_TCPV6)) {
714 gso = true;
715 tcp_hdr(skb)->check = htons(skb_shinfo(skb)->gso_size);
716 }
717 }
718
719 if (mtk_tx_map(skb, dev, tx_num, ring, gso) < 0)
720 goto drop;
721
722 if (unlikely(atomic_read(&ring->free_count) <= ring->thresh)) {
723 netif_stop_queue(dev);
724 if (unlikely(atomic_read(&ring->free_count) >
725 ring->thresh))
726 netif_wake_queue(dev);
727 }
728
729 return NETDEV_TX_OK;
730
731 drop:
732 stats->tx_dropped++;
733 dev_kfree_skb(skb);
734 return NETDEV_TX_OK;
735 }
736
737 static int mtk_poll_rx(struct napi_struct *napi, int budget,
738 struct mtk_eth *eth, u32 rx_intr)
739 {
740 struct mtk_rx_ring *ring = &eth->rx_ring;
741 int idx = ring->calc_idx;
742 struct sk_buff *skb;
743 u8 *data, *new_data;
744 struct mtk_rx_dma *rxd, trxd;
745 int done = 0;
746
747 while (done < budget) {
748 struct net_device *netdev;
749 unsigned int pktlen;
750 dma_addr_t dma_addr;
751 int mac = 0;
752
753 idx = NEXT_RX_DESP_IDX(idx);
754 rxd = &ring->dma[idx];
755 data = ring->data[idx];
756
757 mtk_rx_get_desc(&trxd, rxd);
758 if (!(trxd.rxd2 & RX_DMA_DONE))
759 break;
760
761 /* find out which mac the packet come from. values start at 1 */
762 mac = (trxd.rxd4 >> RX_DMA_FPORT_SHIFT) &
763 RX_DMA_FPORT_MASK;
764 mac--;
765
766 netdev = eth->netdev[mac];
767
768 /* alloc new buffer */
769 new_data = napi_alloc_frag(ring->frag_size);
770 if (unlikely(!new_data)) {
771 netdev->stats.rx_dropped++;
772 goto release_desc;
773 }
774 dma_addr = dma_map_single(&eth->netdev[mac]->dev,
775 new_data + NET_SKB_PAD,
776 ring->buf_size,
777 DMA_FROM_DEVICE);
778 if (unlikely(dma_mapping_error(&netdev->dev, dma_addr))) {
779 skb_free_frag(new_data);
780 goto release_desc;
781 }
782
783 /* receive data */
784 skb = build_skb(data, ring->frag_size);
785 if (unlikely(!skb)) {
786 put_page(virt_to_head_page(new_data));
787 goto release_desc;
788 }
789 skb_reserve(skb, NET_SKB_PAD + NET_IP_ALIGN);
790
791 dma_unmap_single(&netdev->dev, trxd.rxd1,
792 ring->buf_size, DMA_FROM_DEVICE);
793 pktlen = RX_DMA_GET_PLEN0(trxd.rxd2);
794 skb->dev = netdev;
795 skb_put(skb, pktlen);
796 if (trxd.rxd4 & RX_DMA_L4_VALID)
797 skb->ip_summed = CHECKSUM_UNNECESSARY;
798 else
799 skb_checksum_none_assert(skb);
800 skb->protocol = eth_type_trans(skb, netdev);
801
802 if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX &&
803 RX_DMA_VID(trxd.rxd3))
804 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
805 RX_DMA_VID(trxd.rxd3));
806 napi_gro_receive(napi, skb);
807
808 ring->data[idx] = new_data;
809 rxd->rxd1 = (unsigned int)dma_addr;
810
811 release_desc:
812 rxd->rxd2 = RX_DMA_PLEN0(ring->buf_size);
813
814 ring->calc_idx = idx;
815 /* make sure that all changes to the dma ring are flushed before
816 * we continue
817 */
818 wmb();
819 mtk_w32(eth, ring->calc_idx, MTK_QRX_CRX_IDX0);
820 done++;
821 }
822
823 if (done < budget)
824 mtk_w32(eth, rx_intr, MTK_QMTK_INT_STATUS);
825
826 return done;
827 }
828
829 static int mtk_poll_tx(struct mtk_eth *eth, int budget, bool *tx_again)
830 {
831 struct mtk_tx_ring *ring = &eth->tx_ring;
832 struct mtk_tx_dma *desc;
833 struct sk_buff *skb;
834 struct mtk_tx_buf *tx_buf;
835 int total = 0, done[MTK_MAX_DEVS];
836 unsigned int bytes[MTK_MAX_DEVS];
837 u32 cpu, dma;
838 static int condition;
839 int i;
840
841 memset(done, 0, sizeof(done));
842 memset(bytes, 0, sizeof(bytes));
843
844 cpu = mtk_r32(eth, MTK_QTX_CRX_PTR);
845 dma = mtk_r32(eth, MTK_QTX_DRX_PTR);
846
847 desc = mtk_qdma_phys_to_virt(ring, cpu);
848
849 while ((cpu != dma) && budget) {
850 u32 next_cpu = desc->txd2;
851 int mac;
852
853 desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
854 if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
855 break;
856
857 mac = (desc->txd4 >> TX_DMA_FPORT_SHIFT) &
858 TX_DMA_FPORT_MASK;
859 mac--;
860
861 tx_buf = mtk_desc_to_tx_buf(ring, desc);
862 skb = tx_buf->skb;
863 if (!skb) {
864 condition = 1;
865 break;
866 }
867
868 if (skb != (struct sk_buff *)MTK_DMA_DUMMY_DESC) {
869 bytes[mac] += skb->len;
870 done[mac]++;
871 budget--;
872 }
873 mtk_tx_unmap(eth->dev, tx_buf);
874
875 ring->last_free->txd2 = next_cpu;
876 ring->last_free = desc;
877 atomic_inc(&ring->free_count);
878
879 cpu = next_cpu;
880 }
881
882 mtk_w32(eth, cpu, MTK_QTX_CRX_PTR);
883
884 for (i = 0; i < MTK_MAC_COUNT; i++) {
885 if (!eth->netdev[i] || !done[i])
886 continue;
887 netdev_completed_queue(eth->netdev[i], done[i], bytes[i]);
888 total += done[i];
889 }
890
891 /* read hw index again make sure no new tx packet */
892 if (cpu != dma || cpu != mtk_r32(eth, MTK_QTX_DRX_PTR))
893 *tx_again = true;
894 else
895 mtk_w32(eth, MTK_TX_DONE_INT, MTK_QMTK_INT_STATUS);
896
897 if (!total)
898 return 0;
899
900 for (i = 0; i < MTK_MAC_COUNT; i++) {
901 if (!eth->netdev[i] ||
902 unlikely(!netif_queue_stopped(eth->netdev[i])))
903 continue;
904 if (atomic_read(&ring->free_count) > ring->thresh)
905 netif_wake_queue(eth->netdev[i]);
906 }
907
908 return total;
909 }
910
911 static int mtk_poll(struct napi_struct *napi, int budget)
912 {
913 struct mtk_eth *eth = container_of(napi, struct mtk_eth, rx_napi);
914 u32 status, status2, mask, tx_intr, rx_intr, status_intr;
915 int tx_done, rx_done;
916 bool tx_again = false;
917
918 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
919 status2 = mtk_r32(eth, MTK_INT_STATUS2);
920 tx_intr = MTK_TX_DONE_INT;
921 rx_intr = MTK_RX_DONE_INT;
922 status_intr = (MTK_GDM1_AF | MTK_GDM2_AF);
923 tx_done = 0;
924 rx_done = 0;
925 tx_again = 0;
926
927 if (status & tx_intr)
928 tx_done = mtk_poll_tx(eth, budget, &tx_again);
929
930 if (status & rx_intr)
931 rx_done = mtk_poll_rx(napi, budget, eth, rx_intr);
932
933 if (unlikely(status2 & status_intr)) {
934 mtk_stats_update(eth);
935 mtk_w32(eth, status_intr, MTK_INT_STATUS2);
936 }
937
938 if (unlikely(netif_msg_intr(eth))) {
939 mask = mtk_r32(eth, MTK_QDMA_INT_MASK);
940 netdev_info(eth->netdev[0],
941 "done tx %d, rx %d, intr 0x%08x/0x%x\n",
942 tx_done, rx_done, status, mask);
943 }
944
945 if (tx_again || rx_done == budget)
946 return budget;
947
948 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
949 if (status & (tx_intr | rx_intr))
950 return budget;
951
952 napi_complete(napi);
953 mtk_irq_enable(eth, tx_intr | rx_intr);
954
955 return rx_done;
956 }
957
958 static int mtk_tx_alloc(struct mtk_eth *eth)
959 {
960 struct mtk_tx_ring *ring = &eth->tx_ring;
961 int i, sz = sizeof(*ring->dma);
962
963 ring->buf = kcalloc(MTK_DMA_SIZE, sizeof(*ring->buf),
964 GFP_KERNEL);
965 if (!ring->buf)
966 goto no_tx_mem;
967
968 ring->dma = dma_alloc_coherent(eth->dev,
969 MTK_DMA_SIZE * sz,
970 &ring->phys,
971 GFP_ATOMIC | __GFP_ZERO);
972 if (!ring->dma)
973 goto no_tx_mem;
974
975 memset(ring->dma, 0, MTK_DMA_SIZE * sz);
976 for (i = 0; i < MTK_DMA_SIZE; i++) {
977 int next = (i + 1) % MTK_DMA_SIZE;
978 u32 next_ptr = ring->phys + next * sz;
979
980 ring->dma[i].txd2 = next_ptr;
981 ring->dma[i].txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
982 }
983
984 atomic_set(&ring->free_count, MTK_DMA_SIZE - 2);
985 ring->next_free = &ring->dma[0];
986 ring->last_free = &ring->dma[MTK_DMA_SIZE - 2];
987 ring->thresh = max((unsigned long)MTK_DMA_SIZE >> 2,
988 MAX_SKB_FRAGS);
989
990 /* make sure that all changes to the dma ring are flushed before we
991 * continue
992 */
993 wmb();
994
995 mtk_w32(eth, ring->phys, MTK_QTX_CTX_PTR);
996 mtk_w32(eth, ring->phys, MTK_QTX_DTX_PTR);
997 mtk_w32(eth,
998 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
999 MTK_QTX_CRX_PTR);
1000 mtk_w32(eth,
1001 ring->phys + ((MTK_DMA_SIZE - 1) * sz),
1002 MTK_QTX_DRX_PTR);
1003
1004 return 0;
1005
1006 no_tx_mem:
1007 return -ENOMEM;
1008 }
1009
1010 static void mtk_tx_clean(struct mtk_eth *eth)
1011 {
1012 struct mtk_tx_ring *ring = &eth->tx_ring;
1013 int i;
1014
1015 if (ring->buf) {
1016 for (i = 0; i < MTK_DMA_SIZE; i++)
1017 mtk_tx_unmap(eth->dev, &ring->buf[i]);
1018 kfree(ring->buf);
1019 ring->buf = NULL;
1020 }
1021
1022 if (ring->dma) {
1023 dma_free_coherent(eth->dev,
1024 MTK_DMA_SIZE * sizeof(*ring->dma),
1025 ring->dma,
1026 ring->phys);
1027 ring->dma = NULL;
1028 }
1029 }
1030
1031 static int mtk_rx_alloc(struct mtk_eth *eth)
1032 {
1033 struct mtk_rx_ring *ring = &eth->rx_ring;
1034 int i;
1035
1036 ring->frag_size = mtk_max_frag_size(ETH_DATA_LEN);
1037 ring->buf_size = mtk_max_buf_size(ring->frag_size);
1038 ring->data = kcalloc(MTK_DMA_SIZE, sizeof(*ring->data),
1039 GFP_KERNEL);
1040 if (!ring->data)
1041 return -ENOMEM;
1042
1043 for (i = 0; i < MTK_DMA_SIZE; i++) {
1044 ring->data[i] = netdev_alloc_frag(ring->frag_size);
1045 if (!ring->data[i])
1046 return -ENOMEM;
1047 }
1048
1049 ring->dma = dma_alloc_coherent(eth->dev,
1050 MTK_DMA_SIZE * sizeof(*ring->dma),
1051 &ring->phys,
1052 GFP_ATOMIC | __GFP_ZERO);
1053 if (!ring->dma)
1054 return -ENOMEM;
1055
1056 for (i = 0; i < MTK_DMA_SIZE; i++) {
1057 dma_addr_t dma_addr = dma_map_single(eth->dev,
1058 ring->data[i] + NET_SKB_PAD,
1059 ring->buf_size,
1060 DMA_FROM_DEVICE);
1061 if (unlikely(dma_mapping_error(eth->dev, dma_addr)))
1062 return -ENOMEM;
1063 ring->dma[i].rxd1 = (unsigned int)dma_addr;
1064
1065 ring->dma[i].rxd2 = RX_DMA_PLEN0(ring->buf_size);
1066 }
1067 ring->calc_idx = MTK_DMA_SIZE - 1;
1068 /* make sure that all changes to the dma ring are flushed before we
1069 * continue
1070 */
1071 wmb();
1072
1073 mtk_w32(eth, eth->rx_ring.phys, MTK_QRX_BASE_PTR0);
1074 mtk_w32(eth, MTK_DMA_SIZE, MTK_QRX_MAX_CNT0);
1075 mtk_w32(eth, eth->rx_ring.calc_idx, MTK_QRX_CRX_IDX0);
1076 mtk_w32(eth, MTK_PST_DRX_IDX0, MTK_QDMA_RST_IDX);
1077 mtk_w32(eth, (QDMA_RES_THRES << 8) | QDMA_RES_THRES, MTK_QTX_CFG(0));
1078
1079 return 0;
1080 }
1081
1082 static void mtk_rx_clean(struct mtk_eth *eth)
1083 {
1084 struct mtk_rx_ring *ring = &eth->rx_ring;
1085 int i;
1086
1087 if (ring->data && ring->dma) {
1088 for (i = 0; i < MTK_DMA_SIZE; i++) {
1089 if (!ring->data[i])
1090 continue;
1091 if (!ring->dma[i].rxd1)
1092 continue;
1093 dma_unmap_single(eth->dev,
1094 ring->dma[i].rxd1,
1095 ring->buf_size,
1096 DMA_FROM_DEVICE);
1097 skb_free_frag(ring->data[i]);
1098 }
1099 kfree(ring->data);
1100 ring->data = NULL;
1101 }
1102
1103 if (ring->dma) {
1104 dma_free_coherent(eth->dev,
1105 MTK_DMA_SIZE * sizeof(*ring->dma),
1106 ring->dma,
1107 ring->phys);
1108 ring->dma = NULL;
1109 }
1110 }
1111
1112 /* wait for DMA to finish whatever it is doing before we start using it again */
1113 static int mtk_dma_busy_wait(struct mtk_eth *eth)
1114 {
1115 unsigned long t_start = jiffies;
1116
1117 while (1) {
1118 if (!(mtk_r32(eth, MTK_QDMA_GLO_CFG) &
1119 (MTK_RX_DMA_BUSY | MTK_TX_DMA_BUSY)))
1120 return 0;
1121 if (time_after(jiffies, t_start + MTK_DMA_BUSY_TIMEOUT))
1122 break;
1123 }
1124
1125 dev_err(eth->dev, "DMA init timeout\n");
1126 return -1;
1127 }
1128
1129 static int mtk_dma_init(struct mtk_eth *eth)
1130 {
1131 int err;
1132
1133 if (mtk_dma_busy_wait(eth))
1134 return -EBUSY;
1135
1136 /* QDMA needs scratch memory for internal reordering of the
1137 * descriptors
1138 */
1139 err = mtk_init_fq_dma(eth);
1140 if (err)
1141 return err;
1142
1143 err = mtk_tx_alloc(eth);
1144 if (err)
1145 return err;
1146
1147 err = mtk_rx_alloc(eth);
1148 if (err)
1149 return err;
1150
1151 /* Enable random early drop and set drop threshold automatically */
1152 mtk_w32(eth, FC_THRES_DROP_MODE | FC_THRES_DROP_EN | FC_THRES_MIN,
1153 MTK_QDMA_FC_THRES);
1154 mtk_w32(eth, 0x0, MTK_QDMA_HRED2);
1155
1156 return 0;
1157 }
1158
1159 static void mtk_dma_free(struct mtk_eth *eth)
1160 {
1161 int i;
1162
1163 for (i = 0; i < MTK_MAC_COUNT; i++)
1164 if (eth->netdev[i])
1165 netdev_reset_queue(eth->netdev[i]);
1166 mtk_tx_clean(eth);
1167 mtk_rx_clean(eth);
1168 kfree(eth->scratch_head);
1169 }
1170
1171 static void mtk_tx_timeout(struct net_device *dev)
1172 {
1173 struct mtk_mac *mac = netdev_priv(dev);
1174 struct mtk_eth *eth = mac->hw;
1175
1176 eth->netdev[mac->id]->stats.tx_errors++;
1177 netif_err(eth, tx_err, dev,
1178 "transmit timed out\n");
1179 schedule_work(&mac->pending_work);
1180 }
1181
1182 static irqreturn_t mtk_handle_irq(int irq, void *_eth)
1183 {
1184 struct mtk_eth *eth = _eth;
1185 u32 status;
1186
1187 status = mtk_r32(eth, MTK_QMTK_INT_STATUS);
1188 if (unlikely(!status))
1189 return IRQ_NONE;
1190
1191 if (likely(status & (MTK_RX_DONE_INT | MTK_TX_DONE_INT))) {
1192 if (likely(napi_schedule_prep(&eth->rx_napi)))
1193 __napi_schedule(&eth->rx_napi);
1194 } else {
1195 mtk_w32(eth, status, MTK_QMTK_INT_STATUS);
1196 }
1197 mtk_irq_disable(eth, (MTK_RX_DONE_INT | MTK_TX_DONE_INT));
1198
1199 return IRQ_HANDLED;
1200 }
1201
1202 #ifdef CONFIG_NET_POLL_CONTROLLER
1203 static void mtk_poll_controller(struct net_device *dev)
1204 {
1205 struct mtk_mac *mac = netdev_priv(dev);
1206 struct mtk_eth *eth = mac->hw;
1207 u32 int_mask = MTK_TX_DONE_INT | MTK_RX_DONE_INT;
1208
1209 mtk_irq_disable(eth, int_mask);
1210 mtk_handle_irq(dev->irq, dev);
1211 mtk_irq_enable(eth, int_mask);
1212 }
1213 #endif
1214
1215 static int mtk_start_dma(struct mtk_eth *eth)
1216 {
1217 int err;
1218
1219 err = mtk_dma_init(eth);
1220 if (err) {
1221 mtk_dma_free(eth);
1222 return err;
1223 }
1224
1225 mtk_w32(eth,
1226 MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN |
1227 MTK_RX_2B_OFFSET | MTK_DMA_SIZE_16DWORDS |
1228 MTK_RX_BT_32DWORDS,
1229 MTK_QDMA_GLO_CFG);
1230
1231 return 0;
1232 }
1233
1234 static int mtk_open(struct net_device *dev)
1235 {
1236 struct mtk_mac *mac = netdev_priv(dev);
1237 struct mtk_eth *eth = mac->hw;
1238
1239 /* we run 2 netdevs on the same dma ring so we only bring it up once */
1240 if (!atomic_read(&eth->dma_refcnt)) {
1241 int err = mtk_start_dma(eth);
1242
1243 if (err)
1244 return err;
1245
1246 napi_enable(&eth->rx_napi);
1247 mtk_irq_enable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1248 }
1249 atomic_inc(&eth->dma_refcnt);
1250
1251 phy_start(mac->phy_dev);
1252 netif_start_queue(dev);
1253
1254 return 0;
1255 }
1256
1257 static void mtk_stop_dma(struct mtk_eth *eth, u32 glo_cfg)
1258 {
1259 unsigned long flags;
1260 u32 val;
1261 int i;
1262
1263 /* stop the dma engine */
1264 spin_lock_irqsave(&eth->page_lock, flags);
1265 val = mtk_r32(eth, glo_cfg);
1266 mtk_w32(eth, val & ~(MTK_TX_WB_DDONE | MTK_RX_DMA_EN | MTK_TX_DMA_EN),
1267 glo_cfg);
1268 spin_unlock_irqrestore(&eth->page_lock, flags);
1269
1270 /* wait for dma stop */
1271 for (i = 0; i < 10; i++) {
1272 val = mtk_r32(eth, glo_cfg);
1273 if (val & (MTK_TX_DMA_BUSY | MTK_RX_DMA_BUSY)) {
1274 msleep(20);
1275 continue;
1276 }
1277 break;
1278 }
1279 }
1280
1281 static int mtk_stop(struct net_device *dev)
1282 {
1283 struct mtk_mac *mac = netdev_priv(dev);
1284 struct mtk_eth *eth = mac->hw;
1285
1286 netif_tx_disable(dev);
1287 phy_stop(mac->phy_dev);
1288
1289 /* only shutdown DMA if this is the last user */
1290 if (!atomic_dec_and_test(&eth->dma_refcnt))
1291 return 0;
1292
1293 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1294 napi_disable(&eth->rx_napi);
1295
1296 mtk_stop_dma(eth, MTK_QDMA_GLO_CFG);
1297
1298 mtk_dma_free(eth);
1299
1300 return 0;
1301 }
1302
1303 static int __init mtk_hw_init(struct mtk_eth *eth)
1304 {
1305 int err, i;
1306
1307 /* reset the frame engine */
1308 reset_control_assert(eth->rstc);
1309 usleep_range(10, 20);
1310 reset_control_deassert(eth->rstc);
1311 usleep_range(10, 20);
1312
1313 /* Set GE2 driving and slew rate */
1314 regmap_write(eth->pctl, GPIO_DRV_SEL10, 0xa00);
1315
1316 /* set GE2 TDSEL */
1317 regmap_write(eth->pctl, GPIO_OD33_CTRL8, 0x5);
1318
1319 /* set GE2 TUNE */
1320 regmap_write(eth->pctl, GPIO_BIAS_CTRL, 0x0);
1321
1322 /* GE1, Force 1000M/FD, FC ON */
1323 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(0));
1324
1325 /* GE2, Force 1000M/FD, FC ON */
1326 mtk_w32(eth, MAC_MCR_FIXED_LINK, MTK_MAC_MCR(1));
1327
1328 /* Enable RX VLan Offloading */
1329 mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
1330
1331 err = devm_request_irq(eth->dev, eth->irq, mtk_handle_irq, 0,
1332 dev_name(eth->dev), eth);
1333 if (err)
1334 return err;
1335
1336 err = mtk_mdio_init(eth);
1337 if (err)
1338 return err;
1339
1340 /* disable delay and normal interrupt */
1341 mtk_w32(eth, 0, MTK_QDMA_DELAY_INT);
1342 mtk_irq_disable(eth, MTK_TX_DONE_INT | MTK_RX_DONE_INT);
1343 mtk_w32(eth, RST_GL_PSE, MTK_RST_GL);
1344 mtk_w32(eth, 0, MTK_RST_GL);
1345
1346 /* FE int grouping */
1347 mtk_w32(eth, 0, MTK_FE_INT_GRP);
1348
1349 for (i = 0; i < 2; i++) {
1350 u32 val = mtk_r32(eth, MTK_GDMA_FWD_CFG(i));
1351
1352 /* setup the forward port to send frame to QDMA */
1353 val &= ~0xffff;
1354 val |= 0x5555;
1355
1356 /* Enable RX checksum */
1357 val |= MTK_GDMA_ICS_EN | MTK_GDMA_TCS_EN | MTK_GDMA_UCS_EN;
1358
1359 /* setup the mac dma */
1360 mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
1361 }
1362
1363 return 0;
1364 }
1365
1366 static int __init mtk_init(struct net_device *dev)
1367 {
1368 struct mtk_mac *mac = netdev_priv(dev);
1369 struct mtk_eth *eth = mac->hw;
1370 const char *mac_addr;
1371
1372 mac_addr = of_get_mac_address(mac->of_node);
1373 if (mac_addr)
1374 ether_addr_copy(dev->dev_addr, mac_addr);
1375
1376 /* If the mac address is invalid, use random mac address */
1377 if (!is_valid_ether_addr(dev->dev_addr)) {
1378 random_ether_addr(dev->dev_addr);
1379 dev_err(eth->dev, "generated random MAC address %pM\n",
1380 dev->dev_addr);
1381 dev->addr_assign_type = NET_ADDR_RANDOM;
1382 }
1383
1384 return mtk_phy_connect(mac);
1385 }
1386
1387 static void mtk_uninit(struct net_device *dev)
1388 {
1389 struct mtk_mac *mac = netdev_priv(dev);
1390 struct mtk_eth *eth = mac->hw;
1391
1392 phy_disconnect(mac->phy_dev);
1393 mtk_mdio_cleanup(eth);
1394 mtk_irq_disable(eth, ~0);
1395 free_irq(dev->irq, dev);
1396 }
1397
1398 static int mtk_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1399 {
1400 struct mtk_mac *mac = netdev_priv(dev);
1401
1402 switch (cmd) {
1403 case SIOCGMIIPHY:
1404 case SIOCGMIIREG:
1405 case SIOCSMIIREG:
1406 return phy_mii_ioctl(mac->phy_dev, ifr, cmd);
1407 default:
1408 break;
1409 }
1410
1411 return -EOPNOTSUPP;
1412 }
1413
1414 static void mtk_pending_work(struct work_struct *work)
1415 {
1416 struct mtk_mac *mac = container_of(work, struct mtk_mac, pending_work);
1417 struct mtk_eth *eth = mac->hw;
1418 struct net_device *dev = eth->netdev[mac->id];
1419 int err;
1420
1421 rtnl_lock();
1422 mtk_stop(dev);
1423
1424 err = mtk_open(dev);
1425 if (err) {
1426 netif_alert(eth, ifup, dev,
1427 "Driver up/down cycle failed, closing device.\n");
1428 dev_close(dev);
1429 }
1430 rtnl_unlock();
1431 }
1432
1433 static int mtk_cleanup(struct mtk_eth *eth)
1434 {
1435 int i;
1436
1437 for (i = 0; i < MTK_MAC_COUNT; i++) {
1438 struct mtk_mac *mac = netdev_priv(eth->netdev[i]);
1439
1440 if (!eth->netdev[i])
1441 continue;
1442
1443 unregister_netdev(eth->netdev[i]);
1444 free_netdev(eth->netdev[i]);
1445 cancel_work_sync(&mac->pending_work);
1446 }
1447
1448 return 0;
1449 }
1450
1451 static int mtk_get_settings(struct net_device *dev,
1452 struct ethtool_cmd *cmd)
1453 {
1454 struct mtk_mac *mac = netdev_priv(dev);
1455 int err;
1456
1457 err = phy_read_status(mac->phy_dev);
1458 if (err)
1459 return -ENODEV;
1460
1461 return phy_ethtool_gset(mac->phy_dev, cmd);
1462 }
1463
1464 static int mtk_set_settings(struct net_device *dev,
1465 struct ethtool_cmd *cmd)
1466 {
1467 struct mtk_mac *mac = netdev_priv(dev);
1468
1469 if (cmd->phy_address != mac->phy_dev->mdio.addr) {
1470 mac->phy_dev = mdiobus_get_phy(mac->hw->mii_bus,
1471 cmd->phy_address);
1472 if (!mac->phy_dev)
1473 return -ENODEV;
1474 }
1475
1476 return phy_ethtool_sset(mac->phy_dev, cmd);
1477 }
1478
1479 static void mtk_get_drvinfo(struct net_device *dev,
1480 struct ethtool_drvinfo *info)
1481 {
1482 struct mtk_mac *mac = netdev_priv(dev);
1483
1484 strlcpy(info->driver, mac->hw->dev->driver->name, sizeof(info->driver));
1485 strlcpy(info->bus_info, dev_name(mac->hw->dev), sizeof(info->bus_info));
1486 info->n_stats = ARRAY_SIZE(mtk_ethtool_stats);
1487 }
1488
1489 static u32 mtk_get_msglevel(struct net_device *dev)
1490 {
1491 struct mtk_mac *mac = netdev_priv(dev);
1492
1493 return mac->hw->msg_enable;
1494 }
1495
1496 static void mtk_set_msglevel(struct net_device *dev, u32 value)
1497 {
1498 struct mtk_mac *mac = netdev_priv(dev);
1499
1500 mac->hw->msg_enable = value;
1501 }
1502
1503 static int mtk_nway_reset(struct net_device *dev)
1504 {
1505 struct mtk_mac *mac = netdev_priv(dev);
1506
1507 return genphy_restart_aneg(mac->phy_dev);
1508 }
1509
1510 static u32 mtk_get_link(struct net_device *dev)
1511 {
1512 struct mtk_mac *mac = netdev_priv(dev);
1513 int err;
1514
1515 err = genphy_update_link(mac->phy_dev);
1516 if (err)
1517 return ethtool_op_get_link(dev);
1518
1519 return mac->phy_dev->link;
1520 }
1521
1522 static void mtk_get_strings(struct net_device *dev, u32 stringset, u8 *data)
1523 {
1524 int i;
1525
1526 switch (stringset) {
1527 case ETH_SS_STATS:
1528 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++) {
1529 memcpy(data, mtk_ethtool_stats[i].str, ETH_GSTRING_LEN);
1530 data += ETH_GSTRING_LEN;
1531 }
1532 break;
1533 }
1534 }
1535
1536 static int mtk_get_sset_count(struct net_device *dev, int sset)
1537 {
1538 switch (sset) {
1539 case ETH_SS_STATS:
1540 return ARRAY_SIZE(mtk_ethtool_stats);
1541 default:
1542 return -EOPNOTSUPP;
1543 }
1544 }
1545
1546 static void mtk_get_ethtool_stats(struct net_device *dev,
1547 struct ethtool_stats *stats, u64 *data)
1548 {
1549 struct mtk_mac *mac = netdev_priv(dev);
1550 struct mtk_hw_stats *hwstats = mac->hw_stats;
1551 u64 *data_src, *data_dst;
1552 unsigned int start;
1553 int i;
1554
1555 if (netif_running(dev) && netif_device_present(dev)) {
1556 if (spin_trylock(&hwstats->stats_lock)) {
1557 mtk_stats_update_mac(mac);
1558 spin_unlock(&hwstats->stats_lock);
1559 }
1560 }
1561
1562 do {
1563 data_src = (u64*)hwstats;
1564 data_dst = data;
1565 start = u64_stats_fetch_begin_irq(&hwstats->syncp);
1566
1567 for (i = 0; i < ARRAY_SIZE(mtk_ethtool_stats); i++)
1568 *data_dst++ = *(data_src + mtk_ethtool_stats[i].offset);
1569 } while (u64_stats_fetch_retry_irq(&hwstats->syncp, start));
1570 }
1571
1572 static struct ethtool_ops mtk_ethtool_ops = {
1573 .get_settings = mtk_get_settings,
1574 .set_settings = mtk_set_settings,
1575 .get_drvinfo = mtk_get_drvinfo,
1576 .get_msglevel = mtk_get_msglevel,
1577 .set_msglevel = mtk_set_msglevel,
1578 .nway_reset = mtk_nway_reset,
1579 .get_link = mtk_get_link,
1580 .get_strings = mtk_get_strings,
1581 .get_sset_count = mtk_get_sset_count,
1582 .get_ethtool_stats = mtk_get_ethtool_stats,
1583 };
1584
1585 static const struct net_device_ops mtk_netdev_ops = {
1586 .ndo_init = mtk_init,
1587 .ndo_uninit = mtk_uninit,
1588 .ndo_open = mtk_open,
1589 .ndo_stop = mtk_stop,
1590 .ndo_start_xmit = mtk_start_xmit,
1591 .ndo_set_mac_address = mtk_set_mac_address,
1592 .ndo_validate_addr = eth_validate_addr,
1593 .ndo_do_ioctl = mtk_do_ioctl,
1594 .ndo_change_mtu = eth_change_mtu,
1595 .ndo_tx_timeout = mtk_tx_timeout,
1596 .ndo_get_stats64 = mtk_get_stats64,
1597 #ifdef CONFIG_NET_POLL_CONTROLLER
1598 .ndo_poll_controller = mtk_poll_controller,
1599 #endif
1600 };
1601
1602 static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
1603 {
1604 struct mtk_mac *mac;
1605 const __be32 *_id = of_get_property(np, "reg", NULL);
1606 int id, err;
1607
1608 if (!_id) {
1609 dev_err(eth->dev, "missing mac id\n");
1610 return -EINVAL;
1611 }
1612
1613 id = be32_to_cpup(_id);
1614 if (id >= MTK_MAC_COUNT) {
1615 dev_err(eth->dev, "%d is not a valid mac id\n", id);
1616 return -EINVAL;
1617 }
1618
1619 if (eth->netdev[id]) {
1620 dev_err(eth->dev, "duplicate mac id found: %d\n", id);
1621 return -EINVAL;
1622 }
1623
1624 eth->netdev[id] = alloc_etherdev(sizeof(*mac));
1625 if (!eth->netdev[id]) {
1626 dev_err(eth->dev, "alloc_etherdev failed\n");
1627 return -ENOMEM;
1628 }
1629 mac = netdev_priv(eth->netdev[id]);
1630 eth->mac[id] = mac;
1631 mac->id = id;
1632 mac->hw = eth;
1633 mac->of_node = np;
1634 INIT_WORK(&mac->pending_work, mtk_pending_work);
1635
1636 mac->hw_stats = devm_kzalloc(eth->dev,
1637 sizeof(*mac->hw_stats),
1638 GFP_KERNEL);
1639 if (!mac->hw_stats) {
1640 dev_err(eth->dev, "failed to allocate counter memory\n");
1641 err = -ENOMEM;
1642 goto free_netdev;
1643 }
1644 spin_lock_init(&mac->hw_stats->stats_lock);
1645 mac->hw_stats->reg_offset = id * MTK_STAT_OFFSET;
1646
1647 SET_NETDEV_DEV(eth->netdev[id], eth->dev);
1648 eth->netdev[id]->netdev_ops = &mtk_netdev_ops;
1649 eth->netdev[id]->base_addr = (unsigned long)eth->base;
1650 eth->netdev[id]->vlan_features = MTK_HW_FEATURES &
1651 ~(NETIF_F_HW_VLAN_CTAG_TX | NETIF_F_HW_VLAN_CTAG_RX);
1652 eth->netdev[id]->features |= MTK_HW_FEATURES;
1653 eth->netdev[id]->ethtool_ops = &mtk_ethtool_ops;
1654
1655 err = register_netdev(eth->netdev[id]);
1656 if (err) {
1657 dev_err(eth->dev, "error bringing up device\n");
1658 goto free_netdev;
1659 }
1660 eth->netdev[id]->irq = eth->irq;
1661 netif_info(eth, probe, eth->netdev[id],
1662 "mediatek frame engine at 0x%08lx, irq %d\n",
1663 eth->netdev[id]->base_addr, eth->netdev[id]->irq);
1664
1665 return 0;
1666
1667 free_netdev:
1668 free_netdev(eth->netdev[id]);
1669 return err;
1670 }
1671
1672 static int mtk_probe(struct platform_device *pdev)
1673 {
1674 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1675 struct device_node *mac_np;
1676 const struct of_device_id *match;
1677 struct mtk_soc_data *soc;
1678 struct mtk_eth *eth;
1679 int err;
1680
1681 err = device_reset(&pdev->dev);
1682 if (err)
1683 return err;
1684
1685 match = of_match_device(of_mtk_match, &pdev->dev);
1686 soc = (struct mtk_soc_data *)match->data;
1687
1688 eth = devm_kzalloc(&pdev->dev, sizeof(*eth), GFP_KERNEL);
1689 if (!eth)
1690 return -ENOMEM;
1691
1692 eth->base = devm_ioremap_resource(&pdev->dev, res);
1693 if (IS_ERR(eth->base))
1694 return PTR_ERR(eth->base);
1695
1696 spin_lock_init(&eth->page_lock);
1697
1698 eth->ethsys = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1699 "mediatek,ethsys");
1700 if (IS_ERR(eth->ethsys)) {
1701 dev_err(&pdev->dev, "no ethsys regmap found\n");
1702 return PTR_ERR(eth->ethsys);
1703 }
1704
1705 eth->pctl = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
1706 "mediatek,pctl");
1707 if (IS_ERR(eth->pctl)) {
1708 dev_err(&pdev->dev, "no pctl regmap found\n");
1709 return PTR_ERR(eth->pctl);
1710 }
1711
1712 eth->rstc = devm_reset_control_get(&pdev->dev, "eth");
1713 if (IS_ERR(eth->rstc)) {
1714 dev_err(&pdev->dev, "no eth reset found\n");
1715 return PTR_ERR(eth->rstc);
1716 }
1717
1718 eth->irq = platform_get_irq(pdev, 0);
1719 if (eth->irq < 0) {
1720 dev_err(&pdev->dev, "no IRQ resource found\n");
1721 return -ENXIO;
1722 }
1723
1724 eth->clk_ethif = devm_clk_get(&pdev->dev, "ethif");
1725 eth->clk_esw = devm_clk_get(&pdev->dev, "esw");
1726 eth->clk_gp1 = devm_clk_get(&pdev->dev, "gp1");
1727 eth->clk_gp2 = devm_clk_get(&pdev->dev, "gp2");
1728 if (IS_ERR(eth->clk_esw) || IS_ERR(eth->clk_gp1) ||
1729 IS_ERR(eth->clk_gp2) || IS_ERR(eth->clk_ethif))
1730 return -ENODEV;
1731
1732 clk_prepare_enable(eth->clk_ethif);
1733 clk_prepare_enable(eth->clk_esw);
1734 clk_prepare_enable(eth->clk_gp1);
1735 clk_prepare_enable(eth->clk_gp2);
1736
1737 eth->dev = &pdev->dev;
1738 eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
1739
1740 err = mtk_hw_init(eth);
1741 if (err)
1742 return err;
1743
1744 for_each_child_of_node(pdev->dev.of_node, mac_np) {
1745 if (!of_device_is_compatible(mac_np,
1746 "mediatek,eth-mac"))
1747 continue;
1748
1749 if (!of_device_is_available(mac_np))
1750 continue;
1751
1752 err = mtk_add_mac(eth, mac_np);
1753 if (err)
1754 goto err_free_dev;
1755 }
1756
1757 /* we run 2 devices on the same DMA ring so we need a dummy device
1758 * for NAPI to work
1759 */
1760 init_dummy_netdev(&eth->dummy_dev);
1761 netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_poll,
1762 MTK_NAPI_WEIGHT);
1763
1764 platform_set_drvdata(pdev, eth);
1765
1766 return 0;
1767
1768 err_free_dev:
1769 mtk_cleanup(eth);
1770 return err;
1771 }
1772
1773 static int mtk_remove(struct platform_device *pdev)
1774 {
1775 struct mtk_eth *eth = platform_get_drvdata(pdev);
1776
1777 clk_disable_unprepare(eth->clk_ethif);
1778 clk_disable_unprepare(eth->clk_esw);
1779 clk_disable_unprepare(eth->clk_gp1);
1780 clk_disable_unprepare(eth->clk_gp2);
1781
1782 netif_napi_del(&eth->rx_napi);
1783 mtk_cleanup(eth);
1784 platform_set_drvdata(pdev, NULL);
1785
1786 return 0;
1787 }
1788
1789 const struct of_device_id of_mtk_match[] = {
1790 { .compatible = "mediatek,mt7623-eth" },
1791 {},
1792 };
1793
1794 static struct platform_driver mtk_driver = {
1795 .probe = mtk_probe,
1796 .remove = mtk_remove,
1797 .driver = {
1798 .name = "mtk_soc_eth",
1799 .owner = THIS_MODULE,
1800 .of_match_table = of_mtk_match,
1801 },
1802 };
1803
1804 module_platform_driver(mtk_driver);
1805
1806 MODULE_LICENSE("GPL");
1807 MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
1808 MODULE_DESCRIPTION("Ethernet driver for MediaTek SoC");
Linux with added FPC-III support