1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
30 #ifndef __RTL92C_PHY_H__
31 #define __RTL92C_PHY_H__
33 #define MAX_PRECMD_CNT 16
34 #define MAX_RFDEPENDCMD_CNT 16
35 #define MAX_POSTCMD_CNT 16
37 #define MAX_DOZE_WAITING_TIMES_9x 64
39 #define RT_CANNOT_IO(hw) false
40 #define HIGHPOWER_RADIOA_ARRAYLEN 22
42 #define MAX_TOLERANCE 5
44 #define APK_BB_REG_NUM 5
45 #define APK_AFE_REG_NUM 16
46 #define APK_CURVE_REG_NUM 4
50 #define MAX_STALL_TIME 50
51 #define AntennaDiversityValue 0x80
52 #define MAX_TXPWR_IDX_NMODE_92S 63
53 #define Reset_Cnt_Limit 3
55 #define IQK_ADDA_REG_NUM 16
56 #define IQK_MAC_REG_NUM 4
58 #define IQK_DELAY_TIME 1
60 #define RF90_PATH_MAX 2
62 #define CT_OFFSET_MAC_ADDR 0X16
64 #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
65 #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
66 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIF 0x66
67 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
68 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
70 #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
71 #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
73 #define CT_OFFSET_CHANNEL_PLAH 0x75
74 #define CT_OFFSET_THERMAL_METER 0x78
75 #define CT_OFFSET_RF_OPTION 0x79
76 #define CT_OFFSET_VERSION 0x7E
77 #define CT_OFFSET_CUSTOMER_ID 0x7F
79 #define RTL92C_MAX_PATH_NUM 2
81 bool rtl92c_phy_bb_config(struct ieee80211_hw
*hw
);
82 u32
rtl92c_phy_query_bb_reg(struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
);
83 void rtl92c_phy_set_bb_reg(struct ieee80211_hw
*hw
, u32 regaddr
, u32 bitmask
,
85 u32
rtl92c_phy_query_rf_reg(struct ieee80211_hw
*hw
, enum radio_path rfpath
,
86 u32 regaddr
, u32 bitmask
);
87 void rtl92ce_phy_set_rf_reg(struct ieee80211_hw
*hw
, enum radio_path rfpath
,
88 u32 regaddr
, u32 bitmask
, u32 data
);
89 bool rtl92c_phy_mac_config(struct ieee80211_hw
*hw
);
90 bool rtl92ce_phy_bb_config(struct ieee80211_hw
*hw
);
91 bool rtl92c_phy_rf_config(struct ieee80211_hw
*hw
);
92 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw
*hw
,
93 enum radio_path rfpath
);
94 void rtl92c_phy_get_hw_reg_originalvalue(struct ieee80211_hw
*hw
);
95 void rtl92c_phy_get_txpower_level(struct ieee80211_hw
*hw
, long *powerlevel
);
96 void rtl92c_phy_set_txpower_level(struct ieee80211_hw
*hw
, u8 channel
);
97 bool rtl92c_phy_update_txpower_dbm(struct ieee80211_hw
*hw
,
99 void rtl92c_phy_set_bw_mode(struct ieee80211_hw
*hw
,
100 enum nl80211_channel_type ch_type
);
101 void rtl92c_phy_sw_chnl_callback(struct ieee80211_hw
*hw
);
102 u8
rtl92c_phy_sw_chnl(struct ieee80211_hw
*hw
);
103 void rtl92c_phy_iq_calibrate(struct ieee80211_hw
*hw
, bool b_recovery
);
104 void rtl92c_phy_set_beacon_hw_reg(struct ieee80211_hw
*hw
, u16 beaconinterval
);
105 void rtl92c_phy_ap_calibrate(struct ieee80211_hw
*hw
, char delta
);
106 void rtl92c_phy_lc_calibrate(struct ieee80211_hw
*hw
);
107 void _rtl92ce_phy_lc_calibrate(struct ieee80211_hw
*hw
, bool is2t
);
108 void rtl92c_phy_set_rfpath_switch(struct ieee80211_hw
*hw
, bool bmain
);
109 bool rtl92c_phy_config_rf_with_headerfile(struct ieee80211_hw
*hw
,
110 enum radio_path rfpath
);
111 bool rtl8192_phy_check_is_legal_rfpath(struct ieee80211_hw
*hw
,
113 bool rtl92ce_phy_set_rf_power_state(struct ieee80211_hw
*hw
,
114 enum rf_pwrstate rfpwr_state
);
115 void rtl92ce_phy_set_rf_on(struct ieee80211_hw
*hw
);
116 bool rtl92c_phy_set_io_cmd(struct ieee80211_hw
*hw
, enum io_type iotype
);
117 void rtl92c_phy_set_io(struct ieee80211_hw
*hw
);
118 void rtl92c_bb_block_on(struct ieee80211_hw
*hw
);
119 u32
_rtl92c_phy_rf_serial_read(struct ieee80211_hw
*hw
, enum radio_path rfpath
,
121 u32
_rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw
*hw
,
122 enum radio_path rfpath
, u32 offset
);
123 u32
_rtl92c_phy_calculate_bit_shift(u32 bitmask
);
124 void _rtl92c_phy_rf_serial_write(struct ieee80211_hw
*hw
,
125 enum radio_path rfpath
, u32 offset
, u32 data
);
126 void _rtl92c_phy_fw_rf_serial_write(struct ieee80211_hw
*hw
,
127 enum radio_path rfpath
, u32 offset
,
129 void _rtl92c_store_pwrIndex_diffrate_offset(struct ieee80211_hw
*hw
,
130 u32 regaddr
, u32 bitmask
, u32 data
);
131 bool _rtl92ce_phy_config_mac_with_headerfile(struct ieee80211_hw
*hw
);
132 void _rtl92c_phy_init_bb_rf_register_definition(struct ieee80211_hw
*hw
);
133 bool _rtl92c_phy_bb8192c_config_parafile(struct ieee80211_hw
*hw
);
134 void _rtl92c_phy_set_rf_sleep(struct ieee80211_hw
*hw
);
135 bool rtl92c_phy_set_rf_power_state(struct ieee80211_hw
*hw
,
136 enum rf_pwrstate rfpwr_state
);
137 bool _rtl92ce_phy_config_bb_with_headerfile(struct ieee80211_hw
*hw
,
139 bool _rtl92ce_phy_config_bb_with_pgheaderfile(struct ieee80211_hw
*hw
,
141 void rtl92ce_phy_set_bw_mode_callback(struct ieee80211_hw
*hw
);