drivers/net/wireless/realtek/rtlwifi/rtl8723ae/def.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2009-2012  Realtek Corporation.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * The full GNU General Public License is included in this distribution in the
  15  * file called LICENSE.
  16  *
  17  * Contact Information:
  18  * wlanfae <wlanfae@realtek.com>
  19  * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  20  * Hsinchu 300, Taiwan.
  21  *
  22  * Larry Finger <Larry.Finger@lwfinger.net>
  23  *
  24  *****************************************************************************/
  25
  26 #ifndef __RTL8723E_DEF_H__
  27 #define __RTL8723E_DEF_H__
  28
  29 #define HAL_PRIME_CHNL_OFFSET_DONT_CARE         0
  30 #define HAL_PRIME_CHNL_OFFSET_LOWER                     1
  31 #define HAL_PRIME_CHNL_OFFSET_UPPER                     2
  32
  33 #define RX_MPDU_QUEUE                                           0
  34 #define RX_CMD_QUEUE                                            1
  35
  36 #define C2H_RX_CMD_HDR_LEN                                      8
  37 #define GET_C2H_CMD_CMD_LEN(__prxhdr)           \
  38         LE_BITS_TO_4BYTE((__prxhdr), 0, 16)
  39 #define GET_C2H_CMD_ELEMENT_ID(__prxhdr)        \
  40         LE_BITS_TO_4BYTE((__prxhdr), 16, 8)
  41 #define GET_C2H_CMD_CMD_SEQ(__prxhdr)           \
  42         LE_BITS_TO_4BYTE((__prxhdr), 24, 7)
  43 #define GET_C2H_CMD_CONTINUE(__prxhdr)          \
  44         LE_BITS_TO_4BYTE((__prxhdr), 31, 1)
  45 #define GET_C2H_CMD_CONTENT(__prxhdr)           \
  46         ((u8 *)(__prxhdr) + C2H_RX_CMD_HDR_LEN)
  47
  48 #define GET_C2H_CMD_FEEDBACK_ELEMENT_ID(__pcmdfbhdr)    \
  49         LE_BITS_TO_4BYTE((__pcmdfbhdr), 0, 8)
  50 #define GET_C2H_CMD_FEEDBACK_CCX_LEN(__pcmdfbhdr)               \
  51         LE_BITS_TO_4BYTE((__pcmdfbhdr), 8, 8)
  52 #define GET_C2H_CMD_FEEDBACK_CCX_CMD_CNT(__pcmdfbhdr)   \
  53         LE_BITS_TO_4BYTE((__pcmdfbhdr), 16, 16)
  54 #define GET_C2H_CMD_FEEDBACK_CCX_MAC_ID(__pcmdfbhdr)    \
  55         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 0, 5)
  56 #define GET_C2H_CMD_FEEDBACK_CCX_VALID(__pcmdfbhdr)             \
  57         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 7, 1)
  58 #define GET_C2H_CMD_FEEDBACK_CCX_RETRY_CNT(__pcmdfbhdr) \
  59         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 8, 5)
  60 #define GET_C2H_CMD_FEEDBACK_CCX_TOK(__pcmdfbhdr)               \
  61         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 15, 1)
  62 #define GET_C2H_CMD_FEEDBACK_CCX_QSEL(__pcmdfbhdr)              \
  63         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 16, 4)
  64 #define GET_C2H_CMD_FEEDBACK_CCX_SEQ(__pcmdfbhdr)               \
  65         LE_BITS_TO_4BYTE(((__pcmdfbhdr) + 4), 20, 12)
  66
  67 #define CHIP_BONDING_IDENTIFIER(_value) (((_value)>>22)&0x3)
  68 #define CHIP_BONDING_92C_1T2R           0x1
  69
  70 #define CHIP_8723               BIT(0)
  71 #define NORMAL_CHIP             BIT(3)
  72 #define RF_TYPE_1T1R            (~(BIT(4)|BIT(5)|BIT(6)))
  73 #define RF_TYPE_1T2R            BIT(4)
  74 #define RF_TYPE_2T2R            BIT(5)
  75 #define CHIP_VENDOR_UMC         BIT(7)
  76 #define B_CUT_VERSION           BIT(12)
  77 #define C_CUT_VERSION           BIT(13)
  78 #define D_CUT_VERSION           ((BIT(12)|BIT(13)))
  79 #define E_CUT_VERSION           BIT(14)
  80 #define RF_RL_ID                (BIT(31)|BIT(30)|BIT(29)|BIT(28))
  81
  82 /* MASK */
  83 #define IC_TYPE_MASK            (BIT(0)|BIT(1)|BIT(2))
  84 #define CHIP_TYPE_MASK          BIT(3)
  85 #define RF_TYPE_MASK            (BIT(4)|BIT(5)|BIT(6))
  86 #define MANUFACTUER_MASK        BIT(7)
  87 #define ROM_VERSION_MASK        (BIT(11)|BIT(10)|BIT(9)|BIT(8))
  88 #define CUT_VERSION_MASK        (BIT(15)|BIT(14)|BIT(13)|BIT(12))
  89
  90 /* Get element */
  91 #define GET_CVID_IC_TYPE(version)       ((version) & IC_TYPE_MASK)
  92 #define GET_CVID_CHIP_TYPE(version)     ((version) & CHIP_TYPE_MASK)
  93 #define GET_CVID_RF_TYPE(version)       ((version) & RF_TYPE_MASK)
  94 #define GET_CVID_MANUFACTUER(version)   ((version) & MANUFACTUER_MASK)
  95 #define GET_CVID_ROM_VERSION(version)   ((version) & ROM_VERSION_MASK)
  96 #define GET_CVID_CUT_VERSION(version)   ((version) & CUT_VERSION_MASK)
  97
  98 #define IS_81XXC(version)       ((GET_CVID_IC_TYPE(version) == 0) ?\
  99                                                 true : false)
 100 #define IS_8723_SERIES(version) ((GET_CVID_IC_TYPE(version) == CHIP_8723) ? \
 101                                                 true : false)
 102 #define IS_1T1R(version)        ((GET_CVID_RF_TYPE(version)) ? false : true)
 103 #define IS_1T2R(version)        ((GET_CVID_RF_TYPE(version) == RF_TYPE_1T2R)\
 104                                                 ? true : false)
 105 #define IS_2T2R(version)        ((GET_CVID_RF_TYPE(version) == RF_TYPE_2T2R)\
 106                                                 ? true : false)
 107 #define IS_CHIP_VENDOR_UMC(version)     ((GET_CVID_MANUFACTUER(version)) ? \
 108                                                 true : false)
 109
 110 #define IS_VENDOR_UMC_A_CUT(version)    ((IS_CHIP_VENDOR_UMC(version))\
 111                                         ? ((GET_CVID_CUT_VERSION(version)) ? \
 112                                         false : true) : false)
 113 #define IS_VENDOR_8723_A_CUT(version)   ((IS_8723_SERIES(version))\
 114                                         ? ((GET_CVID_CUT_VERSION(version)) ? \
 115                                         false : true) : false)
 116 #define IS_VENDOR_8723A_B_CUT(version)  ((IS_8723_SERIES(version))\
 117                 ? ((GET_CVID_CUT_VERSION(version) == \
 118                 B_CUT_VERSION) ? true : false) : false)
 119 #define IS_81xxC_VENDOR_UMC_B_CUT(version)      ((IS_CHIP_VENDOR_UMC(version))\
 120                 ? ((GET_CVID_CUT_VERSION(version) == \
 121                 B_CUT_VERSION) ? true : false) : false)
 122
 123 enum rf_optype {
 124         RF_OP_BY_SW_3WIRE = 0,
 125         RF_OP_BY_FW,
 126         RF_OP_MAX
 127 };
 128
 129 enum rf_power_state {
 130         RF_ON,
 131         RF_OFF,
 132         RF_SLEEP,
 133         RF_SHUT_DOWN,
 134 };
 135
 136 enum power_save_mode {
 137         POWER_SAVE_MODE_ACTIVE,
 138         POWER_SAVE_MODE_SAVE,
 139 };
 140
 141 enum power_policy_config {
 142         POWERCFG_MAX_POWER_SAVINGS,
 143         POWERCFG_GLOBAL_POWER_SAVINGS,
 144         POWERCFG_LOCAL_POWER_SAVINGS,
 145         POWERCFG_LENOVO,
 146 };
 147
 148 enum interface_select_pci {
 149         INTF_SEL1_MINICARD = 0,
 150         INTF_SEL0_PCIE = 1,
 151         INTF_SEL2_RSV = 2,
 152         INTF_SEL3_RSV = 3,
 153 };
 154
 155 enum hal_fw_c2h_cmd_id {
 156         HAL_FW_C2H_CMD_Read_MACREG = 0,
 157         HAL_FW_C2H_CMD_Read_BBREG = 1,
 158         HAL_FW_C2H_CMD_Read_RFREG = 2,
 159         HAL_FW_C2H_CMD_Read_EEPROM = 3,
 160         HAL_FW_C2H_CMD_Read_EFUSE = 4,
 161         HAL_FW_C2H_CMD_Read_CAM = 5,
 162         HAL_FW_C2H_CMD_Get_BasicRate = 6,
 163         HAL_FW_C2H_CMD_Get_DataRate = 7,
 164         HAL_FW_C2H_CMD_Survey = 8,
 165         HAL_FW_C2H_CMD_SurveyDone = 9,
 166         HAL_FW_C2H_CMD_JoinBss = 10,
 167         HAL_FW_C2H_CMD_AddSTA = 11,
 168         HAL_FW_C2H_CMD_DelSTA = 12,
 169         HAL_FW_C2H_CMD_AtimDone = 13,
 170         HAL_FW_C2H_CMD_TX_Report = 14,
 171         HAL_FW_C2H_CMD_CCX_Report = 15,
 172         HAL_FW_C2H_CMD_DTM_Report = 16,
 173         HAL_FW_C2H_CMD_TX_Rate_Statistics = 17,
 174         HAL_FW_C2H_CMD_C2HLBK = 18,
 175         HAL_FW_C2H_CMD_C2HDBG = 19,
 176         HAL_FW_C2H_CMD_C2HFEEDBACK = 20,
 177         HAL_FW_C2H_CMD_MAX
 178 };
 179
 180 enum rtl_desc_qsel {
 181         QSLT_BK = 0x2,
 182         QSLT_BE = 0x0,
 183         QSLT_VI = 0x5,
 184         QSLT_VO = 0x7,
 185         QSLT_BEACON = 0x10,
 186         QSLT_HIGH = 0x11,
 187         QSLT_MGNT = 0x12,
 188         QSLT_CMD = 0x13,
 189 };
 190
 191 enum rtl_desc8723e_rate {
 192         DESC92C_RATE1M = 0x00,
 193         DESC92C_RATE2M = 0x01,
 194         DESC92C_RATE5_5M = 0x02,
 195         DESC92C_RATE11M = 0x03,
 196
 197         DESC92C_RATE6M = 0x04,
 198         DESC92C_RATE9M = 0x05,
 199         DESC92C_RATE12M = 0x06,
 200         DESC92C_RATE18M = 0x07,
 201         DESC92C_RATE24M = 0x08,
 202         DESC92C_RATE36M = 0x09,
 203         DESC92C_RATE48M = 0x0a,
 204         DESC92C_RATE54M = 0x0b,
 205
 206         DESC92C_RATEMCS0 = 0x0c,
 207         DESC92C_RATEMCS1 = 0x0d,
 208         DESC92C_RATEMCS2 = 0x0e,
 209         DESC92C_RATEMCS3 = 0x0f,
 210         DESC92C_RATEMCS4 = 0x10,
 211         DESC92C_RATEMCS5 = 0x11,
 212         DESC92C_RATEMCS6 = 0x12,
 213         DESC92C_RATEMCS7 = 0x13,
 214         DESC92C_RATEMCS8 = 0x14,
 215         DESC92C_RATEMCS9 = 0x15,
 216         DESC92C_RATEMCS10 = 0x16,
 217         DESC92C_RATEMCS11 = 0x17,
 218         DESC92C_RATEMCS12 = 0x18,
 219         DESC92C_RATEMCS13 = 0x19,
 220         DESC92C_RATEMCS14 = 0x1a,
 221         DESC92C_RATEMCS15 = 0x1b,
 222         DESC92C_RATEMCS15_SG = 0x1c,
 223         DESC92C_RATEMCS32 = 0x20,
 224 };
 225
 226 struct phy_sts_cck_8723e_t {
 227         u8 adc_pwdb_X[4];
 228         u8 sq_rpt;
 229         u8 cck_agc_rpt;
 230 };
 231
 232 struct h2c_cmd_8723e {
 233         u8 element_id;
 234         u32 cmd_len;
 235         u8 *p_cmdbuffer;
 236 };
 237
 238 #endif