1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
22 * Larry Finger <Larry.Finger@lwfinger.net>
24 *****************************************************************************/
36 #include "../rtl8723com/phy_common.h"
38 #include "../rtl8723com/dm_common.h"
40 #include "../rtl8723com/fw_common.h"
43 #include "../pwrseqcmd.h"
49 static void _rtl8723e_set_bcn_ctrl_reg(struct ieee80211_hw
*hw
,
50 u8 set_bits
, u8 clear_bits
)
52 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
53 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
55 rtlpci
->reg_bcn_ctrl_val
|= set_bits
;
56 rtlpci
->reg_bcn_ctrl_val
&= ~clear_bits
;
58 rtl_write_byte(rtlpriv
, REG_BCN_CTRL
, (u8
) rtlpci
->reg_bcn_ctrl_val
);
61 static void _rtl8723e_stop_tx_beacon(struct ieee80211_hw
*hw
)
63 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
66 tmp1byte
= rtl_read_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2);
67 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2, tmp1byte
& (~BIT(6)));
68 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0x64);
69 tmp1byte
= rtl_read_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2);
70 tmp1byte
&= ~(BIT(0));
71 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2, tmp1byte
);
74 static void _rtl8723e_resume_tx_beacon(struct ieee80211_hw
*hw
)
76 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
79 tmp1byte
= rtl_read_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2);
80 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2, tmp1byte
| BIT(6));
81 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
82 tmp1byte
= rtl_read_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2);
84 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 2, tmp1byte
);
87 static void _rtl8723e_enable_bcn_sub_func(struct ieee80211_hw
*hw
)
89 _rtl8723e_set_bcn_ctrl_reg(hw
, 0, BIT(1));
92 static void _rtl8723e_disable_bcn_sub_func(struct ieee80211_hw
*hw
)
94 _rtl8723e_set_bcn_ctrl_reg(hw
, BIT(1), 0);
97 void rtl8723e_get_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
99 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
100 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
101 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
105 *((u32
*)(val
)) = rtlpci
->receive_config
;
107 case HW_VAR_RF_STATE
:
108 *((enum rf_pwrstate
*)(val
)) = ppsc
->rfpwr_state
;
110 case HW_VAR_FWLPS_RF_ON
:{
111 enum rf_pwrstate rfstate
;
114 rtlpriv
->cfg
->ops
->get_hw_reg(hw
,
117 if (rfstate
== ERFOFF
) {
118 *((bool *)(val
)) = true;
120 val_rcr
= rtl_read_dword(rtlpriv
, REG_RCR
);
121 val_rcr
&= 0x00070000;
123 *((bool *)(val
)) = false;
125 *((bool *)(val
)) = true;
129 case HW_VAR_FW_PSMODE_STATUS
:
130 *((bool *)(val
)) = ppsc
->fw_current_inpsmode
;
132 case HW_VAR_CORRECT_TSF
:{
134 u32
*ptsf_low
= (u32
*)&tsf
;
135 u32
*ptsf_high
= ((u32
*)&tsf
) + 1;
137 *ptsf_high
= rtl_read_dword(rtlpriv
, (REG_TSFTR
+ 4));
138 *ptsf_low
= rtl_read_dword(rtlpriv
, REG_TSFTR
);
140 *((u64
*)(val
)) = tsf
;
145 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_LOUD
,
146 "switch case not process\n");
151 void rtl8723e_set_hw_reg(struct ieee80211_hw
*hw
, u8 variable
, u8
*val
)
153 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
154 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
155 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
156 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
157 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
161 case HW_VAR_ETHER_ADDR
:{
162 for (idx
= 0; idx
< ETH_ALEN
; idx
++) {
163 rtl_write_byte(rtlpriv
, (REG_MACID
+ idx
),
168 case HW_VAR_BASIC_RATE
:{
169 u16 b_rate_cfg
= ((u16
*)val
)[0];
172 b_rate_cfg
= b_rate_cfg
& 0x15f;
174 rtl_write_byte(rtlpriv
, REG_RRSR
, b_rate_cfg
& 0xff);
175 rtl_write_byte(rtlpriv
, REG_RRSR
+ 1,
176 (b_rate_cfg
>> 8) & 0xff);
177 while (b_rate_cfg
> 0x1) {
178 b_rate_cfg
= (b_rate_cfg
>> 1);
181 rtl_write_byte(rtlpriv
, REG_INIRTS_RATE_SEL
,
186 for (idx
= 0; idx
< ETH_ALEN
; idx
++) {
187 rtl_write_byte(rtlpriv
, (REG_BSSID
+ idx
),
193 rtl_write_byte(rtlpriv
, REG_SIFS_CTX
+ 1, val
[0]);
194 rtl_write_byte(rtlpriv
, REG_SIFS_TRX
+ 1, val
[1]);
196 rtl_write_byte(rtlpriv
, REG_SPEC_SIFS
+ 1, val
[0]);
197 rtl_write_byte(rtlpriv
, REG_MAC_SPEC_SIFS
+ 1, val
[0]);
200 rtl_write_word(rtlpriv
, REG_RESP_SIFS_OFDM
,
203 rtl_write_word(rtlpriv
, REG_RESP_SIFS_OFDM
,
207 case HW_VAR_SLOT_TIME
:{
210 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
211 "HW_VAR_SLOT_TIME %x\n", val
[0]);
213 rtl_write_byte(rtlpriv
, REG_SLOT
, val
[0]);
215 for (e_aci
= 0; e_aci
< AC_MAX
; e_aci
++) {
216 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
222 case HW_VAR_ACK_PREAMBLE
:{
224 u8 short_preamble
= (bool)(*(u8
*)val
);
226 reg_tmp
= (mac
->cur_40_prime_sc
) << 5;
230 rtl_write_byte(rtlpriv
, REG_RRSR
+ 2, reg_tmp
);
233 case HW_VAR_AMPDU_MIN_SPACE
:{
234 u8 min_spacing_to_set
;
237 min_spacing_to_set
= *((u8
*)val
);
238 if (min_spacing_to_set
<= 7) {
241 if (min_spacing_to_set
< sec_min_space
)
242 min_spacing_to_set
= sec_min_space
;
244 mac
->min_space_cfg
= ((mac
->min_space_cfg
&
248 *val
= min_spacing_to_set
;
250 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
251 "Set HW_VAR_AMPDU_MIN_SPACE: %#x\n",
254 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
,
259 case HW_VAR_SHORTGI_DENSITY
:{
262 density_to_set
= *((u8
*)val
);
263 mac
->min_space_cfg
|= (density_to_set
<< 3);
265 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
266 "Set HW_VAR_SHORTGI_DENSITY: %#x\n",
269 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
,
274 case HW_VAR_AMPDU_FACTOR
:{
275 u8 regtoset_normal
[4] = { 0x41, 0xa8, 0x72, 0xb9 };
276 u8 regtoset_bt
[4] = {0x31, 0x74, 0x42, 0x97};
278 u8
*p_regtoset
= NULL
;
281 if ((rtlpriv
->btcoexist
.bt_coexistence
) &&
282 (rtlpriv
->btcoexist
.bt_coexist_type
==
284 p_regtoset
= regtoset_bt
;
286 p_regtoset
= regtoset_normal
;
288 factor_toset
= *((u8
*)val
);
289 if (factor_toset
<= 3) {
290 factor_toset
= (1 << (factor_toset
+ 2));
291 if (factor_toset
> 0xf)
294 for (index
= 0; index
< 4; index
++) {
295 if ((p_regtoset
[index
] & 0xf0) >
298 (p_regtoset
[index
] & 0x0f) |
301 if ((p_regtoset
[index
] & 0x0f) >
304 (p_regtoset
[index
] & 0xf0) |
307 rtl_write_byte(rtlpriv
,
308 (REG_AGGLEN_LMT
+ index
),
312 RT_TRACE(rtlpriv
, COMP_MLME
, DBG_LOUD
,
313 "Set HW_VAR_AMPDU_FACTOR: %#x\n",
318 case HW_VAR_AC_PARAM
:{
319 u8 e_aci
= *((u8
*)val
);
321 rtl8723_dm_init_edca_turbo(hw
);
323 if (rtlpci
->acm_method
!= EACMWAY2_SW
)
324 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
329 case HW_VAR_ACM_CTRL
:{
330 u8 e_aci
= *((u8
*)val
);
331 union aci_aifsn
*p_aci_aifsn
=
332 (union aci_aifsn
*)(&mac
->ac
[0].aifs
);
333 u8 acm
= p_aci_aifsn
->f
.acm
;
334 u8 acm_ctrl
= rtl_read_byte(rtlpriv
, REG_ACMHWCTRL
);
337 acm_ctrl
| ((rtlpci
->acm_method
== 2) ? 0x0 : 0x1);
342 acm_ctrl
|= ACMHW_BEQEN
;
345 acm_ctrl
|= ACMHW_VIQEN
;
348 acm_ctrl
|= ACMHW_VOQEN
;
351 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
352 "HW_VAR_ACM_CTRL acm set failed: eACI is %d\n",
359 acm_ctrl
&= (~ACMHW_BEQEN
);
362 acm_ctrl
&= (~ACMHW_VIQEN
);
365 acm_ctrl
&= (~ACMHW_VOQEN
);
368 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_LOUD
,
369 "switch case not process\n");
374 RT_TRACE(rtlpriv
, COMP_QOS
, DBG_TRACE
,
375 "SetHwReg8190pci(): [HW_VAR_ACM_CTRL] Write 0x%X\n",
377 rtl_write_byte(rtlpriv
, REG_ACMHWCTRL
, acm_ctrl
);
381 rtl_write_dword(rtlpriv
, REG_RCR
, ((u32
*)(val
))[0]);
382 rtlpci
->receive_config
= ((u32
*)(val
))[0];
385 case HW_VAR_RETRY_LIMIT
:{
386 u8 retry_limit
= ((u8
*)(val
))[0];
388 rtl_write_word(rtlpriv
, REG_RL
,
389 retry_limit
<< RETRY_LIMIT_SHORT_SHIFT
|
390 retry_limit
<< RETRY_LIMIT_LONG_SHIFT
);
393 case HW_VAR_DUAL_TSF_RST
:
394 rtl_write_byte(rtlpriv
, REG_DUAL_TSF_RST
, (BIT(0) | BIT(1)));
396 case HW_VAR_EFUSE_BYTES
:
397 rtlefuse
->efuse_usedbytes
= *((u16
*)val
);
399 case HW_VAR_EFUSE_USAGE
:
400 rtlefuse
->efuse_usedpercentage
= *((u8
*)val
);
403 rtl8723e_phy_set_io_cmd(hw
, (*(enum io_type
*)val
));
405 case HW_VAR_WPA_CONFIG
:
406 rtl_write_byte(rtlpriv
, REG_SECCFG
, *((u8
*)val
));
408 case HW_VAR_SET_RPWM
:{
411 rpwm_val
= rtl_read_byte(rtlpriv
, REG_PCIE_HRPWM
);
414 if (rpwm_val
& BIT(7)) {
415 rtl_write_byte(rtlpriv
, REG_PCIE_HRPWM
,
418 rtl_write_byte(rtlpriv
, REG_PCIE_HRPWM
,
419 ((*(u8
*)val
) | BIT(7)));
424 case HW_VAR_H2C_FW_PWRMODE
:{
425 u8 psmode
= (*(u8
*)val
);
427 if (psmode
!= FW_PS_ACTIVE_MODE
)
428 rtl8723e_dm_rf_saving(hw
, true);
430 rtl8723e_set_fw_pwrmode_cmd(hw
, (*(u8
*)val
));
433 case HW_VAR_FW_PSMODE_STATUS
:
434 ppsc
->fw_current_inpsmode
= *((bool *)val
);
436 case HW_VAR_H2C_FW_JOINBSSRPT
:{
437 u8 mstatus
= (*(u8
*)val
);
438 u8 tmp_regcr
, tmp_reg422
;
439 bool b_recover
= false;
441 if (mstatus
== RT_MEDIA_CONNECT
) {
442 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_AID
,
445 tmp_regcr
= rtl_read_byte(rtlpriv
, REG_CR
+ 1);
446 rtl_write_byte(rtlpriv
, REG_CR
+ 1,
447 (tmp_regcr
| BIT(0)));
449 _rtl8723e_set_bcn_ctrl_reg(hw
, 0, BIT(3));
450 _rtl8723e_set_bcn_ctrl_reg(hw
, BIT(4), 0);
453 rtl_read_byte(rtlpriv
,
454 REG_FWHW_TXQ_CTRL
+ 2);
455 if (tmp_reg422
& BIT(6))
457 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 2,
458 tmp_reg422
& (~BIT(6)));
460 rtl8723e_set_fw_rsvdpagepkt(hw
, 0);
462 _rtl8723e_set_bcn_ctrl_reg(hw
, BIT(3), 0);
463 _rtl8723e_set_bcn_ctrl_reg(hw
, 0, BIT(4));
466 rtl_write_byte(rtlpriv
,
467 REG_FWHW_TXQ_CTRL
+ 2,
471 rtl_write_byte(rtlpriv
, REG_CR
+ 1,
472 (tmp_regcr
& ~(BIT(0))));
474 rtl8723e_set_fw_joinbss_report_cmd(hw
, (*(u8
*)val
));
478 case HW_VAR_H2C_FW_P2P_PS_OFFLOAD
:{
479 rtl8723e_set_p2p_ps_offload_cmd(hw
, (*(u8
*)val
));
485 u2btmp
= rtl_read_word(rtlpriv
, REG_BCN_PSR_RPT
);
487 rtl_write_word(rtlpriv
, REG_BCN_PSR_RPT
,
488 (u2btmp
| mac
->assoc_id
));
492 case HW_VAR_CORRECT_TSF
:{
493 u8 btype_ibss
= ((u8
*)(val
))[0];
496 _rtl8723e_stop_tx_beacon(hw
);
498 _rtl8723e_set_bcn_ctrl_reg(hw
, 0, BIT(3));
500 rtl_write_dword(rtlpriv
, REG_TSFTR
,
501 (u32
)(mac
->tsf
& 0xffffffff));
502 rtl_write_dword(rtlpriv
, REG_TSFTR
+ 4,
503 (u32
)((mac
->tsf
>> 32) & 0xffffffff));
505 _rtl8723e_set_bcn_ctrl_reg(hw
, BIT(3), 0);
508 _rtl8723e_resume_tx_beacon(hw
);
512 case HW_VAR_FW_LPS_ACTION
:{
513 bool b_enter_fwlps
= *((bool *)val
);
514 u8 rpwm_val
, fw_pwrmode
;
515 bool fw_current_inps
;
518 rpwm_val
= 0x02; /* RF off */
519 fw_current_inps
= true;
520 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
521 HW_VAR_FW_PSMODE_STATUS
,
522 (u8
*)(&fw_current_inps
));
523 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
524 HW_VAR_H2C_FW_PWRMODE
,
525 (u8
*)(&ppsc
->fwctrl_psmode
));
527 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
531 rpwm_val
= 0x0C; /* RF on */
532 fw_pwrmode
= FW_PS_ACTIVE_MODE
;
533 fw_current_inps
= false;
534 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
537 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
538 HW_VAR_H2C_FW_PWRMODE
,
539 (u8
*)(&fw_pwrmode
));
541 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
542 HW_VAR_FW_PSMODE_STATUS
,
543 (u8
*)(&fw_current_inps
));
548 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_LOUD
,
549 "switch case not process\n");
554 static bool _rtl8723e_llt_write(struct ieee80211_hw
*hw
, u32 address
, u32 data
)
556 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
559 u32 value
= _LLT_INIT_ADDR(address
) |
560 _LLT_INIT_DATA(data
) | _LLT_OP(_LLT_WRITE_ACCESS
);
562 rtl_write_dword(rtlpriv
, REG_LLT_INIT
, value
);
565 value
= rtl_read_dword(rtlpriv
, REG_LLT_INIT
);
566 if (_LLT_NO_ACTIVE
== _LLT_OP_VALUE(value
))
569 if (count
> POLLING_LLT_THRESHOLD
) {
570 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
571 "Failed to polling write LLT done at address %d!\n",
581 static bool _rtl8723e_llt_table_init(struct ieee80211_hw
*hw
)
583 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
593 #elif LLT_CONFIG == 2
596 #elif LLT_CONFIG == 3
599 #elif LLT_CONFIG == 4
602 #elif LLT_CONFIG == 5
607 rtl_write_byte(rtlpriv
, REG_CR
, 0x8B);
610 rtl_write_byte(rtlpriv
, REG_RQPN_NPQ
, 0x1c);
611 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80a71c1c);
612 #elif LLT_CONFIG == 2
613 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x845B1010);
614 #elif LLT_CONFIG == 3
615 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x84838484);
616 #elif LLT_CONFIG == 4
617 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80bd1c1c);
618 #elif LLT_CONFIG == 5
619 rtl_write_word(rtlpriv
, REG_RQPN_NPQ
, 0x0000);
621 rtl_write_dword(rtlpriv
, REG_RQPN
, 0x80ac1c29);
622 rtl_write_byte(rtlpriv
, REG_RQPN_NPQ
, 0x03);
625 rtl_write_dword(rtlpriv
, REG_TRXFF_BNDY
, (0x27FF0000 | txpktbuf_bndy
));
626 rtl_write_byte(rtlpriv
, REG_TDECTRL
+ 1, txpktbuf_bndy
);
628 rtl_write_byte(rtlpriv
, REG_TXPKTBUF_BCNQ_BDNY
, txpktbuf_bndy
);
629 rtl_write_byte(rtlpriv
, REG_TXPKTBUF_MGQ_BDNY
, txpktbuf_bndy
);
631 rtl_write_byte(rtlpriv
, 0x45D, txpktbuf_bndy
);
632 rtl_write_byte(rtlpriv
, REG_PBP
, 0x11);
633 rtl_write_byte(rtlpriv
, REG_RX_DRVINFO_SZ
, 0x4);
635 for (i
= 0; i
< (txpktbuf_bndy
- 1); i
++) {
636 status
= _rtl8723e_llt_write(hw
, i
, i
+ 1);
641 status
= _rtl8723e_llt_write(hw
, (txpktbuf_bndy
- 1), 0xFF);
645 for (i
= txpktbuf_bndy
; i
< maxpage
; i
++) {
646 status
= _rtl8723e_llt_write(hw
, i
, (i
+ 1));
651 status
= _rtl8723e_llt_write(hw
, maxpage
, txpktbuf_bndy
);
655 rtl_write_byte(rtlpriv
, REG_CR
, 0xff);
656 ubyte
= rtl_read_byte(rtlpriv
, REG_RQPN
+ 3);
657 rtl_write_byte(rtlpriv
, REG_RQPN
+ 3, ubyte
| BIT(7));
662 static void _rtl8723e_gen_refresh_led_state(struct ieee80211_hw
*hw
)
664 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
665 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
666 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
667 struct rtl_led
*pled0
= &pcipriv
->ledctl
.sw_led0
;
669 if (rtlpriv
->rtlhal
.up_first_time
)
672 if (ppsc
->rfoff_reason
== RF_CHANGE_BY_IPS
)
673 rtl8723e_sw_led_on(hw
, pled0
);
674 else if (ppsc
->rfoff_reason
== RF_CHANGE_BY_INIT
)
675 rtl8723e_sw_led_on(hw
, pled0
);
677 rtl8723e_sw_led_off(hw
, pled0
);
680 static bool _rtl8712e_init_mac(struct ieee80211_hw
*hw
)
682 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
683 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
685 unsigned char bytetmp
;
686 unsigned short wordtmp
;
689 bool mac_func_enable
;
691 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
, 0x00);
692 bytetmp
= rtl_read_byte(rtlpriv
, REG_CR
);
694 mac_func_enable
= true;
696 mac_func_enable
= false;
698 /* HW Power on sequence */
699 if (!rtl_hal_pwrseqcmdparsing(rtlpriv
, PWR_CUT_ALL_MSK
, PWR_FAB_ALL_MSK
,
700 PWR_INTF_PCI_MSK
, Rtl8723_NIC_ENABLE_FLOW
))
703 bytetmp
= rtl_read_byte(rtlpriv
, REG_PCIE_CTRL_REG
+2);
704 rtl_write_byte(rtlpriv
, REG_PCIE_CTRL_REG
+2, bytetmp
| BIT(4));
706 /* eMAC time out function enable, 0x369[7]=1 */
707 bytetmp
= rtl_read_byte(rtlpriv
, 0x369);
708 rtl_write_byte(rtlpriv
, 0x369, bytetmp
| BIT(7));
710 /* ePHY reg 0x1e bit[4]=1 using MDIO interface,
711 * we should do this before Enabling ASPM backdoor.
714 rtl_write_word(rtlpriv
, 0x358, 0x5e);
716 rtl_write_word(rtlpriv
, 0x356, 0xc280);
717 rtl_write_word(rtlpriv
, 0x354, 0xc290);
718 rtl_write_word(rtlpriv
, 0x358, 0x3e);
720 rtl_write_word(rtlpriv
, 0x358, 0x5e);
722 tmpu2b
= rtl_read_word(rtlpriv
, 0x356);
724 } while (tmpu2b
!= 0xc290 && retry
< 100);
727 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
728 "InitMAC(): ePHY configure fail!!!\n");
732 rtl_write_word(rtlpriv
, REG_CR
, 0x2ff);
733 rtl_write_word(rtlpriv
, REG_CR
+ 1, 0x06);
735 if (!mac_func_enable
) {
736 if (!_rtl8723e_llt_table_init(hw
))
740 rtl_write_dword(rtlpriv
, REG_HISR
, 0xffffffff);
741 rtl_write_byte(rtlpriv
, REG_HISRE
, 0xff);
743 rtl_write_word(rtlpriv
, REG_TRXFF_BNDY
+ 2, 0x27ff);
745 wordtmp
= rtl_read_word(rtlpriv
, REG_TRXDMA_CTRL
);
748 rtl_write_word(rtlpriv
, REG_TRXDMA_CTRL
, wordtmp
);
750 rtl_write_byte(rtlpriv
, REG_FWHW_TXQ_CTRL
+ 1, 0x1F);
751 rtl_write_dword(rtlpriv
, REG_RCR
, rtlpci
->receive_config
);
752 rtl_write_word(rtlpriv
, REG_RXFLTMAP2
, 0xFFFF);
753 rtl_write_dword(rtlpriv
, REG_TCR
, rtlpci
->transmit_config
);
755 rtl_write_byte(rtlpriv
, 0x4d0, 0x0);
757 rtl_write_dword(rtlpriv
, REG_BCNQ_DESA
,
758 ((u64
) rtlpci
->tx_ring
[BEACON_QUEUE
].dma
) &
760 rtl_write_dword(rtlpriv
, REG_MGQ_DESA
,
761 (u64
) rtlpci
->tx_ring
[MGNT_QUEUE
].dma
&
763 rtl_write_dword(rtlpriv
, REG_VOQ_DESA
,
764 (u64
) rtlpci
->tx_ring
[VO_QUEUE
].dma
& DMA_BIT_MASK(32));
765 rtl_write_dword(rtlpriv
, REG_VIQ_DESA
,
766 (u64
) rtlpci
->tx_ring
[VI_QUEUE
].dma
& DMA_BIT_MASK(32));
767 rtl_write_dword(rtlpriv
, REG_BEQ_DESA
,
768 (u64
) rtlpci
->tx_ring
[BE_QUEUE
].dma
& DMA_BIT_MASK(32));
769 rtl_write_dword(rtlpriv
, REG_BKQ_DESA
,
770 (u64
) rtlpci
->tx_ring
[BK_QUEUE
].dma
& DMA_BIT_MASK(32));
771 rtl_write_dword(rtlpriv
, REG_HQ_DESA
,
772 (u64
) rtlpci
->tx_ring
[HIGH_QUEUE
].dma
&
774 rtl_write_dword(rtlpriv
, REG_RX_DESA
,
775 (u64
) rtlpci
->rx_ring
[RX_MPDU_QUEUE
].dma
&
778 rtl_write_byte(rtlpriv
, REG_PCIE_CTRL_REG
+ 3, 0x74);
780 rtl_write_dword(rtlpriv
, REG_INT_MIG
, 0);
782 bytetmp
= rtl_read_byte(rtlpriv
, REG_APSD_CTRL
);
783 rtl_write_byte(rtlpriv
, REG_APSD_CTRL
, bytetmp
& ~BIT(6));
786 bytetmp
= rtl_read_byte(rtlpriv
, REG_APSD_CTRL
);
787 } while ((retry
< 200) && (bytetmp
& BIT(7)));
789 _rtl8723e_gen_refresh_led_state(hw
);
791 rtl_write_dword(rtlpriv
, REG_MCUTST_1
, 0x0);
796 static void _rtl8723e_hw_configure(struct ieee80211_hw
*hw
)
798 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
799 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
801 u32 reg_ratr
, reg_prsr
;
803 reg_bw_opmode
= BW_OPMODE_20MHZ
;
804 reg_ratr
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
|
805 RATE_ALL_OFDM_1SS
| RATE_ALL_OFDM_2SS
;
806 reg_prsr
= RATE_ALL_CCK
| RATE_ALL_OFDM_AG
;
808 rtl_write_byte(rtlpriv
, REG_INIRTS_RATE_SEL
, 0x8);
810 rtl_write_byte(rtlpriv
, REG_BWOPMODE
, reg_bw_opmode
);
812 rtl_write_dword(rtlpriv
, REG_RRSR
, reg_prsr
);
814 rtl_write_byte(rtlpriv
, REG_SLOT
, 0x09);
816 rtl_write_byte(rtlpriv
, REG_AMPDU_MIN_SPACE
, 0x0);
818 rtl_write_word(rtlpriv
, REG_FWHW_TXQ_CTRL
, 0x1F80);
820 rtl_write_word(rtlpriv
, REG_RL
, 0x0707);
822 rtl_write_dword(rtlpriv
, REG_BAR_MODE_CTRL
, 0x02012802);
824 rtl_write_byte(rtlpriv
, REG_HWSEQ_CTRL
, 0xFF);
826 rtl_write_dword(rtlpriv
, REG_DARFRC
, 0x01000000);
827 rtl_write_dword(rtlpriv
, REG_DARFRC
+ 4, 0x07060504);
828 rtl_write_dword(rtlpriv
, REG_RARFRC
, 0x01000000);
829 rtl_write_dword(rtlpriv
, REG_RARFRC
+ 4, 0x07060504);
831 if ((rtlpriv
->btcoexist
.bt_coexistence
) &&
832 (rtlpriv
->btcoexist
.bt_coexist_type
== BT_CSR_BC4
))
833 rtl_write_dword(rtlpriv
, REG_AGGLEN_LMT
, 0x97427431);
835 rtl_write_dword(rtlpriv
, REG_AGGLEN_LMT
, 0xb972a841);
837 rtl_write_byte(rtlpriv
, REG_ATIMWND
, 0x2);
839 rtl_write_byte(rtlpriv
, REG_BCN_MAX_ERR
, 0xff);
841 rtlpci
->reg_bcn_ctrl_val
= 0x1f;
842 rtl_write_byte(rtlpriv
, REG_BCN_CTRL
, rtlpci
->reg_bcn_ctrl_val
);
844 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
846 rtl_write_byte(rtlpriv
, REG_TBTT_PROHIBIT
+ 1, 0xff);
848 rtl_write_byte(rtlpriv
, REG_PIFS
, 0x1C);
849 rtl_write_byte(rtlpriv
, REG_AGGR_BREAK_TIME
, 0x16);
851 if ((rtlpriv
->btcoexist
.bt_coexistence
) &&
852 (rtlpriv
->btcoexist
.bt_coexist_type
== BT_CSR_BC4
)) {
853 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
854 rtl_write_word(rtlpriv
, REG_PROT_MODE_CTRL
, 0x0402);
856 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
857 rtl_write_word(rtlpriv
, REG_NAV_PROT_LEN
, 0x0020);
860 if ((rtlpriv
->btcoexist
.bt_coexistence
) &&
861 (rtlpriv
->btcoexist
.bt_coexist_type
== BT_CSR_BC4
))
862 rtl_write_dword(rtlpriv
, REG_FAST_EDCA_CTRL
, 0x03086666);
864 rtl_write_dword(rtlpriv
, REG_FAST_EDCA_CTRL
, 0x086666);
866 rtl_write_byte(rtlpriv
, REG_ACKTO
, 0x40);
868 rtl_write_word(rtlpriv
, REG_SPEC_SIFS
, 0x1010);
869 rtl_write_word(rtlpriv
, REG_MAC_SPEC_SIFS
, 0x1010);
871 rtl_write_word(rtlpriv
, REG_SIFS_CTX
, 0x1010);
873 rtl_write_word(rtlpriv
, REG_SIFS_TRX
, 0x1010);
875 rtl_write_dword(rtlpriv
, REG_MAR
, 0xffffffff);
876 rtl_write_dword(rtlpriv
, REG_MAR
+ 4, 0xffffffff);
878 rtl_write_dword(rtlpriv
, 0x394, 0x1);
881 static void _rtl8723e_enable_aspm_back_door(struct ieee80211_hw
*hw
)
883 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
884 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
886 rtl_write_byte(rtlpriv
, 0x34b, 0x93);
887 rtl_write_word(rtlpriv
, 0x350, 0x870c);
888 rtl_write_byte(rtlpriv
, 0x352, 0x1);
890 if (ppsc
->support_backdoor
)
891 rtl_write_byte(rtlpriv
, 0x349, 0x1b);
893 rtl_write_byte(rtlpriv
, 0x349, 0x03);
895 rtl_write_word(rtlpriv
, 0x350, 0x2718);
896 rtl_write_byte(rtlpriv
, 0x352, 0x1);
899 void rtl8723e_enable_hw_security_config(struct ieee80211_hw
*hw
)
901 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
904 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
,
905 "PairwiseEncAlgorithm = %d GroupEncAlgorithm = %d\n",
906 rtlpriv
->sec
.pairwise_enc_algorithm
,
907 rtlpriv
->sec
.group_enc_algorithm
);
909 if (rtlpriv
->cfg
->mod_params
->sw_crypto
|| rtlpriv
->sec
.use_sw_sec
) {
910 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
911 "not open hw encryption\n");
915 sec_reg_value
= SCR_TXENCENABLE
| SCR_RXDECENABLE
;
917 if (rtlpriv
->sec
.use_defaultkey
) {
918 sec_reg_value
|= SCR_TXUSEDK
;
919 sec_reg_value
|= SCR_RXUSEDK
;
922 sec_reg_value
|= (SCR_RXBCUSEDK
| SCR_TXBCUSEDK
);
924 rtl_write_byte(rtlpriv
, REG_CR
+ 1, 0x02);
926 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
927 "The SECR-value %x\n", sec_reg_value
);
929 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_WPA_CONFIG
, &sec_reg_value
);
933 int rtl8723e_hw_init(struct ieee80211_hw
*hw
)
935 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
936 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
937 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
938 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
939 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
940 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
941 bool rtstatus
= true;
946 rtlpriv
->rtlhal
.being_init_adapter
= true;
947 /* As this function can take a very long time (up to 350 ms)
948 * and can be called with irqs disabled, reenable the irqs
949 * to let the other devices continue being serviced.
951 * It is safe doing so since our own interrupts will only be enabled
952 * in a subsequent step.
954 local_save_flags(flags
);
956 rtlhal
->fw_ready
= false;
958 rtlpriv
->intf_ops
->disable_aspm(hw
);
959 rtstatus
= _rtl8712e_init_mac(hw
);
960 if (rtstatus
!= true) {
961 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Init MAC failed\n");
966 err
= rtl8723_download_fw(hw
, false, FW_8723A_POLLING_TIMEOUT_COUNT
);
968 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
969 "Failed to download FW. Init HW without FW now..\n");
973 rtlhal
->fw_ready
= true;
975 rtlhal
->last_hmeboxnum
= 0;
976 rtl8723e_phy_mac_config(hw
);
977 /* because last function modify RCR, so we update
978 * rcr var here, or TP will unstable for receive_config
979 * is wrong, RX RCR_ACRC32 will cause TP unstable & Rx
980 * RCR_APP_ICV will cause mac80211 unassoc for cisco 1252
982 rtlpci
->receive_config
= rtl_read_dword(rtlpriv
, REG_RCR
);
983 rtlpci
->receive_config
&= ~(RCR_ACRC32
| RCR_AICV
);
984 rtl_write_dword(rtlpriv
, REG_RCR
, rtlpci
->receive_config
);
986 rtl8723e_phy_bb_config(hw
);
987 rtlphy
->rf_mode
= RF_OP_BY_SW_3WIRE
;
988 rtl8723e_phy_rf_config(hw
);
989 if (IS_VENDOR_UMC_A_CUT(rtlhal
->version
)) {
990 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_RX_G1
, MASKDWORD
, 0x30255);
991 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_RX_G2
, MASKDWORD
, 0x50a00);
992 } else if (IS_81xxC_VENDOR_UMC_B_CUT(rtlhal
->version
)) {
993 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x0C, MASKDWORD
, 0x894AE);
994 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x0A, MASKDWORD
, 0x1AF31);
995 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_IPA
, MASKDWORD
, 0x8F425);
996 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_SYN_G2
, MASKDWORD
, 0x4F200);
997 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_RCK1
, MASKDWORD
, 0x44053);
998 rtl_set_rfreg(hw
, RF90_PATH_A
, RF_RCK2
, MASKDWORD
, 0x80201);
1000 rtlphy
->rfreg_chnlval
[0] = rtl_get_rfreg(hw
, (enum radio_path
)0,
1001 RF_CHNLBW
, RFREG_OFFSET_MASK
);
1002 rtlphy
->rfreg_chnlval
[1] = rtl_get_rfreg(hw
, (enum radio_path
)1,
1003 RF_CHNLBW
, RFREG_OFFSET_MASK
);
1004 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BCCKEN
, 0x1);
1005 rtl_set_bbreg(hw
, RFPGA0_RFMOD
, BOFDMEN
, 0x1);
1006 rtl_set_bbreg(hw
, RFPGA0_ANALOGPARAMETER2
, BIT(10), 1);
1007 _rtl8723e_hw_configure(hw
);
1008 rtl_cam_reset_all_entry(hw
);
1009 rtl8723e_enable_hw_security_config(hw
);
1011 ppsc
->rfpwr_state
= ERFON
;
1013 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_ETHER_ADDR
, mac
->mac_addr
);
1014 _rtl8723e_enable_aspm_back_door(hw
);
1015 rtlpriv
->intf_ops
->enable_aspm(hw
);
1017 rtl8723e_bt_hw_init(hw
);
1019 if (ppsc
->rfpwr_state
== ERFON
) {
1020 rtl8723e_phy_set_rfpath_switch(hw
, 1);
1021 if (rtlphy
->iqk_initialized
) {
1022 rtl8723e_phy_iq_calibrate(hw
, true);
1024 rtl8723e_phy_iq_calibrate(hw
, false);
1025 rtlphy
->iqk_initialized
= true;
1028 rtl8723e_dm_check_txpower_tracking(hw
);
1029 rtl8723e_phy_lc_calibrate(hw
);
1032 tmp_u1b
= efuse_read_1byte(hw
, 0x1FA);
1033 if (!(tmp_u1b
& BIT(0))) {
1034 rtl_set_rfreg(hw
, RF90_PATH_A
, 0x15, 0x0F, 0x05);
1035 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "PA BIAS path A\n");
1038 if (!(tmp_u1b
& BIT(4))) {
1039 tmp_u1b
= rtl_read_byte(rtlpriv
, 0x16);
1041 rtl_write_byte(rtlpriv
, 0x16, tmp_u1b
| 0x80);
1043 rtl_write_byte(rtlpriv
, 0x16, tmp_u1b
| 0x90);
1044 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
, "under 1.5V\n");
1046 rtl8723e_dm_init(hw
);
1048 local_irq_restore(flags
);
1049 rtlpriv
->rtlhal
.being_init_adapter
= false;
1053 static enum version_8723e
_rtl8723e_read_chip_version(struct ieee80211_hw
*hw
)
1055 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1056 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1057 enum version_8723e version
= 0x0000;
1060 value32
= rtl_read_dword(rtlpriv
, REG_SYS_CFG
);
1061 if (value32
& TRP_VAUX_EN
) {
1062 version
= (enum version_8723e
)(version
|
1063 ((value32
& VENDOR_ID
) ? CHIP_VENDOR_UMC
: 0));
1064 /* RTL8723 with BT function. */
1065 version
= (enum version_8723e
)(version
|
1066 ((value32
& BT_FUNC
) ? CHIP_8723
: 0));
1069 /* Normal mass production chip. */
1070 version
= (enum version_8723e
) NORMAL_CHIP
;
1071 version
= (enum version_8723e
)(version
|
1072 ((value32
& VENDOR_ID
) ? CHIP_VENDOR_UMC
: 0));
1073 /* RTL8723 with BT function. */
1074 version
= (enum version_8723e
)(version
|
1075 ((value32
& BT_FUNC
) ? CHIP_8723
: 0));
1076 if (IS_CHIP_VENDOR_UMC(version
))
1077 version
= (enum version_8723e
)(version
|
1078 ((value32
& CHIP_VER_RTL_MASK
)));/* IC version (CUT) */
1079 if (IS_8723_SERIES(version
)) {
1080 value32
= rtl_read_dword(rtlpriv
, REG_GPIO_OUTSTS
);
1081 /* ROM code version. */
1082 version
= (enum version_8723e
)(version
|
1083 ((value32
& RF_RL_ID
)>>20));
1087 if (IS_8723_SERIES(version
)) {
1088 value32
= rtl_read_dword(rtlpriv
, REG_MULTI_FUNC_CTRL
);
1089 rtlphy
->polarity_ctl
= ((value32
& WL_HWPDN_SL
) ?
1090 RT_POLARITY_HIGH_ACT
:
1091 RT_POLARITY_LOW_ACT
);
1094 case VERSION_TEST_UMC_CHIP_8723
:
1095 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1096 "Chip Version ID: VERSION_TEST_UMC_CHIP_8723.\n");
1098 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT
:
1099 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1100 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_A_CUT.\n");
1102 case VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT
:
1103 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1104 "Chip Version ID: VERSION_NORMAL_UMC_CHIP_8723_1T1R_B_CUT.\n");
1107 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1108 "Chip Version ID: Unknown. Bug?\n");
1112 if (IS_8723_SERIES(version
))
1113 rtlphy
->rf_type
= RF_1T1R
;
1115 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Chip RF Type: %s\n",
1116 (rtlphy
->rf_type
== RF_2T2R
) ? "RF_2T2R" : "RF_1T1R");
1121 static int _rtl8723e_set_media_status(struct ieee80211_hw
*hw
,
1122 enum nl80211_iftype type
)
1124 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1125 u8 bt_msr
= rtl_read_byte(rtlpriv
, MSR
) & 0xfc;
1126 enum led_ctl_mode ledaction
= LED_CTL_NO_LINK
;
1127 u8 mode
= MSR_NOLINK
;
1129 rtl_write_dword(rtlpriv
, REG_BCN_CTRL
, 0);
1130 RT_TRACE(rtlpriv
, COMP_BEACON
, DBG_LOUD
,
1131 "clear 0x550 when set HW_VAR_MEDIA_STATUS\n");
1134 case NL80211_IFTYPE_UNSPECIFIED
:
1136 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1137 "Set Network type to NO LINK!\n");
1139 case NL80211_IFTYPE_ADHOC
:
1141 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1142 "Set Network type to Ad Hoc!\n");
1144 case NL80211_IFTYPE_STATION
:
1146 ledaction
= LED_CTL_LINK
;
1147 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1148 "Set Network type to STA!\n");
1150 case NL80211_IFTYPE_AP
:
1152 ledaction
= LED_CTL_LINK
;
1153 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_TRACE
,
1154 "Set Network type to AP!\n");
1157 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1158 "Network type %d not support!\n", type
);
1163 /* MSR_INFRA == Link in infrastructure network;
1164 * MSR_ADHOC == Link in ad hoc network;
1165 * Therefore, check link state is necessary.
1167 * MSR_AP == AP mode; link state is not cared here.
1169 if (mode
!= MSR_AP
&&
1170 rtlpriv
->mac80211
.link_state
< MAC80211_LINKED
) {
1172 ledaction
= LED_CTL_NO_LINK
;
1174 if (mode
== MSR_NOLINK
|| mode
== MSR_INFRA
) {
1175 _rtl8723e_stop_tx_beacon(hw
);
1176 _rtl8723e_enable_bcn_sub_func(hw
);
1177 } else if (mode
== MSR_ADHOC
|| mode
== MSR_AP
) {
1178 _rtl8723e_resume_tx_beacon(hw
);
1179 _rtl8723e_disable_bcn_sub_func(hw
);
1181 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1182 "Set HW_VAR_MEDIA_STATUS: No such media status(%x).\n",
1186 rtl_write_byte(rtlpriv
, MSR
, bt_msr
| mode
);
1187 rtlpriv
->cfg
->ops
->led_control(hw
, ledaction
);
1189 rtl_write_byte(rtlpriv
, REG_BCNTCFG
+ 1, 0x00);
1191 rtl_write_byte(rtlpriv
, REG_BCNTCFG
+ 1, 0x66);
1195 void rtl8723e_set_check_bssid(struct ieee80211_hw
*hw
, bool check_bssid
)
1197 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1198 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1199 u32 reg_rcr
= rtlpci
->receive_config
;
1201 if (rtlpriv
->psc
.rfpwr_state
!= ERFON
)
1205 reg_rcr
|= (RCR_CBSSID_DATA
| RCR_CBSSID_BCN
);
1206 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_RCR
,
1208 _rtl8723e_set_bcn_ctrl_reg(hw
, 0, BIT(4));
1209 } else if (!check_bssid
) {
1210 reg_rcr
&= (~(RCR_CBSSID_DATA
| RCR_CBSSID_BCN
));
1211 _rtl8723e_set_bcn_ctrl_reg(hw
, BIT(4), 0);
1212 rtlpriv
->cfg
->ops
->set_hw_reg(hw
,
1213 HW_VAR_RCR
, (u8
*)(®_rcr
));
1217 int rtl8723e_set_network_type(struct ieee80211_hw
*hw
,
1218 enum nl80211_iftype type
)
1220 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1222 if (_rtl8723e_set_media_status(hw
, type
))
1225 if (rtlpriv
->mac80211
.link_state
== MAC80211_LINKED
) {
1226 if (type
!= NL80211_IFTYPE_AP
)
1227 rtl8723e_set_check_bssid(hw
, true);
1229 rtl8723e_set_check_bssid(hw
, false);
1235 /* don't set REG_EDCA_BE_PARAM here
1236 * because mac80211 will send pkt when scan
1238 void rtl8723e_set_qos(struct ieee80211_hw
*hw
, int aci
)
1240 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1242 rtl8723_dm_init_edca_turbo(hw
);
1245 rtl_write_dword(rtlpriv
, REG_EDCA_BK_PARAM
, 0xa44f);
1250 rtl_write_dword(rtlpriv
, REG_EDCA_VI_PARAM
, 0x5e4322);
1253 rtl_write_dword(rtlpriv
, REG_EDCA_VO_PARAM
, 0x2f3222);
1256 RT_ASSERT(false, "invalid aci: %d !\n", aci
);
1261 void rtl8723e_enable_interrupt(struct ieee80211_hw
*hw
)
1263 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1264 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1266 rtl_write_dword(rtlpriv
, 0x3a8, rtlpci
->irq_mask
[0] & 0xFFFFFFFF);
1267 rtl_write_dword(rtlpriv
, 0x3ac, rtlpci
->irq_mask
[1] & 0xFFFFFFFF);
1268 rtlpci
->irq_enabled
= true;
1271 void rtl8723e_disable_interrupt(struct ieee80211_hw
*hw
)
1273 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1274 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1275 rtl_write_dword(rtlpriv
, 0x3a8, IMR8190_DISABLED
);
1276 rtl_write_dword(rtlpriv
, 0x3ac, IMR8190_DISABLED
);
1277 rtlpci
->irq_enabled
= false;
1278 /*synchronize_irq(rtlpci->pdev->irq);*/
1281 static void _rtl8723e_poweroff_adapter(struct ieee80211_hw
*hw
)
1283 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1284 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1287 /* Combo (PCIe + USB) Card and PCIe-MF Card */
1288 /* 1. Run LPS WL RFOFF flow */
1289 rtl_hal_pwrseqcmdparsing(rtlpriv
, PWR_CUT_ALL_MSK
, PWR_FAB_ALL_MSK
,
1290 PWR_INTF_PCI_MSK
, Rtl8723_NIC_LPS_ENTER_FLOW
);
1292 /* 2. 0x1F[7:0] = 0 */
1294 rtl_write_byte(rtlpriv
, REG_RF_CTRL
, 0x00);
1295 if ((rtl_read_byte(rtlpriv
, REG_MCUFWDL
) & BIT(7)) &&
1297 rtl8723ae_firmware_selfreset(hw
);
1300 /* Reset MCU. Suggested by Filen. */
1301 u1b_tmp
= rtl_read_byte(rtlpriv
, REG_SYS_FUNC_EN
+1);
1302 rtl_write_byte(rtlpriv
, REG_SYS_FUNC_EN
+1, (u1b_tmp
& (~BIT(2))));
1304 /* g. MCUFWDL 0x80[1:0]=0 */
1305 /* reset MCU ready status */
1306 rtl_write_byte(rtlpriv
, REG_MCUFWDL
, 0x00);
1308 /* HW card disable configuration. */
1309 rtl_hal_pwrseqcmdparsing(rtlpriv
, PWR_CUT_ALL_MSK
, PWR_FAB_ALL_MSK
,
1310 PWR_INTF_PCI_MSK
, Rtl8723_NIC_DISABLE_FLOW
);
1312 /* Reset MCU IO Wrapper */
1313 u1b_tmp
= rtl_read_byte(rtlpriv
, REG_RSV_CTRL
+ 1);
1314 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
+ 1, (u1b_tmp
& (~BIT(0))));
1315 u1b_tmp
= rtl_read_byte(rtlpriv
, REG_RSV_CTRL
+ 1);
1316 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
+ 1, u1b_tmp
| BIT(0));
1318 /* 7. RSV_CTRL 0x1C[7:0] = 0x0E */
1319 /* lock ISO/CLK/Power control register */
1320 rtl_write_byte(rtlpriv
, REG_RSV_CTRL
, 0x0e);
1323 void rtl8723e_card_disable(struct ieee80211_hw
*hw
)
1325 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1326 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
1327 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1328 enum nl80211_iftype opmode
;
1330 mac
->link_state
= MAC80211_NOLINK
;
1331 opmode
= NL80211_IFTYPE_UNSPECIFIED
;
1332 _rtl8723e_set_media_status(hw
, opmode
);
1333 if (rtlpriv
->rtlhal
.driver_is_goingto_unload
||
1334 ppsc
->rfoff_reason
> RF_CHANGE_BY_PS
)
1335 rtlpriv
->cfg
->ops
->led_control(hw
, LED_CTL_POWER_OFF
);
1336 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
1337 _rtl8723e_poweroff_adapter(hw
);
1339 /* after power off we should do iqk again */
1340 rtlpriv
->phy
.iqk_initialized
= false;
1343 void rtl8723e_interrupt_recognized(struct ieee80211_hw
*hw
,
1344 u32
*p_inta
, u32
*p_intb
)
1346 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1347 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1349 *p_inta
= rtl_read_dword(rtlpriv
, 0x3a0) & rtlpci
->irq_mask
[0];
1350 rtl_write_dword(rtlpriv
, 0x3a0, *p_inta
);
1353 void rtl8723e_set_beacon_related_registers(struct ieee80211_hw
*hw
)
1356 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1357 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1358 u16 bcn_interval
, atim_window
;
1360 bcn_interval
= mac
->beacon_interval
;
1361 atim_window
= 2; /*FIX MERGE */
1362 rtl8723e_disable_interrupt(hw
);
1363 rtl_write_word(rtlpriv
, REG_ATIMWND
, atim_window
);
1364 rtl_write_word(rtlpriv
, REG_BCN_INTERVAL
, bcn_interval
);
1365 rtl_write_word(rtlpriv
, REG_BCNTCFG
, 0x660f);
1366 rtl_write_byte(rtlpriv
, REG_RXTSF_OFFSET_CCK
, 0x18);
1367 rtl_write_byte(rtlpriv
, REG_RXTSF_OFFSET_OFDM
, 0x18);
1368 rtl_write_byte(rtlpriv
, 0x606, 0x30);
1369 rtl8723e_enable_interrupt(hw
);
1372 void rtl8723e_set_beacon_interval(struct ieee80211_hw
*hw
)
1374 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1375 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1376 u16 bcn_interval
= mac
->beacon_interval
;
1378 RT_TRACE(rtlpriv
, COMP_BEACON
, DBG_DMESG
,
1379 "beacon_interval:%d\n", bcn_interval
);
1380 rtl8723e_disable_interrupt(hw
);
1381 rtl_write_word(rtlpriv
, REG_BCN_INTERVAL
, bcn_interval
);
1382 rtl8723e_enable_interrupt(hw
);
1385 void rtl8723e_update_interrupt_mask(struct ieee80211_hw
*hw
,
1386 u32 add_msr
, u32 rm_msr
)
1388 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1389 struct rtl_pci
*rtlpci
= rtl_pcidev(rtl_pcipriv(hw
));
1391 RT_TRACE(rtlpriv
, COMP_INTR
, DBG_LOUD
,
1392 "add_msr:%x, rm_msr:%x\n", add_msr
, rm_msr
);
1395 rtlpci
->irq_mask
[0] |= add_msr
;
1397 rtlpci
->irq_mask
[0] &= (~rm_msr
);
1398 rtl8723e_disable_interrupt(hw
);
1399 rtl8723e_enable_interrupt(hw
);
1402 static u8
_rtl8723e_get_chnl_group(u8 chnl
)
1415 static void _rtl8723e_read_txpower_info_from_hwpg(struct ieee80211_hw
*hw
,
1419 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1420 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1421 u8 rf_path
, index
, tempval
;
1424 for (rf_path
= 0; rf_path
< 1; rf_path
++) {
1425 for (i
= 0; i
< 3; i
++) {
1426 if (!autoload_fail
) {
1427 rtlefuse
->eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1428 hwinfo
[EEPROM_TXPOWERCCK
+ rf_path
* 3 + i
];
1429 rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1430 hwinfo
[EEPROM_TXPOWERHT40_1S
+ rf_path
* 3 + i
];
1432 rtlefuse
->eeprom_chnlarea_txpwr_cck
[rf_path
][i
] =
1433 EEPROM_DEFAULT_TXPOWERLEVEL
;
1434 rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
[rf_path
][i
] =
1435 EEPROM_DEFAULT_TXPOWERLEVEL
;
1440 for (i
= 0; i
< 3; i
++) {
1442 tempval
= hwinfo
[EEPROM_TXPOWERHT40_2SDIFF
+ i
];
1444 tempval
= EEPROM_DEFAULT_HT40_2SDIFF
;
1445 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
[RF90_PATH_A
][i
] =
1447 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
[RF90_PATH_B
][i
] =
1448 ((tempval
& 0xf0) >> 4);
1451 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1452 for (i
= 0; i
< 3; i
++)
1453 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1454 "RF(%d) EEPROM CCK Area(%d) = 0x%x\n", rf_path
,
1455 i
, rtlefuse
->eeprom_chnlarea_txpwr_cck
1457 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1458 for (i
= 0; i
< 3; i
++)
1459 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1460 "RF(%d) EEPROM HT40 1S Area(%d) = 0x%x\n",
1462 rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
1464 for (rf_path
= 0; rf_path
< 2; rf_path
++)
1465 for (i
= 0; i
< 3; i
++)
1466 RTPRINT(rtlpriv
, FINIT
, INIT_EEPROM
,
1467 "RF(%d) EEPROM HT40 2S Diff Area(%d) = 0x%x\n",
1469 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
1472 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1473 for (i
= 0; i
< 14; i
++) {
1474 index
= _rtl8723e_get_chnl_group((u8
)i
);
1476 rtlefuse
->txpwrlevel_cck
[rf_path
][i
] =
1477 rtlefuse
->eeprom_chnlarea_txpwr_cck
1479 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
] =
1480 rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
1483 if ((rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
1485 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
1486 [rf_path
][index
]) > 0) {
1487 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] =
1488 rtlefuse
->eeprom_chnlarea_txpwr_ht40_1s
1490 rtlefuse
->eprom_chnl_txpwr_ht40_2sdf
1493 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
] = 0;
1497 for (i
= 0; i
< 14; i
++) {
1498 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1499 "RF(%d)-Ch(%d) [CCK / HT40_1S / HT40_2S] = [0x%x / 0x%x / 0x%x]\n",
1501 rtlefuse
->txpwrlevel_cck
[rf_path
][i
],
1502 rtlefuse
->txpwrlevel_ht40_1s
[rf_path
][i
],
1503 rtlefuse
->txpwrlevel_ht40_2s
[rf_path
][i
]);
1507 for (i
= 0; i
< 3; i
++) {
1508 if (!autoload_fail
) {
1509 rtlefuse
->eeprom_pwrlimit_ht40
[i
] =
1510 hwinfo
[EEPROM_TXPWR_GROUP
+ i
];
1511 rtlefuse
->eeprom_pwrlimit_ht20
[i
] =
1512 hwinfo
[EEPROM_TXPWR_GROUP
+ 3 + i
];
1514 rtlefuse
->eeprom_pwrlimit_ht40
[i
] = 0;
1515 rtlefuse
->eeprom_pwrlimit_ht20
[i
] = 0;
1519 for (rf_path
= 0; rf_path
< 2; rf_path
++) {
1520 for (i
= 0; i
< 14; i
++) {
1521 index
= _rtl8723e_get_chnl_group((u8
)i
);
1523 if (rf_path
== RF90_PATH_A
) {
1524 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1525 (rtlefuse
->eeprom_pwrlimit_ht20
[index
] & 0xf);
1526 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1527 (rtlefuse
->eeprom_pwrlimit_ht40
[index
] & 0xf);
1528 } else if (rf_path
== RF90_PATH_B
) {
1529 rtlefuse
->pwrgroup_ht20
[rf_path
][i
] =
1530 ((rtlefuse
->eeprom_pwrlimit_ht20
[index
] &
1532 rtlefuse
->pwrgroup_ht40
[rf_path
][i
] =
1533 ((rtlefuse
->eeprom_pwrlimit_ht40
[index
] &
1537 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1538 "RF-%d pwrgroup_ht20[%d] = 0x%x\n", rf_path
, i
,
1539 rtlefuse
->pwrgroup_ht20
[rf_path
][i
]);
1540 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1541 "RF-%d pwrgroup_ht40[%d] = 0x%x\n", rf_path
, i
,
1542 rtlefuse
->pwrgroup_ht40
[rf_path
][i
]);
1546 for (i
= 0; i
< 14; i
++) {
1547 index
= _rtl8723e_get_chnl_group((u8
)i
);
1550 tempval
= hwinfo
[EEPROM_TXPOWERHT20DIFF
+ index
];
1552 tempval
= EEPROM_DEFAULT_HT20_DIFF
;
1554 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1555 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] =
1556 ((tempval
>> 4) & 0xF);
1558 if (rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] & BIT(3))
1559 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
] |= 0xF0;
1561 if (rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] & BIT(3))
1562 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
] |= 0xF0;
1564 index
= _rtl8723e_get_chnl_group((u8
)i
);
1567 tempval
= hwinfo
[EEPROM_TXPOWER_OFDMDIFF
+ index
];
1569 tempval
= EEPROM_DEFAULT_LEGACYHTTXPOWERDIFF
;
1571 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
] = (tempval
& 0xF);
1572 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
] =
1573 ((tempval
>> 4) & 0xF);
1576 rtlefuse
->legacy_ht_txpowerdiff
=
1577 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][7];
1579 for (i
= 0; i
< 14; i
++)
1580 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1581 "RF-A Ht20 to HT40 Diff[%d] = 0x%x\n", i
,
1582 rtlefuse
->txpwr_ht20diff
[RF90_PATH_A
][i
]);
1583 for (i
= 0; i
< 14; i
++)
1584 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1585 "RF-A Legacy to Ht40 Diff[%d] = 0x%x\n", i
,
1586 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_A
][i
]);
1587 for (i
= 0; i
< 14; i
++)
1588 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1589 "RF-B Ht20 to HT40 Diff[%d] = 0x%x\n", i
,
1590 rtlefuse
->txpwr_ht20diff
[RF90_PATH_B
][i
]);
1591 for (i
= 0; i
< 14; i
++)
1592 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1593 "RF-B Legacy to HT40 Diff[%d] = 0x%x\n", i
,
1594 rtlefuse
->txpwr_legacyhtdiff
[RF90_PATH_B
][i
]);
1597 rtlefuse
->eeprom_regulatory
= (hwinfo
[RF_OPTION1
] & 0x7);
1599 rtlefuse
->eeprom_regulatory
= 0;
1600 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1601 "eeprom_regulatory = 0x%x\n", rtlefuse
->eeprom_regulatory
);
1604 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = hwinfo
[EEPROM_TSSI_A
];
1606 rtlefuse
->eeprom_tssi
[RF90_PATH_A
] = EEPROM_DEFAULT_TSSI
;
1608 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1609 "TSSI_A = 0x%x, TSSI_B = 0x%x\n",
1610 rtlefuse
->eeprom_tssi
[RF90_PATH_A
],
1611 rtlefuse
->eeprom_tssi
[RF90_PATH_B
]);
1614 tempval
= hwinfo
[EEPROM_THERMAL_METER
];
1616 tempval
= EEPROM_DEFAULT_THERMALMETER
;
1617 rtlefuse
->eeprom_thermalmeter
= (tempval
& 0x1f);
1619 if (rtlefuse
->eeprom_thermalmeter
== 0x1f || autoload_fail
)
1620 rtlefuse
->apk_thermalmeterignore
= true;
1622 rtlefuse
->thermalmeter
[0] = rtlefuse
->eeprom_thermalmeter
;
1623 RTPRINT(rtlpriv
, FINIT
, INIT_TXPOWER
,
1624 "thermalmeter = 0x%x\n", rtlefuse
->eeprom_thermalmeter
);
1627 static void _rtl8723e_read_adapter_info(struct ieee80211_hw
*hw
,
1630 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1631 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1632 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1634 u8 hwinfo
[HWSET_MAX_SIZE
];
1637 if (b_pseudo_test
) {
1641 if (rtlefuse
->epromtype
== EEPROM_BOOT_EFUSE
) {
1642 rtl_efuse_shadow_map_update(hw
);
1644 memcpy(hwinfo
, &rtlefuse
->efuse_map
[EFUSE_INIT_MAP
][0],
1646 } else if (rtlefuse
->epromtype
== EEPROM_93C46
) {
1647 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
,
1648 "RTL819X Not boot from eeprom, check it !!");
1651 RT_PRINT_DATA(rtlpriv
, COMP_INIT
, DBG_DMESG
, "MAP\n",
1652 hwinfo
, HWSET_MAX_SIZE
);
1654 eeprom_id
= *((u16
*)&hwinfo
[0]);
1655 if (eeprom_id
!= RTL8190_EEPROM_ID
) {
1656 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_WARNING
,
1657 "EEPROM ID(%#x) is invalid!!\n", eeprom_id
);
1658 rtlefuse
->autoload_failflag
= true;
1660 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1661 rtlefuse
->autoload_failflag
= false;
1664 if (rtlefuse
->autoload_failflag
)
1667 rtlefuse
->eeprom_vid
= *(u16
*)&hwinfo
[EEPROM_VID
];
1668 rtlefuse
->eeprom_did
= *(u16
*)&hwinfo
[EEPROM_DID
];
1669 rtlefuse
->eeprom_svid
= *(u16
*)&hwinfo
[EEPROM_SVID
];
1670 rtlefuse
->eeprom_smid
= *(u16
*)&hwinfo
[EEPROM_SMID
];
1671 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1672 "EEPROMId = 0x%4x\n", eeprom_id
);
1673 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1674 "EEPROM VID = 0x%4x\n", rtlefuse
->eeprom_vid
);
1675 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1676 "EEPROM DID = 0x%4x\n", rtlefuse
->eeprom_did
);
1677 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1678 "EEPROM SVID = 0x%4x\n", rtlefuse
->eeprom_svid
);
1679 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1680 "EEPROM SMID = 0x%4x\n", rtlefuse
->eeprom_smid
);
1682 for (i
= 0; i
< 6; i
+= 2) {
1683 usvalue
= *(u16
*)&hwinfo
[EEPROM_MAC_ADDR
+ i
];
1684 *((u16
*)(&rtlefuse
->dev_addr
[i
])) = usvalue
;
1687 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
,
1688 "dev_addr: %pM\n", rtlefuse
->dev_addr
);
1690 _rtl8723e_read_txpower_info_from_hwpg(hw
, rtlefuse
->autoload_failflag
,
1693 rtl8723e_read_bt_coexist_info_from_hwpg(hw
,
1694 rtlefuse
->autoload_failflag
, hwinfo
);
1696 rtlefuse
->eeprom_channelplan
= hwinfo
[EEPROM_CHANNELPLAN
];
1697 rtlefuse
->eeprom_version
= *(u16
*)&hwinfo
[EEPROM_VERSION
];
1698 rtlefuse
->txpwr_fromeprom
= true;
1699 rtlefuse
->eeprom_oemid
= hwinfo
[EEPROM_CUSTOMER_ID
];
1701 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
,
1702 "EEPROM Customer ID: 0x%2x\n", rtlefuse
->eeprom_oemid
);
1704 /* set channel paln to world wide 13 */
1705 rtlefuse
->channel_plan
= COUNTRY_CODE_WORLD_WIDE_13
;
1707 if (rtlhal
->oem_id
== RT_CID_DEFAULT
) {
1708 switch (rtlefuse
->eeprom_oemid
) {
1709 case EEPROM_CID_DEFAULT
:
1710 if (rtlefuse
->eeprom_did
== 0x8176) {
1711 if (CHK_SVID_SMID(0x10EC, 0x6151) ||
1712 CHK_SVID_SMID(0x10EC, 0x6152) ||
1713 CHK_SVID_SMID(0x10EC, 0x6154) ||
1714 CHK_SVID_SMID(0x10EC, 0x6155) ||
1715 CHK_SVID_SMID(0x10EC, 0x6177) ||
1716 CHK_SVID_SMID(0x10EC, 0x6178) ||
1717 CHK_SVID_SMID(0x10EC, 0x6179) ||
1718 CHK_SVID_SMID(0x10EC, 0x6180) ||
1719 CHK_SVID_SMID(0x10EC, 0x7151) ||
1720 CHK_SVID_SMID(0x10EC, 0x7152) ||
1721 CHK_SVID_SMID(0x10EC, 0x7154) ||
1722 CHK_SVID_SMID(0x10EC, 0x7155) ||
1723 CHK_SVID_SMID(0x10EC, 0x7177) ||
1724 CHK_SVID_SMID(0x10EC, 0x7178) ||
1725 CHK_SVID_SMID(0x10EC, 0x7179) ||
1726 CHK_SVID_SMID(0x10EC, 0x7180) ||
1727 CHK_SVID_SMID(0x10EC, 0x8151) ||
1728 CHK_SVID_SMID(0x10EC, 0x8152) ||
1729 CHK_SVID_SMID(0x10EC, 0x8154) ||
1730 CHK_SVID_SMID(0x10EC, 0x8155) ||
1731 CHK_SVID_SMID(0x10EC, 0x8181) ||
1732 CHK_SVID_SMID(0x10EC, 0x8182) ||
1733 CHK_SVID_SMID(0x10EC, 0x8184) ||
1734 CHK_SVID_SMID(0x10EC, 0x8185) ||
1735 CHK_SVID_SMID(0x10EC, 0x9151) ||
1736 CHK_SVID_SMID(0x10EC, 0x9152) ||
1737 CHK_SVID_SMID(0x10EC, 0x9154) ||
1738 CHK_SVID_SMID(0x10EC, 0x9155) ||
1739 CHK_SVID_SMID(0x10EC, 0x9181) ||
1740 CHK_SVID_SMID(0x10EC, 0x9182) ||
1741 CHK_SVID_SMID(0x10EC, 0x9184) ||
1742 CHK_SVID_SMID(0x10EC, 0x9185))
1743 rtlhal
->oem_id
= RT_CID_TOSHIBA
;
1744 else if (rtlefuse
->eeprom_svid
== 0x1025)
1745 rtlhal
->oem_id
= RT_CID_819X_ACER
;
1746 else if (CHK_SVID_SMID(0x10EC, 0x6191) ||
1747 CHK_SVID_SMID(0x10EC, 0x6192) ||
1748 CHK_SVID_SMID(0x10EC, 0x6193) ||
1749 CHK_SVID_SMID(0x10EC, 0x7191) ||
1750 CHK_SVID_SMID(0x10EC, 0x7192) ||
1751 CHK_SVID_SMID(0x10EC, 0x7193) ||
1752 CHK_SVID_SMID(0x10EC, 0x8191) ||
1753 CHK_SVID_SMID(0x10EC, 0x8192) ||
1754 CHK_SVID_SMID(0x10EC, 0x8193) ||
1755 CHK_SVID_SMID(0x10EC, 0x9191) ||
1756 CHK_SVID_SMID(0x10EC, 0x9192) ||
1757 CHK_SVID_SMID(0x10EC, 0x9193))
1758 rtlhal
->oem_id
= RT_CID_819X_SAMSUNG
;
1759 else if (CHK_SVID_SMID(0x10EC, 0x8195) ||
1760 CHK_SVID_SMID(0x10EC, 0x9195) ||
1761 CHK_SVID_SMID(0x10EC, 0x7194) ||
1762 CHK_SVID_SMID(0x10EC, 0x8200) ||
1763 CHK_SVID_SMID(0x10EC, 0x8201) ||
1764 CHK_SVID_SMID(0x10EC, 0x8202) ||
1765 CHK_SVID_SMID(0x10EC, 0x9200))
1766 rtlhal
->oem_id
= RT_CID_819X_LENOVO
;
1767 else if (CHK_SVID_SMID(0x10EC, 0x8197) ||
1768 CHK_SVID_SMID(0x10EC, 0x9196))
1769 rtlhal
->oem_id
= RT_CID_819X_CLEVO
;
1770 else if (CHK_SVID_SMID(0x1028, 0x8194) ||
1771 CHK_SVID_SMID(0x1028, 0x8198) ||
1772 CHK_SVID_SMID(0x1028, 0x9197) ||
1773 CHK_SVID_SMID(0x1028, 0x9198))
1774 rtlhal
->oem_id
= RT_CID_819X_DELL
;
1775 else if (CHK_SVID_SMID(0x103C, 0x1629))
1776 rtlhal
->oem_id
= RT_CID_819X_HP
;
1777 else if (CHK_SVID_SMID(0x1A32, 0x2315))
1778 rtlhal
->oem_id
= RT_CID_819X_QMI
;
1779 else if (CHK_SVID_SMID(0x10EC, 0x8203))
1780 rtlhal
->oem_id
= RT_CID_819X_PRONETS
;
1781 else if (CHK_SVID_SMID(0x1043, 0x84B5))
1783 RT_CID_819X_EDIMAX_ASUS
;
1785 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1786 } else if (rtlefuse
->eeprom_did
== 0x8178) {
1787 if (CHK_SVID_SMID(0x10EC, 0x6181) ||
1788 CHK_SVID_SMID(0x10EC, 0x6182) ||
1789 CHK_SVID_SMID(0x10EC, 0x6184) ||
1790 CHK_SVID_SMID(0x10EC, 0x6185) ||
1791 CHK_SVID_SMID(0x10EC, 0x7181) ||
1792 CHK_SVID_SMID(0x10EC, 0x7182) ||
1793 CHK_SVID_SMID(0x10EC, 0x7184) ||
1794 CHK_SVID_SMID(0x10EC, 0x7185) ||
1795 CHK_SVID_SMID(0x10EC, 0x8181) ||
1796 CHK_SVID_SMID(0x10EC, 0x8182) ||
1797 CHK_SVID_SMID(0x10EC, 0x8184) ||
1798 CHK_SVID_SMID(0x10EC, 0x8185) ||
1799 CHK_SVID_SMID(0x10EC, 0x9181) ||
1800 CHK_SVID_SMID(0x10EC, 0x9182) ||
1801 CHK_SVID_SMID(0x10EC, 0x9184) ||
1802 CHK_SVID_SMID(0x10EC, 0x9185))
1803 rtlhal
->oem_id
= RT_CID_TOSHIBA
;
1804 else if (rtlefuse
->eeprom_svid
== 0x1025)
1805 rtlhal
->oem_id
= RT_CID_819X_ACER
;
1806 else if (CHK_SVID_SMID(0x10EC, 0x8186))
1807 rtlhal
->oem_id
= RT_CID_819X_PRONETS
;
1808 else if (CHK_SVID_SMID(0x1043, 0x8486))
1810 RT_CID_819X_EDIMAX_ASUS
;
1812 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1814 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1817 case EEPROM_CID_TOSHIBA
:
1818 rtlhal
->oem_id
= RT_CID_TOSHIBA
;
1820 case EEPROM_CID_CCX
:
1821 rtlhal
->oem_id
= RT_CID_CCX
;
1823 case EEPROM_CID_QMI
:
1824 rtlhal
->oem_id
= RT_CID_819X_QMI
;
1826 case EEPROM_CID_WHQL
:
1829 rtlhal
->oem_id
= RT_CID_DEFAULT
;
1836 static void _rtl8723e_hal_customized_behavior(struct ieee80211_hw
*hw
)
1838 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1839 struct rtl_pci_priv
*pcipriv
= rtl_pcipriv(hw
);
1840 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1842 pcipriv
->ledctl
.led_opendrain
= true;
1843 switch (rtlhal
->oem_id
) {
1844 case RT_CID_819X_HP
:
1845 pcipriv
->ledctl
.led_opendrain
= true;
1847 case RT_CID_819X_LENOVO
:
1848 case RT_CID_DEFAULT
:
1849 case RT_CID_TOSHIBA
:
1851 case RT_CID_819X_ACER
:
1856 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
,
1857 "RT Customized ID: 0x%02X\n", rtlhal
->oem_id
);
1860 void rtl8723e_read_eeprom_info(struct ieee80211_hw
*hw
)
1862 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1863 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
1864 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1865 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1869 value32
= rtl_read_dword(rtlpriv
, rtlpriv
->cfg
->maps
[EFUSE_TEST
]);
1870 value32
= (value32
& ~EFUSE_SEL_MASK
) | EFUSE_SEL(EFUSE_WIFI_SEL_0
);
1871 rtl_write_dword(rtlpriv
, rtlpriv
->cfg
->maps
[EFUSE_TEST
], value32
);
1873 rtlhal
->version
= _rtl8723e_read_chip_version(hw
);
1875 if (get_rf_type(rtlphy
) == RF_1T1R
)
1876 rtlpriv
->dm
.rfpath_rxenable
[0] = true;
1878 rtlpriv
->dm
.rfpath_rxenable
[0] =
1879 rtlpriv
->dm
.rfpath_rxenable
[1] = true;
1880 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "VersionID = 0x%4x\n",
1883 tmp_u1b
= rtl_read_byte(rtlpriv
, REG_9346CR
);
1884 if (tmp_u1b
& BIT(4)) {
1885 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EEPROM\n");
1886 rtlefuse
->epromtype
= EEPROM_93C46
;
1888 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_DMESG
, "Boot from EFUSE\n");
1889 rtlefuse
->epromtype
= EEPROM_BOOT_EFUSE
;
1891 if (tmp_u1b
& BIT(5)) {
1892 RT_TRACE(rtlpriv
, COMP_INIT
, DBG_LOUD
, "Autoload OK\n");
1893 rtlefuse
->autoload_failflag
= false;
1894 _rtl8723e_read_adapter_info(hw
, false);
1896 rtlefuse
->autoload_failflag
= true;
1897 _rtl8723e_read_adapter_info(hw
, false);
1898 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_EMERG
, "Autoload ERR!!\n");
1900 _rtl8723e_hal_customized_behavior(hw
);
1903 static void rtl8723e_update_hal_rate_table(struct ieee80211_hw
*hw
,
1904 struct ieee80211_sta
*sta
)
1906 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1907 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1908 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1909 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
1912 u8 b_nmode
= mac
->ht_enable
;
1915 u8 curtxbw_40mhz
= mac
->bw_40
;
1916 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
1918 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
1920 enum wireless_mode wirelessmode
= mac
->mode
;
1923 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
1924 ratr_value
= sta
->supp_rates
[1] << 4;
1926 ratr_value
= sta
->supp_rates
[0];
1927 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
)
1929 ratr_value
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
1930 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
1931 switch (wirelessmode
) {
1932 case WIRELESS_MODE_B
:
1933 if (ratr_value
& 0x0000000c)
1934 ratr_value
&= 0x0000000d;
1936 ratr_value
&= 0x0000000f;
1938 case WIRELESS_MODE_G
:
1939 ratr_value
&= 0x00000FF5;
1941 case WIRELESS_MODE_N_24G
:
1942 case WIRELESS_MODE_N_5G
:
1944 if (get_rf_type(rtlphy
) == RF_1T2R
||
1945 get_rf_type(rtlphy
) == RF_1T1R
)
1946 ratr_mask
= 0x000ff005;
1948 ratr_mask
= 0x0f0ff005;
1950 ratr_value
&= ratr_mask
;
1953 if (rtlphy
->rf_type
== RF_1T2R
)
1954 ratr_value
&= 0x000ff0ff;
1956 ratr_value
&= 0x0f0ff0ff;
1961 if ((rtlpriv
->btcoexist
.bt_coexistence
) &&
1962 (rtlpriv
->btcoexist
.bt_coexist_type
== BT_CSR_BC4
) &&
1963 (rtlpriv
->btcoexist
.bt_cur_state
) &&
1964 (rtlpriv
->btcoexist
.bt_ant_isolation
) &&
1965 ((rtlpriv
->btcoexist
.bt_service
== BT_SCO
) ||
1966 (rtlpriv
->btcoexist
.bt_service
== BT_BUSY
)))
1967 ratr_value
&= 0x0fffcfc0;
1969 ratr_value
&= 0x0FFFFFFF;
1972 ((curtxbw_40mhz
&& curshortgi_40mhz
) ||
1973 (!curtxbw_40mhz
&& curshortgi_20mhz
))) {
1974 ratr_value
|= 0x10000000;
1975 tmp_ratr_value
= (ratr_value
>> 12);
1977 for (shortgi_rate
= 15; shortgi_rate
> 0; shortgi_rate
--) {
1978 if ((1 << shortgi_rate
) & tmp_ratr_value
)
1982 shortgi_rate
= (shortgi_rate
<< 12) | (shortgi_rate
<< 8) |
1983 (shortgi_rate
<< 4) | (shortgi_rate
);
1986 rtl_write_dword(rtlpriv
, REG_ARFR0
+ ratr_index
* 4, ratr_value
);
1988 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
1989 "%x\n", rtl_read_dword(rtlpriv
, REG_ARFR0
));
1992 static void rtl8723e_update_hal_rate_mask(struct ieee80211_hw
*hw
,
1993 struct ieee80211_sta
*sta
,
1996 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
1997 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
1998 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
1999 struct rtl_hal
*rtlhal
= rtl_hal(rtl_priv(hw
));
2000 struct rtl_sta_info
*sta_entry
= NULL
;
2003 u8 curtxbw_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SUP_WIDTH_20_40
)
2005 u8 curshortgi_40mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_40
) ?
2007 u8 curshortgi_20mhz
= (sta
->ht_cap
.cap
& IEEE80211_HT_CAP_SGI_20
) ?
2009 enum wireless_mode wirelessmode
= 0;
2010 bool shortgi
= false;
2013 /*u8 mimo_ps = IEEE80211_SMPS_OFF;*/
2015 sta_entry
= (struct rtl_sta_info
*)sta
->drv_priv
;
2016 wirelessmode
= sta_entry
->wireless_mode
;
2017 if (mac
->opmode
== NL80211_IFTYPE_STATION
)
2018 curtxbw_40mhz
= mac
->bw_40
;
2019 else if (mac
->opmode
== NL80211_IFTYPE_AP
||
2020 mac
->opmode
== NL80211_IFTYPE_ADHOC
)
2021 macid
= sta
->aid
+ 1;
2023 if (rtlhal
->current_bandtype
== BAND_ON_5G
)
2024 ratr_bitmap
= sta
->supp_rates
[1] << 4;
2026 ratr_bitmap
= sta
->supp_rates
[0];
2027 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
)
2028 ratr_bitmap
= 0xfff;
2029 ratr_bitmap
|= (sta
->ht_cap
.mcs
.rx_mask
[1] << 20 |
2030 sta
->ht_cap
.mcs
.rx_mask
[0] << 12);
2031 switch (wirelessmode
) {
2032 case WIRELESS_MODE_B
:
2033 ratr_index
= RATR_INX_WIRELESS_B
;
2034 if (ratr_bitmap
& 0x0000000c)
2035 ratr_bitmap
&= 0x0000000d;
2037 ratr_bitmap
&= 0x0000000f;
2039 case WIRELESS_MODE_G
:
2040 ratr_index
= RATR_INX_WIRELESS_GB
;
2042 if (rssi_level
== 1)
2043 ratr_bitmap
&= 0x00000f00;
2044 else if (rssi_level
== 2)
2045 ratr_bitmap
&= 0x00000ff0;
2047 ratr_bitmap
&= 0x00000ff5;
2049 case WIRELESS_MODE_A
:
2050 ratr_index
= RATR_INX_WIRELESS_G
;
2051 ratr_bitmap
&= 0x00000ff0;
2053 case WIRELESS_MODE_N_24G
:
2054 case WIRELESS_MODE_N_5G
:
2055 ratr_index
= RATR_INX_WIRELESS_NGB
;
2056 if (rtlphy
->rf_type
== RF_1T2R
||
2057 rtlphy
->rf_type
== RF_1T1R
) {
2058 if (curtxbw_40mhz
) {
2059 if (rssi_level
== 1)
2060 ratr_bitmap
&= 0x000f0000;
2061 else if (rssi_level
== 2)
2062 ratr_bitmap
&= 0x000ff000;
2064 ratr_bitmap
&= 0x000ff015;
2066 if (rssi_level
== 1)
2067 ratr_bitmap
&= 0x000f0000;
2068 else if (rssi_level
== 2)
2069 ratr_bitmap
&= 0x000ff000;
2071 ratr_bitmap
&= 0x000ff005;
2074 if (curtxbw_40mhz
) {
2075 if (rssi_level
== 1)
2076 ratr_bitmap
&= 0x0f0f0000;
2077 else if (rssi_level
== 2)
2078 ratr_bitmap
&= 0x0f0ff000;
2080 ratr_bitmap
&= 0x0f0ff015;
2082 if (rssi_level
== 1)
2083 ratr_bitmap
&= 0x0f0f0000;
2084 else if (rssi_level
== 2)
2085 ratr_bitmap
&= 0x0f0ff000;
2087 ratr_bitmap
&= 0x0f0ff005;
2091 if ((curtxbw_40mhz
&& curshortgi_40mhz
) ||
2092 (!curtxbw_40mhz
&& curshortgi_20mhz
)) {
2095 else if (macid
== 1)
2100 ratr_index
= RATR_INX_WIRELESS_NGB
;
2102 if (rtlphy
->rf_type
== RF_1T2R
)
2103 ratr_bitmap
&= 0x000ff0ff;
2105 ratr_bitmap
&= 0x0f0ff0ff;
2108 sta_entry
->ratr_index
= ratr_index
;
2110 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
2111 "ratr_bitmap :%x\n", ratr_bitmap
);
2112 *(u32
*)&rate_mask
= (ratr_bitmap
& 0x0fffffff) |
2114 rate_mask
[4] = macid
| (shortgi
? 0x20 : 0x00) | 0x80;
2115 RT_TRACE(rtlpriv
, COMP_RATR
, DBG_DMESG
,
2116 "Rate_index:%x, ratr_val:%x, %x:%x:%x:%x:%x\n",
2117 ratr_index
, ratr_bitmap
,
2118 rate_mask
[0], rate_mask
[1],
2119 rate_mask
[2], rate_mask
[3],
2121 rtl8723e_fill_h2c_cmd(hw
, H2C_RA_MASK
, 5, rate_mask
);
2124 void rtl8723e_update_hal_rate_tbl(struct ieee80211_hw
*hw
,
2125 struct ieee80211_sta
*sta
, u8 rssi_level
)
2127 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2129 if (rtlpriv
->dm
.useramask
)
2130 rtl8723e_update_hal_rate_mask(hw
, sta
, rssi_level
);
2132 rtl8723e_update_hal_rate_table(hw
, sta
);
2135 void rtl8723e_update_channel_access_setting(struct ieee80211_hw
*hw
)
2137 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2138 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2141 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SLOT_TIME
, &mac
->slot_time
);
2142 if (!mac
->ht_enable
)
2143 sifs_timer
= 0x0a0a;
2145 sifs_timer
= 0x1010;
2146 rtlpriv
->cfg
->ops
->set_hw_reg(hw
, HW_VAR_SIFS
, (u8
*)&sifs_timer
);
2149 bool rtl8723e_gpio_radio_on_off_checking(struct ieee80211_hw
*hw
, u8
*valid
)
2151 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2152 struct rtl_ps_ctl
*ppsc
= rtl_psc(rtl_priv(hw
));
2153 struct rtl_phy
*rtlphy
= &(rtlpriv
->phy
);
2154 enum rf_pwrstate e_rfpowerstate_toset
, cur_rfstate
;
2156 bool b_actuallyset
= false;
2158 if (rtlpriv
->rtlhal
.being_init_adapter
)
2161 if (ppsc
->swrf_processing
)
2164 spin_lock(&rtlpriv
->locks
.rf_ps_lock
);
2165 if (ppsc
->rfchange_inprogress
) {
2166 spin_unlock(&rtlpriv
->locks
.rf_ps_lock
);
2169 ppsc
->rfchange_inprogress
= true;
2170 spin_unlock(&rtlpriv
->locks
.rf_ps_lock
);
2173 cur_rfstate
= ppsc
->rfpwr_state
;
2175 rtl_write_byte(rtlpriv
, REG_GPIO_IO_SEL_2
,
2176 rtl_read_byte(rtlpriv
, REG_GPIO_IO_SEL_2
)&~(BIT(1)));
2178 u1tmp
= rtl_read_byte(rtlpriv
, REG_GPIO_PIN_CTRL_2
);
2180 if (rtlphy
->polarity_ctl
)
2181 e_rfpowerstate_toset
= (u1tmp
& BIT(1)) ? ERFOFF
: ERFON
;
2183 e_rfpowerstate_toset
= (u1tmp
& BIT(1)) ? ERFON
: ERFOFF
;
2185 if (ppsc
->hwradiooff
&& (e_rfpowerstate_toset
== ERFON
)) {
2186 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
2187 "GPIOChangeRF - HW Radio ON, RF ON\n");
2189 e_rfpowerstate_toset
= ERFON
;
2190 ppsc
->hwradiooff
= false;
2191 b_actuallyset
= true;
2192 } else if (!ppsc
->hwradiooff
&& (e_rfpowerstate_toset
== ERFOFF
)) {
2193 RT_TRACE(rtlpriv
, COMP_RF
, DBG_DMESG
,
2194 "GPIOChangeRF - HW Radio OFF, RF OFF\n");
2196 e_rfpowerstate_toset
= ERFOFF
;
2197 ppsc
->hwradiooff
= true;
2198 b_actuallyset
= true;
2201 if (b_actuallyset
) {
2202 spin_lock(&rtlpriv
->locks
.rf_ps_lock
);
2203 ppsc
->rfchange_inprogress
= false;
2204 spin_unlock(&rtlpriv
->locks
.rf_ps_lock
);
2206 if (ppsc
->reg_rfps_level
& RT_RF_OFF_LEVL_HALT_NIC
)
2207 RT_SET_PS_LEVEL(ppsc
, RT_RF_OFF_LEVL_HALT_NIC
);
2209 spin_lock(&rtlpriv
->locks
.rf_ps_lock
);
2210 ppsc
->rfchange_inprogress
= false;
2211 spin_unlock(&rtlpriv
->locks
.rf_ps_lock
);
2215 return !ppsc
->hwradiooff
;
2219 void rtl8723e_set_key(struct ieee80211_hw
*hw
, u32 key_index
,
2220 u8
*p_macaddr
, bool is_group
, u8 enc_algo
,
2221 bool is_wepkey
, bool clear_all
)
2223 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2224 struct rtl_mac
*mac
= rtl_mac(rtl_priv(hw
));
2225 struct rtl_efuse
*rtlefuse
= rtl_efuse(rtl_priv(hw
));
2226 u8
*macaddr
= p_macaddr
;
2228 bool is_pairwise
= false;
2230 static u8 cam_const_addr
[4][6] = {
2231 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
2232 {0x00, 0x00, 0x00, 0x00, 0x00, 0x01},
2233 {0x00, 0x00, 0x00, 0x00, 0x00, 0x02},
2234 {0x00, 0x00, 0x00, 0x00, 0x00, 0x03}
2236 static u8 cam_const_broad
[] = {
2237 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
2243 u8 clear_number
= 5;
2245 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
, "clear_all\n");
2247 for (idx
= 0; idx
< clear_number
; idx
++) {
2248 rtl_cam_mark_invalid(hw
, cam_offset
+ idx
);
2249 rtl_cam_empty_entry(hw
, cam_offset
+ idx
);
2252 memset(rtlpriv
->sec
.key_buf
[idx
], 0,
2254 rtlpriv
->sec
.key_len
[idx
] = 0;
2260 case WEP40_ENCRYPTION
:
2261 enc_algo
= CAM_WEP40
;
2263 case WEP104_ENCRYPTION
:
2264 enc_algo
= CAM_WEP104
;
2266 case TKIP_ENCRYPTION
:
2267 enc_algo
= CAM_TKIP
;
2269 case AESCCMP_ENCRYPTION
:
2273 RT_TRACE(rtlpriv
, COMP_ERR
, DBG_LOUD
,
2274 "switch case not process\n");
2275 enc_algo
= CAM_TKIP
;
2279 if (is_wepkey
|| rtlpriv
->sec
.use_defaultkey
) {
2280 macaddr
= cam_const_addr
[key_index
];
2281 entry_id
= key_index
;
2284 macaddr
= cam_const_broad
;
2285 entry_id
= key_index
;
2287 if (mac
->opmode
== NL80211_IFTYPE_AP
) {
2289 rtl_cam_get_free_entry(hw
, p_macaddr
);
2290 if (entry_id
>= TOTAL_CAM_ENTRY
) {
2291 RT_TRACE(rtlpriv
, COMP_SEC
,
2293 "Can not find free hw security cam entry\n");
2297 entry_id
= CAM_PAIRWISE_KEY_POSITION
;
2300 key_index
= PAIRWISE_KEYIDX
;
2305 if (rtlpriv
->sec
.key_len
[key_index
] == 0) {
2306 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2307 "delete one entry, entry_id is %d\n",
2309 if (mac
->opmode
== NL80211_IFTYPE_AP
)
2310 rtl_cam_del_entry(hw
, p_macaddr
);
2311 rtl_cam_delete_one_entry(hw
, p_macaddr
, entry_id
);
2313 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2316 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2317 "set Pairwiase key\n");
2319 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2321 CAM_CONFIG_NO_USEDK
,
2322 rtlpriv
->sec
.key_buf
[key_index
]);
2324 RT_TRACE(rtlpriv
, COMP_SEC
, DBG_DMESG
,
2327 if (mac
->opmode
== NL80211_IFTYPE_ADHOC
) {
2328 rtl_cam_add_one_entry(hw
,
2331 CAM_PAIRWISE_KEY_POSITION
,
2333 CAM_CONFIG_NO_USEDK
,
2334 rtlpriv
->sec
.key_buf
2338 rtl_cam_add_one_entry(hw
, macaddr
, key_index
,
2340 CAM_CONFIG_NO_USEDK
,
2341 rtlpriv
->sec
.key_buf
[entry_id
]);
2348 static void rtl8723e_bt_var_init(struct ieee80211_hw
*hw
)
2350 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2352 rtlpriv
->btcoexist
.bt_coexistence
=
2353 rtlpriv
->btcoexist
.eeprom_bt_coexist
;
2354 rtlpriv
->btcoexist
.bt_ant_num
=
2355 rtlpriv
->btcoexist
.eeprom_bt_ant_num
;
2356 rtlpriv
->btcoexist
.bt_coexist_type
=
2357 rtlpriv
->btcoexist
.eeprom_bt_type
;
2359 rtlpriv
->btcoexist
.bt_ant_isolation
=
2360 rtlpriv
->btcoexist
.eeprom_bt_ant_isol
;
2362 rtlpriv
->btcoexist
.bt_radio_shared_type
=
2363 rtlpriv
->btcoexist
.eeprom_bt_radio_shared
;
2365 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2366 "BT Coexistance = 0x%x\n",
2367 rtlpriv
->btcoexist
.bt_coexistence
);
2369 if (rtlpriv
->btcoexist
.bt_coexistence
) {
2370 rtlpriv
->btcoexist
.bt_busy_traffic
= false;
2371 rtlpriv
->btcoexist
.bt_traffic_mode_set
= false;
2372 rtlpriv
->btcoexist
.bt_non_traffic_mode_set
= false;
2374 rtlpriv
->btcoexist
.cstate
= 0;
2375 rtlpriv
->btcoexist
.previous_state
= 0;
2377 if (rtlpriv
->btcoexist
.bt_ant_num
== ANT_X2
) {
2378 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2379 "BlueTooth BT_Ant_Num = Antx2\n");
2380 } else if (rtlpriv
->btcoexist
.bt_ant_num
== ANT_X1
) {
2381 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2382 "BlueTooth BT_Ant_Num = Antx1\n");
2384 switch (rtlpriv
->btcoexist
.bt_coexist_type
) {
2386 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2387 "BlueTooth BT_CoexistType = BT_2Wire\n");
2390 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2391 "BlueTooth BT_CoexistType = BT_ISSC_3Wire\n");
2394 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2395 "BlueTooth BT_CoexistType = BT_ACCEL\n");
2398 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2399 "BlueTooth BT_CoexistType = BT_CSR_BC4\n");
2402 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2403 "BlueTooth BT_CoexistType = BT_CSR_BC8\n");
2406 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2407 "BlueTooth BT_CoexistType = BT_RTL8756\n");
2410 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2411 "BlueTooth BT_CoexistType = Unknown\n");
2414 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2415 "BlueTooth BT_Ant_isolation = %d\n",
2416 rtlpriv
->btcoexist
.bt_ant_isolation
);
2417 RT_TRACE(rtlpriv
, COMP_BT_COEXIST
, DBG_TRACE
,
2418 "BT_RadioSharedType = 0x%x\n",
2419 rtlpriv
->btcoexist
.bt_radio_shared_type
);
2420 rtlpriv
->btcoexist
.bt_active_zero_cnt
= 0;
2421 rtlpriv
->btcoexist
.cur_bt_disabled
= false;
2422 rtlpriv
->btcoexist
.pre_bt_disabled
= false;
2426 void rtl8723e_read_bt_coexist_info_from_hwpg(struct ieee80211_hw
*hw
,
2427 bool auto_load_fail
, u8
*hwinfo
)
2429 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2433 if (!auto_load_fail
) {
2434 tmpu_32
= rtl_read_dword(rtlpriv
, REG_MULTI_FUNC_CTRL
);
2435 if (tmpu_32
& BIT(18))
2436 rtlpriv
->btcoexist
.eeprom_bt_coexist
= 1;
2438 rtlpriv
->btcoexist
.eeprom_bt_coexist
= 0;
2439 value
= hwinfo
[RF_OPTION4
];
2440 rtlpriv
->btcoexist
.eeprom_bt_type
= BT_RTL8723A
;
2441 rtlpriv
->btcoexist
.eeprom_bt_ant_num
= (value
& 0x1);
2442 rtlpriv
->btcoexist
.eeprom_bt_ant_isol
= ((value
& 0x10) >> 4);
2443 rtlpriv
->btcoexist
.eeprom_bt_radio_shared
=
2444 ((value
& 0x20) >> 5);
2446 rtlpriv
->btcoexist
.eeprom_bt_coexist
= 0;
2447 rtlpriv
->btcoexist
.eeprom_bt_type
= BT_RTL8723A
;
2448 rtlpriv
->btcoexist
.eeprom_bt_ant_num
= ANT_X2
;
2449 rtlpriv
->btcoexist
.eeprom_bt_ant_isol
= 0;
2450 rtlpriv
->btcoexist
.eeprom_bt_radio_shared
= BT_RADIO_SHARED
;
2453 rtl8723e_bt_var_init(hw
);
2456 void rtl8723e_bt_reg_init(struct ieee80211_hw
*hw
)
2458 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2460 /* 0:Low, 1:High, 2:From Efuse. */
2461 rtlpriv
->btcoexist
.reg_bt_iso
= 2;
2462 /* 0:Idle, 1:None-SCO, 2:SCO, 3:From Counter. */
2463 rtlpriv
->btcoexist
.reg_bt_sco
= 3;
2464 /* 0:Disable BT control A-MPDU, 1:Enable BT control A-MPDU. */
2465 rtlpriv
->btcoexist
.reg_bt_sco
= 0;
2468 void rtl8723e_bt_hw_init(struct ieee80211_hw
*hw
)
2470 struct rtl_priv
*rtlpriv
= rtl_priv(hw
);
2472 if (rtlpriv
->cfg
->ops
->get_btc_status())
2473 rtlpriv
->btcoexist
.btc_ops
->btc_init_hw_config(rtlpriv
);
2476 void rtl8723e_suspend(struct ieee80211_hw
*hw
)
2480 void rtl8723e_resume(struct ieee80211_hw
*hw
)