2 * Designware application register space functions for Keystone PCI controller
4 * Copyright (C) 2013-2014 Texas Instruments., Ltd.
7 * Author: Murali Karicheri <m-karicheri2@ti.com>
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
15 #include <linux/irq.h>
16 #include <linux/irqdomain.h>
17 #include <linux/module.h>
19 #include <linux/of_pci.h>
20 #include <linux/pci.h>
21 #include <linux/platform_device.h>
23 #include "pcie-designware.h"
24 #include "pci-keystone.h"
26 /* Application register defines */
27 #define LTSSM_EN_VAL 1
28 #define LTSSM_STATE_MASK 0x1f
29 #define LTSSM_STATE_L0 0x11
30 #define DBI_CS2_EN_VAL 0x20
31 #define OB_XLAT_EN_VAL 2
33 /* Application registers */
34 #define CMD_STATUS 0x004
35 #define CFG_SETUP 0x008
37 #define CFG_PCIM_WIN_SZ_IDX 3
38 #define CFG_PCIM_WIN_CNT 32
39 #define SPACE0_REMOTE_CFG_OFFSET 0x1000
40 #define OB_OFFSET_INDEX(n) (0x200 + (8 * n))
41 #define OB_OFFSET_HI(n) (0x204 + (8 * n))
43 /* IRQ register defines */
45 #define IRQ_STATUS 0x184
46 #define IRQ_ENABLE_SET 0x188
47 #define IRQ_ENABLE_CLR 0x18c
50 #define MSI0_IRQ_STATUS 0x104
51 #define MSI0_IRQ_ENABLE_SET 0x108
52 #define MSI0_IRQ_ENABLE_CLR 0x10c
53 #define IRQ_STATUS 0x184
54 #define MSI_IRQ_OFFSET 4
56 /* Config space registers */
59 #define to_keystone_pcie(x) container_of(x, struct keystone_pcie, pp)
61 static inline void update_reg_offset_bit_pos(u32 offset
, u32
*reg_offset
,
64 *reg_offset
= offset
% 8;
65 *bit_pos
= offset
>> 3;
68 phys_addr_t
ks_dw_pcie_get_msi_addr(struct pcie_port
*pp
)
70 struct keystone_pcie
*ks_pcie
= to_keystone_pcie(pp
);
72 return ks_pcie
->app
.start
+ MSI_IRQ
;
75 void ks_dw_pcie_handle_msi_irq(struct keystone_pcie
*ks_pcie
, int offset
)
77 struct pcie_port
*pp
= &ks_pcie
->pp
;
81 pending
= readl(ks_pcie
->va_app_base
+ MSI0_IRQ_STATUS
+ (offset
<< 4));
84 * MSI0 status bit 0-3 shows vectors 0, 8, 16, 24, MSI1 status bit
85 * shows 1, 9, 17, 25 and so forth
87 for (src
= 0; src
< 4; src
++) {
88 if (BIT(src
) & pending
) {
89 vector
= offset
+ (src
<< 3);
90 virq
= irq_linear_revmap(pp
->irq_domain
, vector
);
91 dev_dbg(pp
->dev
, "irq: bit %d, vector %d, virq %d\n",
93 generic_handle_irq(virq
);
98 static void ks_dw_pcie_msi_irq_ack(struct irq_data
*d
)
100 u32 offset
, reg_offset
, bit_pos
;
101 struct keystone_pcie
*ks_pcie
;
102 struct msi_desc
*msi
;
103 struct pcie_port
*pp
;
105 msi
= irq_data_get_msi_desc(d
);
106 pp
= (struct pcie_port
*) msi_desc_to_pci_sysdata(msi
);
107 ks_pcie
= to_keystone_pcie(pp
);
108 offset
= d
->irq
- irq_linear_revmap(pp
->irq_domain
, 0);
109 update_reg_offset_bit_pos(offset
, ®_offset
, &bit_pos
);
112 ks_pcie
->va_app_base
+ MSI0_IRQ_STATUS
+ (reg_offset
<< 4));
113 writel(reg_offset
+ MSI_IRQ_OFFSET
, ks_pcie
->va_app_base
+ IRQ_EOI
);
116 void ks_dw_pcie_msi_set_irq(struct pcie_port
*pp
, int irq
)
118 u32 reg_offset
, bit_pos
;
119 struct keystone_pcie
*ks_pcie
= to_keystone_pcie(pp
);
121 update_reg_offset_bit_pos(irq
, ®_offset
, &bit_pos
);
123 ks_pcie
->va_app_base
+ MSI0_IRQ_ENABLE_SET
+ (reg_offset
<< 4));
126 void ks_dw_pcie_msi_clear_irq(struct pcie_port
*pp
, int irq
)
128 u32 reg_offset
, bit_pos
;
129 struct keystone_pcie
*ks_pcie
= to_keystone_pcie(pp
);
131 update_reg_offset_bit_pos(irq
, ®_offset
, &bit_pos
);
133 ks_pcie
->va_app_base
+ MSI0_IRQ_ENABLE_CLR
+ (reg_offset
<< 4));
136 static void ks_dw_pcie_msi_irq_mask(struct irq_data
*d
)
138 struct keystone_pcie
*ks_pcie
;
139 struct msi_desc
*msi
;
140 struct pcie_port
*pp
;
143 msi
= irq_data_get_msi_desc(d
);
144 pp
= (struct pcie_port
*) msi_desc_to_pci_sysdata(msi
);
145 ks_pcie
= to_keystone_pcie(pp
);
146 offset
= d
->irq
- irq_linear_revmap(pp
->irq_domain
, 0);
148 /* Mask the end point if PVM implemented */
149 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
150 if (msi
->msi_attrib
.maskbit
)
154 ks_dw_pcie_msi_clear_irq(pp
, offset
);
157 static void ks_dw_pcie_msi_irq_unmask(struct irq_data
*d
)
159 struct keystone_pcie
*ks_pcie
;
160 struct msi_desc
*msi
;
161 struct pcie_port
*pp
;
164 msi
= irq_data_get_msi_desc(d
);
165 pp
= (struct pcie_port
*) msi_desc_to_pci_sysdata(msi
);
166 ks_pcie
= to_keystone_pcie(pp
);
167 offset
= d
->irq
- irq_linear_revmap(pp
->irq_domain
, 0);
169 /* Mask the end point if PVM implemented */
170 if (IS_ENABLED(CONFIG_PCI_MSI
)) {
171 if (msi
->msi_attrib
.maskbit
)
172 pci_msi_unmask_irq(d
);
175 ks_dw_pcie_msi_set_irq(pp
, offset
);
178 static struct irq_chip ks_dw_pcie_msi_irq_chip
= {
179 .name
= "Keystone-PCIe-MSI-IRQ",
180 .irq_ack
= ks_dw_pcie_msi_irq_ack
,
181 .irq_mask
= ks_dw_pcie_msi_irq_mask
,
182 .irq_unmask
= ks_dw_pcie_msi_irq_unmask
,
185 static int ks_dw_pcie_msi_map(struct irq_domain
*domain
, unsigned int irq
,
186 irq_hw_number_t hwirq
)
188 irq_set_chip_and_handler(irq
, &ks_dw_pcie_msi_irq_chip
,
190 irq_set_chip_data(irq
, domain
->host_data
);
195 static const struct irq_domain_ops ks_dw_pcie_msi_domain_ops
= {
196 .map
= ks_dw_pcie_msi_map
,
199 int ks_dw_pcie_msi_host_init(struct pcie_port
*pp
, struct msi_controller
*chip
)
201 struct keystone_pcie
*ks_pcie
= to_keystone_pcie(pp
);
204 pp
->irq_domain
= irq_domain_add_linear(ks_pcie
->msi_intc_np
,
206 &ks_dw_pcie_msi_domain_ops
,
208 if (!pp
->irq_domain
) {
209 dev_err(pp
->dev
, "irq domain init failed\n");
213 for (i
= 0; i
< MAX_MSI_IRQS
; i
++)
214 irq_create_mapping(pp
->irq_domain
, i
);
219 void ks_dw_pcie_enable_legacy_irqs(struct keystone_pcie
*ks_pcie
)
223 for (i
= 0; i
< MAX_LEGACY_IRQS
; i
++)
224 writel(0x1, ks_pcie
->va_app_base
+ IRQ_ENABLE_SET
+ (i
<< 4));
227 void ks_dw_pcie_handle_legacy_irq(struct keystone_pcie
*ks_pcie
, int offset
)
229 struct pcie_port
*pp
= &ks_pcie
->pp
;
233 pending
= readl(ks_pcie
->va_app_base
+ IRQ_STATUS
+ (offset
<< 4));
235 if (BIT(0) & pending
) {
236 virq
= irq_linear_revmap(ks_pcie
->legacy_irq_domain
, offset
);
237 dev_dbg(pp
->dev
, ": irq: irq_offset %d, virq %d\n", offset
,
239 generic_handle_irq(virq
);
242 /* EOI the INTx interrupt */
243 writel(offset
, ks_pcie
->va_app_base
+ IRQ_EOI
);
246 static void ks_dw_pcie_ack_legacy_irq(struct irq_data
*d
)
250 static void ks_dw_pcie_mask_legacy_irq(struct irq_data
*d
)
254 static void ks_dw_pcie_unmask_legacy_irq(struct irq_data
*d
)
258 static struct irq_chip ks_dw_pcie_legacy_irq_chip
= {
259 .name
= "Keystone-PCI-Legacy-IRQ",
260 .irq_ack
= ks_dw_pcie_ack_legacy_irq
,
261 .irq_mask
= ks_dw_pcie_mask_legacy_irq
,
262 .irq_unmask
= ks_dw_pcie_unmask_legacy_irq
,
265 static int ks_dw_pcie_init_legacy_irq_map(struct irq_domain
*d
,
266 unsigned int irq
, irq_hw_number_t hw_irq
)
268 irq_set_chip_and_handler(irq
, &ks_dw_pcie_legacy_irq_chip
,
270 irq_set_chip_data(irq
, d
->host_data
);
275 static const struct irq_domain_ops ks_dw_pcie_legacy_irq_domain_ops
= {
276 .map
= ks_dw_pcie_init_legacy_irq_map
,
277 .xlate
= irq_domain_xlate_onetwocell
,
281 * ks_dw_pcie_set_dbi_mode() - Set DBI mode to access overlaid BAR mask
284 * Since modification of dbi_cs2 involves different clock domain, read the
285 * status back to ensure the transition is complete.
287 static void ks_dw_pcie_set_dbi_mode(void __iomem
*reg_virt
)
291 writel(DBI_CS2_EN_VAL
| readl(reg_virt
+ CMD_STATUS
),
292 reg_virt
+ CMD_STATUS
);
295 val
= readl(reg_virt
+ CMD_STATUS
);
296 } while (!(val
& DBI_CS2_EN_VAL
));
300 * ks_dw_pcie_clear_dbi_mode() - Disable DBI mode
302 * Since modification of dbi_cs2 involves different clock domain, read the
303 * status back to ensure the transition is complete.
305 static void ks_dw_pcie_clear_dbi_mode(void __iomem
*reg_virt
)
309 writel(~DBI_CS2_EN_VAL
& readl(reg_virt
+ CMD_STATUS
),
310 reg_virt
+ CMD_STATUS
);
313 val
= readl(reg_virt
+ CMD_STATUS
);
314 } while (val
& DBI_CS2_EN_VAL
);
317 void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie
*ks_pcie
)
319 struct pcie_port
*pp
= &ks_pcie
->pp
;
320 u32 start
= pp
->mem
->start
, end
= pp
->mem
->end
;
323 /* Disable BARs for inbound access */
324 ks_dw_pcie_set_dbi_mode(ks_pcie
->va_app_base
);
325 writel(0, pp
->dbi_base
+ PCI_BASE_ADDRESS_0
);
326 writel(0, pp
->dbi_base
+ PCI_BASE_ADDRESS_1
);
327 ks_dw_pcie_clear_dbi_mode(ks_pcie
->va_app_base
);
329 /* Set outbound translation size per window division */
330 writel(CFG_PCIM_WIN_SZ_IDX
& 0x7, ks_pcie
->va_app_base
+ OB_SIZE
);
332 tr_size
= (1 << (CFG_PCIM_WIN_SZ_IDX
& 0x7)) * SZ_1M
;
334 /* Using Direct 1:1 mapping of RC <-> PCI memory space */
335 for (i
= 0; (i
< CFG_PCIM_WIN_CNT
) && (start
< end
); i
++) {
336 writel(start
| 1, ks_pcie
->va_app_base
+ OB_OFFSET_INDEX(i
));
337 writel(0, ks_pcie
->va_app_base
+ OB_OFFSET_HI(i
));
341 /* Enable OB translation */
342 writel(OB_XLAT_EN_VAL
| readl(ks_pcie
->va_app_base
+ CMD_STATUS
),
343 ks_pcie
->va_app_base
+ CMD_STATUS
);
347 * ks_pcie_cfg_setup() - Set up configuration space address for a device
349 * @ks_pcie: ptr to keystone_pcie structure
350 * @bus: Bus number the device is residing on
351 * @devfn: device, function number info
353 * Forms and returns the address of configuration space mapped in PCIESS
354 * address space 0. Also configures CFG_SETUP for remote configuration space
357 * The address space has two regions to access configuration - local and remote.
358 * We access local region for bus 0 (as RC is attached on bus 0) and remote
359 * region for others with TYPE 1 access when bus > 1. As for device on bus = 1,
360 * we will do TYPE 0 access as it will be on our secondary bus (logical).
361 * CFG_SETUP is needed only for remote configuration access.
363 static void __iomem
*ks_pcie_cfg_setup(struct keystone_pcie
*ks_pcie
, u8 bus
,
366 u8 device
= PCI_SLOT(devfn
), function
= PCI_FUNC(devfn
);
367 struct pcie_port
*pp
= &ks_pcie
->pp
;
373 regval
= (bus
<< 16) | (device
<< 8) | function
;
376 * Since Bus#1 will be a virtual bus, we need to have TYPE0
383 writel(regval
, ks_pcie
->va_app_base
+ CFG_SETUP
);
384 return pp
->va_cfg0_base
;
387 int ks_dw_pcie_rd_other_conf(struct pcie_port
*pp
, struct pci_bus
*bus
,
388 unsigned int devfn
, int where
, int size
, u32
*val
)
390 struct keystone_pcie
*ks_pcie
= to_keystone_pcie(pp
);
391 u8 bus_num
= bus
->number
;
394 addr
= ks_pcie_cfg_setup(ks_pcie
, bus_num
, devfn
);
396 return dw_pcie_cfg_read(addr
+ where
, size
, val
);
399 int ks_dw_pcie_wr_other_conf(struct pcie_port
*pp
, struct pci_bus
*bus
,
400 unsigned int devfn
, int where
, int size
, u32 val
)
402 struct keystone_pcie
*ks_pcie
= to_keystone_pcie(pp
);
403 u8 bus_num
= bus
->number
;
406 addr
= ks_pcie_cfg_setup(ks_pcie
, bus_num
, devfn
);
408 return dw_pcie_cfg_write(addr
+ where
, size
, val
);
412 * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization
414 * This sets BAR0 to enable inbound access for MSI_IRQ register
416 void ks_dw_pcie_v3_65_scan_bus(struct pcie_port
*pp
)
418 struct keystone_pcie
*ks_pcie
= to_keystone_pcie(pp
);
420 /* Configure and set up BAR0 */
421 ks_dw_pcie_set_dbi_mode(ks_pcie
->va_app_base
);
424 writel(1, pp
->dbi_base
+ PCI_BASE_ADDRESS_0
);
425 writel(SZ_4K
- 1, pp
->dbi_base
+ PCI_BASE_ADDRESS_0
);
427 ks_dw_pcie_clear_dbi_mode(ks_pcie
->va_app_base
);
430 * For BAR0, just setting bus address for inbound writes (MSI) should
431 * be sufficient. Use physical address to avoid any conflicts.
433 writel(ks_pcie
->app
.start
, pp
->dbi_base
+ PCI_BASE_ADDRESS_0
);
437 * ks_dw_pcie_link_up() - Check if link up
439 int ks_dw_pcie_link_up(struct pcie_port
*pp
)
441 u32 val
= readl(pp
->dbi_base
+ DEBUG0
);
443 return (val
& LTSSM_STATE_MASK
) == LTSSM_STATE_L0
;
446 void ks_dw_pcie_initiate_link_train(struct keystone_pcie
*ks_pcie
)
450 /* Disable Link training */
451 val
= readl(ks_pcie
->va_app_base
+ CMD_STATUS
);
452 val
&= ~LTSSM_EN_VAL
;
453 writel(LTSSM_EN_VAL
| val
, ks_pcie
->va_app_base
+ CMD_STATUS
);
455 /* Initiate Link Training */
456 val
= readl(ks_pcie
->va_app_base
+ CMD_STATUS
);
457 writel(LTSSM_EN_VAL
| val
, ks_pcie
->va_app_base
+ CMD_STATUS
);
461 * ks_dw_pcie_host_init() - initialize host for v3_65 dw hardware
463 * Ioremap the register resources, initialize legacy irq domain
464 * and call dw_pcie_v3_65_host_init() API to initialize the Keystone
465 * PCI host controller.
467 int __init
ks_dw_pcie_host_init(struct keystone_pcie
*ks_pcie
,
468 struct device_node
*msi_intc_np
)
470 struct pcie_port
*pp
= &ks_pcie
->pp
;
471 struct platform_device
*pdev
= to_platform_device(pp
->dev
);
472 struct resource
*res
;
474 /* Index 0 is the config reg. space address */
475 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 0);
476 pp
->dbi_base
= devm_ioremap_resource(pp
->dev
, res
);
477 if (IS_ERR(pp
->dbi_base
))
478 return PTR_ERR(pp
->dbi_base
);
481 * We set these same and is used in pcie rd/wr_other_conf
484 pp
->va_cfg0_base
= pp
->dbi_base
+ SPACE0_REMOTE_CFG_OFFSET
;
485 pp
->va_cfg1_base
= pp
->va_cfg0_base
;
487 /* Index 1 is the application reg. space address */
488 res
= platform_get_resource(pdev
, IORESOURCE_MEM
, 1);
489 ks_pcie
->va_app_base
= devm_ioremap_resource(pp
->dev
, res
);
490 if (IS_ERR(ks_pcie
->va_app_base
))
491 return PTR_ERR(ks_pcie
->va_app_base
);
495 /* Create legacy IRQ domain */
496 ks_pcie
->legacy_irq_domain
=
497 irq_domain_add_linear(ks_pcie
->legacy_intc_np
,
499 &ks_dw_pcie_legacy_irq_domain_ops
,
501 if (!ks_pcie
->legacy_irq_domain
) {
502 dev_err(pp
->dev
, "Failed to add irq domain for legacy irqs\n");
506 return dw_pcie_host_init(pp
);