drivers/pci/host/pci-keystone.c

   1 /*
   2  * PCIe host controller driver for Texas Instruments Keystone SoCs
   3  *
   4  * Copyright (C) 2013-2014 Texas Instruments., Ltd.
   5  *              http://www.ti.com
   6  *
   7  * Author: Murali Karicheri <m-karicheri2@ti.com>
   8  * Implementation based on pci-exynos.c and pcie-designware.c
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/irqchip/chained_irq.h>
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/irqdomain.h>
  19 #include <linux/module.h>
  20 #include <linux/msi.h>
  21 #include <linux/of_irq.h>
  22 #include <linux/of.h>
  23 #include <linux/of_pci.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/phy/phy.h>
  26 #include <linux/resource.h>
  27 #include <linux/signal.h>
  28
  29 #include "pcie-designware.h"
  30 #include "pci-keystone.h"
  31
  32 #define DRIVER_NAME     "keystone-pcie"
  33
  34 /* driver specific constants */
  35 #define MAX_MSI_HOST_IRQS               8
  36 #define MAX_LEGACY_HOST_IRQS            4
  37
  38 /* DEV_STAT_CTRL */
  39 #define PCIE_CAP_BASE           0x70
  40
  41 /* PCIE controller device IDs */
  42 #define PCIE_RC_K2HK            0xb008
  43 #define PCIE_RC_K2E             0xb009
  44 #define PCIE_RC_K2L             0xb00a
  45
  46 #define to_keystone_pcie(x)     container_of(x, struct keystone_pcie, pp)
  47
  48 static void quirk_limit_mrrs(struct pci_dev *dev)
  49 {
  50         struct pci_bus *bus = dev->bus;
  51         struct pci_dev *bridge = bus->self;
  52         static const struct pci_device_id rc_pci_devids[] = {
  53                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2HK),
  54                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  55                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2E),
  56                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  57                 { PCI_DEVICE(PCI_VENDOR_ID_TI, PCIE_RC_K2L),
  58                  .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, },
  59                 { 0, },
  60         };
  61
  62         if (pci_is_root_bus(bus))
  63                 return;
  64
  65         /* look for the host bridge */
  66         while (!pci_is_root_bus(bus)) {
  67                 bridge = bus->self;
  68                 bus = bus->parent;
  69         }
  70
  71         if (bridge) {
  72                 /*
  73                  * Keystone PCI controller has a h/w limitation of
  74                  * 256 bytes maximum read request size.  It can't handle
  75                  * anything higher than this.  So force this limit on
  76                  * all downstream devices.
  77                  */
  78                 if (pci_match_id(rc_pci_devids, bridge)) {
  79                         if (pcie_get_readrq(dev) > 256) {
  80                                 dev_info(&dev->dev, "limiting MRRS to 256\n");
  81                                 pcie_set_readrq(dev, 256);
  82                         }
  83                 }
  84         }
  85 }
  86 DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, quirk_limit_mrrs);
  87
  88 static int ks_pcie_establish_link(struct keystone_pcie *ks_pcie)
  89 {
  90         struct pcie_port *pp = &ks_pcie->pp;
  91         unsigned int retries;
  92
  93         dw_pcie_setup_rc(pp);
  94
  95         if (dw_pcie_link_up(pp)) {
  96                 dev_err(pp->dev, "Link already up\n");
  97                 return 0;
  98         }
  99
 100         /* check if the link is up or not */
 101         for (retries = 0; retries < 5; retries++) {
 102                 ks_dw_pcie_initiate_link_train(ks_pcie);
 103                 if (!dw_pcie_wait_for_link(pp))
 104                         return 0;
 105         }
 106
 107         dev_err(pp->dev, "phy link never came up\n");
 108         return -ETIMEDOUT;
 109 }
 110
 111 static void ks_pcie_msi_irq_handler(struct irq_desc *desc)
 112 {
 113         unsigned int irq = irq_desc_get_irq(desc);
 114         struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
 115         u32 offset = irq - ks_pcie->msi_host_irqs[0];
 116         struct pcie_port *pp = &ks_pcie->pp;
 117         struct irq_chip *chip = irq_desc_get_chip(desc);
 118
 119         dev_dbg(pp->dev, "%s, irq %d\n", __func__, irq);
 120
 121         /*
 122          * The chained irq handler installation would have replaced normal
 123          * interrupt driver handler so we need to take care of mask/unmask and
 124          * ack operation.
 125          */
 126         chained_irq_enter(chip, desc);
 127         ks_dw_pcie_handle_msi_irq(ks_pcie, offset);
 128         chained_irq_exit(chip, desc);
 129 }
 130
 131 /**
 132  * ks_pcie_legacy_irq_handler() - Handle legacy interrupt
 133  * @irq: IRQ line for legacy interrupts
 134  * @desc: Pointer to irq descriptor
 135  *
 136  * Traverse through pending legacy interrupts and invoke handler for each. Also
 137  * takes care of interrupt controller level mask/ack operation.
 138  */
 139 static void ks_pcie_legacy_irq_handler(struct irq_desc *desc)
 140 {
 141         unsigned int irq = irq_desc_get_irq(desc);
 142         struct keystone_pcie *ks_pcie = irq_desc_get_handler_data(desc);
 143         struct pcie_port *pp = &ks_pcie->pp;
 144         u32 irq_offset = irq - ks_pcie->legacy_host_irqs[0];
 145         struct irq_chip *chip = irq_desc_get_chip(desc);
 146
 147         dev_dbg(pp->dev, ": Handling legacy irq %d\n", irq);
 148
 149         /*
 150          * The chained irq handler installation would have replaced normal
 151          * interrupt driver handler so we need to take care of mask/unmask and
 152          * ack operation.
 153          */
 154         chained_irq_enter(chip, desc);
 155         ks_dw_pcie_handle_legacy_irq(ks_pcie, irq_offset);
 156         chained_irq_exit(chip, desc);
 157 }
 158
 159 static int ks_pcie_get_irq_controller_info(struct keystone_pcie *ks_pcie,
 160                                            char *controller, int *num_irqs)
 161 {
 162         int temp, max_host_irqs, legacy = 1, *host_irqs, ret = -EINVAL;
 163         struct device *dev = ks_pcie->pp.dev;
 164         struct device_node *np_pcie = dev->of_node, **np_temp;
 165
 166         if (!strcmp(controller, "msi-interrupt-controller"))
 167                 legacy = 0;
 168
 169         if (legacy) {
 170                 np_temp = &ks_pcie->legacy_intc_np;
 171                 max_host_irqs = MAX_LEGACY_HOST_IRQS;
 172                 host_irqs = &ks_pcie->legacy_host_irqs[0];
 173         } else {
 174                 np_temp = &ks_pcie->msi_intc_np;
 175                 max_host_irqs = MAX_MSI_HOST_IRQS;
 176                 host_irqs =  &ks_pcie->msi_host_irqs[0];
 177         }
 178
 179         /* interrupt controller is in a child node */
 180         *np_temp = of_find_node_by_name(np_pcie, controller);
 181         if (!(*np_temp)) {
 182                 dev_err(dev, "Node for %s is absent\n", controller);
 183                 goto out;
 184         }
 185         temp = of_irq_count(*np_temp);
 186         if (!temp)
 187                 goto out;
 188         if (temp > max_host_irqs)
 189                 dev_warn(dev, "Too many %s interrupts defined %u\n",
 190                         (legacy ? "legacy" : "MSI"), temp);
 191
 192         /*
 193          * support upto max_host_irqs. In dt from index 0 to 3 (legacy) or 0 to
 194          * 7 (MSI)
 195          */
 196         for (temp = 0; temp < max_host_irqs; temp++) {
 197                 host_irqs[temp] = irq_of_parse_and_map(*np_temp, temp);
 198                 if (!host_irqs[temp])
 199                         break;
 200         }
 201         if (temp) {
 202                 *num_irqs = temp;
 203                 ret = 0;
 204         }
 205 out:
 206         return ret;
 207 }
 208
 209 static void ks_pcie_setup_interrupts(struct keystone_pcie *ks_pcie)
 210 {
 211         int i;
 212
 213         /* Legacy IRQ */
 214         for (i = 0; i < ks_pcie->num_legacy_host_irqs; i++) {
 215                 irq_set_chained_handler_and_data(ks_pcie->legacy_host_irqs[i],
 216                                                  ks_pcie_legacy_irq_handler,
 217                                                  ks_pcie);
 218         }
 219         ks_dw_pcie_enable_legacy_irqs(ks_pcie);
 220
 221         /* MSI IRQ */
 222         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 223                 for (i = 0; i < ks_pcie->num_msi_host_irqs; i++) {
 224                         irq_set_chained_handler_and_data(ks_pcie->msi_host_irqs[i],
 225                                                          ks_pcie_msi_irq_handler,
 226                                                          ks_pcie);
 227                 }
 228         }
 229 }
 230
 231 /*
 232  * When a PCI device does not exist during config cycles, keystone host gets a
 233  * bus error instead of returning 0xffffffff. This handler always returns 0
 234  * for this kind of faults.
 235  */
 236 static int keystone_pcie_fault(unsigned long addr, unsigned int fsr,
 237                                 struct pt_regs *regs)
 238 {
 239         unsigned long instr = *(unsigned long *) instruction_pointer(regs);
 240
 241         if ((instr & 0x0e100090) == 0x00100090) {
 242                 int reg = (instr >> 12) & 15;
 243
 244                 regs->uregs[reg] = -1;
 245                 regs->ARM_pc += 4;
 246         }
 247
 248         return 0;
 249 }
 250
 251 static void __init ks_pcie_host_init(struct pcie_port *pp)
 252 {
 253         struct keystone_pcie *ks_pcie = to_keystone_pcie(pp);
 254         u32 val;
 255
 256         ks_pcie_establish_link(ks_pcie);
 257         ks_dw_pcie_setup_rc_app_regs(ks_pcie);
 258         ks_pcie_setup_interrupts(ks_pcie);
 259         writew(PCI_IO_RANGE_TYPE_32 | (PCI_IO_RANGE_TYPE_32 << 8),
 260                         pp->dbi_base + PCI_IO_BASE);
 261
 262         /* update the Vendor ID */
 263         writew(ks_pcie->device_id, pp->dbi_base + PCI_DEVICE_ID);
 264
 265         /* update the DEV_STAT_CTRL to publish right mrrs */
 266         val = readl(pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
 267         val &= ~PCI_EXP_DEVCTL_READRQ;
 268         /* set the mrrs to 256 bytes */
 269         val |= BIT(12);
 270         writel(val, pp->dbi_base + PCIE_CAP_BASE + PCI_EXP_DEVCTL);
 271
 272         /*
 273          * PCIe access errors that result into OCP errors are caught by ARM as
 274          * "External aborts"
 275          */
 276         hook_fault_code(17, keystone_pcie_fault, SIGBUS, 0,
 277                         "Asynchronous external abort");
 278 }
 279
 280 static struct pcie_host_ops keystone_pcie_host_ops = {
 281         .rd_other_conf = ks_dw_pcie_rd_other_conf,
 282         .wr_other_conf = ks_dw_pcie_wr_other_conf,
 283         .link_up = ks_dw_pcie_link_up,
 284         .host_init = ks_pcie_host_init,
 285         .msi_set_irq = ks_dw_pcie_msi_set_irq,
 286         .msi_clear_irq = ks_dw_pcie_msi_clear_irq,
 287         .get_msi_addr = ks_dw_pcie_get_msi_addr,
 288         .msi_host_init = ks_dw_pcie_msi_host_init,
 289         .scan_bus = ks_dw_pcie_v3_65_scan_bus,
 290 };
 291
 292 static int __init ks_add_pcie_port(struct keystone_pcie *ks_pcie,
 293                          struct platform_device *pdev)
 294 {
 295         struct pcie_port *pp = &ks_pcie->pp;
 296         int ret;
 297
 298         ret = ks_pcie_get_irq_controller_info(ks_pcie,
 299                                         "legacy-interrupt-controller",
 300                                         &ks_pcie->num_legacy_host_irqs);
 301         if (ret)
 302                 return ret;
 303
 304         if (IS_ENABLED(CONFIG_PCI_MSI)) {
 305                 ret = ks_pcie_get_irq_controller_info(ks_pcie,
 306                                                 "msi-interrupt-controller",
 307                                                 &ks_pcie->num_msi_host_irqs);
 308                 if (ret)
 309                         return ret;
 310         }
 311
 312         pp->root_bus_nr = -1;
 313         pp->ops = &keystone_pcie_host_ops;
 314         ret = ks_dw_pcie_host_init(ks_pcie, ks_pcie->msi_intc_np);
 315         if (ret) {
 316                 dev_err(&pdev->dev, "failed to initialize host\n");
 317                 return ret;
 318         }
 319
 320         return ret;
 321 }
 322
 323 static const struct of_device_id ks_pcie_of_match[] = {
 324         {
 325                 .type = "pci",
 326                 .compatible = "ti,keystone-pcie",
 327         },
 328         { },
 329 };
 330 MODULE_DEVICE_TABLE(of, ks_pcie_of_match);
 331
 332 static int __exit ks_pcie_remove(struct platform_device *pdev)
 333 {
 334         struct keystone_pcie *ks_pcie = platform_get_drvdata(pdev);
 335
 336         clk_disable_unprepare(ks_pcie->clk);
 337
 338         return 0;
 339 }
 340
 341 static int __init ks_pcie_probe(struct platform_device *pdev)
 342 {
 343         struct device *dev = &pdev->dev;
 344         struct keystone_pcie *ks_pcie;
 345         struct pcie_port *pp;
 346         struct resource *res;
 347         void __iomem *reg_p;
 348         struct phy *phy;
 349         int ret = 0;
 350
 351         ks_pcie = devm_kzalloc(&pdev->dev, sizeof(*ks_pcie),
 352                                 GFP_KERNEL);
 353         if (!ks_pcie)
 354                 return -ENOMEM;
 355
 356         pp = &ks_pcie->pp;
 357
 358         /* initialize SerDes Phy if present */
 359         phy = devm_phy_get(dev, "pcie-phy");
 360         if (PTR_ERR_OR_ZERO(phy) == -EPROBE_DEFER)
 361                 return PTR_ERR(phy);
 362
 363         if (!IS_ERR_OR_NULL(phy)) {
 364                 ret = phy_init(phy);
 365                 if (ret < 0)
 366                         return ret;
 367         }
 368
 369         /* index 2 is to read PCI DEVICE_ID */
 370         res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
 371         reg_p = devm_ioremap_resource(dev, res);
 372         if (IS_ERR(reg_p))
 373                 return PTR_ERR(reg_p);
 374         ks_pcie->device_id = readl(reg_p) >> 16;
 375         devm_iounmap(dev, reg_p);
 376         devm_release_mem_region(dev, res->start, resource_size(res));
 377
 378         pp->dev = dev;
 379         platform_set_drvdata(pdev, ks_pcie);
 380         ks_pcie->clk = devm_clk_get(dev, "pcie");
 381         if (IS_ERR(ks_pcie->clk)) {
 382                 dev_err(dev, "Failed to get pcie rc clock\n");
 383                 return PTR_ERR(ks_pcie->clk);
 384         }
 385         ret = clk_prepare_enable(ks_pcie->clk);
 386         if (ret)
 387                 return ret;
 388
 389         ret = ks_add_pcie_port(ks_pcie, pdev);
 390         if (ret < 0)
 391                 goto fail_clk;
 392
 393         return 0;
 394 fail_clk:
 395         clk_disable_unprepare(ks_pcie->clk);
 396
 397         return ret;
 398 }
 399
 400 static struct platform_driver ks_pcie_driver __refdata = {
 401         .probe  = ks_pcie_probe,
 402         .remove = __exit_p(ks_pcie_remove),
 403         .driver = {
 404                 .name   = "keystone-pcie",
 405                 .of_match_table = of_match_ptr(ks_pcie_of_match),
 406         },
 407 };
 408
 409 module_platform_driver(ks_pcie_driver);
 410
 411 MODULE_AUTHOR("Murali Karicheri <m-karicheri2@ti.com>");
 412 MODULE_DESCRIPTION("Keystone PCIe host controller driver");
 413 MODULE_LICENSE("GPL v2");