drivers/pci/host/pci-rcar-gen2.c

   1 /*
   2  *  pci-rcar-gen2: internal PCI bus support
   3  *
   4  * Copyright (C) 2013 Renesas Solutions Corp.
   5  * Copyright (C) 2013 Cogent Embedded, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License version 2 as
   9  * published by the Free Software Foundation.
  10  */
  11
  12 #include <linux/delay.h>
  13 #include <linux/init.h>
  14 #include <linux/interrupt.h>
  15 #include <linux/io.h>
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/of_address.h>
  19 #include <linux/of_pci.h>
  20 #include <linux/pci.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/pm_runtime.h>
  23 #include <linux/sizes.h>
  24 #include <linux/slab.h>
  25
  26 /* AHB-PCI Bridge PCI communication registers */
  27 #define RCAR_AHBPCI_PCICOM_OFFSET       0x800
  28
  29 #define RCAR_PCIAHB_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
  30 #define RCAR_PCIAHB_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
  31 #define RCAR_PCIAHB_PREFETCH0           0x0
  32 #define RCAR_PCIAHB_PREFETCH4           0x1
  33 #define RCAR_PCIAHB_PREFETCH8           0x2
  34 #define RCAR_PCIAHB_PREFETCH16          0x3
  35
  36 #define RCAR_AHBPCI_WIN1_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
  37 #define RCAR_AHBPCI_WIN2_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
  38 #define RCAR_AHBPCI_WIN_CTR_MEM         (3 << 1)
  39 #define RCAR_AHBPCI_WIN_CTR_CFG         (5 << 1)
  40 #define RCAR_AHBPCI_WIN1_HOST           (1 << 30)
  41 #define RCAR_AHBPCI_WIN1_DEVICE         (1 << 31)
  42
  43 #define RCAR_PCI_INT_ENABLE_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
  44 #define RCAR_PCI_INT_STATUS_REG         (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
  45 #define RCAR_PCI_INT_SIGTABORT          (1 << 0)
  46 #define RCAR_PCI_INT_SIGRETABORT        (1 << 1)
  47 #define RCAR_PCI_INT_REMABORT           (1 << 2)
  48 #define RCAR_PCI_INT_PERR               (1 << 3)
  49 #define RCAR_PCI_INT_SIGSERR            (1 << 4)
  50 #define RCAR_PCI_INT_RESERR             (1 << 5)
  51 #define RCAR_PCI_INT_WIN1ERR            (1 << 12)
  52 #define RCAR_PCI_INT_WIN2ERR            (1 << 13)
  53 #define RCAR_PCI_INT_A                  (1 << 16)
  54 #define RCAR_PCI_INT_B                  (1 << 17)
  55 #define RCAR_PCI_INT_PME                (1 << 19)
  56 #define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT          | \
  57                                 RCAR_PCI_INT_SIGRETABORT        | \
  58                                 RCAR_PCI_INT_SIGRETABORT        | \
  59                                 RCAR_PCI_INT_REMABORT           | \
  60                                 RCAR_PCI_INT_PERR               | \
  61                                 RCAR_PCI_INT_SIGSERR            | \
  62                                 RCAR_PCI_INT_RESERR             | \
  63                                 RCAR_PCI_INT_WIN1ERR            | \
  64                                 RCAR_PCI_INT_WIN2ERR)
  65
  66 #define RCAR_AHB_BUS_CTR_REG            (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
  67 #define RCAR_AHB_BUS_MMODE_HTRANS       (1 << 0)
  68 #define RCAR_AHB_BUS_MMODE_BYTE_BURST   (1 << 1)
  69 #define RCAR_AHB_BUS_MMODE_WR_INCR      (1 << 2)
  70 #define RCAR_AHB_BUS_MMODE_HBUS_REQ     (1 << 7)
  71 #define RCAR_AHB_BUS_SMODE_READYCTR     (1 << 17)
  72 #define RCAR_AHB_BUS_MODE               (RCAR_AHB_BUS_MMODE_HTRANS |    \
  73                                         RCAR_AHB_BUS_MMODE_BYTE_BURST | \
  74                                         RCAR_AHB_BUS_MMODE_WR_INCR |    \
  75                                         RCAR_AHB_BUS_MMODE_HBUS_REQ |   \
  76                                         RCAR_AHB_BUS_SMODE_READYCTR)
  77
  78 #define RCAR_USBCTR_REG                 (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
  79 #define RCAR_USBCTR_USBH_RST            (1 << 0)
  80 #define RCAR_USBCTR_PCICLK_MASK         (1 << 1)
  81 #define RCAR_USBCTR_PLL_RST             (1 << 2)
  82 #define RCAR_USBCTR_DIRPD               (1 << 8)
  83 #define RCAR_USBCTR_PCIAHB_WIN2_EN      (1 << 9)
  84 #define RCAR_USBCTR_PCIAHB_WIN1_256M    (0 << 10)
  85 #define RCAR_USBCTR_PCIAHB_WIN1_512M    (1 << 10)
  86 #define RCAR_USBCTR_PCIAHB_WIN1_1G      (2 << 10)
  87 #define RCAR_USBCTR_PCIAHB_WIN1_2G      (3 << 10)
  88 #define RCAR_USBCTR_PCIAHB_WIN1_MASK    (3 << 10)
  89
  90 #define RCAR_PCI_ARBITER_CTR_REG        (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
  91 #define RCAR_PCI_ARBITER_PCIREQ0        (1 << 0)
  92 #define RCAR_PCI_ARBITER_PCIREQ1        (1 << 1)
  93 #define RCAR_PCI_ARBITER_PCIBP_MODE     (1 << 12)
  94
  95 #define RCAR_PCI_UNIT_REV_REG           (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
  96
  97 struct rcar_pci_priv {
  98         struct device *dev;
  99         void __iomem *reg;
 100         struct resource io_res;
 101         struct resource mem_res;
 102         struct resource *cfg_res;
 103         unsigned busnr;
 104         int irq;
 105         unsigned long window_size;
 106         unsigned long window_addr;
 107         unsigned long window_pci;
 108 };
 109
 110 /* PCI configuration space operations */
 111 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
 112                                        int where)
 113 {
 114         struct pci_sys_data *sys = bus->sysdata;
 115         struct rcar_pci_priv *priv = sys->private_data;
 116         int slot, val;
 117
 118         if (sys->busnr != bus->number || PCI_FUNC(devfn))
 119                 return NULL;
 120
 121         /* Only one EHCI/OHCI device built-in */
 122         slot = PCI_SLOT(devfn);
 123         if (slot > 2)
 124                 return NULL;
 125
 126         /* bridge logic only has registers to 0x40 */
 127         if (slot == 0x0 && where >= 0x40)
 128                 return NULL;
 129
 130         val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
 131                      RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
 132
 133         iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
 134         return priv->reg + (slot >> 1) * 0x100 + where;
 135 }
 136
 137 /* PCI interrupt mapping */
 138 static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 139 {
 140         struct pci_sys_data *sys = dev->bus->sysdata;
 141         struct rcar_pci_priv *priv = sys->private_data;
 142         int irq;
 143
 144         irq = of_irq_parse_and_map_pci(dev, slot, pin);
 145         if (!irq)
 146                 irq = priv->irq;
 147
 148         return irq;
 149 }
 150
 151 #ifdef CONFIG_PCI_DEBUG
 152 /* if debug enabled, then attach an error handler irq to the bridge */
 153
 154 static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
 155 {
 156         struct rcar_pci_priv *priv = pw;
 157         u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
 158
 159         if (status & RCAR_PCI_INT_ALLERRORS) {
 160                 dev_err(priv->dev, "error irq: status %08x\n", status);
 161
 162                 /* clear the error(s) */
 163                 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
 164                           priv->reg + RCAR_PCI_INT_STATUS_REG);
 165                 return IRQ_HANDLED;
 166         }
 167
 168         return IRQ_NONE;
 169 }
 170
 171 static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
 172 {
 173         int ret;
 174         u32 val;
 175
 176         ret = devm_request_irq(priv->dev, priv->irq, rcar_pci_err_irq,
 177                                IRQF_SHARED, "error irq", priv);
 178         if (ret) {
 179                 dev_err(priv->dev, "cannot claim IRQ for error handling\n");
 180                 return;
 181         }
 182
 183         val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
 184         val |= RCAR_PCI_INT_ALLERRORS;
 185         iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
 186 }
 187 #else
 188 static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
 189 #endif
 190
 191 /* PCI host controller setup */
 192 static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
 193 {
 194         struct rcar_pci_priv *priv = sys->private_data;
 195         void __iomem *reg = priv->reg;
 196         u32 val;
 197
 198         pm_runtime_enable(priv->dev);
 199         pm_runtime_get_sync(priv->dev);
 200
 201         val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
 202         dev_info(priv->dev, "PCI: bus%u revision %x\n", sys->busnr, val);
 203
 204         /* Disable Direct Power Down State and assert reset */
 205         val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
 206         val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
 207         iowrite32(val, reg + RCAR_USBCTR_REG);
 208         udelay(4);
 209
 210         /* De-assert reset and reset PCIAHB window1 size */
 211         val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
 212                  RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
 213
 214         /* Setup PCIAHB window1 size */
 215         switch (priv->window_size) {
 216         case SZ_2G:
 217                 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
 218                 break;
 219         case SZ_1G:
 220                 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
 221                 break;
 222         case SZ_512M:
 223                 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
 224                 break;
 225         default:
 226                 pr_warn("unknown window size %ld - defaulting to 256M\n",
 227                         priv->window_size);
 228                 priv->window_size = SZ_256M;
 229                 /* fall-through */
 230         case SZ_256M:
 231                 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
 232                 break;
 233         }
 234         iowrite32(val, reg + RCAR_USBCTR_REG);
 235
 236         /* Configure AHB master and slave modes */
 237         iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
 238
 239         /* Configure PCI arbiter */
 240         val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
 241         val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
 242                RCAR_PCI_ARBITER_PCIBP_MODE;
 243         iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
 244
 245         /* PCI-AHB mapping */
 246         iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16,
 247                   reg + RCAR_PCIAHB_WIN1_CTR_REG);
 248
 249         /* AHB-PCI mapping: OHCI/EHCI registers */
 250         val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
 251         iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
 252
 253         /* Enable AHB-PCI bridge PCI configuration access */
 254         iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
 255                   reg + RCAR_AHBPCI_WIN1_CTR_REG);
 256         /* Set PCI-AHB Window1 address */
 257         iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
 258                   reg + PCI_BASE_ADDRESS_1);
 259         /* Set AHB-PCI bridge PCI communication area address */
 260         val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
 261         iowrite32(val, reg + PCI_BASE_ADDRESS_0);
 262
 263         val = ioread32(reg + PCI_COMMAND);
 264         val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
 265                PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
 266         iowrite32(val, reg + PCI_COMMAND);
 267
 268         /* Enable PCI interrupts */
 269         iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
 270                   reg + RCAR_PCI_INT_ENABLE_REG);
 271
 272         if (priv->irq > 0)
 273                 rcar_pci_setup_errirq(priv);
 274
 275         /* Add PCI resources */
 276         pci_add_resource(&sys->resources, &priv->io_res);
 277         pci_add_resource(&sys->resources, &priv->mem_res);
 278
 279         /* Setup bus number based on platform device id / of bus-range */
 280         sys->busnr = priv->busnr;
 281         return 1;
 282 }
 283
 284 static struct pci_ops rcar_pci_ops = {
 285         .map_bus = rcar_pci_cfg_base,
 286         .read   = pci_generic_config_read,
 287         .write  = pci_generic_config_write,
 288 };
 289
 290 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
 291                                      struct device_node *node)
 292 {
 293         const int na = 3, ns = 2;
 294         int rlen;
 295
 296         parser->node = node;
 297         parser->pna = of_n_addr_cells(node);
 298         parser->np = parser->pna + na + ns;
 299
 300         parser->range = of_get_property(node, "dma-ranges", &rlen);
 301         if (!parser->range)
 302                 return -ENOENT;
 303
 304         parser->end = parser->range + rlen / sizeof(__be32);
 305         return 0;
 306 }
 307
 308 static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
 309                                          struct device_node *np)
 310 {
 311         struct of_pci_range range;
 312         struct of_pci_range_parser parser;
 313         int index = 0;
 314
 315         /* Failure to parse is ok as we fall back to defaults */
 316         if (pci_dma_range_parser_init(&parser, np))
 317                 return 0;
 318
 319         /* Get the dma-ranges from DT */
 320         for_each_of_pci_range(&parser, &range) {
 321                 /* Hardware only allows one inbound 32-bit range */
 322                 if (index)
 323                         return -EINVAL;
 324
 325                 pci->window_addr = (unsigned long)range.cpu_addr;
 326                 pci->window_pci = (unsigned long)range.pci_addr;
 327                 pci->window_size = (unsigned long)range.size;
 328
 329                 /* Catch HW limitations */
 330                 if (!(range.flags & IORESOURCE_PREFETCH)) {
 331                         dev_err(pci->dev, "window must be prefetchable\n");
 332                         return -EINVAL;
 333                 }
 334                 if (pci->window_addr) {
 335                         u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);
 336
 337                         if (lowaddr < pci->window_size) {
 338                                 dev_err(pci->dev, "invalid window size/addr\n");
 339                                 return -EINVAL;
 340                         }
 341                 }
 342                 index++;
 343         }
 344
 345         return 0;
 346 }
 347
 348 static int rcar_pci_probe(struct platform_device *pdev)
 349 {
 350         struct resource *cfg_res, *mem_res;
 351         struct rcar_pci_priv *priv;
 352         void __iomem *reg;
 353         struct hw_pci hw;
 354         void *hw_private[1];
 355
 356         cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 357         reg = devm_ioremap_resource(&pdev->dev, cfg_res);
 358         if (IS_ERR(reg))
 359                 return PTR_ERR(reg);
 360
 361         mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
 362         if (!mem_res || !mem_res->start)
 363                 return -ENODEV;
 364
 365         if (mem_res->start & 0xFFFF)
 366                 return -EINVAL;
 367
 368         priv = devm_kzalloc(&pdev->dev,
 369                             sizeof(struct rcar_pci_priv), GFP_KERNEL);
 370         if (!priv)
 371                 return -ENOMEM;
 372
 373         priv->mem_res = *mem_res;
 374         /*
 375          * The controller does not support/use port I/O,
 376          * so setup a dummy port I/O region here.
 377          */
 378         priv->io_res.start = priv->mem_res.start;
 379         priv->io_res.end = priv->mem_res.end;
 380         priv->io_res.flags = IORESOURCE_IO;
 381
 382         priv->cfg_res = cfg_res;
 383
 384         priv->irq = platform_get_irq(pdev, 0);
 385         priv->reg = reg;
 386         priv->dev = &pdev->dev;
 387
 388         if (priv->irq < 0) {
 389                 dev_err(&pdev->dev, "no valid irq found\n");
 390                 return priv->irq;
 391         }
 392
 393         /* default window addr and size if not specified in DT */
 394         priv->window_addr = 0x40000000;
 395         priv->window_pci = 0x40000000;
 396         priv->window_size = SZ_1G;
 397
 398         if (pdev->dev.of_node) {
 399                 struct resource busnr;
 400                 int ret;
 401
 402                 ret = of_pci_parse_bus_range(pdev->dev.of_node, &busnr);
 403                 if (ret < 0) {
 404                         dev_err(&pdev->dev, "failed to parse bus-range\n");
 405                         return ret;
 406                 }
 407
 408                 priv->busnr = busnr.start;
 409                 if (busnr.end != busnr.start)
 410                         dev_warn(&pdev->dev, "only one bus number supported\n");
 411
 412                 ret = rcar_pci_parse_map_dma_ranges(priv, pdev->dev.of_node);
 413                 if (ret < 0) {
 414                         dev_err(&pdev->dev, "failed to parse dma-range\n");
 415                         return ret;
 416                 }
 417         } else {
 418                 priv->busnr = pdev->id;
 419         }
 420
 421         hw_private[0] = priv;
 422         memset(&hw, 0, sizeof(hw));
 423         hw.nr_controllers = ARRAY_SIZE(hw_private);
 424         hw.private_data = hw_private;
 425         hw.map_irq = rcar_pci_map_irq;
 426         hw.ops = &rcar_pci_ops;
 427         hw.setup = rcar_pci_setup;
 428         pci_common_init_dev(&pdev->dev, &hw);
 429         return 0;
 430 }
 431
 432 static struct of_device_id rcar_pci_of_match[] = {
 433         { .compatible = "renesas,pci-rcar-gen2", },
 434         { .compatible = "renesas,pci-r8a7790", },
 435         { .compatible = "renesas,pci-r8a7791", },
 436         { .compatible = "renesas,pci-r8a7794", },
 437         { },
 438 };
 439
 440 MODULE_DEVICE_TABLE(of, rcar_pci_of_match);
 441
 442 static struct platform_driver rcar_pci_driver = {
 443         .driver = {
 444                 .name = "pci-rcar-gen2",
 445                 .suppress_bind_attrs = true,
 446                 .of_match_table = rcar_pci_of_match,
 447         },
 448         .probe = rcar_pci_probe,
 449 };
 450
 451 module_platform_driver(rcar_pci_driver);
 452
 453 MODULE_LICENSE("GPL v2");
 454 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
 455 MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");