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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / pci / host / pcie-rcar.c
blob35092188039b99264f7911a3fdd91005c043d4d0
1 /*
2 * PCIe driver for Renesas R-Car SoCs
3 * Copyright (C) 2014 Renesas Electronics Europe Ltd
4 *
5 * Based on:
6 * arch/sh/drivers/pci/pcie-sh7786.c
7 * arch/sh/drivers/pci/ops-sh7786.c
8 * Copyright (C) 2009 - 2011 Paul Mundt
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/interrupt.h>
18 #include <linux/irq.h>
19 #include <linux/irqdomain.h>
20 #include <linux/kernel.h>
21 #include <linux/module.h>
22 #include <linux/msi.h>
23 #include <linux/of_address.h>
24 #include <linux/of_irq.h>
25 #include <linux/of_pci.h>
26 #include <linux/of_platform.h>
27 #include <linux/pci.h>
28 #include <linux/platform_device.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/slab.h>
31
32 #define DRV_NAME "rcar-pcie"
33
34 #define PCIECAR 0x000010
35 #define PCIECCTLR 0x000018
36 #define CONFIG_SEND_ENABLE (1 << 31)
37 #define TYPE0 (0 << 8)
38 #define TYPE1 (1 << 8)
39 #define PCIECDR 0x000020
40 #define PCIEMSR 0x000028
41 #define PCIEINTXR 0x000400
42 #define PCIEMSITXR 0x000840
43
44 /* Transfer control */
45 #define PCIETCTLR 0x02000
46 #define CFINIT 1
47 #define PCIETSTR 0x02004
48 #define DATA_LINK_ACTIVE 1
49 #define PCIEERRFR 0x02020
50 #define UNSUPPORTED_REQUEST (1 << 4)
51 #define PCIEMSIFR 0x02044
52 #define PCIEMSIALR 0x02048
53 #define MSIFE 1
54 #define PCIEMSIAUR 0x0204c
55 #define PCIEMSIIER 0x02050
56
57 /* root port address */
58 #define PCIEPRAR(x) (0x02080 + ((x) * 0x4))
59
60 /* local address reg & mask */
61 #define PCIELAR(x) (0x02200 + ((x) * 0x20))
62 #define PCIELAMR(x) (0x02208 + ((x) * 0x20))
63 #define LAM_PREFETCH (1 << 3)
64 #define LAM_64BIT (1 << 2)
65 #define LAR_ENABLE (1 << 1)
66
67 /* PCIe address reg & mask */
68 #define PCIEPALR(x) (0x03400 + ((x) * 0x20))
69 #define PCIEPAUR(x) (0x03404 + ((x) * 0x20))
70 #define PCIEPAMR(x) (0x03408 + ((x) * 0x20))
71 #define PCIEPTCTLR(x) (0x0340c + ((x) * 0x20))
72 #define PAR_ENABLE (1 << 31)
73 #define IO_SPACE (1 << 8)
74
75 /* Configuration */
76 #define PCICONF(x) (0x010000 + ((x) * 0x4))
77 #define PMCAP(x) (0x010040 + ((x) * 0x4))
78 #define EXPCAP(x) (0x010070 + ((x) * 0x4))
79 #define VCCAP(x) (0x010100 + ((x) * 0x4))
80
81 /* link layer */
82 #define IDSETR1 0x011004
83 #define TLCTLR 0x011048
84 #define MACSR 0x011054
85 #define MACCTLR 0x011058
86 #define SCRAMBLE_DISABLE (1 << 27)
87
88 /* R-Car H1 PHY */
89 #define H1_PCIEPHYADRR 0x04000c
90 #define WRITE_CMD (1 << 16)
91 #define PHY_ACK (1 << 24)
92 #define RATE_POS 12
93 #define LANE_POS 8
94 #define ADR_POS 0
95 #define H1_PCIEPHYDOUTR 0x040014
96 #define H1_PCIEPHYSR 0x040018
97
98 /* R-Car Gen2 PHY */
99 #define GEN2_PCIEPHYADDR 0x780
100 #define GEN2_PCIEPHYDATA 0x784
101 #define GEN2_PCIEPHYCTRL 0x78c
102
103 #define INT_PCI_MSI_NR 32
104
105 #define RCONF(x) (PCICONF(0)+(x))
106 #define RPMCAP(x) (PMCAP(0)+(x))
107 #define REXPCAP(x) (EXPCAP(0)+(x))
108 #define RVCCAP(x) (VCCAP(0)+(x))
109
110 #define PCIE_CONF_BUS(b) (((b) & 0xff) << 24)
111 #define PCIE_CONF_DEV(d) (((d) & 0x1f) << 19)
112 #define PCIE_CONF_FUNC(f) (((f) & 0x7) << 16)
113
114 #define RCAR_PCI_MAX_RESOURCES 4
115 #define MAX_NR_INBOUND_MAPS 6
116
117 struct rcar_msi {
118 DECLARE_BITMAP(used, INT_PCI_MSI_NR);
119 struct irq_domain *domain;
120 struct msi_controller chip;
121 unsigned long pages;
122 struct mutex lock;
123 int irq1;
124 int irq2;
125 };
126
127 static inline struct rcar_msi *to_rcar_msi(struct msi_controller *chip)
128 {
129 return container_of(chip, struct rcar_msi, chip);
130 }
131
132 /* Structure representing the PCIe interface */
133 struct rcar_pcie {
134 struct device *dev;
135 void __iomem *base;
136 struct list_head resources;
137 int root_bus_nr;
138 struct clk *clk;
139 struct clk *bus_clk;
140 struct rcar_msi msi;
141 };
142
143 static void rcar_pci_write_reg(struct rcar_pcie *pcie, unsigned long val,
144 unsigned long reg)
145 {
146 writel(val, pcie->base + reg);
147 }
148
149 static unsigned long rcar_pci_read_reg(struct rcar_pcie *pcie,
150 unsigned long reg)
151 {
152 return readl(pcie->base + reg);
153 }
154
155 enum {
156 RCAR_PCI_ACCESS_READ,
157 RCAR_PCI_ACCESS_WRITE,
158 };
159
160 static void rcar_rmw32(struct rcar_pcie *pcie, int where, u32 mask, u32 data)
161 {
162 int shift = 8 * (where & 3);
163 u32 val = rcar_pci_read_reg(pcie, where & ~3);
164
165 val &= ~(mask << shift);
166 val |= data << shift;
167 rcar_pci_write_reg(pcie, val, where & ~3);
168 }
169
170 static u32 rcar_read_conf(struct rcar_pcie *pcie, int where)
171 {
172 int shift = 8 * (where & 3);
173 u32 val = rcar_pci_read_reg(pcie, where & ~3);
174
175 return val >> shift;
176 }
177
178 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
179 static int rcar_pcie_config_access(struct rcar_pcie *pcie,
180 unsigned char access_type, struct pci_bus *bus,
181 unsigned int devfn, int where, u32 *data)
182 {
183 int dev, func, reg, index;
184
185 dev = PCI_SLOT(devfn);
186 func = PCI_FUNC(devfn);
187 reg = where & ~3;
188 index = reg / 4;
189
190 /*
191 * While each channel has its own memory-mapped extended config
192 * space, it's generally only accessible when in endpoint mode.
193 * When in root complex mode, the controller is unable to target
194 * itself with either type 0 or type 1 accesses, and indeed, any
195 * controller initiated target transfer to its own config space
196 * result in a completer abort.
197 *
198 * Each channel effectively only supports a single device, but as
199 * the same channel <-> device access works for any PCI_SLOT()
200 * value, we cheat a bit here and bind the controller's config
201 * space to devfn 0 in order to enable self-enumeration. In this
202 * case the regular ECAR/ECDR path is sidelined and the mangled
203 * config access itself is initiated as an internal bus transaction.
204 */
205 if (pci_is_root_bus(bus)) {
206 if (dev != 0)
207 return PCIBIOS_DEVICE_NOT_FOUND;
208
209 if (access_type == RCAR_PCI_ACCESS_READ) {
210 *data = rcar_pci_read_reg(pcie, PCICONF(index));
211 } else {
212 /* Keep an eye out for changes to the root bus number */
213 if (pci_is_root_bus(bus) && (reg == PCI_PRIMARY_BUS))
214 pcie->root_bus_nr = *data & 0xff;
215
216 rcar_pci_write_reg(pcie, *data, PCICONF(index));
217 }
218
219 return PCIBIOS_SUCCESSFUL;
220 }
221
222 if (pcie->root_bus_nr < 0)
223 return PCIBIOS_DEVICE_NOT_FOUND;
224
225 /* Clear errors */
226 rcar_pci_write_reg(pcie, rcar_pci_read_reg(pcie, PCIEERRFR), PCIEERRFR);
227
228 /* Set the PIO address */
229 rcar_pci_write_reg(pcie, PCIE_CONF_BUS(bus->number) |
230 PCIE_CONF_DEV(dev) | PCIE_CONF_FUNC(func) | reg, PCIECAR);
231
232 /* Enable the configuration access */
233 if (bus->parent->number == pcie->root_bus_nr)
234 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE0, PCIECCTLR);
235 else
236 rcar_pci_write_reg(pcie, CONFIG_SEND_ENABLE | TYPE1, PCIECCTLR);
237
238 /* Check for errors */
239 if (rcar_pci_read_reg(pcie, PCIEERRFR) & UNSUPPORTED_REQUEST)
240 return PCIBIOS_DEVICE_NOT_FOUND;
241
242 /* Check for master and target aborts */
243 if (rcar_read_conf(pcie, RCONF(PCI_STATUS)) &
244 (PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT))
245 return PCIBIOS_DEVICE_NOT_FOUND;
246
247 if (access_type == RCAR_PCI_ACCESS_READ)
248 *data = rcar_pci_read_reg(pcie, PCIECDR);
249 else
250 rcar_pci_write_reg(pcie, *data, PCIECDR);
251
252 /* Disable the configuration access */
253 rcar_pci_write_reg(pcie, 0, PCIECCTLR);
254
255 return PCIBIOS_SUCCESSFUL;
256 }
257
258 static int rcar_pcie_read_conf(struct pci_bus *bus, unsigned int devfn,
259 int where, int size, u32 *val)
260 {
261 struct rcar_pcie *pcie = bus->sysdata;
262 int ret;
263
264 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
265 bus, devfn, where, val);
266 if (ret != PCIBIOS_SUCCESSFUL) {
267 *val = 0xffffffff;
268 return ret;
269 }
270
271 if (size == 1)
272 *val = (*val >> (8 * (where & 3))) & 0xff;
273 else if (size == 2)
274 *val = (*val >> (8 * (where & 2))) & 0xffff;
275
276 dev_dbg(&bus->dev, "pcie-config-read: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
277 bus->number, devfn, where, size, (unsigned long)*val);
278
279 return ret;
280 }
281
282 /* Serialization is provided by 'pci_lock' in drivers/pci/access.c */
283 static int rcar_pcie_write_conf(struct pci_bus *bus, unsigned int devfn,
284 int where, int size, u32 val)
285 {
286 struct rcar_pcie *pcie = bus->sysdata;
287 int shift, ret;
288 u32 data;
289
290 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_READ,
291 bus, devfn, where, &data);
292 if (ret != PCIBIOS_SUCCESSFUL)
293 return ret;
294
295 dev_dbg(&bus->dev, "pcie-config-write: bus=%3d devfn=0x%04x where=0x%04x size=%d val=0x%08lx\n",
296 bus->number, devfn, where, size, (unsigned long)val);
297
298 if (size == 1) {
299 shift = 8 * (where & 3);
300 data &= ~(0xff << shift);
301 data |= ((val & 0xff) << shift);
302 } else if (size == 2) {
303 shift = 8 * (where & 2);
304 data &= ~(0xffff << shift);
305 data |= ((val & 0xffff) << shift);
306 } else
307 data = val;
308
309 ret = rcar_pcie_config_access(pcie, RCAR_PCI_ACCESS_WRITE,
310 bus, devfn, where, &data);
311
312 return ret;
313 }
314
315 static struct pci_ops rcar_pcie_ops = {
316 .read = rcar_pcie_read_conf,
317 .write = rcar_pcie_write_conf,
318 };
319
320 static void rcar_pcie_setup_window(int win, struct rcar_pcie *pcie,
321 struct resource *res)
322 {
323 /* Setup PCIe address space mappings for each resource */
324 resource_size_t size;
325 resource_size_t res_start;
326 u32 mask;
327
328 rcar_pci_write_reg(pcie, 0x00000000, PCIEPTCTLR(win));
329
330 /*
331 * The PAMR mask is calculated in units of 128Bytes, which
332 * keeps things pretty simple.
333 */
334 size = resource_size(res);
335 mask = (roundup_pow_of_two(size) / SZ_128) - 1;
336 rcar_pci_write_reg(pcie, mask << 7, PCIEPAMR(win));
337
338 if (res->flags & IORESOURCE_IO)
339 res_start = pci_pio_to_address(res->start);
340 else
341 res_start = res->start;
342
343 rcar_pci_write_reg(pcie, upper_32_bits(res_start), PCIEPAUR(win));
344 rcar_pci_write_reg(pcie, lower_32_bits(res_start) & ~0x7F,
345 PCIEPALR(win));
346
347 /* First resource is for IO */
348 mask = PAR_ENABLE;
349 if (res->flags & IORESOURCE_IO)
350 mask |= IO_SPACE;
351
352 rcar_pci_write_reg(pcie, mask, PCIEPTCTLR(win));
353 }
354
355 static int rcar_pcie_setup(struct list_head *resource, struct rcar_pcie *pci)
356 {
357 struct resource_entry *win;
358 int i = 0;
359
360 /* Setup PCI resources */
361 resource_list_for_each_entry(win, &pci->resources) {
362 struct resource *res = win->res;
363
364 if (!res->flags)
365 continue;
366
367 switch (resource_type(res)) {
368 case IORESOURCE_IO:
369 case IORESOURCE_MEM:
370 rcar_pcie_setup_window(i, pci, res);
371 i++;
372 break;
373 case IORESOURCE_BUS:
374 pci->root_bus_nr = res->start;
375 break;
376 default:
377 continue;
378 }
379
380 pci_add_resource(resource, res);
381 }
382
383 return 1;
384 }
385
386 static int rcar_pcie_enable(struct rcar_pcie *pcie)
387 {
388 struct pci_bus *bus, *child;
389 LIST_HEAD(res);
390
391 rcar_pcie_setup(&res, pcie);
392
393 pci_add_flags(PCI_REASSIGN_ALL_RSRC | PCI_REASSIGN_ALL_BUS);
394
395 if (IS_ENABLED(CONFIG_PCI_MSI))
396 bus = pci_scan_root_bus_msi(pcie->dev, pcie->root_bus_nr,
397 &rcar_pcie_ops, pcie, &res, &pcie->msi.chip);
398 else
399 bus = pci_scan_root_bus(pcie->dev, pcie->root_bus_nr,
400 &rcar_pcie_ops, pcie, &res);
401
402 if (!bus) {
403 dev_err(pcie->dev, "Scanning rootbus failed");
404 return -ENODEV;
405 }
406
407 pci_fixup_irqs(pci_common_swizzle, of_irq_parse_and_map_pci);
408
409 pci_bus_size_bridges(bus);
410 pci_bus_assign_resources(bus);
411
412 list_for_each_entry(child, &bus->children, node)
413 pcie_bus_configure_settings(child);
414
415 pci_bus_add_devices(bus);
416
417 return 0;
418 }
419
420 static int phy_wait_for_ack(struct rcar_pcie *pcie)
421 {
422 unsigned int timeout = 100;
423
424 while (timeout--) {
425 if (rcar_pci_read_reg(pcie, H1_PCIEPHYADRR) & PHY_ACK)
426 return 0;
427
428 udelay(100);
429 }
430
431 dev_err(pcie->dev, "Access to PCIe phy timed out\n");
432
433 return -ETIMEDOUT;
434 }
435
436 static void phy_write_reg(struct rcar_pcie *pcie,
437 unsigned int rate, unsigned int addr,
438 unsigned int lane, unsigned int data)
439 {
440 unsigned long phyaddr;
441
442 phyaddr = WRITE_CMD |
443 ((rate & 1) << RATE_POS) |
444 ((lane & 0xf) << LANE_POS) |
445 ((addr & 0xff) << ADR_POS);
446
447 /* Set write data */
448 rcar_pci_write_reg(pcie, data, H1_PCIEPHYDOUTR);
449 rcar_pci_write_reg(pcie, phyaddr, H1_PCIEPHYADRR);
450
451 /* Ignore errors as they will be dealt with if the data link is down */
452 phy_wait_for_ack(pcie);
453
454 /* Clear command */
455 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYDOUTR);
456 rcar_pci_write_reg(pcie, 0, H1_PCIEPHYADRR);
457
458 /* Ignore errors as they will be dealt with if the data link is down */
459 phy_wait_for_ack(pcie);
460 }
461
462 static int rcar_pcie_wait_for_dl(struct rcar_pcie *pcie)
463 {
464 unsigned int timeout = 10;
465
466 while (timeout--) {
467 if ((rcar_pci_read_reg(pcie, PCIETSTR) & DATA_LINK_ACTIVE))
468 return 0;
469
470 msleep(5);
471 }
472
473 return -ETIMEDOUT;
474 }
475
476 static int rcar_pcie_hw_init(struct rcar_pcie *pcie)
477 {
478 int err;
479
480 /* Begin initialization */
481 rcar_pci_write_reg(pcie, 0, PCIETCTLR);
482
483 /* Set mode */
484 rcar_pci_write_reg(pcie, 1, PCIEMSR);
485
486 /*
487 * Initial header for port config space is type 1, set the device
488 * class to match. Hardware takes care of propagating the IDSETR
489 * settings, so there is no need to bother with a quirk.
490 */
491 rcar_pci_write_reg(pcie, PCI_CLASS_BRIDGE_PCI << 16, IDSETR1);
492
493 /*
494 * Setup Secondary Bus Number & Subordinate Bus Number, even though
495 * they aren't used, to avoid bridge being detected as broken.
496 */
497 rcar_rmw32(pcie, RCONF(PCI_SECONDARY_BUS), 0xff, 1);
498 rcar_rmw32(pcie, RCONF(PCI_SUBORDINATE_BUS), 0xff, 1);
499
500 /* Initialize default capabilities. */
501 rcar_rmw32(pcie, REXPCAP(0), 0xff, PCI_CAP_ID_EXP);
502 rcar_rmw32(pcie, REXPCAP(PCI_EXP_FLAGS),
503 PCI_EXP_FLAGS_TYPE, PCI_EXP_TYPE_ROOT_PORT << 4);
504 rcar_rmw32(pcie, RCONF(PCI_HEADER_TYPE), 0x7f,
505 PCI_HEADER_TYPE_BRIDGE);
506
507 /* Enable data link layer active state reporting */
508 rcar_rmw32(pcie, REXPCAP(PCI_EXP_LNKCAP), PCI_EXP_LNKCAP_DLLLARC,
509 PCI_EXP_LNKCAP_DLLLARC);
510
511 /* Write out the physical slot number = 0 */
512 rcar_rmw32(pcie, REXPCAP(PCI_EXP_SLTCAP), PCI_EXP_SLTCAP_PSN, 0);
513
514 /* Set the completion timer timeout to the maximum 50ms. */
515 rcar_rmw32(pcie, TLCTLR + 1, 0x3f, 50);
516
517 /* Terminate list of capabilities (Next Capability Offset=0) */
518 rcar_rmw32(pcie, RVCCAP(0), 0xfff00000, 0);
519
520 /* Enable MSI */
521 if (IS_ENABLED(CONFIG_PCI_MSI))
522 rcar_pci_write_reg(pcie, 0x801f0000, PCIEMSITXR);
523
524 /* Finish initialization - establish a PCI Express link */
525 rcar_pci_write_reg(pcie, CFINIT, PCIETCTLR);
526
527 /* This will timeout if we don't have a link. */
528 err = rcar_pcie_wait_for_dl(pcie);
529 if (err)
530 return err;
531
532 /* Enable INTx interrupts */
533 rcar_rmw32(pcie, PCIEINTXR, 0, 0xF << 8);
534
535 wmb();
536
537 return 0;
538 }
539
540 static int rcar_pcie_hw_init_h1(struct rcar_pcie *pcie)
541 {
542 unsigned int timeout = 10;
543
544 /* Initialize the phy */
545 phy_write_reg(pcie, 0, 0x42, 0x1, 0x0EC34191);
546 phy_write_reg(pcie, 1, 0x42, 0x1, 0x0EC34180);
547 phy_write_reg(pcie, 0, 0x43, 0x1, 0x00210188);
548 phy_write_reg(pcie, 1, 0x43, 0x1, 0x00210188);
549 phy_write_reg(pcie, 0, 0x44, 0x1, 0x015C0014);
550 phy_write_reg(pcie, 1, 0x44, 0x1, 0x015C0014);
551 phy_write_reg(pcie, 1, 0x4C, 0x1, 0x786174A0);
552 phy_write_reg(pcie, 1, 0x4D, 0x1, 0x048000BB);
553 phy_write_reg(pcie, 0, 0x51, 0x1, 0x079EC062);
554 phy_write_reg(pcie, 0, 0x52, 0x1, 0x20000000);
555 phy_write_reg(pcie, 1, 0x52, 0x1, 0x20000000);
556 phy_write_reg(pcie, 1, 0x56, 0x1, 0x00003806);
557
558 phy_write_reg(pcie, 0, 0x60, 0x1, 0x004B03A5);
559 phy_write_reg(pcie, 0, 0x64, 0x1, 0x3F0F1F0F);
560 phy_write_reg(pcie, 0, 0x66, 0x1, 0x00008000);
561
562 while (timeout--) {
563 if (rcar_pci_read_reg(pcie, H1_PCIEPHYSR))
564 return rcar_pcie_hw_init(pcie);
565
566 msleep(5);
567 }
568
569 return -ETIMEDOUT;
570 }
571
572 static int rcar_pcie_hw_init_gen2(struct rcar_pcie *pcie)
573 {
574 /*
575 * These settings come from the R-Car Series, 2nd Generation User's
576 * Manual, section 50.3.1 (2) Initialization of the physical layer.
577 */
578 rcar_pci_write_reg(pcie, 0x000f0030, GEN2_PCIEPHYADDR);
579 rcar_pci_write_reg(pcie, 0x00381203, GEN2_PCIEPHYDATA);
580 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
581 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
582
583 rcar_pci_write_reg(pcie, 0x000f0054, GEN2_PCIEPHYADDR);
584 /* The following value is for DC connection, no termination resistor */
585 rcar_pci_write_reg(pcie, 0x13802007, GEN2_PCIEPHYDATA);
586 rcar_pci_write_reg(pcie, 0x00000001, GEN2_PCIEPHYCTRL);
587 rcar_pci_write_reg(pcie, 0x00000006, GEN2_PCIEPHYCTRL);
588
589 return rcar_pcie_hw_init(pcie);
590 }
591
592 static int rcar_msi_alloc(struct rcar_msi *chip)
593 {
594 int msi;
595
596 mutex_lock(&chip->lock);
597
598 msi = find_first_zero_bit(chip->used, INT_PCI_MSI_NR);
599 if (msi < INT_PCI_MSI_NR)
600 set_bit(msi, chip->used);
601 else
602 msi = -ENOSPC;
603
604 mutex_unlock(&chip->lock);
605
606 return msi;
607 }
608
609 static void rcar_msi_free(struct rcar_msi *chip, unsigned long irq)
610 {
611 mutex_lock(&chip->lock);
612 clear_bit(irq, chip->used);
613 mutex_unlock(&chip->lock);
614 }
615
616 static irqreturn_t rcar_pcie_msi_irq(int irq, void *data)
617 {
618 struct rcar_pcie *pcie = data;
619 struct rcar_msi *msi = &pcie->msi;
620 unsigned long reg;
621
622 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
623
624 /* MSI & INTx share an interrupt - we only handle MSI here */
625 if (!reg)
626 return IRQ_NONE;
627
628 while (reg) {
629 unsigned int index = find_first_bit(&reg, 32);
630 unsigned int irq;
631
632 /* clear the interrupt */
633 rcar_pci_write_reg(pcie, 1 << index, PCIEMSIFR);
634
635 irq = irq_find_mapping(msi->domain, index);
636 if (irq) {
637 if (test_bit(index, msi->used))
638 generic_handle_irq(irq);
639 else
640 dev_info(pcie->dev, "unhandled MSI\n");
641 } else {
642 /* Unknown MSI, just clear it */
643 dev_dbg(pcie->dev, "unexpected MSI\n");
644 }
645
646 /* see if there's any more pending in this vector */
647 reg = rcar_pci_read_reg(pcie, PCIEMSIFR);
648 }
649
650 return IRQ_HANDLED;
651 }
652
653 static int rcar_msi_setup_irq(struct msi_controller *chip, struct pci_dev *pdev,
654 struct msi_desc *desc)
655 {
656 struct rcar_msi *msi = to_rcar_msi(chip);
657 struct rcar_pcie *pcie = container_of(chip, struct rcar_pcie, msi.chip);
658 struct msi_msg msg;
659 unsigned int irq;
660 int hwirq;
661
662 hwirq = rcar_msi_alloc(msi);
663 if (hwirq < 0)
664 return hwirq;
665
666 irq = irq_create_mapping(msi->domain, hwirq);
667 if (!irq) {
668 rcar_msi_free(msi, hwirq);
669 return -EINVAL;
670 }
671
672 irq_set_msi_desc(irq, desc);
673
674 msg.address_lo = rcar_pci_read_reg(pcie, PCIEMSIALR) & ~MSIFE;
675 msg.address_hi = rcar_pci_read_reg(pcie, PCIEMSIAUR);
676 msg.data = hwirq;
677
678 pci_write_msi_msg(irq, &msg);
679
680 return 0;
681 }
682
683 static void rcar_msi_teardown_irq(struct msi_controller *chip, unsigned int irq)
684 {
685 struct rcar_msi *msi = to_rcar_msi(chip);
686 struct irq_data *d = irq_get_irq_data(irq);
687
688 rcar_msi_free(msi, d->hwirq);
689 }
690
691 static struct irq_chip rcar_msi_irq_chip = {
692 .name = "R-Car PCIe MSI",
693 .irq_enable = pci_msi_unmask_irq,
694 .irq_disable = pci_msi_mask_irq,
695 .irq_mask = pci_msi_mask_irq,
696 .irq_unmask = pci_msi_unmask_irq,
697 };
698
699 static int rcar_msi_map(struct irq_domain *domain, unsigned int irq,
700 irq_hw_number_t hwirq)
701 {
702 irq_set_chip_and_handler(irq, &rcar_msi_irq_chip, handle_simple_irq);
703 irq_set_chip_data(irq, domain->host_data);
704
705 return 0;
706 }
707
708 static const struct irq_domain_ops msi_domain_ops = {
709 .map = rcar_msi_map,
710 };
711
712 static int rcar_pcie_enable_msi(struct rcar_pcie *pcie)
713 {
714 struct platform_device *pdev = to_platform_device(pcie->dev);
715 struct rcar_msi *msi = &pcie->msi;
716 unsigned long base;
717 int err;
718
719 mutex_init(&msi->lock);
720
721 msi->chip.dev = pcie->dev;
722 msi->chip.setup_irq = rcar_msi_setup_irq;
723 msi->chip.teardown_irq = rcar_msi_teardown_irq;
724
725 msi->domain = irq_domain_add_linear(pcie->dev->of_node, INT_PCI_MSI_NR,
726 &msi_domain_ops, &msi->chip);
727 if (!msi->domain) {
728 dev_err(&pdev->dev, "failed to create IRQ domain\n");
729 return -ENOMEM;
730 }
731
732 /* Two irqs are for MSI, but they are also used for non-MSI irqs */
733 err = devm_request_irq(&pdev->dev, msi->irq1, rcar_pcie_msi_irq,
734 IRQF_SHARED | IRQF_NO_THREAD,
735 rcar_msi_irq_chip.name, pcie);
736 if (err < 0) {
737 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
738 goto err;
739 }
740
741 err = devm_request_irq(&pdev->dev, msi->irq2, rcar_pcie_msi_irq,
742 IRQF_SHARED | IRQF_NO_THREAD,
743 rcar_msi_irq_chip.name, pcie);
744 if (err < 0) {
745 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err);
746 goto err;
747 }
748
749 /* setup MSI data target */
750 msi->pages = __get_free_pages(GFP_KERNEL, 0);
751 base = virt_to_phys((void *)msi->pages);
752
753 rcar_pci_write_reg(pcie, base | MSIFE, PCIEMSIALR);
754 rcar_pci_write_reg(pcie, 0, PCIEMSIAUR);
755
756 /* enable all MSI interrupts */
757 rcar_pci_write_reg(pcie, 0xffffffff, PCIEMSIIER);
758
759 return 0;
760
761 err:
762 irq_domain_remove(msi->domain);
763 return err;
764 }
765
766 static int rcar_pcie_get_resources(struct platform_device *pdev,
767 struct rcar_pcie *pcie)
768 {
769 struct resource res;
770 int err, i;
771
772 err = of_address_to_resource(pdev->dev.of_node, 0, &res);
773 if (err)
774 return err;
775
776 pcie->clk = devm_clk_get(&pdev->dev, "pcie");
777 if (IS_ERR(pcie->clk)) {
778 dev_err(pcie->dev, "cannot get platform clock\n");
779 return PTR_ERR(pcie->clk);
780 }
781 err = clk_prepare_enable(pcie->clk);
782 if (err)
783 goto fail_clk;
784
785 pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus");
786 if (IS_ERR(pcie->bus_clk)) {
787 dev_err(pcie->dev, "cannot get pcie bus clock\n");
788 err = PTR_ERR(pcie->bus_clk);
789 goto fail_clk;
790 }
791 err = clk_prepare_enable(pcie->bus_clk);
792 if (err)
793 goto err_map_reg;
794
795 i = irq_of_parse_and_map(pdev->dev.of_node, 0);
796 if (!i) {
797 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
798 err = -ENOENT;
799 goto err_map_reg;
800 }
801 pcie->msi.irq1 = i;
802
803 i = irq_of_parse_and_map(pdev->dev.of_node, 1);
804 if (!i) {
805 dev_err(pcie->dev, "cannot get platform resources for msi interrupt\n");
806 err = -ENOENT;
807 goto err_map_reg;
808 }
809 pcie->msi.irq2 = i;
810
811 pcie->base = devm_ioremap_resource(&pdev->dev, &res);
812 if (IS_ERR(pcie->base)) {
813 err = PTR_ERR(pcie->base);
814 goto err_map_reg;
815 }
816
817 return 0;
818
819 err_map_reg:
820 clk_disable_unprepare(pcie->bus_clk);
821 fail_clk:
822 clk_disable_unprepare(pcie->clk);
823
824 return err;
825 }
826
827 static int rcar_pcie_inbound_ranges(struct rcar_pcie *pcie,
828 struct of_pci_range *range,
829 int *index)
830 {
831 u64 restype = range->flags;
832 u64 cpu_addr = range->cpu_addr;
833 u64 cpu_end = range->cpu_addr + range->size;
834 u64 pci_addr = range->pci_addr;
835 u32 flags = LAM_64BIT | LAR_ENABLE;
836 u64 mask;
837 u64 size;
838 int idx = *index;
839
840 if (restype & IORESOURCE_PREFETCH)
841 flags |= LAM_PREFETCH;
842
843 /*
844 * If the size of the range is larger than the alignment of the start
845 * address, we have to use multiple entries to perform the mapping.
846 */
847 if (cpu_addr > 0) {
848 unsigned long nr_zeros = __ffs64(cpu_addr);
849 u64 alignment = 1ULL << nr_zeros;
850
851 size = min(range->size, alignment);
852 } else {
853 size = range->size;
854 }
855 /* Hardware supports max 4GiB inbound region */
856 size = min(size, 1ULL << 32);
857
858 mask = roundup_pow_of_two(size) - 1;
859 mask &= ~0xf;
860
861 while (cpu_addr < cpu_end) {
862 /*
863 * Set up 64-bit inbound regions as the range parser doesn't
864 * distinguish between 32 and 64-bit types.
865 */
866 rcar_pci_write_reg(pcie, lower_32_bits(pci_addr), PCIEPRAR(idx));
867 rcar_pci_write_reg(pcie, lower_32_bits(cpu_addr), PCIELAR(idx));
868 rcar_pci_write_reg(pcie, lower_32_bits(mask) | flags, PCIELAMR(idx));
869
870 rcar_pci_write_reg(pcie, upper_32_bits(pci_addr), PCIEPRAR(idx+1));
871 rcar_pci_write_reg(pcie, upper_32_bits(cpu_addr), PCIELAR(idx+1));
872 rcar_pci_write_reg(pcie, 0, PCIELAMR(idx + 1));
873
874 pci_addr += size;
875 cpu_addr += size;
876 idx += 2;
877
878 if (idx > MAX_NR_INBOUND_MAPS) {
879 dev_err(pcie->dev, "Failed to map inbound regions!\n");
880 return -EINVAL;
881 }
882 }
883 *index = idx;
884
885 return 0;
886 }
887
888 static int pci_dma_range_parser_init(struct of_pci_range_parser *parser,
889 struct device_node *node)
890 {
891 const int na = 3, ns = 2;
892 int rlen;
893
894 parser->node = node;
895 parser->pna = of_n_addr_cells(node);
896 parser->np = parser->pna + na + ns;
897
898 parser->range = of_get_property(node, "dma-ranges", &rlen);
899 if (!parser->range)
900 return -ENOENT;
901
902 parser->end = parser->range + rlen / sizeof(__be32);
903 return 0;
904 }
905
906 static int rcar_pcie_parse_map_dma_ranges(struct rcar_pcie *pcie,
907 struct device_node *np)
908 {
909 struct of_pci_range range;
910 struct of_pci_range_parser parser;
911 int index = 0;
912 int err;
913
914 if (pci_dma_range_parser_init(&parser, np))
915 return -EINVAL;
916
917 /* Get the dma-ranges from DT */
918 for_each_of_pci_range(&parser, &range) {
919 u64 end = range.cpu_addr + range.size - 1;
920 dev_dbg(pcie->dev, "0x%08x 0x%016llx..0x%016llx -> 0x%016llx\n",
921 range.flags, range.cpu_addr, end, range.pci_addr);
922
923 err = rcar_pcie_inbound_ranges(pcie, &range, &index);
924 if (err)
925 return err;
926 }
927
928 return 0;
929 }
930
931 static const struct of_device_id rcar_pcie_of_match[] = {
932 { .compatible = "renesas,pcie-r8a7779", .data = rcar_pcie_hw_init_h1 },
933 { .compatible = "renesas,pcie-rcar-gen2", .data = rcar_pcie_hw_init_gen2 },
934 { .compatible = "renesas,pcie-r8a7790", .data = rcar_pcie_hw_init_gen2 },
935 { .compatible = "renesas,pcie-r8a7791", .data = rcar_pcie_hw_init_gen2 },
936 { .compatible = "renesas,pcie-r8a7795", .data = rcar_pcie_hw_init },
937 {},
938 };
939 MODULE_DEVICE_TABLE(of, rcar_pcie_of_match);
940
941 static void rcar_pcie_release_of_pci_ranges(struct rcar_pcie *pci)
942 {
943 pci_free_resource_list(&pci->resources);
944 }
945
946 static int rcar_pcie_parse_request_of_pci_ranges(struct rcar_pcie *pci)
947 {
948 int err;
949 struct device *dev = pci->dev;
950 struct device_node *np = dev->of_node;
951 resource_size_t iobase;
952 struct resource_entry *win;
953
954 err = of_pci_get_host_bridge_resources(np, 0, 0xff, &pci->resources, &iobase);
955 if (err)
956 return err;
957
958 resource_list_for_each_entry(win, &pci->resources) {
959 struct resource *parent, *res = win->res;
960
961 switch (resource_type(res)) {
962 case IORESOURCE_IO:
963 parent = &ioport_resource;
964 err = pci_remap_iospace(res, iobase);
965 if (err) {
966 dev_warn(dev, "error %d: failed to map resource %pR\n",
967 err, res);
968 continue;
969 }
970 break;
971 case IORESOURCE_MEM:
972 parent = &iomem_resource;
973 break;
974
975 case IORESOURCE_BUS:
976 default:
977 continue;
978 }
979
980 err = devm_request_resource(dev, parent, res);
981 if (err)
982 goto out_release_res;
983 }
984
985 return 0;
986
987 out_release_res:
988 rcar_pcie_release_of_pci_ranges(pci);
989 return err;
990 }
991
992 static int rcar_pcie_probe(struct platform_device *pdev)
993 {
994 struct rcar_pcie *pcie;
995 unsigned int data;
996 const struct of_device_id *of_id;
997 int err;
998 int (*hw_init_fn)(struct rcar_pcie *);
999
1000 pcie = devm_kzalloc(&pdev->dev, sizeof(*pcie), GFP_KERNEL);
1001 if (!pcie)
1002 return -ENOMEM;
1003
1004 pcie->dev = &pdev->dev;
1005 platform_set_drvdata(pdev, pcie);
1006
1007 INIT_LIST_HEAD(&pcie->resources);
1008
1009 rcar_pcie_parse_request_of_pci_ranges(pcie);
1010
1011 err = rcar_pcie_get_resources(pdev, pcie);
1012 if (err < 0) {
1013 dev_err(&pdev->dev, "failed to request resources: %d\n", err);
1014 return err;
1015 }
1016
1017 err = rcar_pcie_parse_map_dma_ranges(pcie, pdev->dev.of_node);
1018 if (err)
1019 return err;
1020
1021 of_id = of_match_device(rcar_pcie_of_match, pcie->dev);
1022 if (!of_id || !of_id->data)
1023 return -EINVAL;
1024 hw_init_fn = of_id->data;
1025
1026 pm_runtime_enable(pcie->dev);
1027 err = pm_runtime_get_sync(pcie->dev);
1028 if (err < 0) {
1029 dev_err(pcie->dev, "pm_runtime_get_sync failed\n");
1030 goto err_pm_disable;
1031 }
1032
1033 /* Failure to get a link might just be that no cards are inserted */
1034 err = hw_init_fn(pcie);
1035 if (err) {
1036 dev_info(&pdev->dev, "PCIe link down\n");
1037 err = 0;
1038 goto err_pm_put;
1039 }
1040
1041 data = rcar_pci_read_reg(pcie, MACSR);
1042 dev_info(&pdev->dev, "PCIe x%d: link up\n", (data >> 20) & 0x3f);
1043
1044 if (IS_ENABLED(CONFIG_PCI_MSI)) {
1045 err = rcar_pcie_enable_msi(pcie);
1046 if (err < 0) {
1047 dev_err(&pdev->dev,
1048 "failed to enable MSI support: %d\n",
1049 err);
1050 goto err_pm_put;
1051 }
1052 }
1053
1054 err = rcar_pcie_enable(pcie);
1055 if (err)
1056 goto err_pm_put;
1057
1058 return 0;
1059
1060 err_pm_put:
1061 pm_runtime_put(pcie->dev);
1062
1063 err_pm_disable:
1064 pm_runtime_disable(pcie->dev);
1065 return err;
1066 }
1067
1068 static struct platform_driver rcar_pcie_driver = {
1069 .driver = {
1070 .name = DRV_NAME,
1071 .of_match_table = rcar_pcie_of_match,
1072 .suppress_bind_attrs = true,
1073 },
1074 .probe = rcar_pcie_probe,
1075 };
1076 module_platform_driver(rcar_pcie_driver);
1077
1078 MODULE_AUTHOR("Phil Edworthy <phil.edworthy@renesas.com>");
1079 MODULE_DESCRIPTION("Renesas R-Car PCIe driver");
1080 MODULE_LICENSE("GPL v2");
Linux with added FPC-III support