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Merge branch 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/evalenti/linux...
[linux/fpc-iii.git] / drivers / pinctrl / intel / pinctrl-baytrail.c
blob21b79a446d5ab4c31cb08f7a083b282d87aad0d2
1 /*
2 * Pinctrl GPIO driver for Intel Baytrail
3 * Copyright (c) 2012-2013, Intel Corporation.
4 *
5 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,
9 * version 2, as published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 */
16
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/init.h>
20 #include <linux/types.h>
21 #include <linux/bitops.h>
22 #include <linux/interrupt.h>
23 #include <linux/gpio/driver.h>
24 #include <linux/acpi.h>
25 #include <linux/platform_device.h>
26 #include <linux/seq_file.h>
27 #include <linux/io.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/pinctrl/pinctrl.h>
30
31 /* memory mapped register offsets */
32 #define BYT_CONF0_REG 0x000
33 #define BYT_CONF1_REG 0x004
34 #define BYT_VAL_REG 0x008
35 #define BYT_DFT_REG 0x00c
36 #define BYT_INT_STAT_REG 0x800
37
38 /* BYT_CONF0_REG register bits */
39 #define BYT_IODEN BIT(31)
40 #define BYT_DIRECT_IRQ_EN BIT(27)
41 #define BYT_TRIG_NEG BIT(26)
42 #define BYT_TRIG_POS BIT(25)
43 #define BYT_TRIG_LVL BIT(24)
44 #define BYT_PULL_STR_SHIFT 9
45 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
46 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
47 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
48 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
49 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
50 #define BYT_PULL_ASSIGN_SHIFT 7
51 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
52 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
53 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
54 #define BYT_PIN_MUX 0x07
55
56 /* BYT_VAL_REG register bits */
57 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
58 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
59 #define BYT_LEVEL BIT(0)
60
61 #define BYT_DIR_MASK (BIT(1) | BIT(2))
62 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
63
64 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
65 BYT_PIN_MUX)
66 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
67
68 #define BYT_NGPIO_SCORE 102
69 #define BYT_NGPIO_NCORE 28
70 #define BYT_NGPIO_SUS 44
71
72 #define BYT_SCORE_ACPI_UID "1"
73 #define BYT_NCORE_ACPI_UID "2"
74 #define BYT_SUS_ACPI_UID "3"
75
76 /*
77 * Baytrail gpio controller consist of three separate sub-controllers called
78 * SCORE, NCORE and SUS. The sub-controllers are identified by their acpi UID.
79 *
80 * GPIO numbering is _not_ ordered meaning that gpio # 0 in ACPI namespace does
81 * _not_ correspond to the first gpio register at controller's gpio base.
82 * There is no logic or pattern in mapping gpio numbers to registers (pads) so
83 * each sub-controller needs to have its own mapping table
84 */
85
86 /* score_pins[gpio_nr] = pad_nr */
87
88 static unsigned const score_pins[BYT_NGPIO_SCORE] = {
89 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
90 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
91 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
92 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
93 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
94 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
95 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
96 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
97 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
98 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
99 97, 100,
100 };
101
102 static unsigned const ncore_pins[BYT_NGPIO_NCORE] = {
103 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
104 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
105 3, 6, 10, 13, 2, 5, 9, 7,
106 };
107
108 static unsigned const sus_pins[BYT_NGPIO_SUS] = {
109 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
110 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
111 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
112 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
113 52, 53, 59, 40,
114 };
115
116 static struct pinctrl_gpio_range byt_ranges[] = {
117 {
118 .name = BYT_SCORE_ACPI_UID, /* match with acpi _UID in probe */
119 .npins = BYT_NGPIO_SCORE,
120 .pins = score_pins,
121 },
122 {
123 .name = BYT_NCORE_ACPI_UID,
124 .npins = BYT_NGPIO_NCORE,
125 .pins = ncore_pins,
126 },
127 {
128 .name = BYT_SUS_ACPI_UID,
129 .npins = BYT_NGPIO_SUS,
130 .pins = sus_pins,
131 },
132 {
133 },
134 };
135
136 struct byt_gpio_pin_context {
137 u32 conf0;
138 u32 val;
139 };
140
141 struct byt_gpio {
142 struct gpio_chip chip;
143 struct platform_device *pdev;
144 raw_spinlock_t lock;
145 void __iomem *reg_base;
146 struct pinctrl_gpio_range *range;
147 struct byt_gpio_pin_context *saved_context;
148 };
149
150 static void __iomem *byt_gpio_reg(struct gpio_chip *chip, unsigned offset,
151 int reg)
152 {
153 struct byt_gpio *vg = gpiochip_get_data(chip);
154 u32 reg_offset;
155
156 if (reg == BYT_INT_STAT_REG)
157 reg_offset = (offset / 32) * 4;
158 else
159 reg_offset = vg->range->pins[offset] * 16;
160
161 return vg->reg_base + reg_offset + reg;
162 }
163
164 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned offset)
165 {
166 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
167 unsigned long flags;
168 u32 value;
169
170 raw_spin_lock_irqsave(&vg->lock, flags);
171 value = readl(reg);
172 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
173 writel(value, reg);
174 raw_spin_unlock_irqrestore(&vg->lock, flags);
175 }
176
177 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
178 {
179 /* SCORE pin 92-93 */
180 if (!strcmp(vg->range->name, BYT_SCORE_ACPI_UID) &&
181 offset >= 92 && offset <= 93)
182 return 1;
183
184 /* SUS pin 11-21 */
185 if (!strcmp(vg->range->name, BYT_SUS_ACPI_UID) &&
186 offset >= 11 && offset <= 21)
187 return 1;
188
189 return 0;
190 }
191
192 static int byt_gpio_request(struct gpio_chip *chip, unsigned offset)
193 {
194 struct byt_gpio *vg = gpiochip_get_data(chip);
195 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_CONF0_REG);
196 u32 value, gpio_mux;
197 unsigned long flags;
198
199 raw_spin_lock_irqsave(&vg->lock, flags);
200
201 /*
202 * In most cases, func pin mux 000 means GPIO function.
203 * But, some pins may have func pin mux 001 represents
204 * GPIO function.
205 *
206 * Because there are devices out there where some pins were not
207 * configured correctly we allow changing the mux value from
208 * request (but print out warning about that).
209 */
210 value = readl(reg) & BYT_PIN_MUX;
211 gpio_mux = byt_get_gpio_mux(vg, offset);
212 if (WARN_ON(gpio_mux != value)) {
213 value = readl(reg) & ~BYT_PIN_MUX;
214 value |= gpio_mux;
215 writel(value, reg);
216
217 dev_warn(&vg->pdev->dev,
218 "pin %u forcibly re-configured as GPIO\n", offset);
219 }
220
221 raw_spin_unlock_irqrestore(&vg->lock, flags);
222
223 pm_runtime_get(&vg->pdev->dev);
224
225 return 0;
226 }
227
228 static void byt_gpio_free(struct gpio_chip *chip, unsigned offset)
229 {
230 struct byt_gpio *vg = gpiochip_get_data(chip);
231
232 byt_gpio_clear_triggering(vg, offset);
233 pm_runtime_put(&vg->pdev->dev);
234 }
235
236 static int byt_irq_type(struct irq_data *d, unsigned type)
237 {
238 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
239 u32 offset = irqd_to_hwirq(d);
240 u32 value;
241 unsigned long flags;
242 void __iomem *reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
243
244 if (offset >= vg->chip.ngpio)
245 return -EINVAL;
246
247 raw_spin_lock_irqsave(&vg->lock, flags);
248 value = readl(reg);
249
250 WARN(value & BYT_DIRECT_IRQ_EN,
251 "Bad pad config for io mode, force direct_irq_en bit clearing");
252
253 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
254 * are used to indicate high and low level triggering
255 */
256 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
257 BYT_TRIG_LVL);
258
259 writel(value, reg);
260
261 if (type & IRQ_TYPE_EDGE_BOTH)
262 irq_set_handler_locked(d, handle_edge_irq);
263 else if (type & IRQ_TYPE_LEVEL_MASK)
264 irq_set_handler_locked(d, handle_level_irq);
265
266 raw_spin_unlock_irqrestore(&vg->lock, flags);
267
268 return 0;
269 }
270
271 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
272 {
273 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
274 struct byt_gpio *vg = gpiochip_get_data(chip);
275 unsigned long flags;
276 u32 val;
277
278 raw_spin_lock_irqsave(&vg->lock, flags);
279 val = readl(reg);
280 raw_spin_unlock_irqrestore(&vg->lock, flags);
281
282 return !!(val & BYT_LEVEL);
283 }
284
285 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
286 {
287 struct byt_gpio *vg = gpiochip_get_data(chip);
288 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
289 unsigned long flags;
290 u32 old_val;
291
292 raw_spin_lock_irqsave(&vg->lock, flags);
293
294 old_val = readl(reg);
295
296 if (value)
297 writel(old_val | BYT_LEVEL, reg);
298 else
299 writel(old_val & ~BYT_LEVEL, reg);
300
301 raw_spin_unlock_irqrestore(&vg->lock, flags);
302 }
303
304 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
305 {
306 struct byt_gpio *vg = gpiochip_get_data(chip);
307 void __iomem *reg = byt_gpio_reg(chip, offset, BYT_VAL_REG);
308 unsigned long flags;
309 u32 value;
310
311 raw_spin_lock_irqsave(&vg->lock, flags);
312
313 value = readl(reg) | BYT_DIR_MASK;
314 value &= ~BYT_INPUT_EN; /* active low */
315 writel(value, reg);
316
317 raw_spin_unlock_irqrestore(&vg->lock, flags);
318
319 return 0;
320 }
321
322 static int byt_gpio_direction_output(struct gpio_chip *chip,
323 unsigned gpio, int value)
324 {
325 struct byt_gpio *vg = gpiochip_get_data(chip);
326 void __iomem *conf_reg = byt_gpio_reg(chip, gpio, BYT_CONF0_REG);
327 void __iomem *reg = byt_gpio_reg(chip, gpio, BYT_VAL_REG);
328 unsigned long flags;
329 u32 reg_val;
330
331 raw_spin_lock_irqsave(&vg->lock, flags);
332
333 /*
334 * Before making any direction modifications, do a check if gpio
335 * is set for direct IRQ. On baytrail, setting GPIO to output does
336 * not make sense, so let's at least warn the caller before they shoot
337 * themselves in the foot.
338 */
339 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
340 "Potential Error: Setting GPIO with direct_irq_en to output");
341
342 reg_val = readl(reg) | BYT_DIR_MASK;
343 reg_val &= ~(BYT_OUTPUT_EN | BYT_INPUT_EN);
344
345 if (value)
346 writel(reg_val | BYT_LEVEL, reg);
347 else
348 writel(reg_val & ~BYT_LEVEL, reg);
349
350 raw_spin_unlock_irqrestore(&vg->lock, flags);
351
352 return 0;
353 }
354
355 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
356 {
357 struct byt_gpio *vg = gpiochip_get_data(chip);
358 int i;
359 u32 conf0, val, offs;
360
361 for (i = 0; i < vg->chip.ngpio; i++) {
362 const char *pull_str = NULL;
363 const char *pull = NULL;
364 unsigned long flags;
365 const char *label;
366 offs = vg->range->pins[i] * 16;
367
368 raw_spin_lock_irqsave(&vg->lock, flags);
369 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
370 val = readl(vg->reg_base + offs + BYT_VAL_REG);
371 raw_spin_unlock_irqrestore(&vg->lock, flags);
372
373 label = gpiochip_is_requested(chip, i);
374 if (!label)
375 label = "Unrequested";
376
377 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
378 case BYT_PULL_ASSIGN_UP:
379 pull = "up";
380 break;
381 case BYT_PULL_ASSIGN_DOWN:
382 pull = "down";
383 break;
384 }
385
386 switch (conf0 & BYT_PULL_STR_MASK) {
387 case BYT_PULL_STR_2K:
388 pull_str = "2k";
389 break;
390 case BYT_PULL_STR_10K:
391 pull_str = "10k";
392 break;
393 case BYT_PULL_STR_20K:
394 pull_str = "20k";
395 break;
396 case BYT_PULL_STR_40K:
397 pull_str = "40k";
398 break;
399 }
400
401 seq_printf(s,
402 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
403 i,
404 label,
405 val & BYT_INPUT_EN ? " " : "in",
406 val & BYT_OUTPUT_EN ? " " : "out",
407 val & BYT_LEVEL ? "hi" : "lo",
408 vg->range->pins[i], offs,
409 conf0 & 0x7,
410 conf0 & BYT_TRIG_NEG ? " fall" : " ",
411 conf0 & BYT_TRIG_POS ? " rise" : " ",
412 conf0 & BYT_TRIG_LVL ? " level" : " ");
413
414 if (pull && pull_str)
415 seq_printf(s, " %-4s %-3s", pull, pull_str);
416 else
417 seq_puts(s, " ");
418
419 if (conf0 & BYT_IODEN)
420 seq_puts(s, " open-drain");
421
422 seq_puts(s, "\n");
423 }
424 }
425
426 static void byt_gpio_irq_handler(struct irq_desc *desc)
427 {
428 struct irq_data *data = irq_desc_get_irq_data(desc);
429 struct byt_gpio *vg = gpiochip_get_data(irq_desc_get_handler_data(desc));
430 struct irq_chip *chip = irq_data_get_irq_chip(data);
431 u32 base, pin;
432 void __iomem *reg;
433 unsigned long pending;
434 unsigned virq;
435
436 /* check from GPIO controller which pin triggered the interrupt */
437 for (base = 0; base < vg->chip.ngpio; base += 32) {
438 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
439 pending = readl(reg);
440 for_each_set_bit(pin, &pending, 32) {
441 virq = irq_find_mapping(vg->chip.irqdomain, base + pin);
442 generic_handle_irq(virq);
443 }
444 }
445 chip->irq_eoi(data);
446 }
447
448 static void byt_irq_ack(struct irq_data *d)
449 {
450 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
451 struct byt_gpio *vg = gpiochip_get_data(gc);
452 unsigned offset = irqd_to_hwirq(d);
453 void __iomem *reg;
454
455 raw_spin_lock(&vg->lock);
456 reg = byt_gpio_reg(&vg->chip, offset, BYT_INT_STAT_REG);
457 writel(BIT(offset % 32), reg);
458 raw_spin_unlock(&vg->lock);
459 }
460
461 static void byt_irq_unmask(struct irq_data *d)
462 {
463 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
464 struct byt_gpio *vg = gpiochip_get_data(gc);
465 unsigned offset = irqd_to_hwirq(d);
466 unsigned long flags;
467 void __iomem *reg;
468 u32 value;
469
470 reg = byt_gpio_reg(&vg->chip, offset, BYT_CONF0_REG);
471
472 raw_spin_lock_irqsave(&vg->lock, flags);
473 value = readl(reg);
474
475 switch (irqd_get_trigger_type(d)) {
476 case IRQ_TYPE_LEVEL_HIGH:
477 value |= BYT_TRIG_LVL;
478 case IRQ_TYPE_EDGE_RISING:
479 value |= BYT_TRIG_POS;
480 break;
481 case IRQ_TYPE_LEVEL_LOW:
482 value |= BYT_TRIG_LVL;
483 case IRQ_TYPE_EDGE_FALLING:
484 value |= BYT_TRIG_NEG;
485 break;
486 case IRQ_TYPE_EDGE_BOTH:
487 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
488 break;
489 }
490
491 writel(value, reg);
492
493 raw_spin_unlock_irqrestore(&vg->lock, flags);
494 }
495
496 static void byt_irq_mask(struct irq_data *d)
497 {
498 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
499 struct byt_gpio *vg = gpiochip_get_data(gc);
500
501 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
502 }
503
504 static struct irq_chip byt_irqchip = {
505 .name = "BYT-GPIO",
506 .irq_ack = byt_irq_ack,
507 .irq_mask = byt_irq_mask,
508 .irq_unmask = byt_irq_unmask,
509 .irq_set_type = byt_irq_type,
510 .flags = IRQCHIP_SKIP_SET_WAKE,
511 };
512
513 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
514 {
515 void __iomem *reg;
516 u32 base, value;
517 int i;
518
519 /*
520 * Clear interrupt triggers for all pins that are GPIOs and
521 * do not use direct IRQ mode. This will prevent spurious
522 * interrupts from misconfigured pins.
523 */
524 for (i = 0; i < vg->chip.ngpio; i++) {
525 value = readl(byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG));
526 if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i) &&
527 !(value & BYT_DIRECT_IRQ_EN)) {
528 byt_gpio_clear_triggering(vg, i);
529 dev_dbg(&vg->pdev->dev, "disabling GPIO %d\n", i);
530 }
531 }
532
533 /* clear interrupt status trigger registers */
534 for (base = 0; base < vg->chip.ngpio; base += 32) {
535 reg = byt_gpio_reg(&vg->chip, base, BYT_INT_STAT_REG);
536 writel(0xffffffff, reg);
537 /* make sure trigger bits are cleared, if not then a pin
538 might be misconfigured in bios */
539 value = readl(reg);
540 if (value)
541 dev_err(&vg->pdev->dev,
542 "GPIO interrupt error, pins misconfigured\n");
543 }
544 }
545
546 static int byt_gpio_probe(struct platform_device *pdev)
547 {
548 struct byt_gpio *vg;
549 struct gpio_chip *gc;
550 struct resource *mem_rc, *irq_rc;
551 struct device *dev = &pdev->dev;
552 struct acpi_device *acpi_dev;
553 struct pinctrl_gpio_range *range;
554 acpi_handle handle = ACPI_HANDLE(dev);
555 int ret;
556
557 if (acpi_bus_get_device(handle, &acpi_dev))
558 return -ENODEV;
559
560 vg = devm_kzalloc(dev, sizeof(struct byt_gpio), GFP_KERNEL);
561 if (!vg) {
562 dev_err(&pdev->dev, "can't allocate byt_gpio chip data\n");
563 return -ENOMEM;
564 }
565
566 for (range = byt_ranges; range->name; range++) {
567 if (!strcmp(acpi_dev->pnp.unique_id, range->name)) {
568 vg->chip.ngpio = range->npins;
569 vg->range = range;
570 break;
571 }
572 }
573
574 if (!vg->chip.ngpio || !vg->range)
575 return -ENODEV;
576
577 vg->pdev = pdev;
578 platform_set_drvdata(pdev, vg);
579
580 mem_rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
581 vg->reg_base = devm_ioremap_resource(dev, mem_rc);
582 if (IS_ERR(vg->reg_base))
583 return PTR_ERR(vg->reg_base);
584
585 raw_spin_lock_init(&vg->lock);
586
587 gc = &vg->chip;
588 gc->label = dev_name(&pdev->dev);
589 gc->owner = THIS_MODULE;
590 gc->request = byt_gpio_request;
591 gc->free = byt_gpio_free;
592 gc->direction_input = byt_gpio_direction_input;
593 gc->direction_output = byt_gpio_direction_output;
594 gc->get = byt_gpio_get;
595 gc->set = byt_gpio_set;
596 gc->dbg_show = byt_gpio_dbg_show;
597 gc->base = -1;
598 gc->can_sleep = false;
599 gc->parent = dev;
600
601 #ifdef CONFIG_PM_SLEEP
602 vg->saved_context = devm_kcalloc(&pdev->dev, gc->ngpio,
603 sizeof(*vg->saved_context), GFP_KERNEL);
604 #endif
605
606 ret = gpiochip_add_data(gc, vg);
607 if (ret) {
608 dev_err(&pdev->dev, "failed adding byt-gpio chip\n");
609 return ret;
610 }
611
612 /* set up interrupts */
613 irq_rc = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
614 if (irq_rc && irq_rc->start) {
615 byt_gpio_irq_init_hw(vg);
616 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
617 handle_simple_irq, IRQ_TYPE_NONE);
618 if (ret) {
619 dev_err(dev, "failed to add irqchip\n");
620 gpiochip_remove(gc);
621 return ret;
622 }
623
624 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
625 (unsigned)irq_rc->start,
626 byt_gpio_irq_handler);
627 }
628
629 pm_runtime_enable(dev);
630
631 return 0;
632 }
633
634 #ifdef CONFIG_PM_SLEEP
635 static int byt_gpio_suspend(struct device *dev)
636 {
637 struct platform_device *pdev = to_platform_device(dev);
638 struct byt_gpio *vg = platform_get_drvdata(pdev);
639 int i;
640
641 for (i = 0; i < vg->chip.ngpio; i++) {
642 void __iomem *reg;
643 u32 value;
644
645 reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG);
646 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
647 vg->saved_context[i].conf0 = value;
648
649 reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG);
650 value = readl(reg) & BYT_VAL_RESTORE_MASK;
651 vg->saved_context[i].val = value;
652 }
653
654 return 0;
655 }
656
657 static int byt_gpio_resume(struct device *dev)
658 {
659 struct platform_device *pdev = to_platform_device(dev);
660 struct byt_gpio *vg = platform_get_drvdata(pdev);
661 int i;
662
663 for (i = 0; i < vg->chip.ngpio; i++) {
664 void __iomem *reg;
665 u32 value;
666
667 reg = byt_gpio_reg(&vg->chip, i, BYT_CONF0_REG);
668 value = readl(reg);
669 if ((value & BYT_CONF0_RESTORE_MASK) !=
670 vg->saved_context[i].conf0) {
671 value &= ~BYT_CONF0_RESTORE_MASK;
672 value |= vg->saved_context[i].conf0;
673 writel(value, reg);
674 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
675 }
676
677 reg = byt_gpio_reg(&vg->chip, i, BYT_VAL_REG);
678 value = readl(reg);
679 if ((value & BYT_VAL_RESTORE_MASK) !=
680 vg->saved_context[i].val) {
681 u32 v;
682
683 v = value & ~BYT_VAL_RESTORE_MASK;
684 v |= vg->saved_context[i].val;
685 if (v != value) {
686 writel(v, reg);
687 dev_dbg(dev, "restored pin %d val %#08x\n",
688 i, v);
689 }
690 }
691 }
692
693 return 0;
694 }
695 #endif
696
697 #ifdef CONFIG_PM
698 static int byt_gpio_runtime_suspend(struct device *dev)
699 {
700 return 0;
701 }
702
703 static int byt_gpio_runtime_resume(struct device *dev)
704 {
705 return 0;
706 }
707 #endif
708
709 static const struct dev_pm_ops byt_gpio_pm_ops = {
710 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
711 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
712 NULL)
713 };
714
715 static const struct acpi_device_id byt_gpio_acpi_match[] = {
716 { "INT33B2", 0 },
717 { "INT33FC", 0 },
718 { }
719 };
720 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
721
722 static int byt_gpio_remove(struct platform_device *pdev)
723 {
724 struct byt_gpio *vg = platform_get_drvdata(pdev);
725
726 pm_runtime_disable(&pdev->dev);
727 gpiochip_remove(&vg->chip);
728
729 return 0;
730 }
731
732 static struct platform_driver byt_gpio_driver = {
733 .probe = byt_gpio_probe,
734 .remove = byt_gpio_remove,
735 .driver = {
736 .name = "byt_gpio",
737 .pm = &byt_gpio_pm_ops,
738 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
739 },
740 };
741
742 static int __init byt_gpio_init(void)
743 {
744 return platform_driver_register(&byt_gpio_driver);
745 }
746 subsys_initcall(byt_gpio_init);
747
748 static void __exit byt_gpio_exit(void)
749 {
750 platform_driver_unregister(&byt_gpio_driver);
751 }
752 module_exit(byt_gpio_exit);
Linux with added FPC-III support