drivers/pinctrl/sh-pfc/pfc-r8a7790.c

   1 /*
   2  * R8A7790 processor support
   3  *
   4  * Copyright (C) 2013  Renesas Electronics Corporation
   5  * Copyright (C) 2013  Magnus Damm
   6  * Copyright (C) 2012  Renesas Solutions Corp.
   7  * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; version 2 of the
  12  * License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  22  */
  23
  24 #include <linux/kernel.h>
  25
  26 #include "core.h"
  27 #include "sh_pfc.h"
  28
  29 #define CPU_ALL_PORT(fn, sfx)                                           \
  30         PORT_GP_32(0, fn, sfx),                                         \
  31         PORT_GP_30(1, fn, sfx),                                         \
  32         PORT_GP_30(2, fn, sfx),                                         \
  33         PORT_GP_32(3, fn, sfx),                                         \
  34         PORT_GP_32(4, fn, sfx),                                         \
  35         PORT_GP_32(5, fn, sfx)
  36
  37 enum {
  38         PINMUX_RESERVED = 0,
  39
  40         PINMUX_DATA_BEGIN,
  41         GP_ALL(DATA),
  42         PINMUX_DATA_END,
  43
  44         PINMUX_FUNCTION_BEGIN,
  45         GP_ALL(FN),
  46
  47         /* GPSR0 */
  48         FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
  49         FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
  50         FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
  51         FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
  52         FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
  53         FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
  54         FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
  55         FN_IP3_14_12, FN_IP3_17_15,
  56
  57         /* GPSR1 */
  58         FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
  59         FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
  60         FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
  61         FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
  62         FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
  63         FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
  64         FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
  65
  66         /* GPSR2 */
  67         FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
  68         FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
  69         FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
  70         FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
  71         FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
  72         FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
  73         FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
  74
  75         /* GPSR3 */
  76         FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
  77         FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
  78         FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
  79         FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
  80         FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
  81         FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
  82         FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
  83
  84         /* GPSR4 */
  85         FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
  86         FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
  87         FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
  88         FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
  89         FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
  90         FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
  91         FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
  92         FN_IP14_15_12, FN_IP14_18_16,
  93
  94         /* GPSR5 */
  95         FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
  96         FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
  97         FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
  98         FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
  99         FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
 100         FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
 101         FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
 102
 103         /* IPSR0 */
 104         FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
 105         FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
 106         FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
 107         FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
 108         FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
 109         FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
 110         FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
 111         FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
 112         FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
 113         FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
 114         FN_I2C2_SCL_C, FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
 115         FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C, FN_TCLK1,
 116         FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0,
 117         FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
 118
 119         /* IPSR1 */
 120         FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1,
 121         FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
 122         FN_SCIFA1_TXD_C, FN_AVB_TXD2,
 123         FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
 124         FN_SCIFA1_CTS_N_C, FN_AVB_TXD3,
 125         FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
 126         FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
 127         FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
 128         FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
 129         FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
 130         FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
 131         FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
 132         FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
 133         FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
 134         FN_A0, FN_PWM3, FN_A1, FN_PWM4,
 135
 136         /* IPSR2 */
 137         FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
 138         FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
 139         FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
 140         FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
 141         FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
 142         FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
 143         FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
 144         FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
 145         FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
 146         FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
 147         FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
 148
 149         /* IPSR3 */
 150         FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
 151         FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
 152         FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
 153         FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
 154         FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
 155         FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
 156         FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
 157         FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
 158         FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
 159         FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
 160         FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
 161         FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
 162         FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
 163
 164         /* IPSR4 */
 165         FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
 166         FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
 167         FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
 168         FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
 169         FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
 170         FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
 171         FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
 172         FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
 173         FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
 174         FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
 175         FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
 176         FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
 177         FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
 178         FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
 179         FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
 180
 181         /* IPSR5 */
 182         FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
 183         FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
 184         FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
 185         FN_INTC_EN0_N, FN_I2C1_SCL, FN_EX_CS5_N, FN_CAN0_RX,
 186         FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
 187         FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
 188         FN_I2C1_SDA, FN_BS_N, FN_IETX, FN_HTX1_B,
 189         FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
 190         FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
 191         FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
 192         FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
 193         FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
 194         FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
 195         FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
 196         FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
 197         FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
 198         FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
 199         FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
 200         FN_SSI_WS78_B,
 201
 202         /* IPSR6 */
 203         FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
 204         FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
 205         FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
 206         FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
 207         FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
 208         FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
 209         FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
 210         FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
 211         FN_ETH_CRS_DV, FN_STP_ISCLK_0_B,
 212         FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
 213         FN_I2C2_SCL_E, FN_ETH_RX_ER,
 214         FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
 215         FN_IIC2_SDA_E, FN_I2C2_SDA_E, FN_ETH_RXD0,
 216         FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
 217         FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
 218         FN_HRX0_E, FN_STP_ISSYNC_0_B,
 219         FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
 220         FN_RX1_E, FN_ETH_LINK, FN_HTX0_E,
 221         FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
 222         FN_ETH_REF_CLK, FN_HCTS0_N_E,
 223         FN_STP_IVCXO27_1_B, FN_HRX0_F,
 224
 225         /* IPSR7 */
 226         FN_ETH_MDIO, FN_HRTS0_N_E,
 227         FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
 228         FN_HTX0_F, FN_BPFCLK_G,
 229         FN_ETH_TX_EN, FN_SIM0_CLK_C,
 230         FN_HRTS0_N_F, FN_ETH_MAGIC,
 231         FN_SIM0_RST_C, FN_ETH_TXD0,
 232         FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
 233         FN_ETH_MDC, FN_STP_ISD_1_B,
 234         FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
 235         FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
 236         FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
 237         FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
 238         FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
 239         FN_PCMWE_N, FN_IECLK_C, FN_DU_DOTCLKIN1,
 240         FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
 241         FN_ATACS00_N, FN_AVB_RXD1,
 242         FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
 243
 244         /* IPSR8 */
 245         FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
 246         FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
 247         FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
 248         FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
 249         FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
 250         FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
 251         FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
 252         FN_VI1_CLK, FN_AVB_RX_DV,
 253         FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
 254         FN_AVB_CRS, FN_VI1_DATA1_VI1_B1,
 255         FN_SCIFA1_RXD_D, FN_AVB_MDC,
 256         FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
 257         FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
 258         FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
 259         FN_AVB_MAGIC, FN_VI1_DATA5_VI1_B5,
 260         FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
 261         FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
 262         FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
 263
 264         /* IPSR9 */
 265         FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
 266         FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
 267         FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
 268         FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
 269         FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
 270         FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
 271         FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
 272         FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
 273         FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
 274         FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
 275         FN_AVB_TX_EN, FN_SD1_CMD,
 276         FN_AVB_TX_ER, FN_SCIFB0_SCK_B,
 277         FN_SD1_DAT0, FN_AVB_TX_CLK,
 278         FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
 279         FN_SCIFB0_TXD_B, FN_SD1_DAT2,
 280         FN_AVB_COL, FN_SCIFB0_CTS_N_B,
 281         FN_SD1_DAT3, FN_AVB_RXD0,
 282         FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
 283         FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
 284         FN_IIC2_SCL_D, FN_I2C2_SCL_D, FN_SIM0_CLK_B,
 285         FN_VI3_CLK_B,
 286
 287         /* IPSR10 */
 288         FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
 289         FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
 290         FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
 291         FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
 292         FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
 293         FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
 294         FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
 295         FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
 296         FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
 297         FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
 298         FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B,
 299         FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
 300         FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
 301         FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B,
 302         FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
 303         FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
 304         FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
 305         FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
 306         FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
 307         FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
 308         FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
 309         FN_GLO_I0_B, FN_VI3_DATA6_B,
 310
 311         /* IPSR11 */
 312         FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
 313         FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
 314         FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
 315         FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
 316         FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
 317         FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
 318         FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
 319         FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
 320         FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
 321         FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
 322         FN_FMIN_E, FN_FMIN_F,
 323         FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B,
 324         FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B,
 325         FN_I2C2_SDA_B, FN_MLB_DAT,
 326         FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
 327         FN_SSI_SCK0129, FN_CAN_CLK_B,
 328         FN_MOUT0,
 329
 330         /* IPSR12 */
 331         FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
 332         FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
 333         FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
 334         FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
 335         FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
 336         FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
 337         FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
 338         FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
 339         FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
 340         FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
 341         FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
 342         FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
 343         FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
 344         FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
 345         FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
 346         FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
 347         FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
 348         FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
 349         FN_CAN_DEBUGOUT4,
 350
 351         /* IPSR13 */
 352         FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
 353         FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
 354         FN_SCIFB1_CTS_N, FN_BPFCLK_D,
 355         FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
 356         FN_BPFCLK_F, FN_SSI_WS6,
 357         FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
 358         FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
 359         FN_FMIN_D, FN_DU2_DR5, FN_LCDOUT5,
 360         FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
 361         FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
 362         FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
 363         FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
 364         FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
 365         FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
 366         FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
 367         FN_BPFCLK_E, FN_SSI_SDATA7_B,
 368         FN_FMIN_G, FN_SSI_SDATA8,
 369         FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
 370         FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
 371         FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
 372         FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
 373         FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
 374
 375         /* IPSR14 */
 376         FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
 377         FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
 378         FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
 379         FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_IIC1_SDA_C,
 380         FN_I2C1_SDA_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
 381         FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
 382         FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
 383         FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
 384         FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
 385         FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
 386         FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
 387         FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
 388         FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
 389         FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
 390         FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
 391         FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
 392         FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
 393         FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
 394         FN_HRTS0_N_C,
 395
 396         /* IPSR15 */
 397         FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
 398         FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
 399         FN_TX2, FN_DU2_DB0, FN_LCDOUT16, FN_IIC2_SCL, FN_I2C2_SCL,
 400         FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
 401         FN_IIC2_SDA, FN_I2C2_SDA, FN_HSCK0, FN_TS_SDEN0,
 402         FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
 403         FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
 404         FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
 405         FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
 406         FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
 407         FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
 408         FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
 409         FN_HRX0_C, FN_MSIOF0_SS1, FN_ADICHS0,
 410         FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
 411         FN_DU2_DG6, FN_LCDOUT14,
 412
 413         /* IPSR16 */
 414         FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
 415         FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
 416         FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
 417         FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B,
 418         FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
 419         FN_TCLK1_B,
 420
 421         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
 422         FN_SEL_SCIF1_4,
 423         FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
 424         FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
 425         FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
 426         FN_SEL_SCIFB1_4,
 427         FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
 428         FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
 429         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
 430         FN_SEL_SCFA_0, FN_SEL_SCFA_1,
 431         FN_SEL_SOF1_0, FN_SEL_SOF1_1,
 432         FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
 433         FN_SEL_SSI6_0, FN_SEL_SSI6_1,
 434         FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
 435         FN_SEL_VI3_0, FN_SEL_VI3_1,
 436         FN_SEL_VI2_0, FN_SEL_VI2_1,
 437         FN_SEL_VI1_0, FN_SEL_VI1_1,
 438         FN_SEL_VI0_0, FN_SEL_VI0_1,
 439         FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
 440         FN_SEL_LBS_0, FN_SEL_LBS_1,
 441         FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
 442         FN_SEL_SOF3_0, FN_SEL_SOF3_1,
 443         FN_SEL_SOF0_0, FN_SEL_SOF0_1,
 444
 445         FN_SEL_TMU1_0, FN_SEL_TMU1_1,
 446         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
 447         FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
 448         FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
 449         FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
 450         FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
 451         FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 452         FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
 453         FN_SEL_ADI_0, FN_SEL_ADI_1,
 454         FN_SEL_SSP_0, FN_SEL_SSP_1,
 455         FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
 456         FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
 457         FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
 458         FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
 459         FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
 460         FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
 461         FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
 462
 463         FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
 464         FN_SEL_IIC0_0, FN_SEL_IIC0_1,
 465         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
 466         FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
 467         FN_SEL_IIC2_4,
 468         FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
 469         FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
 470         FN_SEL_I2C2_4,
 471         FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
 472         PINMUX_FUNCTION_END,
 473
 474         PINMUX_MARK_BEGIN,
 475
 476         VI1_DATA7_VI1_B7_MARK,
 477
 478         USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
 479         USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
 480         DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
 481
 482         D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
 483         D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
 484         VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
 485         VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
 486         VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
 487         SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
 488         VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
 489         SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
 490         VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
 491         IIC2_SCL_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
 492         I2C2_SCL_C_MARK, D7_MARK, AD_DI_B_MARK, IIC2_SDA_C_MARK,
 493         VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, I2C2_SDA_C_MARK, TCLK1_MARK,
 494         D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK,
 495         VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
 496
 497         D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK,
 498         VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
 499         SCIFA1_TXD_C_MARK, AVB_TXD2_MARK,
 500         VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
 501         SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK,
 502         VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
 503         D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
 504         VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
 505         D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
 506         VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
 507         SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
 508         VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
 509         D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
 510         VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
 511         A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
 512
 513         A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
 514         PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
 515         TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
 516         A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
 517         SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
 518         A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
 519         VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, RX2_B_MARK, VI2_DATA0_VI2_B0_B_MARK,
 520         A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
 521         VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, TX2_B_MARK, VI2_DATA1_VI2_B1_B_MARK,
 522         A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
 523         VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
 524
 525         A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
 526         VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
 527         A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
 528         VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
 529         A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
 530         MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
 531         VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
 532         ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
 533         ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
 534         A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
 535         AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
 536         ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
 537         VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
 538
 539         A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
 540         A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
 541         VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
 542         VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
 543         VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
 544         VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
 545         VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
 546         VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
 547         CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
 548         VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
 549         VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
 550         MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
 551         HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
 552         VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
 553         VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
 554
 555         EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
 556         VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
 557         EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
 558         VI2_HSYNC_N_MARK, IIC1_SCL_MARK, VI2_HSYNC_N_B_MARK,
 559         INTC_EN0_N_MARK, I2C1_SCL_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
 560         MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
 561         VI1_G2_B_MARK, VI2_R4_MARK, IIC1_SDA_MARK, INTC_EN1_N_MARK,
 562         I2C1_SDA_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
 563         CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
 564         CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
 565         VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
 566         INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
 567         VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
 568         WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
 569         VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
 570         IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
 571         VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
 572         MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
 573         VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
 574         SSI_WS78_B_MARK,
 575
 576         DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
 577         VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
 578         DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
 579         SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
 580         INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
 581         DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
 582         MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
 583         SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
 584         ETH_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
 585         TS_SDEN0_D_MARK, GLO_Q0_C_MARK, IIC2_SCL_E_MARK,
 586         I2C2_SCL_E_MARK, ETH_RX_ER_MARK,
 587         STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
 588         IIC2_SDA_E_MARK, I2C2_SDA_E_MARK, ETH_RXD0_MARK,
 589         STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
 590         SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
 591         HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
 592         TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
 593         RX1_E_MARK, ETH_LINK_MARK, HTX0_E_MARK,
 594         STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
 595         ETH_REF_CLK_MARK, HCTS0_N_E_MARK,
 596         STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
 597
 598         ETH_MDIO_MARK, HRTS0_N_E_MARK,
 599         SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
 600         HTX0_F_MARK, BPFCLK_G_MARK,
 601         ETH_TX_EN_MARK, SIM0_CLK_C_MARK,
 602         HRTS0_N_F_MARK, ETH_MAGIC_MARK,
 603         SIM0_RST_C_MARK, ETH_TXD0_MARK,
 604         STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
 605         ETH_MDC_MARK, STP_ISD_1_B_MARK,
 606         TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
 607         SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
 608         GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
 609         STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
 610         PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
 611         PCMWE_N_MARK, IECLK_C_MARK, DU_DOTCLKIN1_MARK,
 612         AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
 613         ATACS00_N_MARK, AVB_RXD1_MARK,
 614         VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
 615
 616         VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
 617         VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
 618         AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
 619         AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
 620         AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
 621         AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
 622         VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
 623         VI1_CLK_MARK, AVB_RX_DV_MARK,
 624         VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
 625         AVB_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
 626         SCIFA1_RXD_D_MARK, AVB_MDC_MARK,
 627         VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
 628         VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
 629         AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
 630         AVB_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
 631         AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
 632         SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
 633         SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
 634
 635         SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
 636         SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
 637         SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
 638         SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
 639         SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
 640         GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, IIC1_SCL_B_MARK,
 641         I2C1_SCL_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
 642         MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
 643         GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, IIC1_SDA_B_MARK,
 644         I2C1_SDA_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
 645         AVB_TX_EN_MARK, SD1_CMD_MARK,
 646         AVB_TX_ER_MARK, SCIFB0_SCK_B_MARK,
 647         SD1_DAT0_MARK, AVB_TX_CLK_MARK,
 648         SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
 649         SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
 650         AVB_COL_MARK, SCIFB0_CTS_N_B_MARK,
 651         SD1_DAT3_MARK, AVB_RXD0_MARK,
 652         SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
 653         TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
 654         IIC2_SCL_D_MARK, I2C2_SCL_D_MARK, SIM0_CLK_B_MARK,
 655         VI3_CLK_B_MARK,
 656
 657         SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
 658         GLO_RFON_MARK, VI1_CLK_B_MARK, IIC2_SDA_D_MARK, I2C2_SDA_D_MARK,
 659         SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
 660         VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
 661         VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
 662         VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
 663         TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
 664         SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
 665         VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
 666         TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
 667         SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK,
 668         VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
 669         TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
 670         SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK,
 671         VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
 672         GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
 673         MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
 674         HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
 675         VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
 676         TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
 677         VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
 678         GLO_I0_B_MARK, VI3_DATA6_B_MARK,
 679
 680         SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
 681         GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
 682         TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
 683         SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
 684         MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
 685         SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
 686         MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
 687         SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
 688         VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
 689         MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
 690         FMIN_E_MARK, FMIN_F_MARK,
 691         MLB_CLK_MARK, IIC2_SCL_B_MARK, I2C2_SCL_B_MARK,
 692         MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, IIC2_SDA_B_MARK,
 693         I2C2_SDA_B_MARK, MLB_DAT_MARK,
 694         SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
 695         SSI_SCK0129_MARK, CAN_CLK_B_MARK,
 696         MOUT0_MARK,
 697
 698         SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
 699         SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
 700         SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
 701         SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
 702         SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
 703         MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
 704         STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
 705         CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
 706         SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
 707         SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
 708         MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
 709         SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
 710         MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
 711         SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
 712         CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
 713         IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
 714         CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
 715         IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
 716         CAN_DEBUGOUT4_MARK,
 717
 718         SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
 719         LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
 720         SCIFB1_CTS_N_MARK, BPFCLK_D_MARK,
 721         DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
 722         BPFCLK_F_MARK, SSI_WS6_MARK,
 723         SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
 724         LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
 725         FMIN_D_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
 726         CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
 727         SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
 728         CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
 729         SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
 730         LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
 731         STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
 732         TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
 733         BPFCLK_E_MARK, SSI_SDATA7_B_MARK,
 734         FMIN_G_MARK, SSI_SDATA8_MARK,
 735         STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
 736         CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
 737         STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
 738         SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
 739         SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
 740
 741         AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
 742         DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
 743         REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
 744         MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, IIC1_SDA_C_MARK,
 745         I2C1_SDA_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
 746         DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
 747         TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
 748         HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
 749         LCDOUT11_MARK, PWM0_B_MARK, IIC1_SCL_C_MARK, I2C1_SCL_C_MARK,
 750         SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_MARK,
 751         MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
 752         SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
 753         DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
 754         SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
 755         LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
 756         CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
 757         SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_MARK,
 758         MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
 759         HRTS0_N_C_MARK,
 760
 761         SCIFA2_SCK_MARK, FMCLK_MARK, SCK2_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
 762         LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
 763         TX2_MARK, DU2_DB0_MARK, LCDOUT16_MARK, IIC2_SCL_MARK, I2C2_SCL_MARK,
 764         SCIFA2_TXD_MARK, BPFCLK_MARK, RX2_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
 765         IIC2_SDA_MARK, I2C2_SDA_MARK, HSCK0_MARK, TS_SDEN0_MARK,
 766         DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
 767         DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
 768         LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
 769         LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
 770         LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
 771         DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
 772         SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
 773         HRX0_C_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
 774         DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
 775         DU2_DG6_MARK, LCDOUT14_MARK,
 776
 777         MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
 778         DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
 779         MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
 780         ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
 781         USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
 782         TCLK1_B_MARK,
 783
 784         IIC0_SCL_MARK, IIC0_SDA_MARK, I2C0_SCL_MARK, I2C0_SDA_MARK,
 785         IIC3_SCL_MARK, IIC3_SDA_MARK, I2C3_SCL_MARK, I2C3_SDA_MARK,
 786         PINMUX_MARK_END,
 787 };
 788
 789 static const u16 pinmux_data[] = {
 790         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 791
 792         PINMUX_SINGLE(VI1_DATA7_VI1_B7),
 793         PINMUX_SINGLE(USB0_PWEN),
 794         PINMUX_SINGLE(USB0_OVC_VBUS),
 795         PINMUX_SINGLE(USB2_PWEN),
 796         PINMUX_SINGLE(USB2_OVC),
 797         PINMUX_SINGLE(AVS1),
 798         PINMUX_SINGLE(AVS2),
 799         PINMUX_SINGLE(DU_DOTCLKIN0),
 800         PINMUX_SINGLE(DU_DOTCLKIN2),
 801
 802         PINMUX_IPSR_GPSR(IP0_2_0, D0),
 803         PINMUX_IPSR_MSEL(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
 804         PINMUX_IPSR_MSEL(IP0_2_0, VI3_DATA0, SEL_VI3_0),
 805         PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4, SEL_VI0_0),
 806         PINMUX_IPSR_MSEL(IP0_2_0, VI0_G4_B, SEL_VI0_1),
 807         PINMUX_IPSR_GPSR(IP0_5_3, D1),
 808         PINMUX_IPSR_MSEL(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
 809         PINMUX_IPSR_MSEL(IP0_5_3, VI3_DATA1, SEL_VI3_0),
 810         PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5, SEL_VI0_0),
 811         PINMUX_IPSR_MSEL(IP0_5_3, VI0_G5_B, SEL_VI0_1),
 812         PINMUX_IPSR_GPSR(IP0_8_6, D2),
 813         PINMUX_IPSR_MSEL(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
 814         PINMUX_IPSR_MSEL(IP0_8_6, VI3_DATA2, SEL_VI3_0),
 815         PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6, SEL_VI0_0),
 816         PINMUX_IPSR_MSEL(IP0_8_6, VI0_G6_B, SEL_VI0_1),
 817         PINMUX_IPSR_GPSR(IP0_11_9, D3),
 818         PINMUX_IPSR_MSEL(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
 819         PINMUX_IPSR_MSEL(IP0_11_9, VI3_DATA3, SEL_VI3_0),
 820         PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7, SEL_VI0_0),
 821         PINMUX_IPSR_MSEL(IP0_11_9, VI0_G7_B, SEL_VI0_1),
 822         PINMUX_IPSR_GPSR(IP0_15_12, D4),
 823         PINMUX_IPSR_MSEL(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
 824         PINMUX_IPSR_MSEL(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
 825         PINMUX_IPSR_MSEL(IP0_15_12, VI3_DATA4, SEL_VI3_0),
 826         PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0, SEL_VI0_0),
 827         PINMUX_IPSR_MSEL(IP0_15_12, VI0_R0_B, SEL_VI0_1),
 828         PINMUX_IPSR_MSEL(IP0_15_12, RX0_B, SEL_SCIF0_1),
 829         PINMUX_IPSR_GPSR(IP0_19_16, D5),
 830         PINMUX_IPSR_MSEL(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
 831         PINMUX_IPSR_MSEL(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
 832         PINMUX_IPSR_MSEL(IP0_19_16, VI3_DATA5, SEL_VI3_0),
 833         PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1, SEL_VI0_0),
 834         PINMUX_IPSR_MSEL(IP0_19_16, VI0_R1_B, SEL_VI0_1),
 835         PINMUX_IPSR_MSEL(IP0_19_16, TX0_B, SEL_SCIF0_1),
 836         PINMUX_IPSR_GPSR(IP0_22_20, D6),
 837         PINMUX_IPSR_MSEL(IP0_22_20, IIC2_SCL_C, SEL_IIC2_2),
 838         PINMUX_IPSR_MSEL(IP0_22_20, VI3_DATA6, SEL_VI3_0),
 839         PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2, SEL_VI0_0),
 840         PINMUX_IPSR_MSEL(IP0_22_20, VI0_R2_B, SEL_VI0_1),
 841         PINMUX_IPSR_MSEL(IP0_22_20, I2C2_SCL_C, SEL_I2C2_2),
 842         PINMUX_IPSR_GPSR(IP0_26_23, D7),
 843         PINMUX_IPSR_MSEL(IP0_26_23, AD_DI_B, SEL_ADI_1),
 844         PINMUX_IPSR_MSEL(IP0_26_23, IIC2_SDA_C, SEL_IIC2_2),
 845         PINMUX_IPSR_MSEL(IP0_26_23, VI3_DATA7, SEL_VI3_0),
 846         PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3, SEL_VI0_0),
 847         PINMUX_IPSR_MSEL(IP0_26_23, VI0_R3_B, SEL_VI0_1),
 848         PINMUX_IPSR_MSEL(IP0_26_23, I2C2_SDA_C, SEL_I2C2_2),
 849         PINMUX_IPSR_MSEL(IP0_26_23, TCLK1, SEL_TMU1_0),
 850         PINMUX_IPSR_GPSR(IP0_30_27, D8),
 851         PINMUX_IPSR_MSEL(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
 852         PINMUX_IPSR_GPSR(IP0_30_27, AVB_TXD0),
 853         PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0, SEL_VI0_0),
 854         PINMUX_IPSR_MSEL(IP0_30_27, VI0_G0_B, SEL_VI0_1),
 855         PINMUX_IPSR_MSEL(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
 856
 857         PINMUX_IPSR_GPSR(IP1_3_0, D9),
 858         PINMUX_IPSR_MSEL(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
 859         PINMUX_IPSR_GPSR(IP1_3_0, AVB_TXD1),
 860         PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1, SEL_VI0_0),
 861         PINMUX_IPSR_MSEL(IP1_3_0, VI0_G1_B, SEL_VI0_1),
 862         PINMUX_IPSR_MSEL(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
 863         PINMUX_IPSR_GPSR(IP1_7_4, D10),
 864         PINMUX_IPSR_MSEL(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
 865         PINMUX_IPSR_GPSR(IP1_7_4, AVB_TXD2),
 866         PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2, SEL_VI0_0),
 867         PINMUX_IPSR_MSEL(IP1_7_4, VI0_G2_B, SEL_VI0_1),
 868         PINMUX_IPSR_MSEL(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
 869         PINMUX_IPSR_GPSR(IP1_11_8, D11),
 870         PINMUX_IPSR_MSEL(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
 871         PINMUX_IPSR_GPSR(IP1_11_8, AVB_TXD3),
 872         PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3, SEL_VI0_0),
 873         PINMUX_IPSR_MSEL(IP1_11_8, VI0_G3_B, SEL_VI0_1),
 874         PINMUX_IPSR_MSEL(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
 875         PINMUX_IPSR_GPSR(IP1_14_12, D12),
 876         PINMUX_IPSR_MSEL(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
 877         PINMUX_IPSR_GPSR(IP1_14_12, AVB_TXD4),
 878         PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
 879         PINMUX_IPSR_MSEL(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
 880         PINMUX_IPSR_MSEL(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
 881         PINMUX_IPSR_GPSR(IP1_17_15, D13),
 882         PINMUX_IPSR_GPSR(IP1_17_15, AVB_TXD5),
 883         PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
 884         PINMUX_IPSR_MSEL(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
 885         PINMUX_IPSR_MSEL(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
 886         PINMUX_IPSR_GPSR(IP1_21_18, D14),
 887         PINMUX_IPSR_MSEL(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
 888         PINMUX_IPSR_GPSR(IP1_21_18, AVB_TXD6),
 889         PINMUX_IPSR_MSEL(IP1_21_18, RX1_B, SEL_SCIF1_1),
 890         PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
 891         PINMUX_IPSR_MSEL(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
 892         PINMUX_IPSR_MSEL(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
 893         PINMUX_IPSR_GPSR(IP1_25_22, D15),
 894         PINMUX_IPSR_MSEL(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
 895         PINMUX_IPSR_GPSR(IP1_25_22, AVB_TXD7),
 896         PINMUX_IPSR_MSEL(IP1_25_22, TX1_B, SEL_SCIF1_1),
 897         PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD, SEL_VI0_0),
 898         PINMUX_IPSR_MSEL(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
 899         PINMUX_IPSR_MSEL(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
 900         PINMUX_IPSR_GPSR(IP1_27_26, A0),
 901         PINMUX_IPSR_GPSR(IP1_27_26, PWM3),
 902         PINMUX_IPSR_GPSR(IP1_29_28, A1),
 903         PINMUX_IPSR_GPSR(IP1_29_28, PWM4),
 904
 905         PINMUX_IPSR_GPSR(IP2_2_0, A2),
 906         PINMUX_IPSR_GPSR(IP2_2_0, PWM5),
 907         PINMUX_IPSR_MSEL(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
 908         PINMUX_IPSR_GPSR(IP2_5_3, A3),
 909         PINMUX_IPSR_GPSR(IP2_5_3, PWM6),
 910         PINMUX_IPSR_MSEL(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
 911         PINMUX_IPSR_GPSR(IP2_8_6, A4),
 912         PINMUX_IPSR_MSEL(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
 913         PINMUX_IPSR_GPSR(IP2_8_6, TPU0TO0),
 914         PINMUX_IPSR_GPSR(IP2_11_9, A5),
 915         PINMUX_IPSR_MSEL(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
 916         PINMUX_IPSR_GPSR(IP2_11_9, TPU0TO1),
 917         PINMUX_IPSR_GPSR(IP2_14_12, A6),
 918         PINMUX_IPSR_MSEL(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
 919         PINMUX_IPSR_GPSR(IP2_14_12, TPU0TO2),
 920         PINMUX_IPSR_GPSR(IP2_17_15, A7),
 921         PINMUX_IPSR_MSEL(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
 922         PINMUX_IPSR_GPSR(IP2_17_15, AUDIO_CLKOUT_B),
 923         PINMUX_IPSR_GPSR(IP2_17_15, TPU0TO3),
 924         PINMUX_IPSR_GPSR(IP2_21_18, A8),
 925         PINMUX_IPSR_MSEL(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
 926         PINMUX_IPSR_MSEL(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
 927         PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4, SEL_VI0_0),
 928         PINMUX_IPSR_MSEL(IP2_21_18, VI0_R4_B, SEL_VI0_1),
 929         PINMUX_IPSR_MSEL(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
 930         PINMUX_IPSR_MSEL(IP2_21_18, RX2_B, SEL_SCIF2_1),
 931         PINMUX_IPSR_MSEL(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
 932         PINMUX_IPSR_GPSR(IP2_25_22, A9),
 933         PINMUX_IPSR_MSEL(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
 934         PINMUX_IPSR_MSEL(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
 935         PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5, SEL_VI0_0),
 936         PINMUX_IPSR_MSEL(IP2_25_22, VI0_R5_B, SEL_VI0_1),
 937         PINMUX_IPSR_MSEL(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
 938         PINMUX_IPSR_MSEL(IP2_25_22, TX2_B, SEL_SCIF2_1),
 939         PINMUX_IPSR_MSEL(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
 940         PINMUX_IPSR_GPSR(IP2_28_26, A10),
 941         PINMUX_IPSR_MSEL(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
 942         PINMUX_IPSR_GPSR(IP2_28_26, MSIOF2_SYNC),
 943         PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6, SEL_VI0_0),
 944         PINMUX_IPSR_MSEL(IP2_28_26, VI0_R6_B, SEL_VI0_1),
 945         PINMUX_IPSR_MSEL(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
 946
 947         PINMUX_IPSR_GPSR(IP3_3_0, A11),
 948         PINMUX_IPSR_MSEL(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
 949         PINMUX_IPSR_GPSR(IP3_3_0, MSIOF2_SCK),
 950         PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0, SEL_VI1_0),
 951         PINMUX_IPSR_MSEL(IP3_3_0, VI1_R0_B, SEL_VI1_1),
 952         PINMUX_IPSR_GPSR(IP3_3_0, VI2_G0),
 953         PINMUX_IPSR_MSEL(IP3_3_0, VI2_DATA3_VI2_B3_B, SEL_VI2_1),
 954         PINMUX_IPSR_GPSR(IP3_7_4, A12),
 955         PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
 956         PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
 957         PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
 958         PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
 959         PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
 960         PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),
 961         PINMUX_IPSR_GPSR(IP3_11_8, A13),
 962         PINMUX_IPSR_MSEL(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
 963         PINMUX_IPSR_GPSR(IP3_11_8, EX_WAIT2),
 964         PINMUX_IPSR_GPSR(IP3_11_8, MSIOF2_RXD),
 965         PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2, SEL_VI1_0),
 966         PINMUX_IPSR_MSEL(IP3_11_8, VI1_R2_B, SEL_VI1_1),
 967         PINMUX_IPSR_GPSR(IP3_11_8, VI2_G2),
 968         PINMUX_IPSR_MSEL(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_1),
 969         PINMUX_IPSR_GPSR(IP3_14_12, A14),
 970         PINMUX_IPSR_MSEL(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
 971         PINMUX_IPSR_GPSR(IP3_14_12, ATACS11_N),
 972         PINMUX_IPSR_GPSR(IP3_14_12, MSIOF2_SS1),
 973         PINMUX_IPSR_GPSR(IP3_17_15, A15),
 974         PINMUX_IPSR_MSEL(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
 975         PINMUX_IPSR_GPSR(IP3_17_15, ATARD1_N),
 976         PINMUX_IPSR_GPSR(IP3_17_15, MSIOF2_SS2),
 977         PINMUX_IPSR_GPSR(IP3_19_18, A16),
 978         PINMUX_IPSR_GPSR(IP3_19_18, ATAWR1_N),
 979         PINMUX_IPSR_GPSR(IP3_22_20, A17),
 980         PINMUX_IPSR_MSEL(IP3_22_20, AD_DO_B, SEL_ADI_1),
 981         PINMUX_IPSR_GPSR(IP3_22_20, ATADIR1_N),
 982         PINMUX_IPSR_GPSR(IP3_25_23, A18),
 983         PINMUX_IPSR_MSEL(IP3_25_23, AD_CLK_B, SEL_ADI_1),
 984         PINMUX_IPSR_GPSR(IP3_25_23, ATAG1_N),
 985         PINMUX_IPSR_GPSR(IP3_28_26, A19),
 986         PINMUX_IPSR_MSEL(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
 987         PINMUX_IPSR_GPSR(IP3_28_26, ATACS01_N),
 988         PINMUX_IPSR_MSEL(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
 989         PINMUX_IPSR_GPSR(IP3_31_29, A20),
 990         PINMUX_IPSR_GPSR(IP3_31_29, SPCLK),
 991         PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3, SEL_VI1_0),
 992         PINMUX_IPSR_MSEL(IP3_31_29, VI1_R3_B, SEL_VI1_1),
 993         PINMUX_IPSR_GPSR(IP3_31_29, VI2_G4),
 994
 995         PINMUX_IPSR_GPSR(IP4_2_0, A21),
 996         PINMUX_IPSR_GPSR(IP4_2_0, MOSI_IO0),
 997         PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4, SEL_VI1_0),
 998         PINMUX_IPSR_MSEL(IP4_2_0, VI1_R4_B, SEL_VI1_1),
 999         PINMUX_IPSR_GPSR(IP4_2_0, VI2_G5),
1000         PINMUX_IPSR_GPSR(IP4_5_3, A22),
1001         PINMUX_IPSR_GPSR(IP4_5_3, MISO_IO1),
1002         PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5, SEL_VI1_0),
1003         PINMUX_IPSR_MSEL(IP4_5_3, VI1_R5_B, SEL_VI1_1),
1004         PINMUX_IPSR_GPSR(IP4_5_3, VI2_G6),
1005         PINMUX_IPSR_GPSR(IP4_8_6, A23),
1006         PINMUX_IPSR_GPSR(IP4_8_6, IO2),
1007         PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7, SEL_VI1_0),
1008         PINMUX_IPSR_MSEL(IP4_8_6, VI1_G7_B, SEL_VI1_1),
1009         PINMUX_IPSR_GPSR(IP4_8_6, VI2_G7),
1010         PINMUX_IPSR_GPSR(IP4_11_9, A24),
1011         PINMUX_IPSR_GPSR(IP4_11_9, IO3),
1012         PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7, SEL_VI1_0),
1013         PINMUX_IPSR_MSEL(IP4_11_9, VI1_R7_B, SEL_VI1_1),
1014         PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
1015         PINMUX_IPSR_MSEL(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
1016         PINMUX_IPSR_GPSR(IP4_14_12, A25),
1017         PINMUX_IPSR_GPSR(IP4_14_12, SSL),
1018         PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6, SEL_VI1_0),
1019         PINMUX_IPSR_MSEL(IP4_14_12, VI1_G6_B, SEL_VI1_1),
1020         PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD, SEL_VI2_0),
1021         PINMUX_IPSR_MSEL(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
1022         PINMUX_IPSR_GPSR(IP4_17_15, CS0_N),
1023         PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6, SEL_VI1_0),
1024         PINMUX_IPSR_MSEL(IP4_17_15, VI1_R6_B, SEL_VI1_1),
1025         PINMUX_IPSR_GPSR(IP4_17_15, VI2_G3),
1026         PINMUX_IPSR_MSEL(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
1027         PINMUX_IPSR_GPSR(IP4_20_18, CS1_N_A26),
1028         PINMUX_IPSR_GPSR(IP4_20_18, SPEEDIN),
1029         PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7, SEL_VI0_0),
1030         PINMUX_IPSR_MSEL(IP4_20_18, VI0_R7_B, SEL_VI0_1),
1031         PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK, SEL_VI2_0),
1032         PINMUX_IPSR_MSEL(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
1033         PINMUX_IPSR_GPSR(IP4_23_21, EX_CS0_N),
1034         PINMUX_IPSR_MSEL(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
1035         PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5, SEL_VI1_0),
1036         PINMUX_IPSR_MSEL(IP4_23_21, VI1_G5_B, SEL_VI1_1),
1037         PINMUX_IPSR_GPSR(IP4_23_21, VI2_R0),
1038         PINMUX_IPSR_MSEL(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
1039         PINMUX_IPSR_MSEL(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
1040         PINMUX_IPSR_GPSR(IP4_26_24, EX_CS1_N),
1041         PINMUX_IPSR_GPSR(IP4_26_24, GPS_CLK),
1042         PINMUX_IPSR_MSEL(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
1043         PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD, SEL_VI1_0),
1044         PINMUX_IPSR_MSEL(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
1045         PINMUX_IPSR_GPSR(IP4_26_24, VI2_R1),
1046         PINMUX_IPSR_GPSR(IP4_29_27, EX_CS2_N),
1047         PINMUX_IPSR_GPSR(IP4_29_27, GPS_SIGN),
1048         PINMUX_IPSR_MSEL(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
1049         PINMUX_IPSR_GPSR(IP4_29_27, VI3_CLKENB),
1050         PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0, SEL_VI1_0),
1051         PINMUX_IPSR_MSEL(IP4_29_27, VI1_G0_B, SEL_VI1_1),
1052         PINMUX_IPSR_GPSR(IP4_29_27, VI2_R2),
1053
1054         PINMUX_IPSR_GPSR(IP5_2_0, EX_CS3_N),
1055         PINMUX_IPSR_GPSR(IP5_2_0, GPS_MAG),
1056         PINMUX_IPSR_GPSR(IP5_2_0, VI3_FIELD),
1057         PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1, SEL_VI1_0),
1058         PINMUX_IPSR_MSEL(IP5_2_0, VI1_G1_B, SEL_VI1_1),
1059         PINMUX_IPSR_GPSR(IP5_2_0, VI2_R3),
1060         PINMUX_IPSR_GPSR(IP5_5_3, EX_CS4_N),
1061         PINMUX_IPSR_MSEL(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
1062         PINMUX_IPSR_GPSR(IP5_5_3, VI3_HSYNC_N),
1063         PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
1064         PINMUX_IPSR_MSEL(IP5_5_3, IIC1_SCL, SEL_IIC1_0),
1065         PINMUX_IPSR_MSEL(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
1066         PINMUX_IPSR_GPSR(IP5_5_3, INTC_EN0_N),
1067         PINMUX_IPSR_MSEL(IP5_5_3, I2C1_SCL, SEL_I2C1_0),
1068         PINMUX_IPSR_GPSR(IP5_9_6, EX_CS5_N),
1069         PINMUX_IPSR_MSEL(IP5_9_6, CAN0_RX, SEL_CAN0_0),
1070         PINMUX_IPSR_MSEL(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
1071         PINMUX_IPSR_GPSR(IP5_9_6, VI3_VSYNC_N),
1072         PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2, SEL_VI1_0),
1073         PINMUX_IPSR_MSEL(IP5_9_6, VI1_G2_B, SEL_VI1_1),
1074         PINMUX_IPSR_GPSR(IP5_9_6, VI2_R4),
1075         PINMUX_IPSR_MSEL(IP5_9_6, IIC1_SDA, SEL_IIC1_0),
1076         PINMUX_IPSR_GPSR(IP5_9_6, INTC_EN1_N),
1077         PINMUX_IPSR_MSEL(IP5_9_6, I2C1_SDA, SEL_I2C1_0),
1078         PINMUX_IPSR_GPSR(IP5_12_10, BS_N),
1079         PINMUX_IPSR_MSEL(IP5_12_10, IETX, SEL_IEB_0),
1080         PINMUX_IPSR_MSEL(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
1081         PINMUX_IPSR_MSEL(IP5_12_10, CAN1_TX, SEL_CAN1_0),
1082         PINMUX_IPSR_GPSR(IP5_12_10, DRACK0),
1083         PINMUX_IPSR_MSEL(IP5_12_10, IETX_C, SEL_IEB_2),
1084         PINMUX_IPSR_GPSR(IP5_14_13, RD_N),
1085         PINMUX_IPSR_MSEL(IP5_14_13, CAN0_TX, SEL_CAN0_0),
1086         PINMUX_IPSR_MSEL(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
1087         PINMUX_IPSR_GPSR(IP5_17_15, RD_WR_N),
1088         PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3, SEL_VI1_0),
1089         PINMUX_IPSR_MSEL(IP5_17_15, VI1_G3_B, SEL_VI1_1),
1090         PINMUX_IPSR_GPSR(IP5_17_15, VI2_R5),
1091         PINMUX_IPSR_MSEL(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
1092         PINMUX_IPSR_GPSR(IP5_17_15, INTC_IRQ4_N),
1093         PINMUX_IPSR_GPSR(IP5_20_18, WE0_N),
1094         PINMUX_IPSR_MSEL(IP5_20_18, IECLK, SEL_IEB_0),
1095         PINMUX_IPSR_MSEL(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
1096         PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
1097         PINMUX_IPSR_MSEL(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
1098         PINMUX_IPSR_MSEL(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
1099         PINMUX_IPSR_GPSR(IP5_23_21, WE1_N),
1100         PINMUX_IPSR_MSEL(IP5_23_21, IERX, SEL_IEB_0),
1101         PINMUX_IPSR_MSEL(IP5_23_21, CAN1_RX, SEL_CAN1_0),
1102         PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4, SEL_VI1_0),
1103         PINMUX_IPSR_MSEL(IP5_23_21, VI1_G4_B, SEL_VI1_1),
1104         PINMUX_IPSR_GPSR(IP5_23_21, VI2_R6),
1105         PINMUX_IPSR_MSEL(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
1106         PINMUX_IPSR_MSEL(IP5_23_21, IERX_C, SEL_IEB_2),
1107         PINMUX_IPSR_MSEL(IP5_26_24, EX_WAIT0, SEL_LBS_0),
1108         PINMUX_IPSR_GPSR(IP5_26_24, IRQ3),
1109         PINMUX_IPSR_GPSR(IP5_26_24, INTC_IRQ3_N),
1110         PINMUX_IPSR_MSEL(IP5_26_24, VI3_CLK, SEL_VI3_0),
1111         PINMUX_IPSR_MSEL(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
1112         PINMUX_IPSR_MSEL(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
1113         PINMUX_IPSR_MSEL(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
1114         PINMUX_IPSR_GPSR(IP5_29_27, DREQ0_N),
1115         PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
1116         PINMUX_IPSR_MSEL(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
1117         PINMUX_IPSR_GPSR(IP5_29_27, VI2_R7),
1118         PINMUX_IPSR_MSEL(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
1119         PINMUX_IPSR_MSEL(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
1120
1121         PINMUX_IPSR_GPSR(IP6_2_0, DACK0),
1122         PINMUX_IPSR_GPSR(IP6_2_0, IRQ0),
1123         PINMUX_IPSR_GPSR(IP6_2_0, INTC_IRQ0_N),
1124         PINMUX_IPSR_MSEL(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
1125         PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
1126         PINMUX_IPSR_MSEL(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
1127         PINMUX_IPSR_MSEL(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
1128         PINMUX_IPSR_GPSR(IP6_5_3, DREQ1_N),
1129         PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
1130         PINMUX_IPSR_MSEL(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
1131         PINMUX_IPSR_MSEL(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
1132         PINMUX_IPSR_MSEL(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
1133         PINMUX_IPSR_GPSR(IP6_8_6, DACK1),
1134         PINMUX_IPSR_GPSR(IP6_8_6, IRQ1),
1135         PINMUX_IPSR_GPSR(IP6_8_6, INTC_IRQ1_N),
1136         PINMUX_IPSR_MSEL(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
1137         PINMUX_IPSR_MSEL(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
1138         PINMUX_IPSR_GPSR(IP6_10_9, DREQ2_N),
1139         PINMUX_IPSR_MSEL(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
1140         PINMUX_IPSR_MSEL(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
1141         PINMUX_IPSR_MSEL(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
1142         PINMUX_IPSR_GPSR(IP6_13_11, DACK2),
1143         PINMUX_IPSR_GPSR(IP6_13_11, IRQ2),
1144         PINMUX_IPSR_GPSR(IP6_13_11, INTC_IRQ2_N),
1145         PINMUX_IPSR_MSEL(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
1146         PINMUX_IPSR_MSEL(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
1147         PINMUX_IPSR_MSEL(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
1148         PINMUX_IPSR_GPSR(IP6_16_14, ETH_CRS_DV),
1149         PINMUX_IPSR_MSEL(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
1150         PINMUX_IPSR_MSEL(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
1151         PINMUX_IPSR_MSEL(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
1152         PINMUX_IPSR_MSEL(IP6_16_14, IIC2_SCL_E, SEL_IIC2_4),
1153         PINMUX_IPSR_MSEL(IP6_16_14, I2C2_SCL_E, SEL_I2C2_4),
1154         PINMUX_IPSR_GPSR(IP6_19_17, ETH_RX_ER),
1155         PINMUX_IPSR_MSEL(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
1156         PINMUX_IPSR_MSEL(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
1157         PINMUX_IPSR_MSEL(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
1158         PINMUX_IPSR_MSEL(IP6_19_17, IIC2_SDA_E, SEL_IIC2_4),
1159         PINMUX_IPSR_MSEL(IP6_19_17, I2C2_SDA_E, SEL_I2C2_4),
1160         PINMUX_IPSR_GPSR(IP6_22_20, ETH_RXD0),
1161         PINMUX_IPSR_MSEL(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
1162         PINMUX_IPSR_MSEL(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
1163         PINMUX_IPSR_MSEL(IP6_22_20, GLO_I0_C, SEL_GPS_2),
1164         PINMUX_IPSR_MSEL(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
1165         PINMUX_IPSR_MSEL(IP6_22_20, SCK1_E, SEL_SCIF1_4),
1166         PINMUX_IPSR_GPSR(IP6_25_23, ETH_RXD1),
1167         PINMUX_IPSR_MSEL(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
1168         PINMUX_IPSR_MSEL(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
1169         PINMUX_IPSR_MSEL(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
1170         PINMUX_IPSR_MSEL(IP6_25_23, GLO_I1_C, SEL_GPS_2),
1171         PINMUX_IPSR_MSEL(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
1172         PINMUX_IPSR_MSEL(IP6_25_23, RX1_E, SEL_SCIF1_4),
1173         PINMUX_IPSR_GPSR(IP6_28_26, ETH_LINK),
1174         PINMUX_IPSR_MSEL(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
1175         PINMUX_IPSR_MSEL(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
1176         PINMUX_IPSR_MSEL(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
1177         PINMUX_IPSR_MSEL(IP6_28_26, TX1_E, SEL_SCIF1_4),
1178         PINMUX_IPSR_GPSR(IP6_31_29, ETH_REF_CLK),
1179         PINMUX_IPSR_MSEL(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
1180         PINMUX_IPSR_MSEL(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
1181         PINMUX_IPSR_MSEL(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
1182
1183         PINMUX_IPSR_GPSR(IP7_2_0, ETH_MDIO),
1184         PINMUX_IPSR_MSEL(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
1185         PINMUX_IPSR_MSEL(IP7_2_0, SIM0_D_C, SEL_SIM_2),
1186         PINMUX_IPSR_MSEL(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
1187         PINMUX_IPSR_GPSR(IP7_5_3, ETH_TXD1),
1188         PINMUX_IPSR_MSEL(IP7_5_3, HTX0_F, SEL_HSCIF0_5),
1189         PINMUX_IPSR_MSEL(IP7_5_3, BPFCLK_G, SEL_FM_6),
1190         PINMUX_IPSR_GPSR(IP7_7_6, ETH_TX_EN),
1191         PINMUX_IPSR_MSEL(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
1192         PINMUX_IPSR_MSEL(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
1193         PINMUX_IPSR_GPSR(IP7_9_8, ETH_MAGIC),
1194         PINMUX_IPSR_MSEL(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
1195         PINMUX_IPSR_GPSR(IP7_12_10, ETH_TXD0),
1196         PINMUX_IPSR_MSEL(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
1197         PINMUX_IPSR_MSEL(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
1198         PINMUX_IPSR_MSEL(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
1199         PINMUX_IPSR_GPSR(IP7_15_13, ETH_MDC),
1200         PINMUX_IPSR_MSEL(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
1201         PINMUX_IPSR_MSEL(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
1202         PINMUX_IPSR_MSEL(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
1203         PINMUX_IPSR_GPSR(IP7_18_16, PWM0),
1204         PINMUX_IPSR_MSEL(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
1205         PINMUX_IPSR_MSEL(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
1206         PINMUX_IPSR_MSEL(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
1207         PINMUX_IPSR_MSEL(IP7_18_16, GLO_SS_C, SEL_GPS_2),
1208         PINMUX_IPSR_GPSR(IP7_21_19, PWM1),
1209         PINMUX_IPSR_MSEL(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
1210         PINMUX_IPSR_MSEL(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
1211         PINMUX_IPSR_MSEL(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
1212         PINMUX_IPSR_MSEL(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
1213         PINMUX_IPSR_GPSR(IP7_21_19, PCMOE_N),
1214         PINMUX_IPSR_GPSR(IP7_24_22, PWM2),
1215         PINMUX_IPSR_GPSR(IP7_24_22, PWMFSW0),
1216         PINMUX_IPSR_MSEL(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
1217         PINMUX_IPSR_GPSR(IP7_24_22, PCMWE_N),
1218         PINMUX_IPSR_MSEL(IP7_24_22, IECLK_C, SEL_IEB_2),
1219         PINMUX_IPSR_GPSR(IP7_26_25, DU_DOTCLKIN1),
1220         PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKC),
1221         PINMUX_IPSR_GPSR(IP7_26_25, AUDIO_CLKOUT_C),
1222         PINMUX_IPSR_MSEL(IP7_28_27, VI0_CLK, SEL_VI0_0),
1223         PINMUX_IPSR_GPSR(IP7_28_27, ATACS00_N),
1224         PINMUX_IPSR_GPSR(IP7_28_27, AVB_RXD1),
1225         PINMUX_IPSR_MSEL(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
1226         PINMUX_IPSR_GPSR(IP7_30_29, ATACS10_N),
1227         PINMUX_IPSR_GPSR(IP7_30_29, AVB_RXD2),
1228
1229         PINMUX_IPSR_MSEL(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
1230         PINMUX_IPSR_GPSR(IP8_1_0, ATARD0_N),
1231         PINMUX_IPSR_GPSR(IP8_1_0, AVB_RXD3),
1232         PINMUX_IPSR_MSEL(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
1233         PINMUX_IPSR_GPSR(IP8_3_2, ATAWR0_N),
1234         PINMUX_IPSR_GPSR(IP8_3_2, AVB_RXD4),
1235         PINMUX_IPSR_MSEL(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
1236         PINMUX_IPSR_GPSR(IP8_5_4, ATADIR0_N),
1237         PINMUX_IPSR_GPSR(IP8_5_4, AVB_RXD5),
1238         PINMUX_IPSR_MSEL(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
1239         PINMUX_IPSR_GPSR(IP8_7_6, ATAG0_N),
1240         PINMUX_IPSR_GPSR(IP8_7_6, AVB_RXD6),
1241         PINMUX_IPSR_MSEL(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
1242         PINMUX_IPSR_GPSR(IP8_9_8, EX_WAIT1),
1243         PINMUX_IPSR_GPSR(IP8_9_8, AVB_RXD7),
1244         PINMUX_IPSR_MSEL(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
1245         PINMUX_IPSR_GPSR(IP8_11_10, AVB_RX_ER),
1246         PINMUX_IPSR_MSEL(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
1247         PINMUX_IPSR_GPSR(IP8_13_12, AVB_RX_CLK),
1248         PINMUX_IPSR_MSEL(IP8_15_14, VI1_CLK, SEL_VI1_0),
1249         PINMUX_IPSR_GPSR(IP8_15_14, AVB_RX_DV),
1250         PINMUX_IPSR_MSEL(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
1251         PINMUX_IPSR_MSEL(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
1252         PINMUX_IPSR_GPSR(IP8_17_16, AVB_CRS),
1253         PINMUX_IPSR_MSEL(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
1254         PINMUX_IPSR_MSEL(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
1255         PINMUX_IPSR_GPSR(IP8_19_18, AVB_MDC),
1256         PINMUX_IPSR_MSEL(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
1257         PINMUX_IPSR_MSEL(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
1258         PINMUX_IPSR_GPSR(IP8_21_20, AVB_MDIO),
1259         PINMUX_IPSR_MSEL(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
1260         PINMUX_IPSR_MSEL(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
1261         PINMUX_IPSR_GPSR(IP8_23_22, AVB_GTX_CLK),
1262         PINMUX_IPSR_MSEL(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
1263         PINMUX_IPSR_MSEL(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
1264         PINMUX_IPSR_GPSR(IP8_25_24, AVB_MAGIC),
1265         PINMUX_IPSR_MSEL(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
1266         PINMUX_IPSR_GPSR(IP8_26, AVB_PHY_INT),
1267         PINMUX_IPSR_MSEL(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
1268         PINMUX_IPSR_GPSR(IP8_27, AVB_GTXREFCLK),
1269         PINMUX_IPSR_GPSR(IP8_28, SD0_CLK),
1270         PINMUX_IPSR_MSEL(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
1271         PINMUX_IPSR_GPSR(IP8_30_29, SD0_CMD),
1272         PINMUX_IPSR_MSEL(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
1273         PINMUX_IPSR_MSEL(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
1274
1275         PINMUX_IPSR_GPSR(IP9_1_0, SD0_DAT0),
1276         PINMUX_IPSR_MSEL(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
1277         PINMUX_IPSR_MSEL(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
1278         PINMUX_IPSR_GPSR(IP9_3_2, SD0_DAT1),
1279         PINMUX_IPSR_MSEL(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
1280         PINMUX_IPSR_MSEL(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
1281         PINMUX_IPSR_GPSR(IP9_5_4, SD0_DAT2),
1282         PINMUX_IPSR_MSEL(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
1283         PINMUX_IPSR_MSEL(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
1284         PINMUX_IPSR_GPSR(IP9_7_6, SD0_DAT3),
1285         PINMUX_IPSR_MSEL(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
1286         PINMUX_IPSR_MSEL(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
1287         PINMUX_IPSR_GPSR(IP9_11_8, SD0_CD),
1288         PINMUX_IPSR_GPSR(IP9_11_8, MMC0_D6),
1289         PINMUX_IPSR_MSEL(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
1290         PINMUX_IPSR_GPSR(IP9_11_8, USB0_EXTP),
1291         PINMUX_IPSR_MSEL(IP9_11_8, GLO_SCLK, SEL_GPS_0),
1292         PINMUX_IPSR_MSEL(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
1293         PINMUX_IPSR_MSEL(IP9_11_8, IIC1_SCL_B, SEL_IIC1_1),
1294         PINMUX_IPSR_MSEL(IP9_11_8, I2C1_SCL_B, SEL_I2C1_1),
1295         PINMUX_IPSR_MSEL(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
1296         PINMUX_IPSR_GPSR(IP9_15_12, SD0_WP),
1297         PINMUX_IPSR_GPSR(IP9_15_12, MMC0_D7),
1298         PINMUX_IPSR_MSEL(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
1299         PINMUX_IPSR_GPSR(IP9_15_12, USB0_IDIN),
1300         PINMUX_IPSR_MSEL(IP9_15_12, GLO_SDATA, SEL_GPS_0),
1301         PINMUX_IPSR_MSEL(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
1302         PINMUX_IPSR_MSEL(IP9_15_12, IIC1_SDA_B, SEL_IIC1_1),
1303         PINMUX_IPSR_MSEL(IP9_15_12, I2C1_SDA_B, SEL_I2C1_1),
1304         PINMUX_IPSR_MSEL(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
1305         PINMUX_IPSR_GPSR(IP9_17_16, SD1_CLK),
1306         PINMUX_IPSR_GPSR(IP9_17_16, AVB_TX_EN),
1307         PINMUX_IPSR_GPSR(IP9_19_18, SD1_CMD),
1308         PINMUX_IPSR_GPSR(IP9_19_18, AVB_TX_ER),
1309         PINMUX_IPSR_MSEL(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
1310         PINMUX_IPSR_GPSR(IP9_21_20, SD1_DAT0),
1311         PINMUX_IPSR_GPSR(IP9_21_20, AVB_TX_CLK),
1312         PINMUX_IPSR_MSEL(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
1313         PINMUX_IPSR_GPSR(IP9_23_22, SD1_DAT1),
1314         PINMUX_IPSR_GPSR(IP9_23_22, AVB_LINK),
1315         PINMUX_IPSR_MSEL(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
1316         PINMUX_IPSR_GPSR(IP9_25_24, SD1_DAT2),
1317         PINMUX_IPSR_GPSR(IP9_25_24, AVB_COL),
1318         PINMUX_IPSR_MSEL(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
1319         PINMUX_IPSR_GPSR(IP9_27_26, SD1_DAT3),
1320         PINMUX_IPSR_GPSR(IP9_27_26, AVB_RXD0),
1321         PINMUX_IPSR_MSEL(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
1322         PINMUX_IPSR_GPSR(IP9_31_28, SD1_CD),
1323         PINMUX_IPSR_GPSR(IP9_31_28, MMC1_D6),
1324         PINMUX_IPSR_MSEL(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
1325         PINMUX_IPSR_GPSR(IP9_31_28, USB1_EXTP),
1326         PINMUX_IPSR_MSEL(IP9_31_28, GLO_SS, SEL_GPS_0),
1327         PINMUX_IPSR_MSEL(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
1328         PINMUX_IPSR_MSEL(IP9_31_28, IIC2_SCL_D, SEL_IIC2_3),
1329         PINMUX_IPSR_MSEL(IP9_31_28, I2C2_SCL_D, SEL_I2C2_3),
1330         PINMUX_IPSR_MSEL(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
1331         PINMUX_IPSR_MSEL(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
1332
1333         PINMUX_IPSR_GPSR(IP10_3_0, SD1_WP),
1334         PINMUX_IPSR_GPSR(IP10_3_0, MMC1_D7),
1335         PINMUX_IPSR_MSEL(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
1336         PINMUX_IPSR_GPSR(IP10_3_0, USB1_IDIN),
1337         PINMUX_IPSR_MSEL(IP10_3_0, GLO_RFON, SEL_GPS_0),
1338         PINMUX_IPSR_MSEL(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
1339         PINMUX_IPSR_MSEL(IP10_3_0, IIC2_SDA_D, SEL_IIC2_3),
1340         PINMUX_IPSR_MSEL(IP10_3_0, I2C2_SDA_D, SEL_I2C2_3),
1341         PINMUX_IPSR_MSEL(IP10_3_0, SIM0_D_B, SEL_SIM_1),
1342         PINMUX_IPSR_GPSR(IP10_6_4, SD2_CLK),
1343         PINMUX_IPSR_GPSR(IP10_6_4, MMC0_CLK),
1344         PINMUX_IPSR_MSEL(IP10_6_4, SIM0_CLK, SEL_SIM_0),
1345         PINMUX_IPSR_MSEL(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
1346         PINMUX_IPSR_MSEL(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
1347         PINMUX_IPSR_MSEL(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
1348         PINMUX_IPSR_MSEL(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
1349         PINMUX_IPSR_GPSR(IP10_10_7, SD2_CMD),
1350         PINMUX_IPSR_GPSR(IP10_10_7, MMC0_CMD),
1351         PINMUX_IPSR_MSEL(IP10_10_7, SIM0_D, SEL_SIM_0),
1352         PINMUX_IPSR_MSEL(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
1353         PINMUX_IPSR_MSEL(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
1354         PINMUX_IPSR_MSEL(IP10_10_7, SCK1_D, SEL_SCIF1_3),
1355         PINMUX_IPSR_MSEL(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
1356         PINMUX_IPSR_MSEL(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
1357         PINMUX_IPSR_MSEL(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
1358         PINMUX_IPSR_GPSR(IP10_14_11, SD2_DAT0),
1359         PINMUX_IPSR_GPSR(IP10_14_11, MMC0_D0),
1360         PINMUX_IPSR_MSEL(IP10_14_11, FMCLK_B, SEL_FM_1),
1361         PINMUX_IPSR_MSEL(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
1362         PINMUX_IPSR_MSEL(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
1363         PINMUX_IPSR_MSEL(IP10_14_11, RX1_D, SEL_SCIF1_3),
1364         PINMUX_IPSR_MSEL(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
1365         PINMUX_IPSR_MSEL(IP10_14_11, GLO_SS_B, SEL_GPS_1),
1366         PINMUX_IPSR_MSEL(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
1367         PINMUX_IPSR_GPSR(IP10_18_15, SD2_DAT1),
1368         PINMUX_IPSR_GPSR(IP10_18_15, MMC0_D1),
1369         PINMUX_IPSR_MSEL(IP10_18_15, FMIN_B, SEL_FM_1),
1370         PINMUX_IPSR_MSEL(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
1371         PINMUX_IPSR_MSEL(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
1372         PINMUX_IPSR_MSEL(IP10_18_15, TX1_D, SEL_SCIF1_3),
1373         PINMUX_IPSR_MSEL(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
1374         PINMUX_IPSR_MSEL(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
1375         PINMUX_IPSR_MSEL(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
1376         PINMUX_IPSR_GPSR(IP10_22_19, SD2_DAT2),
1377         PINMUX_IPSR_GPSR(IP10_22_19, MMC0_D2),
1378         PINMUX_IPSR_MSEL(IP10_22_19, BPFCLK_B, SEL_FM_1),
1379         PINMUX_IPSR_MSEL(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
1380         PINMUX_IPSR_MSEL(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
1381         PINMUX_IPSR_MSEL(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
1382         PINMUX_IPSR_MSEL(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
1383         PINMUX_IPSR_MSEL(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
1384         PINMUX_IPSR_GPSR(IP10_25_23, SD2_DAT3),
1385         PINMUX_IPSR_GPSR(IP10_25_23, MMC0_D3),
1386         PINMUX_IPSR_MSEL(IP10_25_23, SIM0_RST, SEL_SIM_0),
1387         PINMUX_IPSR_MSEL(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
1388         PINMUX_IPSR_MSEL(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
1389         PINMUX_IPSR_MSEL(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
1390         PINMUX_IPSR_MSEL(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
1391         PINMUX_IPSR_MSEL(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
1392         PINMUX_IPSR_GPSR(IP10_29_26, SD2_CD),
1393         PINMUX_IPSR_GPSR(IP10_29_26, MMC0_D4),
1394         PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
1395         PINMUX_IPSR_GPSR(IP10_29_26, USB2_EXTP),
1396         PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0, SEL_GPS_0),
1397         PINMUX_IPSR_MSEL(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
1398         PINMUX_IPSR_MSEL(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
1399         PINMUX_IPSR_MSEL(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
1400         PINMUX_IPSR_MSEL(IP10_29_26, GLO_I0_B, SEL_GPS_1),
1401         PINMUX_IPSR_MSEL(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
1402
1403         PINMUX_IPSR_GPSR(IP11_3_0, SD2_WP),
1404         PINMUX_IPSR_GPSR(IP11_3_0, MMC0_D5),
1405         PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
1406         PINMUX_IPSR_GPSR(IP11_3_0, USB2_IDIN),
1407         PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1, SEL_GPS_0),
1408         PINMUX_IPSR_MSEL(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
1409         PINMUX_IPSR_MSEL(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
1410         PINMUX_IPSR_MSEL(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
1411         PINMUX_IPSR_MSEL(IP11_3_0, GLO_I1_B, SEL_GPS_1),
1412         PINMUX_IPSR_MSEL(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
1413         PINMUX_IPSR_GPSR(IP11_4, SD3_CLK),
1414         PINMUX_IPSR_GPSR(IP11_4, MMC1_CLK),
1415         PINMUX_IPSR_GPSR(IP11_6_5, SD3_CMD),
1416         PINMUX_IPSR_GPSR(IP11_6_5, MMC1_CMD),
1417         PINMUX_IPSR_GPSR(IP11_6_5, MTS_N),
1418         PINMUX_IPSR_GPSR(IP11_8_7, SD3_DAT0),
1419         PINMUX_IPSR_GPSR(IP11_8_7, MMC1_D0),
1420         PINMUX_IPSR_GPSR(IP11_8_7, STM_N),
1421         PINMUX_IPSR_GPSR(IP11_10_9, SD3_DAT1),
1422         PINMUX_IPSR_GPSR(IP11_10_9, MMC1_D1),
1423         PINMUX_IPSR_GPSR(IP11_10_9, MDATA),
1424         PINMUX_IPSR_GPSR(IP11_12_11, SD3_DAT2),
1425         PINMUX_IPSR_GPSR(IP11_12_11, MMC1_D2),
1426         PINMUX_IPSR_GPSR(IP11_12_11, SDATA),
1427         PINMUX_IPSR_GPSR(IP11_14_13, SD3_DAT3),
1428         PINMUX_IPSR_GPSR(IP11_14_13, MMC1_D3),
1429         PINMUX_IPSR_GPSR(IP11_14_13, SCKZ),
1430         PINMUX_IPSR_GPSR(IP11_17_15, SD3_CD),
1431         PINMUX_IPSR_GPSR(IP11_17_15, MMC1_D4),
1432         PINMUX_IPSR_MSEL(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
1433         PINMUX_IPSR_GPSR(IP11_17_15, VSP),
1434         PINMUX_IPSR_MSEL(IP11_17_15, GLO_Q0, SEL_GPS_0),
1435         PINMUX_IPSR_MSEL(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
1436         PINMUX_IPSR_GPSR(IP11_21_18, SD3_WP),
1437         PINMUX_IPSR_GPSR(IP11_21_18, MMC1_D5),
1438         PINMUX_IPSR_MSEL(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
1439         PINMUX_IPSR_MSEL(IP11_21_18, GLO_Q1, SEL_GPS_0),
1440         PINMUX_IPSR_MSEL(IP11_21_18, FMIN_C, SEL_FM_2),
1441         PINMUX_IPSR_MSEL(IP11_21_18, FMIN_E, SEL_FM_4),
1442         PINMUX_IPSR_MSEL(IP11_21_18, FMIN_F, SEL_FM_5),
1443         PINMUX_IPSR_GPSR(IP11_23_22, MLB_CLK),
1444         PINMUX_IPSR_MSEL(IP11_23_22, IIC2_SCL_B, SEL_IIC2_1),
1445         PINMUX_IPSR_MSEL(IP11_23_22, I2C2_SCL_B, SEL_I2C2_1),
1446         PINMUX_IPSR_GPSR(IP11_26_24, MLB_SIG),
1447         PINMUX_IPSR_MSEL(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
1448         PINMUX_IPSR_MSEL(IP11_26_24, RX1_C, SEL_SCIF1_2),
1449         PINMUX_IPSR_MSEL(IP11_26_24, IIC2_SDA_B, SEL_IIC2_1),
1450         PINMUX_IPSR_MSEL(IP11_26_24, I2C2_SDA_B, SEL_I2C2_1),
1451         PINMUX_IPSR_GPSR(IP11_29_27, MLB_DAT),
1452         PINMUX_IPSR_MSEL(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
1453         PINMUX_IPSR_MSEL(IP11_29_27, TX1_C, SEL_SCIF1_2),
1454         PINMUX_IPSR_MSEL(IP11_29_27, BPFCLK_C, SEL_FM_2),
1455         PINMUX_IPSR_GPSR(IP11_31_30, SSI_SCK0129),
1456         PINMUX_IPSR_MSEL(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
1457         PINMUX_IPSR_GPSR(IP11_31_30, MOUT0),
1458
1459         PINMUX_IPSR_GPSR(IP12_1_0, SSI_WS0129),
1460         PINMUX_IPSR_MSEL(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
1461         PINMUX_IPSR_GPSR(IP12_1_0, MOUT1),
1462         PINMUX_IPSR_GPSR(IP12_3_2, SSI_SDATA0),
1463         PINMUX_IPSR_MSEL(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
1464         PINMUX_IPSR_GPSR(IP12_3_2, MOUT2),
1465         PINMUX_IPSR_GPSR(IP12_5_4, SSI_SDATA1),
1466         PINMUX_IPSR_MSEL(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
1467         PINMUX_IPSR_GPSR(IP12_5_4, MOUT5),
1468         PINMUX_IPSR_GPSR(IP12_7_6, SSI_SDATA2),
1469         PINMUX_IPSR_MSEL(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
1470         PINMUX_IPSR_GPSR(IP12_7_6, SSI_SCK1),
1471         PINMUX_IPSR_GPSR(IP12_7_6, MOUT6),
1472         PINMUX_IPSR_GPSR(IP12_10_8, SSI_SCK34),
1473         PINMUX_IPSR_GPSR(IP12_10_8, STP_OPWM_0),
1474         PINMUX_IPSR_MSEL(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
1475         PINMUX_IPSR_MSEL(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
1476         PINMUX_IPSR_GPSR(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
1477         PINMUX_IPSR_GPSR(IP12_13_11, SSI_WS34),
1478         PINMUX_IPSR_MSEL(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
1479         PINMUX_IPSR_MSEL(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
1480         PINMUX_IPSR_GPSR(IP12_13_11, MSIOF1_SYNC),
1481         PINMUX_IPSR_GPSR(IP12_13_11, CAN_STEP0),
1482         PINMUX_IPSR_GPSR(IP12_16_14, SSI_SDATA3),
1483         PINMUX_IPSR_MSEL(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
1484         PINMUX_IPSR_MSEL(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
1485         PINMUX_IPSR_MSEL(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
1486         PINMUX_IPSR_GPSR(IP12_16_14, CAN_TXCLK),
1487         PINMUX_IPSR_GPSR(IP12_19_17, SSI_SCK4),
1488         PINMUX_IPSR_MSEL(IP12_19_17, STP_ISD_0, SEL_SSP_0),
1489         PINMUX_IPSR_MSEL(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
1490         PINMUX_IPSR_MSEL(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
1491         PINMUX_IPSR_MSEL(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
1492         PINMUX_IPSR_GPSR(IP12_19_17, CAN_DEBUGOUT0),
1493         PINMUX_IPSR_GPSR(IP12_22_20, SSI_WS4),
1494         PINMUX_IPSR_MSEL(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
1495         PINMUX_IPSR_MSEL(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
1496         PINMUX_IPSR_MSEL(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
1497         PINMUX_IPSR_MSEL(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
1498         PINMUX_IPSR_GPSR(IP12_22_20, CAN_DEBUGOUT1),
1499         PINMUX_IPSR_GPSR(IP12_24_23, SSI_SDATA4),
1500         PINMUX_IPSR_MSEL(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
1501         PINMUX_IPSR_MSEL(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
1502         PINMUX_IPSR_GPSR(IP12_24_23, CAN_DEBUGOUT2),
1503         PINMUX_IPSR_MSEL(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
1504         PINMUX_IPSR_MSEL(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
1505         PINMUX_IPSR_MSEL(IP12_27_25, IERX_B, SEL_IEB_1),
1506         PINMUX_IPSR_GPSR(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
1507         PINMUX_IPSR_GPSR(IP12_27_25, QSTH_QHS),
1508         PINMUX_IPSR_GPSR(IP12_27_25, CAN_DEBUGOUT3),
1509         PINMUX_IPSR_MSEL(IP12_30_28, SSI_WS5, SEL_SSI5_0),
1510         PINMUX_IPSR_MSEL(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
1511         PINMUX_IPSR_MSEL(IP12_30_28, IECLK_B, SEL_IEB_1),
1512         PINMUX_IPSR_GPSR(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
1513         PINMUX_IPSR_GPSR(IP12_30_28, QSTB_QHE),
1514         PINMUX_IPSR_GPSR(IP12_30_28, CAN_DEBUGOUT4),
1515
1516         PINMUX_IPSR_MSEL(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
1517         PINMUX_IPSR_MSEL(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
1518         PINMUX_IPSR_MSEL(IP13_2_0, IETX_B, SEL_IEB_1),
1519         PINMUX_IPSR_GPSR(IP13_2_0, DU2_DR2),
1520         PINMUX_IPSR_GPSR(IP13_2_0, LCDOUT2),
1521         PINMUX_IPSR_GPSR(IP13_2_0, CAN_DEBUGOUT5),
1522         PINMUX_IPSR_MSEL(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
1523         PINMUX_IPSR_MSEL(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
1524         PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_D, SEL_FM_3),
1525         PINMUX_IPSR_GPSR(IP13_6_3, DU2_DR3),
1526         PINMUX_IPSR_GPSR(IP13_6_3, LCDOUT3),
1527         PINMUX_IPSR_GPSR(IP13_6_3, CAN_DEBUGOUT6),
1528         PINMUX_IPSR_MSEL(IP13_6_3, BPFCLK_F, SEL_FM_5),
1529         PINMUX_IPSR_MSEL(IP13_9_7, SSI_WS6, SEL_SSI6_0),
1530         PINMUX_IPSR_MSEL(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
1531         PINMUX_IPSR_MSEL(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
1532         PINMUX_IPSR_GPSR(IP13_9_7, DU2_DR4),
1533         PINMUX_IPSR_GPSR(IP13_9_7, LCDOUT4),
1534         PINMUX_IPSR_GPSR(IP13_9_7, CAN_DEBUGOUT7),
1535         PINMUX_IPSR_MSEL(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
1536         PINMUX_IPSR_MSEL(IP13_12_10, FMIN_D, SEL_FM_3),
1537         PINMUX_IPSR_GPSR(IP13_12_10, DU2_DR5),
1538         PINMUX_IPSR_GPSR(IP13_12_10, LCDOUT5),
1539         PINMUX_IPSR_GPSR(IP13_12_10, CAN_DEBUGOUT8),
1540         PINMUX_IPSR_MSEL(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
1541         PINMUX_IPSR_MSEL(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
1542         PINMUX_IPSR_MSEL(IP13_15_13, SCK1, SEL_SCIF1_0),
1543         PINMUX_IPSR_MSEL(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
1544         PINMUX_IPSR_GPSR(IP13_15_13, DU2_DR6),
1545         PINMUX_IPSR_GPSR(IP13_15_13, LCDOUT6),
1546         PINMUX_IPSR_GPSR(IP13_15_13, CAN_DEBUGOUT9),
1547         PINMUX_IPSR_MSEL(IP13_18_16, SSI_WS78, SEL_SSI7_0),
1548         PINMUX_IPSR_MSEL(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
1549         PINMUX_IPSR_MSEL(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
1550         PINMUX_IPSR_GPSR(IP13_18_16, SCIFA2_CTS_N),
1551         PINMUX_IPSR_GPSR(IP13_18_16, DU2_DR7),
1552         PINMUX_IPSR_GPSR(IP13_18_16, LCDOUT7),
1553         PINMUX_IPSR_GPSR(IP13_18_16, CAN_DEBUGOUT10),
1554         PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
1555         PINMUX_IPSR_MSEL(IP13_22_19, STP_ISD_1, SEL_SSP_0),
1556         PINMUX_IPSR_MSEL(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
1557         PINMUX_IPSR_GPSR(IP13_22_19, SCIFA2_RTS_N),
1558         PINMUX_IPSR_GPSR(IP13_22_19, TCLK2),
1559         PINMUX_IPSR_GPSR(IP13_22_19, QSTVA_QVS),
1560         PINMUX_IPSR_GPSR(IP13_22_19, CAN_DEBUGOUT11),
1561         PINMUX_IPSR_MSEL(IP13_22_19, BPFCLK_E, SEL_FM_4),
1562         PINMUX_IPSR_MSEL(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
1563         PINMUX_IPSR_MSEL(IP13_22_19, FMIN_G, SEL_FM_6),
1564         PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
1565         PINMUX_IPSR_MSEL(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
1566         PINMUX_IPSR_MSEL(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
1567         PINMUX_IPSR_MSEL(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
1568         PINMUX_IPSR_GPSR(IP13_25_23, CAN_DEBUGOUT12),
1569         PINMUX_IPSR_MSEL(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
1570         PINMUX_IPSR_GPSR(IP13_28_26, SSI_SDATA9),
1571         PINMUX_IPSR_MSEL(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
1572         PINMUX_IPSR_MSEL(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
1573         PINMUX_IPSR_GPSR(IP13_28_26, SSI_WS1),
1574         PINMUX_IPSR_MSEL(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
1575         PINMUX_IPSR_GPSR(IP13_28_26, CAN_DEBUGOUT13),
1576         PINMUX_IPSR_GPSR(IP13_30_29, AUDIO_CLKA),
1577         PINMUX_IPSR_MSEL(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
1578         PINMUX_IPSR_GPSR(IP13_30_29, CAN_DEBUGOUT14),
1579
1580         PINMUX_IPSR_GPSR(IP14_2_0, AUDIO_CLKB),
1581         PINMUX_IPSR_MSEL(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
1582         PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
1583         PINMUX_IPSR_GPSR(IP14_2_0, DVC_MUTE),
1584         PINMUX_IPSR_MSEL(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
1585         PINMUX_IPSR_GPSR(IP14_2_0, CAN_DEBUGOUT15),
1586         PINMUX_IPSR_GPSR(IP14_2_0, REMOCON),
1587         PINMUX_IPSR_MSEL(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
1588         PINMUX_IPSR_MSEL(IP14_5_3, HSCK1, SEL_HSCIF1_0),
1589         PINMUX_IPSR_GPSR(IP14_5_3, SCK0),
1590         PINMUX_IPSR_GPSR(IP14_5_3, MSIOF3_SS2),
1591         PINMUX_IPSR_GPSR(IP14_5_3, DU2_DG2),
1592         PINMUX_IPSR_GPSR(IP14_5_3, LCDOUT10),
1593         PINMUX_IPSR_MSEL(IP14_5_3, IIC1_SDA_C, SEL_IIC1_2),
1594         PINMUX_IPSR_MSEL(IP14_5_3, I2C1_SDA_C, SEL_I2C1_2),
1595         PINMUX_IPSR_MSEL(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
1596         PINMUX_IPSR_MSEL(IP14_8_6, HRX1, SEL_HSCIF1_0),
1597         PINMUX_IPSR_MSEL(IP14_8_6, RX0, SEL_SCIF0_0),
1598         PINMUX_IPSR_GPSR(IP14_8_6, DU2_DR0),
1599         PINMUX_IPSR_GPSR(IP14_8_6, LCDOUT0),
1600         PINMUX_IPSR_MSEL(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
1601         PINMUX_IPSR_MSEL(IP14_11_9, HTX1, SEL_HSCIF1_0),
1602         PINMUX_IPSR_MSEL(IP14_11_9, TX0, SEL_SCIF0_0),
1603         PINMUX_IPSR_GPSR(IP14_11_9, DU2_DR1),
1604         PINMUX_IPSR_GPSR(IP14_11_9, LCDOUT1),
1605         PINMUX_IPSR_MSEL(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
1606         PINMUX_IPSR_MSEL(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
1607         PINMUX_IPSR_GPSR(IP14_15_12, CTS0_N),
1608         PINMUX_IPSR_MSEL(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
1609         PINMUX_IPSR_GPSR(IP14_15_12, DU2_DG3),
1610         PINMUX_IPSR_GPSR(IP14_15_12, LCDOUT11),
1611         PINMUX_IPSR_GPSR(IP14_15_12, PWM0_B),
1612         PINMUX_IPSR_MSEL(IP14_15_12, IIC1_SCL_C, SEL_IIC1_2),
1613         PINMUX_IPSR_MSEL(IP14_15_12, I2C1_SCL_C, SEL_I2C1_2),
1614         PINMUX_IPSR_MSEL(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
1615         PINMUX_IPSR_MSEL(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
1616         PINMUX_IPSR_GPSR(IP14_18_16, RTS0_N),
1617         PINMUX_IPSR_GPSR(IP14_18_16, MSIOF3_SS1),
1618         PINMUX_IPSR_GPSR(IP14_18_16, DU2_DG0),
1619         PINMUX_IPSR_GPSR(IP14_18_16, LCDOUT8),
1620         PINMUX_IPSR_GPSR(IP14_18_16, PWM1_B),
1621         PINMUX_IPSR_MSEL(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
1622         PINMUX_IPSR_MSEL(IP14_21_19, AD_DI, SEL_ADI_0),
1623         PINMUX_IPSR_MSEL(IP14_21_19, RX1, SEL_SCIF1_0),
1624         PINMUX_IPSR_GPSR(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
1625         PINMUX_IPSR_GPSR(IP14_21_19, QCPV_QDE),
1626         PINMUX_IPSR_MSEL(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
1627         PINMUX_IPSR_MSEL(IP14_24_22, AD_DO, SEL_ADI_0),
1628         PINMUX_IPSR_MSEL(IP14_24_22, TX1, SEL_SCIF1_0),
1629         PINMUX_IPSR_GPSR(IP14_24_22, DU2_DG1),
1630         PINMUX_IPSR_GPSR(IP14_24_22, LCDOUT9),
1631         PINMUX_IPSR_MSEL(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
1632         PINMUX_IPSR_MSEL(IP14_27_25, AD_CLK, SEL_ADI_0),
1633         PINMUX_IPSR_GPSR(IP14_27_25, CTS1_N),
1634         PINMUX_IPSR_MSEL(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
1635         PINMUX_IPSR_GPSR(IP14_27_25, DU0_DOTCLKOUT),
1636         PINMUX_IPSR_GPSR(IP14_27_25, QCLK),
1637         PINMUX_IPSR_MSEL(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
1638         PINMUX_IPSR_MSEL(IP14_30_28, AD_NCS_N, SEL_ADI_0),
1639         PINMUX_IPSR_GPSR(IP14_30_28, RTS1_N),
1640         PINMUX_IPSR_MSEL(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
1641         PINMUX_IPSR_GPSR(IP14_30_28, DU1_DOTCLKOUT),
1642         PINMUX_IPSR_GPSR(IP14_30_28, QSTVB_QVE),
1643         PINMUX_IPSR_MSEL(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
1644
1645         PINMUX_IPSR_MSEL(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
1646         PINMUX_IPSR_MSEL(IP15_2_0, FMCLK, SEL_FM_0),
1647         PINMUX_IPSR_GPSR(IP15_2_0, SCK2),
1648         PINMUX_IPSR_MSEL(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
1649         PINMUX_IPSR_GPSR(IP15_2_0, DU2_DG7),
1650         PINMUX_IPSR_GPSR(IP15_2_0, LCDOUT15),
1651         PINMUX_IPSR_MSEL(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_1),
1652         PINMUX_IPSR_MSEL(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1653         PINMUX_IPSR_MSEL(IP15_5_3, FMIN, SEL_FM_0),
1654         PINMUX_IPSR_MSEL(IP15_5_3, TX2, SEL_SCIF2_0),
1655         PINMUX_IPSR_GPSR(IP15_5_3, DU2_DB0),
1656         PINMUX_IPSR_GPSR(IP15_5_3, LCDOUT16),
1657         PINMUX_IPSR_MSEL(IP15_5_3, IIC2_SCL, SEL_IIC2_0),
1658         PINMUX_IPSR_MSEL(IP15_5_3, I2C2_SCL, SEL_I2C2_0),
1659         PINMUX_IPSR_MSEL(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
1660         PINMUX_IPSR_MSEL(IP15_8_6, BPFCLK, SEL_FM_0),
1661         PINMUX_IPSR_MSEL(IP15_8_6, RX2, SEL_SCIF2_0),
1662         PINMUX_IPSR_GPSR(IP15_8_6, DU2_DB1),
1663         PINMUX_IPSR_GPSR(IP15_8_6, LCDOUT17),
1664         PINMUX_IPSR_MSEL(IP15_8_6, IIC2_SDA, SEL_IIC2_0),
1665         PINMUX_IPSR_MSEL(IP15_8_6, I2C2_SDA, SEL_I2C2_0),
1666         PINMUX_IPSR_GPSR(IP15_11_9, HSCK0),
1667         PINMUX_IPSR_MSEL(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
1668         PINMUX_IPSR_GPSR(IP15_11_9, DU2_DG4),
1669         PINMUX_IPSR_GPSR(IP15_11_9, LCDOUT12),
1670         PINMUX_IPSR_MSEL(IP15_11_9, HCTS0_N_C, SEL_HSCIF0_2),
1671         PINMUX_IPSR_MSEL(IP15_13_12, HRX0, SEL_HSCIF0_0),
1672         PINMUX_IPSR_GPSR(IP15_13_12, DU2_DB2),
1673         PINMUX_IPSR_GPSR(IP15_13_12, LCDOUT18),
1674         PINMUX_IPSR_MSEL(IP15_15_14, HTX0, SEL_HSCIF0_0),
1675         PINMUX_IPSR_GPSR(IP15_15_14, DU2_DB3),
1676         PINMUX_IPSR_GPSR(IP15_15_14, LCDOUT19),
1677         PINMUX_IPSR_MSEL(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
1678         PINMUX_IPSR_GPSR(IP15_17_16, SSI_SCK9),
1679         PINMUX_IPSR_GPSR(IP15_17_16, DU2_DB4),
1680         PINMUX_IPSR_GPSR(IP15_17_16, LCDOUT20),
1681         PINMUX_IPSR_MSEL(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
1682         PINMUX_IPSR_GPSR(IP15_19_18, SSI_WS9),
1683         PINMUX_IPSR_GPSR(IP15_19_18, DU2_DB5),
1684         PINMUX_IPSR_GPSR(IP15_19_18, LCDOUT21),
1685         PINMUX_IPSR_MSEL(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
1686         PINMUX_IPSR_MSEL(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
1687         PINMUX_IPSR_GPSR(IP15_22_20, ADICLK),
1688         PINMUX_IPSR_GPSR(IP15_22_20, DU2_DB6),
1689         PINMUX_IPSR_GPSR(IP15_22_20, LCDOUT22),
1690         PINMUX_IPSR_GPSR(IP15_25_23, MSIOF0_SYNC),
1691         PINMUX_IPSR_MSEL(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
1692         PINMUX_IPSR_GPSR(IP15_25_23, SSI_SCK2),
1693         PINMUX_IPSR_GPSR(IP15_25_23, ADIDATA),
1694         PINMUX_IPSR_GPSR(IP15_25_23, DU2_DB7),
1695         PINMUX_IPSR_GPSR(IP15_25_23, LCDOUT23),
1696         PINMUX_IPSR_MSEL(IP15_25_23, HRX0_C, SEL_SCIFA2_1),
1697         PINMUX_IPSR_MSEL(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
1698         PINMUX_IPSR_GPSR(IP15_27_26, ADICHS0),
1699         PINMUX_IPSR_GPSR(IP15_27_26, DU2_DG5),
1700         PINMUX_IPSR_GPSR(IP15_27_26, LCDOUT13),
1701         PINMUX_IPSR_MSEL(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
1702         PINMUX_IPSR_GPSR(IP15_29_28, ADICHS1),
1703         PINMUX_IPSR_GPSR(IP15_29_28, DU2_DG6),
1704         PINMUX_IPSR_GPSR(IP15_29_28, LCDOUT14),
1705
1706         PINMUX_IPSR_MSEL(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
1707         PINMUX_IPSR_GPSR(IP16_2_0, AUDIO_CLKOUT),
1708         PINMUX_IPSR_GPSR(IP16_2_0, ADICHS2),
1709         PINMUX_IPSR_GPSR(IP16_2_0, DU2_DISP),
1710         PINMUX_IPSR_GPSR(IP16_2_0, QPOLA),
1711         PINMUX_IPSR_MSEL(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
1712         PINMUX_IPSR_MSEL(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
1713         PINMUX_IPSR_MSEL(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
1714         PINMUX_IPSR_MSEL(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
1715         PINMUX_IPSR_GPSR(IP16_5_3, SSI_WS2),
1716         PINMUX_IPSR_GPSR(IP16_5_3, ADICS_SAMP),
1717         PINMUX_IPSR_GPSR(IP16_5_3, DU2_CDE),
1718         PINMUX_IPSR_GPSR(IP16_5_3, QPOLB),
1719         PINMUX_IPSR_MSEL(IP16_5_3, SCIFA2_RXD_B, SEL_HSCIF0_2),
1720         PINMUX_IPSR_GPSR(IP16_6, USB1_PWEN),
1721         PINMUX_IPSR_GPSR(IP16_6, AUDIO_CLKOUT_D),
1722         PINMUX_IPSR_GPSR(IP16_7, USB1_OVC),
1723         PINMUX_IPSR_MSEL(IP16_7, TCLK1_B, SEL_TMU1_1),
1724
1725         PINMUX_DATA(IIC0_SCL_MARK, FN_SEL_IIC0_0),
1726         PINMUX_DATA(IIC0_SDA_MARK, FN_SEL_IIC0_0),
1727         PINMUX_DATA(I2C0_SCL_MARK, FN_SEL_IIC0_1),
1728         PINMUX_DATA(I2C0_SDA_MARK, FN_SEL_IIC0_1),
1729
1730         PINMUX_DATA(IIC3_SCL_MARK, FN_SEL_IICDVFS_0),
1731         PINMUX_DATA(IIC3_SDA_MARK, FN_SEL_IICDVFS_0),
1732         PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1733         PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1734 };
1735
1736 /* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1737 #define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1738 #define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1739 #define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1740
1741 static const struct sh_pfc_pin pinmux_pins[] = {
1742         PINMUX_GPIO_GP_ALL(),
1743
1744         /* Pins not associated with a GPIO port */
1745         SH_PFC_PIN_NAMED(ROW_GROUP_A('F'), 15, AF15),
1746         SH_PFC_PIN_NAMED(ROW_GROUP_A('G'), 15, AG15),
1747         SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1748         SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1749 };
1750
1751 /* - AUDIO CLOCK ------------------------------------------------------------ */
1752 static const unsigned int audio_clk_a_pins[] = {
1753         /* CLK A */
1754         RCAR_GP_PIN(4, 25),
1755 };
1756 static const unsigned int audio_clk_a_mux[] = {
1757         AUDIO_CLKA_MARK,
1758 };
1759 static const unsigned int audio_clk_b_pins[] = {
1760         /* CLK B */
1761         RCAR_GP_PIN(4, 26),
1762 };
1763 static const unsigned int audio_clk_b_mux[] = {
1764         AUDIO_CLKB_MARK,
1765 };
1766 static const unsigned int audio_clk_c_pins[] = {
1767         /* CLK C */
1768         RCAR_GP_PIN(5, 27),
1769 };
1770 static const unsigned int audio_clk_c_mux[] = {
1771         AUDIO_CLKC_MARK,
1772 };
1773 static const unsigned int audio_clkout_pins[] = {
1774         /* CLK OUT */
1775         RCAR_GP_PIN(5, 16),
1776 };
1777 static const unsigned int audio_clkout_mux[] = {
1778         AUDIO_CLKOUT_MARK,
1779 };
1780 static const unsigned int audio_clkout_b_pins[] = {
1781         /* CLK OUT B */
1782         RCAR_GP_PIN(0, 23),
1783 };
1784 static const unsigned int audio_clkout_b_mux[] = {
1785         AUDIO_CLKOUT_B_MARK,
1786 };
1787 static const unsigned int audio_clkout_c_pins[] = {
1788         /* CLK OUT C */
1789         RCAR_GP_PIN(5, 27),
1790 };
1791 static const unsigned int audio_clkout_c_mux[] = {
1792         AUDIO_CLKOUT_C_MARK,
1793 };
1794 static const unsigned int audio_clkout_d_pins[] = {
1795         /* CLK OUT D */
1796         RCAR_GP_PIN(5, 20),
1797 };
1798 static const unsigned int audio_clkout_d_mux[] = {
1799         AUDIO_CLKOUT_D_MARK,
1800 };
1801 /* - AVB -------------------------------------------------------------------- */
1802 static const unsigned int avb_link_pins[] = {
1803         RCAR_GP_PIN(3, 11),
1804 };
1805 static const unsigned int avb_link_mux[] = {
1806         AVB_LINK_MARK,
1807 };
1808 static const unsigned int avb_magic_pins[] = {
1809         RCAR_GP_PIN(2, 14),
1810 };
1811 static const unsigned int avb_magic_mux[] = {
1812         AVB_MAGIC_MARK,
1813 };
1814 static const unsigned int avb_phy_int_pins[] = {
1815         RCAR_GP_PIN(2, 15),
1816 };
1817 static const unsigned int avb_phy_int_mux[] = {
1818         AVB_PHY_INT_MARK,
1819 };
1820 static const unsigned int avb_mdio_pins[] = {
1821         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
1822 };
1823 static const unsigned int avb_mdio_mux[] = {
1824         AVB_MDC_MARK, AVB_MDIO_MARK,
1825 };
1826 static const unsigned int avb_mii_pins[] = {
1827         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1828         RCAR_GP_PIN(0, 11),
1829
1830         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1831         RCAR_GP_PIN(2, 2),
1832
1833         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1834         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 10),
1835         RCAR_GP_PIN(3, 12),
1836 };
1837 static const unsigned int avb_mii_mux[] = {
1838         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1839         AVB_TXD3_MARK,
1840
1841         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1842         AVB_RXD3_MARK,
1843
1844         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1845         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_CLK_MARK,
1846         AVB_COL_MARK,
1847 };
1848 static const unsigned int avb_gmii_pins[] = {
1849         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
1850         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
1851         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
1852
1853         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1854         RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
1855         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
1856
1857         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1858         RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 16),
1859         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1860         RCAR_GP_PIN(3, 12),
1861 };
1862 static const unsigned int avb_gmii_mux[] = {
1863         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1864         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1865         AVB_TXD6_MARK, AVB_TXD7_MARK,
1866
1867         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1868         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1869         AVB_RXD6_MARK, AVB_RXD7_MARK,
1870
1871         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1872         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1873         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1874         AVB_COL_MARK,
1875 };
1876 /* - DU RGB ----------------------------------------------------------------- */
1877 static const unsigned int du_rgb666_pins[] = {
1878         /* R[7:2], G[7:2], B[7:2] */
1879         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1880         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1881         RCAR_GP_PIN(5, 4),  RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14),
1882         RCAR_GP_PIN(5, 7),  RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
1883         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 11),
1884         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),  RCAR_GP_PIN(5, 8),
1885 };
1886 static const unsigned int du_rgb666_mux[] = {
1887         DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1888         DU2_DR3_MARK, DU2_DR2_MARK,
1889         DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1890         DU2_DG3_MARK, DU2_DG2_MARK,
1891         DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1892         DU2_DB3_MARK, DU2_DB2_MARK,
1893 };
1894 static const unsigned int du_rgb888_pins[] = {
1895         /* R[7:0], G[7:0], B[7:0] */
1896         RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19),
1897         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 16),
1898         RCAR_GP_PIN(4, 29), RCAR_GP_PIN(4, 28), RCAR_GP_PIN(5, 4),
1899         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 7),
1900         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27), RCAR_GP_PIN(5, 1),
1901         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 12),
1902         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 9),
1903         RCAR_GP_PIN(5, 8),  RCAR_GP_PIN(5, 6),  RCAR_GP_PIN(5, 5),
1904 };
1905 static const unsigned int du_rgb888_mux[] = {
1906         DU2_DR7_MARK, DU2_DR6_MARK, DU2_DR5_MARK, DU2_DR4_MARK,
1907         DU2_DR3_MARK, DU2_DR2_MARK, DU2_DR1_MARK, DU2_DR0_MARK,
1908         DU2_DG7_MARK, DU2_DG6_MARK, DU2_DG5_MARK, DU2_DG4_MARK,
1909         DU2_DG3_MARK, DU2_DG2_MARK, DU2_DG1_MARK, DU2_DG0_MARK,
1910         DU2_DB7_MARK, DU2_DB6_MARK, DU2_DB5_MARK, DU2_DB4_MARK,
1911         DU2_DB3_MARK, DU2_DB2_MARK, DU2_DB1_MARK, DU2_DB0_MARK,
1912 };
1913 static const unsigned int du_clk_out_0_pins[] = {
1914         /* CLKOUT */
1915         RCAR_GP_PIN(5, 2),
1916 };
1917 static const unsigned int du_clk_out_0_mux[] = {
1918         DU0_DOTCLKOUT_MARK
1919 };
1920 static const unsigned int du_clk_out_1_pins[] = {
1921         /* CLKOUT */
1922         RCAR_GP_PIN(5, 3),
1923 };
1924 static const unsigned int du_clk_out_1_mux[] = {
1925         DU1_DOTCLKOUT_MARK
1926 };
1927 static const unsigned int du_sync_0_pins[] = {
1928         /* VSYNC, HSYNC, DISP */
1929         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 0),
1930 };
1931 static const unsigned int du_sync_0_mux[] = {
1932         DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1933         DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK
1934 };
1935 static const unsigned int du_sync_1_pins[] = {
1936         /* VSYNC, HSYNC, DISP */
1937         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(5, 16),
1938 };
1939 static const unsigned int du_sync_1_mux[] = {
1940         DU2_EXVSYNC_DU2_VSYNC_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK,
1941         DU2_DISP_MARK
1942 };
1943 static const unsigned int du_cde_pins[] = {
1944         /* CDE */
1945         RCAR_GP_PIN(5, 17),
1946 };
1947 static const unsigned int du_cde_mux[] = {
1948         DU2_CDE_MARK,
1949 };
1950 /* - DU0 -------------------------------------------------------------------- */
1951 static const unsigned int du0_clk_in_pins[] = {
1952         /* CLKIN */
1953         RCAR_GP_PIN(5, 26),
1954 };
1955 static const unsigned int du0_clk_in_mux[] = {
1956         DU_DOTCLKIN0_MARK
1957 };
1958 /* - DU1 -------------------------------------------------------------------- */
1959 static const unsigned int du1_clk_in_pins[] = {
1960         /* CLKIN */
1961         RCAR_GP_PIN(5, 27),
1962 };
1963 static const unsigned int du1_clk_in_mux[] = {
1964         DU_DOTCLKIN1_MARK,
1965 };
1966 /* - DU2 -------------------------------------------------------------------- */
1967 static const unsigned int du2_clk_in_pins[] = {
1968         /* CLKIN */
1969         RCAR_GP_PIN(5, 28),
1970 };
1971 static const unsigned int du2_clk_in_mux[] = {
1972         DU_DOTCLKIN2_MARK,
1973 };
1974 /* - ETH -------------------------------------------------------------------- */
1975 static const unsigned int eth_link_pins[] = {
1976         /* LINK */
1977         RCAR_GP_PIN(2, 22),
1978 };
1979 static const unsigned int eth_link_mux[] = {
1980         ETH_LINK_MARK,
1981 };
1982 static const unsigned int eth_magic_pins[] = {
1983         /* MAGIC */
1984         RCAR_GP_PIN(2, 27),
1985 };
1986 static const unsigned int eth_magic_mux[] = {
1987         ETH_MAGIC_MARK,
1988 };
1989 static const unsigned int eth_mdio_pins[] = {
1990         /* MDC, MDIO */
1991         RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
1992 };
1993 static const unsigned int eth_mdio_mux[] = {
1994         ETH_MDC_MARK, ETH_MDIO_MARK,
1995 };
1996 static const unsigned int eth_rmii_pins[] = {
1997         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1998         RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
1999         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
2000         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
2001 };
2002 static const unsigned int eth_rmii_mux[] = {
2003         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
2004         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
2005 };
2006 /* - HSCIF0 ----------------------------------------------------------------- */
2007 static const unsigned int hscif0_data_pins[] = {
2008         /* RX, TX */
2009         RCAR_GP_PIN(5, 8), RCAR_GP_PIN(5, 9),
2010 };
2011 static const unsigned int hscif0_data_mux[] = {
2012         HRX0_MARK, HTX0_MARK,
2013 };
2014 static const unsigned int hscif0_clk_pins[] = {
2015         /* SCK */
2016         RCAR_GP_PIN(5, 7),
2017 };
2018 static const unsigned int hscif0_clk_mux[] = {
2019         HSCK0_MARK,
2020 };
2021 static const unsigned int hscif0_ctrl_pins[] = {
2022         /* RTS, CTS */
2023         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 10),
2024 };
2025 static const unsigned int hscif0_ctrl_mux[] = {
2026         HRTS0_N_MARK, HCTS0_N_MARK,
2027 };
2028 static const unsigned int hscif0_data_b_pins[] = {
2029         /* RX, TX */
2030         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 12),
2031 };
2032 static const unsigned int hscif0_data_b_mux[] = {
2033         HRX0_B_MARK, HTX0_B_MARK,
2034 };
2035 static const unsigned int hscif0_ctrl_b_pins[] = {
2036         /* RTS, CTS */
2037         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28),
2038 };
2039 static const unsigned int hscif0_ctrl_b_mux[] = {
2040         HRTS0_N_B_MARK, HCTS0_N_B_MARK,
2041 };
2042 static const unsigned int hscif0_data_c_pins[] = {
2043         /* RX, TX */
2044         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
2045 };
2046 static const unsigned int hscif0_data_c_mux[] = {
2047         HRX0_C_MARK, HTX0_C_MARK,
2048 };
2049 static const unsigned int hscif0_ctrl_c_pins[] = {
2050         /* RTS, CTS */
2051         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 7),
2052 };
2053 static const unsigned int hscif0_ctrl_c_mux[] = {
2054         HRTS0_N_C_MARK, HCTS0_N_C_MARK,
2055 };
2056 static const unsigned int hscif0_data_d_pins[] = {
2057         /* RX, TX */
2058         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2059 };
2060 static const unsigned int hscif0_data_d_mux[] = {
2061         HRX0_D_MARK, HTX0_D_MARK,
2062 };
2063 static const unsigned int hscif0_ctrl_d_pins[] = {
2064         /* RTS, CTS */
2065         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22),
2066 };
2067 static const unsigned int hscif0_ctrl_d_mux[] = {
2068         HRTS0_N_D_MARK, HCTS0_N_D_MARK,
2069 };
2070 static const unsigned int hscif0_data_e_pins[] = {
2071         /* RX, TX */
2072         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2073 };
2074 static const unsigned int hscif0_data_e_mux[] = {
2075         HRX0_E_MARK, HTX0_E_MARK,
2076 };
2077 static const unsigned int hscif0_ctrl_e_pins[] = {
2078         /* RTS, CTS */
2079         RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 23),
2080 };
2081 static const unsigned int hscif0_ctrl_e_mux[] = {
2082         HRTS0_N_E_MARK, HCTS0_N_E_MARK,
2083 };
2084 static const unsigned int hscif0_data_f_pins[] = {
2085         /* RX, TX */
2086         RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 25),
2087 };
2088 static const unsigned int hscif0_data_f_mux[] = {
2089         HRX0_F_MARK, HTX0_F_MARK,
2090 };
2091 static const unsigned int hscif0_ctrl_f_pins[] = {
2092         /* RTS, CTS */
2093         RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 24),
2094 };
2095 static const unsigned int hscif0_ctrl_f_mux[] = {
2096         HRTS0_N_F_MARK, HCTS0_N_F_MARK,
2097 };
2098 /* - HSCIF1 ----------------------------------------------------------------- */
2099 static const unsigned int hscif1_data_pins[] = {
2100         /* RX, TX */
2101         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2102 };
2103 static const unsigned int hscif1_data_mux[] = {
2104         HRX1_MARK, HTX1_MARK,
2105 };
2106 static const unsigned int hscif1_clk_pins[] = {
2107         /* SCK */
2108         RCAR_GP_PIN(4, 27),
2109 };
2110 static const unsigned int hscif1_clk_mux[] = {
2111         HSCK1_MARK,
2112 };
2113 static const unsigned int hscif1_ctrl_pins[] = {
2114         /* RTS, CTS */
2115         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2116 };
2117 static const unsigned int hscif1_ctrl_mux[] = {
2118         HRTS1_N_MARK, HCTS1_N_MARK,
2119 };
2120 static const unsigned int hscif1_data_b_pins[] = {
2121         /* RX, TX */
2122         RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 18),
2123 };
2124 static const unsigned int hscif1_data_b_mux[] = {
2125         HRX1_B_MARK, HTX1_B_MARK,
2126 };
2127 static const unsigned int hscif1_clk_b_pins[] = {
2128         /* SCK */
2129         RCAR_GP_PIN(1, 28),
2130 };
2131 static const unsigned int hscif1_clk_b_mux[] = {
2132         HSCK1_B_MARK,
2133 };
2134 static const unsigned int hscif1_ctrl_b_pins[] = {
2135         /* RTS, CTS */
2136         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13),
2137 };
2138 static const unsigned int hscif1_ctrl_b_mux[] = {
2139         HRTS1_N_B_MARK, HCTS1_N_B_MARK,
2140 };
2141 /* - I2C0 ------------------------------------------------------------------- */
2142 static const unsigned int i2c0_pins[] = {
2143         /* SCL, SDA */
2144         PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2145 };
2146 static const unsigned int i2c0_mux[] = {
2147         I2C0_SCL_MARK, I2C0_SDA_MARK,
2148 };
2149 /* - I2C1 ------------------------------------------------------------------- */
2150 static const unsigned int i2c1_pins[] = {
2151         /* SCL, SDA */
2152         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2153 };
2154 static const unsigned int i2c1_mux[] = {
2155         I2C1_SCL_MARK, I2C1_SDA_MARK,
2156 };
2157 static const unsigned int i2c1_b_pins[] = {
2158         /* SCL, SDA */
2159         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2160 };
2161 static const unsigned int i2c1_b_mux[] = {
2162         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2163 };
2164 static const unsigned int i2c1_c_pins[] = {
2165         /* SCL, SDA */
2166         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2167 };
2168 static const unsigned int i2c1_c_mux[] = {
2169         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2170 };
2171 /* - I2C2 ------------------------------------------------------------------- */
2172 static const unsigned int i2c2_pins[] = {
2173         /* SCL, SDA */
2174         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2175 };
2176 static const unsigned int i2c2_mux[] = {
2177         I2C2_SCL_MARK, I2C2_SDA_MARK,
2178 };
2179 static const unsigned int i2c2_b_pins[] = {
2180         /* SCL, SDA */
2181         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2182 };
2183 static const unsigned int i2c2_b_mux[] = {
2184         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2185 };
2186 static const unsigned int i2c2_c_pins[] = {
2187         /* SCL, SDA */
2188         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2189 };
2190 static const unsigned int i2c2_c_mux[] = {
2191         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2192 };
2193 static const unsigned int i2c2_d_pins[] = {
2194         /* SCL, SDA */
2195         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2196 };
2197 static const unsigned int i2c2_d_mux[] = {
2198         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2199 };
2200 static const unsigned int i2c2_e_pins[] = {
2201         /* SCL, SDA */
2202         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2203 };
2204 static const unsigned int i2c2_e_mux[] = {
2205         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2206 };
2207 /* - I2C3 ------------------------------------------------------------------- */
2208 static const unsigned int i2c3_pins[] = {
2209         /* SCL, SDA */
2210         PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2211 };
2212 static const unsigned int i2c3_mux[] = {
2213         I2C3_SCL_MARK, I2C3_SDA_MARK,
2214 };
2215 /* - IIC0 (I2C4) ------------------------------------------------------------ */
2216 static const unsigned int iic0_pins[] = {
2217         /* SCL, SDA */
2218         PIN_A_NUMBER('G', 15), PIN_A_NUMBER('F', 15),
2219 };
2220 static const unsigned int iic0_mux[] = {
2221         IIC0_SCL_MARK, IIC0_SDA_MARK,
2222 };
2223 /* - IIC1 (I2C5) ------------------------------------------------------------ */
2224 static const unsigned int iic1_pins[] = {
2225         /* SCL, SDA */
2226         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2227 };
2228 static const unsigned int iic1_mux[] = {
2229         IIC1_SCL_MARK, IIC1_SDA_MARK,
2230 };
2231 static const unsigned int iic1_b_pins[] = {
2232         /* SCL, SDA */
2233         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2234 };
2235 static const unsigned int iic1_b_mux[] = {
2236         IIC1_SCL_B_MARK, IIC1_SDA_B_MARK,
2237 };
2238 static const unsigned int iic1_c_pins[] = {
2239         /* SCL, SDA */
2240         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2241 };
2242 static const unsigned int iic1_c_mux[] = {
2243         IIC1_SCL_C_MARK, IIC1_SDA_C_MARK,
2244 };
2245 /* - IIC2 (I2C6) ------------------------------------------------------------ */
2246 static const unsigned int iic2_pins[] = {
2247         /* SCL, SDA */
2248         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2249 };
2250 static const unsigned int iic2_mux[] = {
2251         IIC2_SCL_MARK, IIC2_SDA_MARK,
2252 };
2253 static const unsigned int iic2_b_pins[] = {
2254         /* SCL, SDA */
2255         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2256 };
2257 static const unsigned int iic2_b_mux[] = {
2258         IIC2_SCL_B_MARK, IIC2_SDA_B_MARK,
2259 };
2260 static const unsigned int iic2_c_pins[] = {
2261         /* SCL, SDA */
2262         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2263 };
2264 static const unsigned int iic2_c_mux[] = {
2265         IIC2_SCL_C_MARK, IIC2_SDA_C_MARK,
2266 };
2267 static const unsigned int iic2_d_pins[] = {
2268         /* SCL, SDA */
2269         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2270 };
2271 static const unsigned int iic2_d_mux[] = {
2272         IIC2_SCL_D_MARK, IIC2_SDA_D_MARK,
2273 };
2274 static const unsigned int iic2_e_pins[] = {
2275         /* SCL, SDA */
2276         RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2277 };
2278 static const unsigned int iic2_e_mux[] = {
2279         IIC2_SCL_E_MARK, IIC2_SDA_E_MARK,
2280 };
2281 /* - IIC3 (I2C7) ------------------------------------------------------------ */
2282 static const unsigned int iic3_pins[] = {
2283 /* SCL, SDA */
2284         PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2285 };
2286 static const unsigned int iic3_mux[] = {
2287         IIC3_SCL_MARK, IIC3_SDA_MARK,
2288 };
2289 /* - INTC ------------------------------------------------------------------- */
2290 static const unsigned int intc_irq0_pins[] = {
2291         /* IRQ */
2292         RCAR_GP_PIN(1, 25),
2293 };
2294 static const unsigned int intc_irq0_mux[] = {
2295         IRQ0_MARK,
2296 };
2297 static const unsigned int intc_irq1_pins[] = {
2298         /* IRQ */
2299         RCAR_GP_PIN(1, 27),
2300 };
2301 static const unsigned int intc_irq1_mux[] = {
2302         IRQ1_MARK,
2303 };
2304 static const unsigned int intc_irq2_pins[] = {
2305         /* IRQ */
2306         RCAR_GP_PIN(1, 29),
2307 };
2308 static const unsigned int intc_irq2_mux[] = {
2309         IRQ2_MARK,
2310 };
2311 static const unsigned int intc_irq3_pins[] = {
2312         /* IRQ */
2313         RCAR_GP_PIN(1, 23),
2314 };
2315 static const unsigned int intc_irq3_mux[] = {
2316         IRQ3_MARK,
2317 };
2318 /* - MLB+ ------------------------------------------------------------------- */
2319 static const unsigned int mlb_3pin_pins[] = {
2320         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2321 };
2322 static const unsigned int mlb_3pin_mux[] = {
2323         MLB_CLK_MARK, MLB_SIG_MARK, MLB_DAT_MARK,
2324 };
2325 /* - MMCIF0 ----------------------------------------------------------------- */
2326 static const unsigned int mmc0_data1_pins[] = {
2327         /* D[0] */
2328         RCAR_GP_PIN(3, 18),
2329 };
2330 static const unsigned int mmc0_data1_mux[] = {
2331         MMC0_D0_MARK,
2332 };
2333 static const unsigned int mmc0_data4_pins[] = {
2334         /* D[0:3] */
2335         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2336         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2337 };
2338 static const unsigned int mmc0_data4_mux[] = {
2339         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2340 };
2341 static const unsigned int mmc0_data8_pins[] = {
2342         /* D[0:7] */
2343         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2344         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2345         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
2346         RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2347 };
2348 static const unsigned int mmc0_data8_mux[] = {
2349         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
2350         MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
2351 };
2352 static const unsigned int mmc0_ctrl_pins[] = {
2353         /* CLK, CMD */
2354         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
2355 };
2356 static const unsigned int mmc0_ctrl_mux[] = {
2357         MMC0_CLK_MARK, MMC0_CMD_MARK,
2358 };
2359 /* - MMCIF1 ----------------------------------------------------------------- */
2360 static const unsigned int mmc1_data1_pins[] = {
2361         /* D[0] */
2362         RCAR_GP_PIN(3, 26),
2363 };
2364 static const unsigned int mmc1_data1_mux[] = {
2365         MMC1_D0_MARK,
2366 };
2367 static const unsigned int mmc1_data4_pins[] = {
2368         /* D[0:3] */
2369         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2370         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2371 };
2372 static const unsigned int mmc1_data4_mux[] = {
2373         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2374 };
2375 static const unsigned int mmc1_data8_pins[] = {
2376         /* D[0:7] */
2377         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
2378         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
2379         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2380         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2381 };
2382 static const unsigned int mmc1_data8_mux[] = {
2383         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
2384         MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
2385 };
2386 static const unsigned int mmc1_ctrl_pins[] = {
2387         /* CLK, CMD */
2388         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
2389 };
2390 static const unsigned int mmc1_ctrl_mux[] = {
2391         MMC1_CLK_MARK, MMC1_CMD_MARK,
2392 };
2393 /* - MSIOF0 ----------------------------------------------------------------- */
2394 static const unsigned int msiof0_clk_pins[] = {
2395         /* SCK */
2396         RCAR_GP_PIN(5, 12),
2397 };
2398 static const unsigned int msiof0_clk_mux[] = {
2399         MSIOF0_SCK_MARK,
2400 };
2401 static const unsigned int msiof0_sync_pins[] = {
2402         /* SYNC */
2403         RCAR_GP_PIN(5, 13),
2404 };
2405 static const unsigned int msiof0_sync_mux[] = {
2406         MSIOF0_SYNC_MARK,
2407 };
2408 static const unsigned int msiof0_ss1_pins[] = {
2409         /* SS1 */
2410         RCAR_GP_PIN(5, 14),
2411 };
2412 static const unsigned int msiof0_ss1_mux[] = {
2413         MSIOF0_SS1_MARK,
2414 };
2415 static const unsigned int msiof0_ss2_pins[] = {
2416         /* SS2 */
2417         RCAR_GP_PIN(5, 16),
2418 };
2419 static const unsigned int msiof0_ss2_mux[] = {
2420         MSIOF0_SS2_MARK,
2421 };
2422 static const unsigned int msiof0_rx_pins[] = {
2423         /* RXD */
2424         RCAR_GP_PIN(5, 17),
2425 };
2426 static const unsigned int msiof0_rx_mux[] = {
2427         MSIOF0_RXD_MARK,
2428 };
2429 static const unsigned int msiof0_tx_pins[] = {
2430         /* TXD */
2431         RCAR_GP_PIN(5, 15),
2432 };
2433 static const unsigned int msiof0_tx_mux[] = {
2434         MSIOF0_TXD_MARK,
2435 };
2436
2437 static const unsigned int msiof0_clk_b_pins[] = {
2438         /* SCK */
2439         RCAR_GP_PIN(1, 23),
2440 };
2441 static const unsigned int msiof0_clk_b_mux[] = {
2442         MSIOF0_SCK_B_MARK,
2443 };
2444 static const unsigned int msiof0_ss1_b_pins[] = {
2445         /* SS1 */
2446         RCAR_GP_PIN(1, 12),
2447 };
2448 static const unsigned int msiof0_ss1_b_mux[] = {
2449         MSIOF0_SS1_B_MARK,
2450 };
2451 static const unsigned int msiof0_ss2_b_pins[] = {
2452         /* SS2 */
2453         RCAR_GP_PIN(1, 10),
2454 };
2455 static const unsigned int msiof0_ss2_b_mux[] = {
2456         MSIOF0_SS2_B_MARK,
2457 };
2458 static const unsigned int msiof0_rx_b_pins[] = {
2459         /* RXD */
2460         RCAR_GP_PIN(1, 29),
2461 };
2462 static const unsigned int msiof0_rx_b_mux[] = {
2463         MSIOF0_RXD_B_MARK,
2464 };
2465 static const unsigned int msiof0_tx_b_pins[] = {
2466         /* TXD */
2467         RCAR_GP_PIN(1, 28),
2468 };
2469 static const unsigned int msiof0_tx_b_mux[] = {
2470         MSIOF0_TXD_B_MARK,
2471 };
2472 /* - MSIOF1 ----------------------------------------------------------------- */
2473 static const unsigned int msiof1_clk_pins[] = {
2474         /* SCK */
2475         RCAR_GP_PIN(4, 8),
2476 };
2477 static const unsigned int msiof1_clk_mux[] = {
2478         MSIOF1_SCK_MARK,
2479 };
2480 static const unsigned int msiof1_sync_pins[] = {
2481         /* SYNC */
2482         RCAR_GP_PIN(4, 9),
2483 };
2484 static const unsigned int msiof1_sync_mux[] = {
2485         MSIOF1_SYNC_MARK,
2486 };
2487 static const unsigned int msiof1_ss1_pins[] = {
2488         /* SS1 */
2489         RCAR_GP_PIN(4, 10),
2490 };
2491 static const unsigned int msiof1_ss1_mux[] = {
2492         MSIOF1_SS1_MARK,
2493 };
2494 static const unsigned int msiof1_ss2_pins[] = {
2495         /* SS2 */
2496         RCAR_GP_PIN(4, 11),
2497 };
2498 static const unsigned int msiof1_ss2_mux[] = {
2499         MSIOF1_SS2_MARK,
2500 };
2501 static const unsigned int msiof1_rx_pins[] = {
2502         /* RXD */
2503         RCAR_GP_PIN(4, 13),
2504 };
2505 static const unsigned int msiof1_rx_mux[] = {
2506         MSIOF1_RXD_MARK,
2507 };
2508 static const unsigned int msiof1_tx_pins[] = {
2509         /* TXD */
2510         RCAR_GP_PIN(4, 12),
2511 };
2512 static const unsigned int msiof1_tx_mux[] = {
2513         MSIOF1_TXD_MARK,
2514 };
2515
2516 static const unsigned int msiof1_clk_b_pins[] = {
2517         /* SCK */
2518         RCAR_GP_PIN(1, 16),
2519 };
2520 static const unsigned int msiof1_clk_b_mux[] = {
2521         MSIOF1_SCK_B_MARK,
2522 };
2523 static const unsigned int msiof1_ss1_b_pins[] = {
2524         /* SS1 */
2525         RCAR_GP_PIN(0, 18),
2526 };
2527 static const unsigned int msiof1_ss1_b_mux[] = {
2528         MSIOF1_SS1_B_MARK,
2529 };
2530 static const unsigned int msiof1_ss2_b_pins[] = {
2531         /* SS2 */
2532         RCAR_GP_PIN(0, 19),
2533 };
2534 static const unsigned int msiof1_ss2_b_mux[] = {
2535         MSIOF1_SS2_B_MARK,
2536 };
2537 static const unsigned int msiof1_rx_b_pins[] = {
2538         /* RXD */
2539         RCAR_GP_PIN(1, 17),
2540 };
2541 static const unsigned int msiof1_rx_b_mux[] = {
2542         MSIOF1_RXD_B_MARK,
2543 };
2544 static const unsigned int msiof1_tx_b_pins[] = {
2545         /* TXD */
2546         RCAR_GP_PIN(0, 20),
2547 };
2548 static const unsigned int msiof1_tx_b_mux[] = {
2549         MSIOF1_TXD_B_MARK,
2550 };
2551 /* - MSIOF2 ----------------------------------------------------------------- */
2552 static const unsigned int msiof2_clk_pins[] = {
2553         /* SCK */
2554         RCAR_GP_PIN(0, 27),
2555 };
2556 static const unsigned int msiof2_clk_mux[] = {
2557         MSIOF2_SCK_MARK,
2558 };
2559 static const unsigned int msiof2_sync_pins[] = {
2560         /* SYNC */
2561         RCAR_GP_PIN(0, 26),
2562 };
2563 static const unsigned int msiof2_sync_mux[] = {
2564         MSIOF2_SYNC_MARK,
2565 };
2566 static const unsigned int msiof2_ss1_pins[] = {
2567         /* SS1 */
2568         RCAR_GP_PIN(0, 30),
2569 };
2570 static const unsigned int msiof2_ss1_mux[] = {
2571         MSIOF2_SS1_MARK,
2572 };
2573 static const unsigned int msiof2_ss2_pins[] = {
2574         /* SS2 */
2575         RCAR_GP_PIN(0, 31),
2576 };
2577 static const unsigned int msiof2_ss2_mux[] = {
2578         MSIOF2_SS2_MARK,
2579 };
2580 static const unsigned int msiof2_rx_pins[] = {
2581         /* RXD */
2582         RCAR_GP_PIN(0, 29),
2583 };
2584 static const unsigned int msiof2_rx_mux[] = {
2585         MSIOF2_RXD_MARK,
2586 };
2587 static const unsigned int msiof2_tx_pins[] = {
2588         /* TXD */
2589         RCAR_GP_PIN(0, 28),
2590 };
2591 static const unsigned int msiof2_tx_mux[] = {
2592         MSIOF2_TXD_MARK,
2593 };
2594 /* - MSIOF3 ----------------------------------------------------------------- */
2595 static const unsigned int msiof3_clk_pins[] = {
2596         /* SCK */
2597         RCAR_GP_PIN(5, 4),
2598 };
2599 static const unsigned int msiof3_clk_mux[] = {
2600         MSIOF3_SCK_MARK,
2601 };
2602 static const unsigned int msiof3_sync_pins[] = {
2603         /* SYNC */
2604         RCAR_GP_PIN(4, 30),
2605 };
2606 static const unsigned int msiof3_sync_mux[] = {
2607         MSIOF3_SYNC_MARK,
2608 };
2609 static const unsigned int msiof3_ss1_pins[] = {
2610         /* SS1 */
2611         RCAR_GP_PIN(4, 31),
2612 };
2613 static const unsigned int msiof3_ss1_mux[] = {
2614         MSIOF3_SS1_MARK,
2615 };
2616 static const unsigned int msiof3_ss2_pins[] = {
2617         /* SS2 */
2618         RCAR_GP_PIN(4, 27),
2619 };
2620 static const unsigned int msiof3_ss2_mux[] = {
2621         MSIOF3_SS2_MARK,
2622 };
2623 static const unsigned int msiof3_rx_pins[] = {
2624         /* RXD */
2625         RCAR_GP_PIN(5, 2),
2626 };
2627 static const unsigned int msiof3_rx_mux[] = {
2628         MSIOF3_RXD_MARK,
2629 };
2630 static const unsigned int msiof3_tx_pins[] = {
2631         /* TXD */
2632         RCAR_GP_PIN(5, 3),
2633 };
2634 static const unsigned int msiof3_tx_mux[] = {
2635         MSIOF3_TXD_MARK,
2636 };
2637
2638 static const unsigned int msiof3_clk_b_pins[] = {
2639         /* SCK */
2640         RCAR_GP_PIN(0, 0),
2641 };
2642 static const unsigned int msiof3_clk_b_mux[] = {
2643         MSIOF3_SCK_B_MARK,
2644 };
2645 static const unsigned int msiof3_sync_b_pins[] = {
2646         /* SYNC */
2647         RCAR_GP_PIN(0, 1),
2648 };
2649 static const unsigned int msiof3_sync_b_mux[] = {
2650         MSIOF3_SYNC_B_MARK,
2651 };
2652 static const unsigned int msiof3_rx_b_pins[] = {
2653         /* RXD */
2654         RCAR_GP_PIN(0, 2),
2655 };
2656 static const unsigned int msiof3_rx_b_mux[] = {
2657         MSIOF3_RXD_B_MARK,
2658 };
2659 static const unsigned int msiof3_tx_b_pins[] = {
2660         /* TXD */
2661         RCAR_GP_PIN(0, 3),
2662 };
2663 static const unsigned int msiof3_tx_b_mux[] = {
2664         MSIOF3_TXD_B_MARK,
2665 };
2666 /* - PWM -------------------------------------------------------------------- */
2667 static const unsigned int pwm0_pins[] = {
2668         RCAR_GP_PIN(5, 29),
2669 };
2670 static const unsigned int pwm0_mux[] = {
2671         PWM0_MARK,
2672 };
2673 static const unsigned int pwm0_b_pins[] = {
2674         RCAR_GP_PIN(4, 30),
2675 };
2676 static const unsigned int pwm0_b_mux[] = {
2677         PWM0_B_MARK,
2678 };
2679 static const unsigned int pwm1_pins[] = {
2680         RCAR_GP_PIN(5, 30),
2681 };
2682 static const unsigned int pwm1_mux[] = {
2683         PWM1_MARK,
2684 };
2685 static const unsigned int pwm1_b_pins[] = {
2686         RCAR_GP_PIN(4, 31),
2687 };
2688 static const unsigned int pwm1_b_mux[] = {
2689         PWM1_B_MARK,
2690 };
2691 static const unsigned int pwm2_pins[] = {
2692         RCAR_GP_PIN(5, 31),
2693 };
2694 static const unsigned int pwm2_mux[] = {
2695         PWM2_MARK,
2696 };
2697 static const unsigned int pwm3_pins[] = {
2698         RCAR_GP_PIN(0, 16),
2699 };
2700 static const unsigned int pwm3_mux[] = {
2701         PWM3_MARK,
2702 };
2703 static const unsigned int pwm4_pins[] = {
2704         RCAR_GP_PIN(0, 17),
2705 };
2706 static const unsigned int pwm4_mux[] = {
2707         PWM4_MARK,
2708 };
2709 static const unsigned int pwm5_pins[] = {
2710         RCAR_GP_PIN(0, 18),
2711 };
2712 static const unsigned int pwm5_mux[] = {
2713         PWM5_MARK,
2714 };
2715 static const unsigned int pwm6_pins[] = {
2716         RCAR_GP_PIN(0, 19),
2717 };
2718 static const unsigned int pwm6_mux[] = {
2719         PWM6_MARK,
2720 };
2721 /* - QSPI ------------------------------------------------------------------- */
2722 static const unsigned int qspi_ctrl_pins[] = {
2723         /* SPCLK, SSL */
2724         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2725 };
2726 static const unsigned int qspi_ctrl_mux[] = {
2727         SPCLK_MARK, SSL_MARK,
2728 };
2729 static const unsigned int qspi_data2_pins[] = {
2730         /* MOSI_IO0, MISO_IO1 */
2731         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2732 };
2733 static const unsigned int qspi_data2_mux[] = {
2734         MOSI_IO0_MARK, MISO_IO1_MARK,
2735 };
2736 static const unsigned int qspi_data4_pins[] = {
2737         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2738         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2739         RCAR_GP_PIN(1, 8),
2740 };
2741 static const unsigned int qspi_data4_mux[] = {
2742         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2743 };
2744 /* - SCIF0 ------------------------------------------------------------------ */
2745 static const unsigned int scif0_data_pins[] = {
2746         /* RX, TX */
2747         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2748 };
2749 static const unsigned int scif0_data_mux[] = {
2750         RX0_MARK, TX0_MARK,
2751 };
2752 static const unsigned int scif0_clk_pins[] = {
2753         /* SCK */
2754         RCAR_GP_PIN(4, 27),
2755 };
2756 static const unsigned int scif0_clk_mux[] = {
2757         SCK0_MARK,
2758 };
2759 static const unsigned int scif0_ctrl_pins[] = {
2760         /* RTS, CTS */
2761         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2762 };
2763 static const unsigned int scif0_ctrl_mux[] = {
2764         RTS0_N_MARK, CTS0_N_MARK,
2765 };
2766 static const unsigned int scif0_data_b_pins[] = {
2767         /* RX, TX */
2768         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
2769 };
2770 static const unsigned int scif0_data_b_mux[] = {
2771         RX0_B_MARK, TX0_B_MARK,
2772 };
2773 /* - SCIF1 ------------------------------------------------------------------ */
2774 static const unsigned int scif1_data_pins[] = {
2775         /* RX, TX */
2776         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2777 };
2778 static const unsigned int scif1_data_mux[] = {
2779         RX1_MARK, TX1_MARK,
2780 };
2781 static const unsigned int scif1_clk_pins[] = {
2782         /* SCK */
2783         RCAR_GP_PIN(4, 20),
2784 };
2785 static const unsigned int scif1_clk_mux[] = {
2786         SCK1_MARK,
2787 };
2788 static const unsigned int scif1_ctrl_pins[] = {
2789         /* RTS, CTS */
2790         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2791 };
2792 static const unsigned int scif1_ctrl_mux[] = {
2793         RTS1_N_MARK, CTS1_N_MARK,
2794 };
2795 static const unsigned int scif1_data_b_pins[] = {
2796         /* RX, TX */
2797         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2798 };
2799 static const unsigned int scif1_data_b_mux[] = {
2800         RX1_B_MARK, TX1_B_MARK,
2801 };
2802 static const unsigned int scif1_data_c_pins[] = {
2803         /* RX, TX */
2804         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
2805 };
2806 static const unsigned int scif1_data_c_mux[] = {
2807         RX1_C_MARK, TX1_C_MARK,
2808 };
2809 static const unsigned int scif1_data_d_pins[] = {
2810         /* RX, TX */
2811         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
2812 };
2813 static const unsigned int scif1_data_d_mux[] = {
2814         RX1_D_MARK, TX1_D_MARK,
2815 };
2816 static const unsigned int scif1_clk_d_pins[] = {
2817         /* SCK */
2818         RCAR_GP_PIN(3, 17),
2819 };
2820 static const unsigned int scif1_clk_d_mux[] = {
2821         SCK1_D_MARK,
2822 };
2823 static const unsigned int scif1_data_e_pins[] = {
2824         /* RX, TX */
2825         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
2826 };
2827 static const unsigned int scif1_data_e_mux[] = {
2828         RX1_E_MARK, TX1_E_MARK,
2829 };
2830 static const unsigned int scif1_clk_e_pins[] = {
2831         /* SCK */
2832         RCAR_GP_PIN(2, 20),
2833 };
2834 static const unsigned int scif1_clk_e_mux[] = {
2835         SCK1_E_MARK,
2836 };
2837 /* - SCIF2 ------------------------------------------------------------------ */
2838 static const unsigned int scif2_data_pins[] = {
2839         /* RX, TX */
2840         RCAR_GP_PIN(5, 6), RCAR_GP_PIN(5, 5),
2841 };
2842 static const unsigned int scif2_data_mux[] = {
2843         RX2_MARK, TX2_MARK,
2844 };
2845 static const unsigned int scif2_clk_pins[] = {
2846         /* SCK */
2847         RCAR_GP_PIN(5, 4),
2848 };
2849 static const unsigned int scif2_clk_mux[] = {
2850         SCK2_MARK,
2851 };
2852 static const unsigned int scif2_data_b_pins[] = {
2853         /* RX, TX */
2854         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2855 };
2856 static const unsigned int scif2_data_b_mux[] = {
2857         RX2_B_MARK, TX2_B_MARK,
2858 };
2859 /* - SCIFA0 ----------------------------------------------------------------- */
2860 static const unsigned int scifa0_data_pins[] = {
2861         /* RXD, TXD */
2862         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2863 };
2864 static const unsigned int scifa0_data_mux[] = {
2865         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2866 };
2867 static const unsigned int scifa0_clk_pins[] = {
2868         /* SCK */
2869         RCAR_GP_PIN(4, 27),
2870 };
2871 static const unsigned int scifa0_clk_mux[] = {
2872         SCIFA0_SCK_MARK,
2873 };
2874 static const unsigned int scifa0_ctrl_pins[] = {
2875         /* RTS, CTS */
2876         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
2877 };
2878 static const unsigned int scifa0_ctrl_mux[] = {
2879         SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
2880 };
2881 static const unsigned int scifa0_data_b_pins[] = {
2882         /* RXD, TXD */
2883         RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2884 };
2885 static const unsigned int scifa0_data_b_mux[] = {
2886         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2887 };
2888 static const unsigned int scifa0_clk_b_pins[] = {
2889         /* SCK */
2890         RCAR_GP_PIN(1, 19),
2891 };
2892 static const unsigned int scifa0_clk_b_mux[] = {
2893         SCIFA0_SCK_B_MARK,
2894 };
2895 static const unsigned int scifa0_ctrl_b_pins[] = {
2896         /* RTS, CTS */
2897         RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
2898 };
2899 static const unsigned int scifa0_ctrl_b_mux[] = {
2900         SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
2901 };
2902 /* - SCIFA1 ----------------------------------------------------------------- */
2903 static const unsigned int scifa1_data_pins[] = {
2904         /* RXD, TXD */
2905         RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
2906 };
2907 static const unsigned int scifa1_data_mux[] = {
2908         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2909 };
2910 static const unsigned int scifa1_clk_pins[] = {
2911         /* SCK */
2912         RCAR_GP_PIN(4, 20),
2913 };
2914 static const unsigned int scifa1_clk_mux[] = {
2915         SCIFA1_SCK_MARK,
2916 };
2917 static const unsigned int scifa1_ctrl_pins[] = {
2918         /* RTS, CTS */
2919         RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
2920 };
2921 static const unsigned int scifa1_ctrl_mux[] = {
2922         SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
2923 };
2924 static const unsigned int scifa1_data_b_pins[] = {
2925         /* RXD, TXD */
2926         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
2927 };
2928 static const unsigned int scifa1_data_b_mux[] = {
2929         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2930 };
2931 static const unsigned int scifa1_clk_b_pins[] = {
2932         /* SCK */
2933         RCAR_GP_PIN(0, 23),
2934 };
2935 static const unsigned int scifa1_clk_b_mux[] = {
2936         SCIFA1_SCK_B_MARK,
2937 };
2938 static const unsigned int scifa1_ctrl_b_pins[] = {
2939         /* RTS, CTS */
2940         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
2941 };
2942 static const unsigned int scifa1_ctrl_b_mux[] = {
2943         SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
2944 };
2945 static const unsigned int scifa1_data_c_pins[] = {
2946         /* RXD, TXD */
2947         RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
2948 };
2949 static const unsigned int scifa1_data_c_mux[] = {
2950         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2951 };
2952 static const unsigned int scifa1_clk_c_pins[] = {
2953         /* SCK */
2954         RCAR_GP_PIN(0, 8),
2955 };
2956 static const unsigned int scifa1_clk_c_mux[] = {
2957         SCIFA1_SCK_C_MARK,
2958 };
2959 static const unsigned int scifa1_ctrl_c_pins[] = {
2960         /* RTS, CTS */
2961         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
2962 };
2963 static const unsigned int scifa1_ctrl_c_mux[] = {
2964         SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
2965 };
2966 static const unsigned int scifa1_data_d_pins[] = {
2967         /* RXD, TXD */
2968         RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
2969 };
2970 static const unsigned int scifa1_data_d_mux[] = {
2971         SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
2972 };
2973 static const unsigned int scifa1_clk_d_pins[] = {
2974         /* SCK */
2975         RCAR_GP_PIN(2, 10),
2976 };
2977 static const unsigned int scifa1_clk_d_mux[] = {
2978         SCIFA1_SCK_D_MARK,
2979 };
2980 static const unsigned int scifa1_ctrl_d_pins[] = {
2981         /* RTS, CTS */
2982         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
2983 };
2984 static const unsigned int scifa1_ctrl_d_mux[] = {
2985         SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
2986 };
2987 /* - SCIFA2 ----------------------------------------------------------------- */
2988 static const unsigned int scifa2_data_pins[] = {
2989         /* RXD, TXD */
2990         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2991 };
2992 static const unsigned int scifa2_data_mux[] = {
2993         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2994 };
2995 static const unsigned int scifa2_clk_pins[] = {
2996         /* SCK */
2997         RCAR_GP_PIN(5, 4),
2998 };
2999 static const unsigned int scifa2_clk_mux[] = {
3000         SCIFA2_SCK_MARK,
3001 };
3002 static const unsigned int scifa2_ctrl_pins[] = {
3003         /* RTS, CTS */
3004         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
3005 };
3006 static const unsigned int scifa2_ctrl_mux[] = {
3007         SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
3008 };
3009 static const unsigned int scifa2_data_b_pins[] = {
3010         /* RXD, TXD */
3011         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
3012 };
3013 static const unsigned int scifa2_data_b_mux[] = {
3014         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
3015 };
3016 static const unsigned int scifa2_data_c_pins[] = {
3017         /* RXD, TXD */
3018         RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
3019 };
3020 static const unsigned int scifa2_data_c_mux[] = {
3021         SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
3022 };
3023 static const unsigned int scifa2_clk_c_pins[] = {
3024         /* SCK */
3025         RCAR_GP_PIN(5, 29),
3026 };
3027 static const unsigned int scifa2_clk_c_mux[] = {
3028         SCIFA2_SCK_C_MARK,
3029 };
3030 /* - SCIFB0 ----------------------------------------------------------------- */
3031 static const unsigned int scifb0_data_pins[] = {
3032         /* RXD, TXD */
3033         RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
3034 };
3035 static const unsigned int scifb0_data_mux[] = {
3036         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
3037 };
3038 static const unsigned int scifb0_clk_pins[] = {
3039         /* SCK */
3040         RCAR_GP_PIN(4, 8),
3041 };
3042 static const unsigned int scifb0_clk_mux[] = {
3043         SCIFB0_SCK_MARK,
3044 };
3045 static const unsigned int scifb0_ctrl_pins[] = {
3046         /* RTS, CTS */
3047         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
3048 };
3049 static const unsigned int scifb0_ctrl_mux[] = {
3050         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
3051 };
3052 static const unsigned int scifb0_data_b_pins[] = {
3053         /* RXD, TXD */
3054         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
3055 };
3056 static const unsigned int scifb0_data_b_mux[] = {
3057         SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
3058 };
3059 static const unsigned int scifb0_clk_b_pins[] = {
3060         /* SCK */
3061         RCAR_GP_PIN(3, 9),
3062 };
3063 static const unsigned int scifb0_clk_b_mux[] = {
3064         SCIFB0_SCK_B_MARK,
3065 };
3066 static const unsigned int scifb0_ctrl_b_pins[] = {
3067         /* RTS, CTS */
3068         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
3069 };
3070 static const unsigned int scifb0_ctrl_b_mux[] = {
3071         SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
3072 };
3073 static const unsigned int scifb0_data_c_pins[] = {
3074         /* RXD, TXD */
3075         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3076 };
3077 static const unsigned int scifb0_data_c_mux[] = {
3078         SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
3079 };
3080 /* - SCIFB1 ----------------------------------------------------------------- */
3081 static const unsigned int scifb1_data_pins[] = {
3082         /* RXD, TXD */
3083         RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
3084 };
3085 static const unsigned int scifb1_data_mux[] = {
3086         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
3087 };
3088 static const unsigned int scifb1_clk_pins[] = {
3089         /* SCK */
3090         RCAR_GP_PIN(4, 14),
3091 };
3092 static const unsigned int scifb1_clk_mux[] = {
3093         SCIFB1_SCK_MARK,
3094 };
3095 static const unsigned int scifb1_ctrl_pins[] = {
3096         /* RTS, CTS */
3097         RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
3098 };
3099 static const unsigned int scifb1_ctrl_mux[] = {
3100         SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
3101 };
3102 static const unsigned int scifb1_data_b_pins[] = {
3103         /* RXD, TXD */
3104         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
3105 };
3106 static const unsigned int scifb1_data_b_mux[] = {
3107         SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
3108 };
3109 static const unsigned int scifb1_clk_b_pins[] = {
3110         /* SCK */
3111         RCAR_GP_PIN(3, 1),
3112 };
3113 static const unsigned int scifb1_clk_b_mux[] = {
3114         SCIFB1_SCK_B_MARK,
3115 };
3116 static const unsigned int scifb1_ctrl_b_pins[] = {
3117         /* RTS, CTS */
3118         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
3119 };
3120 static const unsigned int scifb1_ctrl_b_mux[] = {
3121         SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
3122 };
3123 static const unsigned int scifb1_data_c_pins[] = {
3124         /* RXD, TXD */
3125         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3126 };
3127 static const unsigned int scifb1_data_c_mux[] = {
3128         SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
3129 };
3130 static const unsigned int scifb1_data_d_pins[] = {
3131         /* RXD, TXD */
3132         RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
3133 };
3134 static const unsigned int scifb1_data_d_mux[] = {
3135         SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
3136 };
3137 static const unsigned int scifb1_data_e_pins[] = {
3138         /* RXD, TXD */
3139         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
3140 };
3141 static const unsigned int scifb1_data_e_mux[] = {
3142         SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
3143 };
3144 static const unsigned int scifb1_clk_e_pins[] = {
3145         /* SCK */
3146         RCAR_GP_PIN(3, 17),
3147 };
3148 static const unsigned int scifb1_clk_e_mux[] = {
3149         SCIFB1_SCK_E_MARK,
3150 };
3151 static const unsigned int scifb1_data_f_pins[] = {
3152         /* RXD, TXD */
3153         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3154 };
3155 static const unsigned int scifb1_data_f_mux[] = {
3156         SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
3157 };
3158 static const unsigned int scifb1_data_g_pins[] = {
3159         /* RXD, TXD */
3160         RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
3161 };
3162 static const unsigned int scifb1_data_g_mux[] = {
3163         SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
3164 };
3165 static const unsigned int scifb1_clk_g_pins[] = {
3166         /* SCK */
3167         RCAR_GP_PIN(2, 20),
3168 };
3169 static const unsigned int scifb1_clk_g_mux[] = {
3170         SCIFB1_SCK_G_MARK,
3171 };
3172 /* - SCIFB2 ----------------------------------------------------------------- */
3173 static const unsigned int scifb2_data_pins[] = {
3174         /* RXD, TXD */
3175         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3176 };
3177 static const unsigned int scifb2_data_mux[] = {
3178         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
3179 };
3180 static const unsigned int scifb2_clk_pins[] = {
3181         /* SCK */
3182         RCAR_GP_PIN(4, 21),
3183 };
3184 static const unsigned int scifb2_clk_mux[] = {
3185         SCIFB2_SCK_MARK,
3186 };
3187 static const unsigned int scifb2_ctrl_pins[] = {
3188         /* RTS, CTS */
3189         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
3190 };
3191 static const unsigned int scifb2_ctrl_mux[] = {
3192         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
3193 };
3194 static const unsigned int scifb2_data_b_pins[] = {
3195         /* RXD, TXD */
3196         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
3197 };
3198 static const unsigned int scifb2_data_b_mux[] = {
3199         SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
3200 };
3201 static const unsigned int scifb2_clk_b_pins[] = {
3202         /* SCK */
3203         RCAR_GP_PIN(0, 31),
3204 };
3205 static const unsigned int scifb2_clk_b_mux[] = {
3206         SCIFB2_SCK_B_MARK,
3207 };
3208 static const unsigned int scifb2_ctrl_b_pins[] = {
3209         /* RTS, CTS */
3210         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
3211 };
3212 static const unsigned int scifb2_ctrl_b_mux[] = {
3213         SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
3214 };
3215 static const unsigned int scifb2_data_c_pins[] = {
3216         /* RXD, TXD */
3217         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3218 };
3219 static const unsigned int scifb2_data_c_mux[] = {
3220         SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
3221 };
3222 /* - SCIF Clock ------------------------------------------------------------- */
3223 static const unsigned int scif_clk_pins[] = {
3224         /* SCIF_CLK */
3225         RCAR_GP_PIN(4, 26),
3226 };
3227 static const unsigned int scif_clk_mux[] = {
3228         SCIF_CLK_MARK,
3229 };
3230 static const unsigned int scif_clk_b_pins[] = {
3231         /* SCIF_CLK */
3232         RCAR_GP_PIN(5, 4),
3233 };
3234 static const unsigned int scif_clk_b_mux[] = {
3235         SCIF_CLK_B_MARK,
3236 };
3237 /* - SDHI0 ------------------------------------------------------------------ */
3238 static const unsigned int sdhi0_data1_pins[] = {
3239         /* D0 */
3240         RCAR_GP_PIN(3, 2),
3241 };
3242 static const unsigned int sdhi0_data1_mux[] = {
3243         SD0_DAT0_MARK,
3244 };
3245 static const unsigned int sdhi0_data4_pins[] = {
3246         /* D[0:3] */
3247         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
3248 };
3249 static const unsigned int sdhi0_data4_mux[] = {
3250         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
3251 };
3252 static const unsigned int sdhi0_ctrl_pins[] = {
3253         /* CLK, CMD */
3254         RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
3255 };
3256 static const unsigned int sdhi0_ctrl_mux[] = {
3257         SD0_CLK_MARK, SD0_CMD_MARK,
3258 };
3259 static const unsigned int sdhi0_cd_pins[] = {
3260         /* CD */
3261         RCAR_GP_PIN(3, 6),
3262 };
3263 static const unsigned int sdhi0_cd_mux[] = {
3264         SD0_CD_MARK,
3265 };
3266 static const unsigned int sdhi0_wp_pins[] = {
3267         /* WP */
3268         RCAR_GP_PIN(3, 7),
3269 };
3270 static const unsigned int sdhi0_wp_mux[] = {
3271         SD0_WP_MARK,
3272 };
3273 /* - SDHI1 ------------------------------------------------------------------ */
3274 static const unsigned int sdhi1_data1_pins[] = {
3275         /* D0 */
3276         RCAR_GP_PIN(3, 10),
3277 };
3278 static const unsigned int sdhi1_data1_mux[] = {
3279         SD1_DAT0_MARK,
3280 };
3281 static const unsigned int sdhi1_data4_pins[] = {
3282         /* D[0:3] */
3283         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3284 };
3285 static const unsigned int sdhi1_data4_mux[] = {
3286         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
3287 };
3288 static const unsigned int sdhi1_ctrl_pins[] = {
3289         /* CLK, CMD */
3290         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
3291 };
3292 static const unsigned int sdhi1_ctrl_mux[] = {
3293         SD1_CLK_MARK, SD1_CMD_MARK,
3294 };
3295 static const unsigned int sdhi1_cd_pins[] = {
3296         /* CD */
3297         RCAR_GP_PIN(3, 14),
3298 };
3299 static const unsigned int sdhi1_cd_mux[] = {
3300         SD1_CD_MARK,
3301 };
3302 static const unsigned int sdhi1_wp_pins[] = {
3303         /* WP */
3304         RCAR_GP_PIN(3, 15),
3305 };
3306 static const unsigned int sdhi1_wp_mux[] = {
3307         SD1_WP_MARK,
3308 };
3309 /* - SDHI2 ------------------------------------------------------------------ */
3310 static const unsigned int sdhi2_data1_pins[] = {
3311         /* D0 */
3312         RCAR_GP_PIN(3, 18),
3313 };
3314 static const unsigned int sdhi2_data1_mux[] = {
3315         SD2_DAT0_MARK,
3316 };
3317 static const unsigned int sdhi2_data4_pins[] = {
3318         /* D[0:3] */
3319         RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
3320 };
3321 static const unsigned int sdhi2_data4_mux[] = {
3322         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
3323 };
3324 static const unsigned int sdhi2_ctrl_pins[] = {
3325         /* CLK, CMD */
3326         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
3327 };
3328 static const unsigned int sdhi2_ctrl_mux[] = {
3329         SD2_CLK_MARK, SD2_CMD_MARK,
3330 };
3331 static const unsigned int sdhi2_cd_pins[] = {
3332         /* CD */
3333         RCAR_GP_PIN(3, 22),
3334 };
3335 static const unsigned int sdhi2_cd_mux[] = {
3336         SD2_CD_MARK,
3337 };
3338 static const unsigned int sdhi2_wp_pins[] = {
3339         /* WP */
3340         RCAR_GP_PIN(3, 23),
3341 };
3342 static const unsigned int sdhi2_wp_mux[] = {
3343         SD2_WP_MARK,
3344 };
3345 /* - SDHI3 ------------------------------------------------------------------ */
3346 static const unsigned int sdhi3_data1_pins[] = {
3347         /* D0 */
3348         RCAR_GP_PIN(3, 26),
3349 };
3350 static const unsigned int sdhi3_data1_mux[] = {
3351         SD3_DAT0_MARK,
3352 };
3353 static const unsigned int sdhi3_data4_pins[] = {
3354         /* D[0:3] */
3355         RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
3356 };
3357 static const unsigned int sdhi3_data4_mux[] = {
3358         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
3359 };
3360 static const unsigned int sdhi3_ctrl_pins[] = {
3361         /* CLK, CMD */
3362         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
3363 };
3364 static const unsigned int sdhi3_ctrl_mux[] = {
3365         SD3_CLK_MARK, SD3_CMD_MARK,
3366 };
3367 static const unsigned int sdhi3_cd_pins[] = {
3368         /* CD */
3369         RCAR_GP_PIN(3, 30),
3370 };
3371 static const unsigned int sdhi3_cd_mux[] = {
3372         SD3_CD_MARK,
3373 };
3374 static const unsigned int sdhi3_wp_pins[] = {
3375         /* WP */
3376         RCAR_GP_PIN(3, 31),
3377 };
3378 static const unsigned int sdhi3_wp_mux[] = {
3379         SD3_WP_MARK,
3380 };
3381 /* - SSI -------------------------------------------------------------------- */
3382 static const unsigned int ssi0_data_pins[] = {
3383         /* SDATA0 */
3384         RCAR_GP_PIN(4, 5),
3385 };
3386 static const unsigned int ssi0_data_mux[] = {
3387         SSI_SDATA0_MARK,
3388 };
3389 static const unsigned int ssi0129_ctrl_pins[] = {
3390         /* SCK, WS */
3391         RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3392 };
3393 static const unsigned int ssi0129_ctrl_mux[] = {
3394         SSI_SCK0129_MARK, SSI_WS0129_MARK,
3395 };
3396 static const unsigned int ssi1_data_pins[] = {
3397         /* SDATA1 */
3398         RCAR_GP_PIN(4, 6),
3399 };
3400 static const unsigned int ssi1_data_mux[] = {
3401         SSI_SDATA1_MARK,
3402 };
3403 static const unsigned int ssi1_ctrl_pins[] = {
3404         /* SCK, WS */
3405         RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3406 };
3407 static const unsigned int ssi1_ctrl_mux[] = {
3408         SSI_SCK1_MARK, SSI_WS1_MARK,
3409 };
3410 static const unsigned int ssi2_data_pins[] = {
3411         /* SDATA2 */
3412         RCAR_GP_PIN(4, 7),
3413 };
3414 static const unsigned int ssi2_data_mux[] = {
3415         SSI_SDATA2_MARK,
3416 };
3417 static const unsigned int ssi2_ctrl_pins[] = {
3418         /* SCK, WS */
3419         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3420 };
3421 static const unsigned int ssi2_ctrl_mux[] = {
3422         SSI_SCK2_MARK, SSI_WS2_MARK,
3423 };
3424 static const unsigned int ssi3_data_pins[] = {
3425         /* SDATA3 */
3426         RCAR_GP_PIN(4, 10),
3427 };
3428 static const unsigned int ssi3_data_mux[] = {
3429         SSI_SDATA3_MARK
3430 };
3431 static const unsigned int ssi34_ctrl_pins[] = {
3432         /* SCK, WS */
3433         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3434 };
3435 static const unsigned int ssi34_ctrl_mux[] = {
3436         SSI_SCK34_MARK, SSI_WS34_MARK,
3437 };
3438 static const unsigned int ssi4_data_pins[] = {
3439         /* SDATA4 */
3440         RCAR_GP_PIN(4, 13),
3441 };
3442 static const unsigned int ssi4_data_mux[] = {
3443         SSI_SDATA4_MARK,
3444 };
3445 static const unsigned int ssi4_ctrl_pins[] = {
3446         /* SCK, WS */
3447         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3448 };
3449 static const unsigned int ssi4_ctrl_mux[] = {
3450         SSI_SCK4_MARK, SSI_WS4_MARK,
3451 };
3452 static const unsigned int ssi5_pins[] = {
3453         /* SDATA5, SCK, WS */
3454         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3455 };
3456 static const unsigned int ssi5_mux[] = {
3457         SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3458 };
3459 static const unsigned int ssi5_b_pins[] = {
3460         /* SDATA5, SCK, WS */
3461         RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3462 };
3463 static const unsigned int ssi5_b_mux[] = {
3464         SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3465 };
3466 static const unsigned int ssi5_c_pins[] = {
3467         /* SDATA5, SCK, WS */
3468         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3469 };
3470 static const unsigned int ssi5_c_mux[] = {
3471         SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3472 };
3473 static const unsigned int ssi6_pins[] = {
3474         /* SDATA6, SCK, WS */
3475         RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3476 };
3477 static const unsigned int ssi6_mux[] = {
3478         SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3479 };
3480 static const unsigned int ssi6_b_pins[] = {
3481         /* SDATA6, SCK, WS */
3482         RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3483 };
3484 static const unsigned int ssi6_b_mux[] = {
3485         SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3486 };
3487 static const unsigned int ssi7_data_pins[] = {
3488         /* SDATA7 */
3489         RCAR_GP_PIN(4, 22),
3490 };
3491 static const unsigned int ssi7_data_mux[] = {
3492         SSI_SDATA7_MARK,
3493 };
3494 static const unsigned int ssi7_b_data_pins[] = {
3495         /* SDATA7 */
3496         RCAR_GP_PIN(4, 22),
3497 };
3498 static const unsigned int ssi7_b_data_mux[] = {
3499         SSI_SDATA7_B_MARK,
3500 };
3501 static const unsigned int ssi7_c_data_pins[] = {
3502         /* SDATA7 */
3503         RCAR_GP_PIN(1, 26),
3504 };
3505 static const unsigned int ssi7_c_data_mux[] = {
3506         SSI_SDATA7_C_MARK,
3507 };
3508 static const unsigned int ssi78_ctrl_pins[] = {
3509         /* SCK, WS */
3510         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3511 };
3512 static const unsigned int ssi78_ctrl_mux[] = {
3513         SSI_SCK78_MARK, SSI_WS78_MARK,
3514 };
3515 static const unsigned int ssi78_b_ctrl_pins[] = {
3516         /* SCK, WS */
3517         RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3518 };
3519 static const unsigned int ssi78_b_ctrl_mux[] = {
3520         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3521 };
3522 static const unsigned int ssi78_c_ctrl_pins[] = {
3523         /* SCK, WS */
3524         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3525 };
3526 static const unsigned int ssi78_c_ctrl_mux[] = {
3527         SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3528 };
3529 static const unsigned int ssi8_data_pins[] = {
3530         /* SDATA8 */
3531         RCAR_GP_PIN(4, 23),
3532 };
3533 static const unsigned int ssi8_data_mux[] = {
3534         SSI_SDATA8_MARK,
3535 };
3536 static const unsigned int ssi8_b_data_pins[] = {
3537         /* SDATA8 */
3538         RCAR_GP_PIN(4, 23),
3539 };
3540 static const unsigned int ssi8_b_data_mux[] = {
3541         SSI_SDATA8_B_MARK,
3542 };
3543 static const unsigned int ssi8_c_data_pins[] = {
3544         /* SDATA8 */
3545         RCAR_GP_PIN(1, 27),
3546 };
3547 static const unsigned int ssi8_c_data_mux[] = {
3548         SSI_SDATA8_C_MARK,
3549 };
3550 static const unsigned int ssi9_data_pins[] = {
3551         /* SDATA9 */
3552         RCAR_GP_PIN(4, 24),
3553 };
3554 static const unsigned int ssi9_data_mux[] = {
3555         SSI_SDATA9_MARK,
3556 };
3557 static const unsigned int ssi9_ctrl_pins[] = {
3558         /* SCK, WS */
3559         RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3560 };
3561 static const unsigned int ssi9_ctrl_mux[] = {
3562         SSI_SCK9_MARK, SSI_WS9_MARK,
3563 };
3564 /* - TPU0 ------------------------------------------------------------------- */
3565 static const unsigned int tpu0_to0_pins[] = {
3566         /* TO */
3567         RCAR_GP_PIN(0, 20),
3568 };
3569 static const unsigned int tpu0_to0_mux[] = {
3570         TPU0TO0_MARK,
3571 };
3572 static const unsigned int tpu0_to1_pins[] = {
3573         /* TO */
3574         RCAR_GP_PIN(0, 21),
3575 };
3576 static const unsigned int tpu0_to1_mux[] = {
3577         TPU0TO1_MARK,
3578 };
3579 static const unsigned int tpu0_to2_pins[] = {
3580         /* TO */
3581         RCAR_GP_PIN(0, 22),
3582 };
3583 static const unsigned int tpu0_to2_mux[] = {
3584         TPU0TO2_MARK,
3585 };
3586 static const unsigned int tpu0_to3_pins[] = {
3587         /* TO */
3588         RCAR_GP_PIN(0, 23),
3589 };
3590 static const unsigned int tpu0_to3_mux[] = {
3591         TPU0TO3_MARK,
3592 };
3593 /* - USB0 ------------------------------------------------------------------- */
3594 static const unsigned int usb0_pins[] = {
3595         /* PWEN, OVC/VBUS */
3596         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3597 };
3598 static const unsigned int usb0_mux[] = {
3599         USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
3600 };
3601 static const unsigned int usb0_ovc_vbus_pins[] = {
3602         /* OVC/VBUS */
3603         RCAR_GP_PIN(5, 19),
3604 };
3605 static const unsigned int usb0_ovc_vbus_mux[] = {
3606         USB0_OVC_VBUS_MARK,
3607 };
3608 /* - USB1 ------------------------------------------------------------------- */
3609 static const unsigned int usb1_pins[] = {
3610         /* PWEN, OVC */
3611         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
3612 };
3613 static const unsigned int usb1_mux[] = {
3614         USB1_PWEN_MARK, USB1_OVC_MARK,
3615 };
3616 /* - USB2 ------------------------------------------------------------------- */
3617 static const unsigned int usb2_pins[] = {
3618         /* PWEN, OVC */
3619         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
3620 };
3621 static const unsigned int usb2_mux[] = {
3622         USB2_PWEN_MARK, USB2_OVC_MARK,
3623 };
3624 /* - VIN0 ------------------------------------------------------------------- */
3625 static const union vin_data vin0_data_pins = {
3626         .data24 = {
3627                 /* B */
3628                 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3629                 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3630                 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3631                 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3632                 /* G */
3633                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3634                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3635                 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3636                 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3637                 /* R */
3638                 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3639                 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3640                 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3641                 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3642         },
3643 };
3644 static const union vin_data vin0_data_mux = {
3645         .data24 = {
3646                 /* B */
3647                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3648                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3649                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3650                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3651                 /* G */
3652                 VI0_G0_MARK, VI0_G1_MARK,
3653                 VI0_G2_MARK, VI0_G3_MARK,
3654                 VI0_G4_MARK, VI0_G5_MARK,
3655                 VI0_G6_MARK, VI0_G7_MARK,
3656                 /* R */
3657                 VI0_R0_MARK, VI0_R1_MARK,
3658                 VI0_R2_MARK, VI0_R3_MARK,
3659                 VI0_R4_MARK, VI0_R5_MARK,
3660                 VI0_R6_MARK, VI0_R7_MARK,
3661         },
3662 };
3663 static const unsigned int vin0_data18_pins[] = {
3664         /* B */
3665         RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3666         RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3667         RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3668         /* G */
3669         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3670         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3671         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3672         /* R */
3673         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3674         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3675         RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3676 };
3677 static const unsigned int vin0_data18_mux[] = {
3678         /* B */
3679         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3680         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3681         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3682         /* G */
3683         VI0_G2_MARK, VI0_G3_MARK,
3684         VI0_G4_MARK, VI0_G5_MARK,
3685         VI0_G6_MARK, VI0_G7_MARK,
3686         /* R */
3687         VI0_R2_MARK, VI0_R3_MARK,
3688         VI0_R4_MARK, VI0_R5_MARK,
3689         VI0_R6_MARK, VI0_R7_MARK,
3690 };
3691 static const unsigned int vin0_sync_pins[] = {
3692         RCAR_GP_PIN(0, 12), /* HSYNC */
3693         RCAR_GP_PIN(0, 13), /* VSYNC */
3694 };
3695 static const unsigned int vin0_sync_mux[] = {
3696         VI0_HSYNC_N_MARK,
3697         VI0_VSYNC_N_MARK,
3698 };
3699 static const unsigned int vin0_field_pins[] = {
3700         RCAR_GP_PIN(0, 15),
3701 };
3702 static const unsigned int vin0_field_mux[] = {
3703         VI0_FIELD_MARK,
3704 };
3705 static const unsigned int vin0_clkenb_pins[] = {
3706         RCAR_GP_PIN(0, 14),
3707 };
3708 static const unsigned int vin0_clkenb_mux[] = {
3709         VI0_CLKENB_MARK,
3710 };
3711 static const unsigned int vin0_clk_pins[] = {
3712         RCAR_GP_PIN(2, 0),
3713 };
3714 static const unsigned int vin0_clk_mux[] = {
3715         VI0_CLK_MARK,
3716 };
3717 /* - VIN1 ------------------------------------------------------------------- */
3718 static const union vin_data vin1_data_pins = {
3719         .data24 = {
3720                 /* B */
3721                 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3722                 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3723                 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3724                 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3725                 /* G */
3726                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3727                 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3728                 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3729                 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3730                 /* R */
3731                 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3732                 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3733                 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3734                 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3735         },
3736 };
3737 static const union vin_data vin1_data_mux = {
3738         .data24 = {
3739                 /* B */
3740                 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3741                 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3742                 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3743                 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3744                 /* G */
3745                 VI1_G0_MARK, VI1_G1_MARK,
3746                 VI1_G2_MARK, VI1_G3_MARK,
3747                 VI1_G4_MARK, VI1_G5_MARK,
3748                 VI1_G6_MARK, VI1_G7_MARK,
3749                 /* R */
3750                 VI1_R0_MARK, VI1_R1_MARK,
3751                 VI1_R2_MARK, VI1_R3_MARK,
3752                 VI1_R4_MARK, VI1_R5_MARK,
3753                 VI1_R6_MARK, VI1_R7_MARK,
3754         },
3755 };
3756 static const unsigned int vin1_data18_pins[] = {
3757         /* B */
3758         RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3759         RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3760         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3761         /* G */
3762         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3763         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3764         RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3765         /* R */
3766         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3767         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3768         RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3769 };
3770 static const unsigned int vin1_data18_mux[] = {
3771         /* B */
3772         VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3773         VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3774         VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3775         /* G */
3776         VI1_G2_MARK, VI1_G3_MARK,
3777         VI1_G4_MARK, VI1_G5_MARK,
3778         VI1_G6_MARK, VI1_G7_MARK,
3779         /* R */
3780         VI1_R2_MARK, VI1_R3_MARK,
3781         VI1_R4_MARK, VI1_R5_MARK,
3782         VI1_R6_MARK, VI1_R7_MARK,
3783 };
3784 static const unsigned int vin1_sync_pins[] = {
3785         RCAR_GP_PIN(1, 24), /* HSYNC */
3786         RCAR_GP_PIN(1, 25), /* VSYNC */
3787 };
3788 static const unsigned int vin1_sync_mux[] = {
3789         VI1_HSYNC_N_MARK,
3790         VI1_VSYNC_N_MARK,
3791 };
3792 static const unsigned int vin1_field_pins[] = {
3793         RCAR_GP_PIN(1, 13),
3794 };
3795 static const unsigned int vin1_field_mux[] = {
3796         VI1_FIELD_MARK,
3797 };
3798 static const unsigned int vin1_clkenb_pins[] = {
3799         RCAR_GP_PIN(1, 26),
3800 };
3801 static const unsigned int vin1_clkenb_mux[] = {
3802         VI1_CLKENB_MARK,
3803 };
3804 static const unsigned int vin1_clk_pins[] = {
3805         RCAR_GP_PIN(2, 9),
3806 };
3807 static const unsigned int vin1_clk_mux[] = {
3808         VI1_CLK_MARK,
3809 };
3810 /* - VIN2 ----------------------------------------------------------------- */
3811 static const union vin_data vin2_data_pins = {
3812         .data24 = {
3813                 /* B */
3814                 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3815                 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3816                 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3817                 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3818                 /* G */
3819                 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3820                 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3821                 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3822                 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3823                 /* R */
3824                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3825                 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3826                 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3827                 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3828         },
3829 };
3830 static const union vin_data vin2_data_mux = {
3831         .data24 = {
3832                 /* B */
3833                 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3834                 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3835                 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3836                 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3837                 /* G */
3838                 VI2_G0_MARK, VI2_G1_MARK,
3839                 VI2_G2_MARK, VI2_G3_MARK,
3840                 VI2_G4_MARK, VI2_G5_MARK,
3841                 VI2_G6_MARK, VI2_G7_MARK,
3842                 /* R */
3843                 VI2_R0_MARK, VI2_R1_MARK,
3844                 VI2_R2_MARK, VI2_R3_MARK,
3845                 VI2_R4_MARK, VI2_R5_MARK,
3846                 VI2_R6_MARK, VI2_R7_MARK,
3847         },
3848 };
3849 static const unsigned int vin2_data18_pins[] = {
3850         /* B */
3851         RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3852         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3853         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3854         /* G */
3855         RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3856         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3857         RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3858         /* R */
3859         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3860         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3861         RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3862 };
3863 static const unsigned int vin2_data18_mux[] = {
3864         /* B */
3865         VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3866         VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3867         VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3868         /* G */
3869         VI2_G2_MARK, VI2_G3_MARK,
3870         VI2_G4_MARK, VI2_G5_MARK,
3871         VI2_G6_MARK, VI2_G7_MARK,
3872         /* R */
3873         VI2_R2_MARK, VI2_R3_MARK,
3874         VI2_R4_MARK, VI2_R5_MARK,
3875         VI2_R6_MARK, VI2_R7_MARK,
3876 };
3877 static const unsigned int vin2_sync_pins[] = {
3878         RCAR_GP_PIN(1, 16), /* HSYNC */
3879         RCAR_GP_PIN(1, 21), /* VSYNC */
3880 };
3881 static const unsigned int vin2_sync_mux[] = {
3882         VI2_HSYNC_N_MARK,
3883         VI2_VSYNC_N_MARK,
3884 };
3885 static const unsigned int vin2_field_pins[] = {
3886         RCAR_GP_PIN(1, 9),
3887 };
3888 static const unsigned int vin2_field_mux[] = {
3889         VI2_FIELD_MARK,
3890 };
3891 static const unsigned int vin2_clkenb_pins[] = {
3892         RCAR_GP_PIN(1, 8),
3893 };
3894 static const unsigned int vin2_clkenb_mux[] = {
3895         VI2_CLKENB_MARK,
3896 };
3897 static const unsigned int vin2_clk_pins[] = {
3898         RCAR_GP_PIN(1, 11),
3899 };
3900 static const unsigned int vin2_clk_mux[] = {
3901         VI2_CLK_MARK,
3902 };
3903 /* - VIN3 ----------------------------------------------------------------- */
3904 static const unsigned int vin3_data8_pins[] = {
3905         RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3906         RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3907         RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3908         RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3909 };
3910 static const unsigned int vin3_data8_mux[] = {
3911         VI3_DATA0_MARK, VI3_DATA1_MARK,
3912         VI3_DATA2_MARK, VI3_DATA3_MARK,
3913         VI3_DATA4_MARK, VI3_DATA5_MARK,
3914         VI3_DATA6_MARK, VI3_DATA7_MARK,
3915 };
3916 static const unsigned int vin3_sync_pins[] = {
3917         RCAR_GP_PIN(1, 16), /* HSYNC */
3918         RCAR_GP_PIN(1, 17), /* VSYNC */
3919 };
3920 static const unsigned int vin3_sync_mux[] = {
3921         VI3_HSYNC_N_MARK,
3922         VI3_VSYNC_N_MARK,
3923 };
3924 static const unsigned int vin3_field_pins[] = {
3925         RCAR_GP_PIN(1, 15),
3926 };
3927 static const unsigned int vin3_field_mux[] = {
3928         VI3_FIELD_MARK,
3929 };
3930 static const unsigned int vin3_clkenb_pins[] = {
3931         RCAR_GP_PIN(1, 14),
3932 };
3933 static const unsigned int vin3_clkenb_mux[] = {
3934         VI3_CLKENB_MARK,
3935 };
3936 static const unsigned int vin3_clk_pins[] = {
3937         RCAR_GP_PIN(1, 23),
3938 };
3939 static const unsigned int vin3_clk_mux[] = {
3940         VI3_CLK_MARK,
3941 };
3942
3943 static const struct sh_pfc_pin_group pinmux_groups[] = {
3944         SH_PFC_PIN_GROUP(audio_clk_a),
3945         SH_PFC_PIN_GROUP(audio_clk_b),
3946         SH_PFC_PIN_GROUP(audio_clk_c),
3947         SH_PFC_PIN_GROUP(audio_clkout),
3948         SH_PFC_PIN_GROUP(audio_clkout_b),
3949         SH_PFC_PIN_GROUP(audio_clkout_c),
3950         SH_PFC_PIN_GROUP(audio_clkout_d),
3951         SH_PFC_PIN_GROUP(avb_link),
3952         SH_PFC_PIN_GROUP(avb_magic),
3953         SH_PFC_PIN_GROUP(avb_phy_int),
3954         SH_PFC_PIN_GROUP(avb_mdio),
3955         SH_PFC_PIN_GROUP(avb_mii),
3956         SH_PFC_PIN_GROUP(avb_gmii),
3957         SH_PFC_PIN_GROUP(du_rgb666),
3958         SH_PFC_PIN_GROUP(du_rgb888),
3959         SH_PFC_PIN_GROUP(du_clk_out_0),
3960         SH_PFC_PIN_GROUP(du_clk_out_1),
3961         SH_PFC_PIN_GROUP(du_sync_0),
3962         SH_PFC_PIN_GROUP(du_sync_1),
3963         SH_PFC_PIN_GROUP(du_cde),
3964         SH_PFC_PIN_GROUP(du0_clk_in),
3965         SH_PFC_PIN_GROUP(du1_clk_in),
3966         SH_PFC_PIN_GROUP(du2_clk_in),
3967         SH_PFC_PIN_GROUP(eth_link),
3968         SH_PFC_PIN_GROUP(eth_magic),
3969         SH_PFC_PIN_GROUP(eth_mdio),
3970         SH_PFC_PIN_GROUP(eth_rmii),
3971         SH_PFC_PIN_GROUP(hscif0_data),
3972         SH_PFC_PIN_GROUP(hscif0_clk),
3973         SH_PFC_PIN_GROUP(hscif0_ctrl),
3974         SH_PFC_PIN_GROUP(hscif0_data_b),
3975         SH_PFC_PIN_GROUP(hscif0_ctrl_b),
3976         SH_PFC_PIN_GROUP(hscif0_data_c),
3977         SH_PFC_PIN_GROUP(hscif0_ctrl_c),
3978         SH_PFC_PIN_GROUP(hscif0_data_d),
3979         SH_PFC_PIN_GROUP(hscif0_ctrl_d),
3980         SH_PFC_PIN_GROUP(hscif0_data_e),
3981         SH_PFC_PIN_GROUP(hscif0_ctrl_e),
3982         SH_PFC_PIN_GROUP(hscif0_data_f),
3983         SH_PFC_PIN_GROUP(hscif0_ctrl_f),
3984         SH_PFC_PIN_GROUP(hscif1_data),
3985         SH_PFC_PIN_GROUP(hscif1_clk),
3986         SH_PFC_PIN_GROUP(hscif1_ctrl),
3987         SH_PFC_PIN_GROUP(hscif1_data_b),
3988         SH_PFC_PIN_GROUP(hscif1_clk_b),
3989         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3990         SH_PFC_PIN_GROUP(i2c0),
3991         SH_PFC_PIN_GROUP(i2c1),
3992         SH_PFC_PIN_GROUP(i2c1_b),
3993         SH_PFC_PIN_GROUP(i2c1_c),
3994         SH_PFC_PIN_GROUP(i2c2),
3995         SH_PFC_PIN_GROUP(i2c2_b),
3996         SH_PFC_PIN_GROUP(i2c2_c),
3997         SH_PFC_PIN_GROUP(i2c2_d),
3998         SH_PFC_PIN_GROUP(i2c2_e),
3999         SH_PFC_PIN_GROUP(i2c3),
4000         SH_PFC_PIN_GROUP(iic0),
4001         SH_PFC_PIN_GROUP(iic1),
4002         SH_PFC_PIN_GROUP(iic1_b),
4003         SH_PFC_PIN_GROUP(iic1_c),
4004         SH_PFC_PIN_GROUP(iic2),
4005         SH_PFC_PIN_GROUP(iic2_b),
4006         SH_PFC_PIN_GROUP(iic2_c),
4007         SH_PFC_PIN_GROUP(iic2_d),
4008         SH_PFC_PIN_GROUP(iic2_e),
4009         SH_PFC_PIN_GROUP(iic3),
4010         SH_PFC_PIN_GROUP(intc_irq0),
4011         SH_PFC_PIN_GROUP(intc_irq1),
4012         SH_PFC_PIN_GROUP(intc_irq2),
4013         SH_PFC_PIN_GROUP(intc_irq3),
4014         SH_PFC_PIN_GROUP(mlb_3pin),
4015         SH_PFC_PIN_GROUP(mmc0_data1),
4016         SH_PFC_PIN_GROUP(mmc0_data4),
4017         SH_PFC_PIN_GROUP(mmc0_data8),
4018         SH_PFC_PIN_GROUP(mmc0_ctrl),
4019         SH_PFC_PIN_GROUP(mmc1_data1),
4020         SH_PFC_PIN_GROUP(mmc1_data4),
4021         SH_PFC_PIN_GROUP(mmc1_data8),
4022         SH_PFC_PIN_GROUP(mmc1_ctrl),
4023         SH_PFC_PIN_GROUP(msiof0_clk),
4024         SH_PFC_PIN_GROUP(msiof0_sync),
4025         SH_PFC_PIN_GROUP(msiof0_ss1),
4026         SH_PFC_PIN_GROUP(msiof0_ss2),
4027         SH_PFC_PIN_GROUP(msiof0_rx),
4028         SH_PFC_PIN_GROUP(msiof0_tx),
4029         SH_PFC_PIN_GROUP(msiof0_clk_b),
4030         SH_PFC_PIN_GROUP(msiof0_ss1_b),
4031         SH_PFC_PIN_GROUP(msiof0_ss2_b),
4032         SH_PFC_PIN_GROUP(msiof0_rx_b),
4033         SH_PFC_PIN_GROUP(msiof0_tx_b),
4034         SH_PFC_PIN_GROUP(msiof1_clk),
4035         SH_PFC_PIN_GROUP(msiof1_sync),
4036         SH_PFC_PIN_GROUP(msiof1_ss1),
4037         SH_PFC_PIN_GROUP(msiof1_ss2),
4038         SH_PFC_PIN_GROUP(msiof1_rx),
4039         SH_PFC_PIN_GROUP(msiof1_tx),
4040         SH_PFC_PIN_GROUP(msiof1_clk_b),
4041         SH_PFC_PIN_GROUP(msiof1_ss1_b),
4042         SH_PFC_PIN_GROUP(msiof1_ss2_b),
4043         SH_PFC_PIN_GROUP(msiof1_rx_b),
4044         SH_PFC_PIN_GROUP(msiof1_tx_b),
4045         SH_PFC_PIN_GROUP(msiof2_clk),
4046         SH_PFC_PIN_GROUP(msiof2_sync),
4047         SH_PFC_PIN_GROUP(msiof2_ss1),
4048         SH_PFC_PIN_GROUP(msiof2_ss2),
4049         SH_PFC_PIN_GROUP(msiof2_rx),
4050         SH_PFC_PIN_GROUP(msiof2_tx),
4051         SH_PFC_PIN_GROUP(msiof3_clk),
4052         SH_PFC_PIN_GROUP(msiof3_sync),
4053         SH_PFC_PIN_GROUP(msiof3_ss1),
4054         SH_PFC_PIN_GROUP(msiof3_ss2),
4055         SH_PFC_PIN_GROUP(msiof3_rx),
4056         SH_PFC_PIN_GROUP(msiof3_tx),
4057         SH_PFC_PIN_GROUP(msiof3_clk_b),
4058         SH_PFC_PIN_GROUP(msiof3_sync_b),
4059         SH_PFC_PIN_GROUP(msiof3_rx_b),
4060         SH_PFC_PIN_GROUP(msiof3_tx_b),
4061         SH_PFC_PIN_GROUP(pwm0),
4062         SH_PFC_PIN_GROUP(pwm0_b),
4063         SH_PFC_PIN_GROUP(pwm1),
4064         SH_PFC_PIN_GROUP(pwm1_b),
4065         SH_PFC_PIN_GROUP(pwm2),
4066         SH_PFC_PIN_GROUP(pwm3),
4067         SH_PFC_PIN_GROUP(pwm4),
4068         SH_PFC_PIN_GROUP(pwm5),
4069         SH_PFC_PIN_GROUP(pwm6),
4070         SH_PFC_PIN_GROUP(qspi_ctrl),
4071         SH_PFC_PIN_GROUP(qspi_data2),
4072         SH_PFC_PIN_GROUP(qspi_data4),
4073         SH_PFC_PIN_GROUP(scif0_data),
4074         SH_PFC_PIN_GROUP(scif0_clk),
4075         SH_PFC_PIN_GROUP(scif0_ctrl),
4076         SH_PFC_PIN_GROUP(scif0_data_b),
4077         SH_PFC_PIN_GROUP(scif1_data),
4078         SH_PFC_PIN_GROUP(scif1_clk),
4079         SH_PFC_PIN_GROUP(scif1_ctrl),
4080         SH_PFC_PIN_GROUP(scif1_data_b),
4081         SH_PFC_PIN_GROUP(scif1_data_c),
4082         SH_PFC_PIN_GROUP(scif1_data_d),
4083         SH_PFC_PIN_GROUP(scif1_clk_d),
4084         SH_PFC_PIN_GROUP(scif1_data_e),
4085         SH_PFC_PIN_GROUP(scif1_clk_e),
4086         SH_PFC_PIN_GROUP(scif2_data),
4087         SH_PFC_PIN_GROUP(scif2_clk),
4088         SH_PFC_PIN_GROUP(scif2_data_b),
4089         SH_PFC_PIN_GROUP(scifa0_data),
4090         SH_PFC_PIN_GROUP(scifa0_clk),
4091         SH_PFC_PIN_GROUP(scifa0_ctrl),
4092         SH_PFC_PIN_GROUP(scifa0_data_b),
4093         SH_PFC_PIN_GROUP(scifa0_clk_b),
4094         SH_PFC_PIN_GROUP(scifa0_ctrl_b),
4095         SH_PFC_PIN_GROUP(scifa1_data),
4096         SH_PFC_PIN_GROUP(scifa1_clk),
4097         SH_PFC_PIN_GROUP(scifa1_ctrl),
4098         SH_PFC_PIN_GROUP(scifa1_data_b),
4099         SH_PFC_PIN_GROUP(scifa1_clk_b),
4100         SH_PFC_PIN_GROUP(scifa1_ctrl_b),
4101         SH_PFC_PIN_GROUP(scifa1_data_c),
4102         SH_PFC_PIN_GROUP(scifa1_clk_c),
4103         SH_PFC_PIN_GROUP(scifa1_ctrl_c),
4104         SH_PFC_PIN_GROUP(scifa1_data_d),
4105         SH_PFC_PIN_GROUP(scifa1_clk_d),
4106         SH_PFC_PIN_GROUP(scifa1_ctrl_d),
4107         SH_PFC_PIN_GROUP(scifa2_data),
4108         SH_PFC_PIN_GROUP(scifa2_clk),
4109         SH_PFC_PIN_GROUP(scifa2_ctrl),
4110         SH_PFC_PIN_GROUP(scifa2_data_b),
4111         SH_PFC_PIN_GROUP(scifa2_data_c),
4112         SH_PFC_PIN_GROUP(scifa2_clk_c),
4113         SH_PFC_PIN_GROUP(scifb0_data),
4114         SH_PFC_PIN_GROUP(scifb0_clk),
4115         SH_PFC_PIN_GROUP(scifb0_ctrl),
4116         SH_PFC_PIN_GROUP(scifb0_data_b),
4117         SH_PFC_PIN_GROUP(scifb0_clk_b),
4118         SH_PFC_PIN_GROUP(scifb0_ctrl_b),
4119         SH_PFC_PIN_GROUP(scifb0_data_c),
4120         SH_PFC_PIN_GROUP(scifb1_data),
4121         SH_PFC_PIN_GROUP(scifb1_clk),
4122         SH_PFC_PIN_GROUP(scifb1_ctrl),
4123         SH_PFC_PIN_GROUP(scifb1_data_b),
4124         SH_PFC_PIN_GROUP(scifb1_clk_b),
4125         SH_PFC_PIN_GROUP(scifb1_ctrl_b),
4126         SH_PFC_PIN_GROUP(scifb1_data_c),
4127         SH_PFC_PIN_GROUP(scifb1_data_d),
4128         SH_PFC_PIN_GROUP(scifb1_data_e),
4129         SH_PFC_PIN_GROUP(scifb1_clk_e),
4130         SH_PFC_PIN_GROUP(scifb1_data_f),
4131         SH_PFC_PIN_GROUP(scifb1_data_g),
4132         SH_PFC_PIN_GROUP(scifb1_clk_g),
4133         SH_PFC_PIN_GROUP(scifb2_data),
4134         SH_PFC_PIN_GROUP(scifb2_clk),
4135         SH_PFC_PIN_GROUP(scifb2_ctrl),
4136         SH_PFC_PIN_GROUP(scifb2_data_b),
4137         SH_PFC_PIN_GROUP(scifb2_clk_b),
4138         SH_PFC_PIN_GROUP(scifb2_ctrl_b),
4139         SH_PFC_PIN_GROUP(scifb2_data_c),
4140         SH_PFC_PIN_GROUP(scif_clk),
4141         SH_PFC_PIN_GROUP(scif_clk_b),
4142         SH_PFC_PIN_GROUP(sdhi0_data1),
4143         SH_PFC_PIN_GROUP(sdhi0_data4),
4144         SH_PFC_PIN_GROUP(sdhi0_ctrl),
4145         SH_PFC_PIN_GROUP(sdhi0_cd),
4146         SH_PFC_PIN_GROUP(sdhi0_wp),
4147         SH_PFC_PIN_GROUP(sdhi1_data1),
4148         SH_PFC_PIN_GROUP(sdhi1_data4),
4149         SH_PFC_PIN_GROUP(sdhi1_ctrl),
4150         SH_PFC_PIN_GROUP(sdhi1_cd),
4151         SH_PFC_PIN_GROUP(sdhi1_wp),
4152         SH_PFC_PIN_GROUP(sdhi2_data1),
4153         SH_PFC_PIN_GROUP(sdhi2_data4),
4154         SH_PFC_PIN_GROUP(sdhi2_ctrl),
4155         SH_PFC_PIN_GROUP(sdhi2_cd),
4156         SH_PFC_PIN_GROUP(sdhi2_wp),
4157         SH_PFC_PIN_GROUP(sdhi3_data1),
4158         SH_PFC_PIN_GROUP(sdhi3_data4),
4159         SH_PFC_PIN_GROUP(sdhi3_ctrl),
4160         SH_PFC_PIN_GROUP(sdhi3_cd),
4161         SH_PFC_PIN_GROUP(sdhi3_wp),
4162         SH_PFC_PIN_GROUP(ssi0_data),
4163         SH_PFC_PIN_GROUP(ssi0129_ctrl),
4164         SH_PFC_PIN_GROUP(ssi1_data),
4165         SH_PFC_PIN_GROUP(ssi1_ctrl),
4166         SH_PFC_PIN_GROUP(ssi2_data),
4167         SH_PFC_PIN_GROUP(ssi2_ctrl),
4168         SH_PFC_PIN_GROUP(ssi3_data),
4169         SH_PFC_PIN_GROUP(ssi34_ctrl),
4170         SH_PFC_PIN_GROUP(ssi4_data),
4171         SH_PFC_PIN_GROUP(ssi4_ctrl),
4172         SH_PFC_PIN_GROUP(ssi5),
4173         SH_PFC_PIN_GROUP(ssi5_b),
4174         SH_PFC_PIN_GROUP(ssi5_c),
4175         SH_PFC_PIN_GROUP(ssi6),
4176         SH_PFC_PIN_GROUP(ssi6_b),
4177         SH_PFC_PIN_GROUP(ssi7_data),
4178         SH_PFC_PIN_GROUP(ssi7_b_data),
4179         SH_PFC_PIN_GROUP(ssi7_c_data),
4180         SH_PFC_PIN_GROUP(ssi78_ctrl),
4181         SH_PFC_PIN_GROUP(ssi78_b_ctrl),
4182         SH_PFC_PIN_GROUP(ssi78_c_ctrl),
4183         SH_PFC_PIN_GROUP(ssi8_data),
4184         SH_PFC_PIN_GROUP(ssi8_b_data),
4185         SH_PFC_PIN_GROUP(ssi8_c_data),
4186         SH_PFC_PIN_GROUP(ssi9_data),
4187         SH_PFC_PIN_GROUP(ssi9_ctrl),
4188         SH_PFC_PIN_GROUP(tpu0_to0),
4189         SH_PFC_PIN_GROUP(tpu0_to1),
4190         SH_PFC_PIN_GROUP(tpu0_to2),
4191         SH_PFC_PIN_GROUP(tpu0_to3),
4192         SH_PFC_PIN_GROUP(usb0),
4193         SH_PFC_PIN_GROUP(usb0_ovc_vbus),
4194         SH_PFC_PIN_GROUP(usb1),
4195         SH_PFC_PIN_GROUP(usb2),
4196         VIN_DATA_PIN_GROUP(vin0_data, 24),
4197         VIN_DATA_PIN_GROUP(vin0_data, 20),
4198         SH_PFC_PIN_GROUP(vin0_data18),
4199         VIN_DATA_PIN_GROUP(vin0_data, 16),
4200         VIN_DATA_PIN_GROUP(vin0_data, 12),
4201         VIN_DATA_PIN_GROUP(vin0_data, 10),
4202         VIN_DATA_PIN_GROUP(vin0_data, 8),
4203         VIN_DATA_PIN_GROUP(vin0_data, 4),
4204         SH_PFC_PIN_GROUP(vin0_sync),
4205         SH_PFC_PIN_GROUP(vin0_field),
4206         SH_PFC_PIN_GROUP(vin0_clkenb),
4207         SH_PFC_PIN_GROUP(vin0_clk),
4208         VIN_DATA_PIN_GROUP(vin1_data, 24),
4209         VIN_DATA_PIN_GROUP(vin1_data, 20),
4210         SH_PFC_PIN_GROUP(vin1_data18),
4211         VIN_DATA_PIN_GROUP(vin1_data, 16),
4212         VIN_DATA_PIN_GROUP(vin1_data, 12),
4213         VIN_DATA_PIN_GROUP(vin1_data, 10),
4214         VIN_DATA_PIN_GROUP(vin1_data, 8),
4215         VIN_DATA_PIN_GROUP(vin1_data, 4),
4216         SH_PFC_PIN_GROUP(vin1_sync),
4217         SH_PFC_PIN_GROUP(vin1_field),
4218         SH_PFC_PIN_GROUP(vin1_clkenb),
4219         SH_PFC_PIN_GROUP(vin1_clk),
4220         VIN_DATA_PIN_GROUP(vin2_data, 24),
4221         SH_PFC_PIN_GROUP(vin2_data18),
4222         VIN_DATA_PIN_GROUP(vin2_data, 16),
4223         VIN_DATA_PIN_GROUP(vin2_data, 8),
4224         VIN_DATA_PIN_GROUP(vin2_data, 4),
4225         SH_PFC_PIN_GROUP(vin2_sync),
4226         SH_PFC_PIN_GROUP(vin2_field),
4227         SH_PFC_PIN_GROUP(vin2_clkenb),
4228         SH_PFC_PIN_GROUP(vin2_clk),
4229         SH_PFC_PIN_GROUP(vin3_data8),
4230         SH_PFC_PIN_GROUP(vin3_sync),
4231         SH_PFC_PIN_GROUP(vin3_field),
4232         SH_PFC_PIN_GROUP(vin3_clkenb),
4233         SH_PFC_PIN_GROUP(vin3_clk),
4234 };
4235
4236 static const char * const audio_clk_groups[] = {
4237         "audio_clk_a",
4238         "audio_clk_b",
4239         "audio_clk_c",
4240         "audio_clkout",
4241         "audio_clkout_b",
4242         "audio_clkout_c",
4243         "audio_clkout_d",
4244 };
4245
4246 static const char * const avb_groups[] = {
4247         "avb_link",
4248         "avb_magic",
4249         "avb_phy_int",
4250         "avb_mdio",
4251         "avb_mii",
4252         "avb_gmii",
4253 };
4254
4255 static const char * const du_groups[] = {
4256         "du_rgb666",
4257         "du_rgb888",
4258         "du_clk_out_0",
4259         "du_clk_out_1",
4260         "du_sync_0",
4261         "du_sync_1",
4262         "du_cde",
4263 };
4264
4265 static const char * const du0_groups[] = {
4266         "du0_clk_in",
4267 };
4268
4269 static const char * const du1_groups[] = {
4270         "du1_clk_in",
4271 };
4272
4273 static const char * const du2_groups[] = {
4274         "du2_clk_in",
4275 };
4276
4277 static const char * const eth_groups[] = {
4278         "eth_link",
4279         "eth_magic",
4280         "eth_mdio",
4281         "eth_rmii",
4282 };
4283
4284 static const char * const hscif0_groups[] = {
4285         "hscif0_data",
4286         "hscif0_clk",
4287         "hscif0_ctrl",
4288         "hscif0_data_b",
4289         "hscif0_ctrl_b",
4290         "hscif0_data_c",
4291         "hscif0_ctrl_c",
4292         "hscif0_data_d",
4293         "hscif0_ctrl_d",
4294         "hscif0_data_e",
4295         "hscif0_ctrl_e",
4296         "hscif0_data_f",
4297         "hscif0_ctrl_f",
4298 };
4299
4300 static const char * const hscif1_groups[] = {
4301         "hscif1_data",
4302         "hscif1_clk",
4303         "hscif1_ctrl",
4304         "hscif1_data_b",
4305         "hscif1_clk_b",
4306         "hscif1_ctrl_b",
4307 };
4308
4309 static const char * const i2c0_groups[] = {
4310         "i2c0",
4311 };
4312
4313 static const char * const i2c1_groups[] = {
4314         "i2c1",
4315         "i2c1_b",
4316         "i2c1_c",
4317 };
4318
4319 static const char * const i2c2_groups[] = {
4320         "i2c2",
4321         "i2c2_b",
4322         "i2c2_c",
4323         "i2c2_d",
4324         "i2c2_e",
4325 };
4326
4327 static const char * const i2c3_groups[] = {
4328         "i2c3",
4329 };
4330
4331 static const char * const iic0_groups[] = {
4332         "iic0",
4333 };
4334
4335 static const char * const iic1_groups[] = {
4336         "iic1",
4337         "iic1_b",
4338         "iic1_c",
4339 };
4340
4341 static const char * const iic2_groups[] = {
4342         "iic2",
4343         "iic2_b",
4344         "iic2_c",
4345         "iic2_d",
4346         "iic2_e",
4347 };
4348
4349 static const char * const iic3_groups[] = {
4350         "iic3",
4351 };
4352
4353 static const char * const intc_groups[] = {
4354         "intc_irq0",
4355         "intc_irq1",
4356         "intc_irq2",
4357         "intc_irq3",
4358 };
4359
4360 static const char * const mlb_groups[] = {
4361         "mlb_3pin",
4362 };
4363
4364 static const char * const mmc0_groups[] = {
4365         "mmc0_data1",
4366         "mmc0_data4",
4367         "mmc0_data8",
4368         "mmc0_ctrl",
4369 };
4370
4371 static const char * const mmc1_groups[] = {
4372         "mmc1_data1",
4373         "mmc1_data4",
4374         "mmc1_data8",
4375         "mmc1_ctrl",
4376 };
4377
4378 static const char * const msiof0_groups[] = {
4379         "msiof0_clk",
4380         "msiof0_sync",
4381         "msiof0_ss1",
4382         "msiof0_ss2",
4383         "msiof0_rx",
4384         "msiof0_tx",
4385         "msiof0_clk_b",
4386         "msiof0_ss1_b",
4387         "msiof0_ss2_b",
4388         "msiof0_rx_b",
4389         "msiof0_tx_b",
4390 };
4391
4392 static const char * const msiof1_groups[] = {
4393         "msiof1_clk",
4394         "msiof1_sync",
4395         "msiof1_ss1",
4396         "msiof1_ss2",
4397         "msiof1_rx",
4398         "msiof1_tx",
4399         "msiof1_clk_b",
4400         "msiof1_ss1_b",
4401         "msiof1_ss2_b",
4402         "msiof1_rx_b",
4403         "msiof1_tx_b",
4404 };
4405
4406 static const char * const msiof2_groups[] = {
4407         "msiof2_clk",
4408         "msiof2_sync",
4409         "msiof2_ss1",
4410         "msiof2_ss2",
4411         "msiof2_rx",
4412         "msiof2_tx",
4413 };
4414
4415 static const char * const msiof3_groups[] = {
4416         "msiof3_clk",
4417         "msiof3_sync",
4418         "msiof3_ss1",
4419         "msiof3_ss2",
4420         "msiof3_rx",
4421         "msiof3_tx",
4422         "msiof3_clk_b",
4423         "msiof3_sync_b",
4424         "msiof3_rx_b",
4425         "msiof3_tx_b",
4426 };
4427
4428 static const char * const pwm0_groups[] = {
4429         "pwm0",
4430         "pwm0_b",
4431 };
4432
4433 static const char * const pwm1_groups[] = {
4434         "pwm1",
4435         "pwm1_b",
4436 };
4437
4438 static const char * const pwm2_groups[] = {
4439         "pwm2",
4440 };
4441
4442 static const char * const pwm3_groups[] = {
4443         "pwm3",
4444 };
4445
4446 static const char * const pwm4_groups[] = {
4447         "pwm4",
4448 };
4449
4450 static const char * const pwm5_groups[] = {
4451         "pwm5",
4452 };
4453
4454 static const char * const pwm6_groups[] = {
4455         "pwm6",
4456 };
4457
4458 static const char * const qspi_groups[] = {
4459         "qspi_ctrl",
4460         "qspi_data2",
4461         "qspi_data4",
4462 };
4463
4464 static const char * const scif0_groups[] = {
4465         "scif0_data",
4466         "scif0_clk",
4467         "scif0_ctrl",
4468         "scif0_data_b",
4469 };
4470
4471 static const char * const scif1_groups[] = {
4472         "scif1_data",
4473         "scif1_clk",
4474         "scif1_ctrl",
4475         "scif1_data_b",
4476         "scif1_data_c",
4477         "scif1_data_d",
4478         "scif1_clk_d",
4479         "scif1_data_e",
4480         "scif1_clk_e",
4481 };
4482
4483 static const char * const scif2_groups[] = {
4484         "scif2_data",
4485         "scif2_clk",
4486         "scif2_data_b",
4487 };
4488
4489 static const char * const scifa0_groups[] = {
4490         "scifa0_data",
4491         "scifa0_clk",
4492         "scifa0_ctrl",
4493         "scifa0_data_b",
4494         "scifa0_clk_b",
4495         "scifa0_ctrl_b",
4496 };
4497
4498 static const char * const scifa1_groups[] = {
4499         "scifa1_data",
4500         "scifa1_clk",
4501         "scifa1_ctrl",
4502         "scifa1_data_b",
4503         "scifa1_clk_b",
4504         "scifa1_ctrl_b",
4505         "scifa1_data_c",
4506         "scifa1_clk_c",
4507         "scifa1_ctrl_c",
4508         "scifa1_data_d",
4509         "scifa1_clk_d",
4510         "scifa1_ctrl_d",
4511 };
4512
4513 static const char * const scifa2_groups[] = {
4514         "scifa2_data",
4515         "scifa2_clk",
4516         "scifa2_ctrl",
4517         "scifa2_data_b",
4518         "scifa2_data_c",
4519         "scifa2_clk_c",
4520 };
4521
4522 static const char * const scifb0_groups[] = {
4523         "scifb0_data",
4524         "scifb0_clk",
4525         "scifb0_ctrl",
4526         "scifb0_data_b",
4527         "scifb0_clk_b",
4528         "scifb0_ctrl_b",
4529         "scifb0_data_c",
4530 };
4531
4532 static const char * const scifb1_groups[] = {
4533         "scifb1_data",
4534         "scifb1_clk",
4535         "scifb1_ctrl",
4536         "scifb1_data_b",
4537         "scifb1_clk_b",
4538         "scifb1_ctrl_b",
4539         "scifb1_data_c",
4540         "scifb1_data_d",
4541         "scifb1_data_e",
4542         "scifb1_clk_e",
4543         "scifb1_data_f",
4544         "scifb1_data_g",
4545         "scifb1_clk_g",
4546 };
4547
4548 static const char * const scifb2_groups[] = {
4549         "scifb2_data",
4550         "scifb2_clk",
4551         "scifb2_ctrl",
4552         "scifb2_data_b",
4553         "scifb2_clk_b",
4554         "scifb2_ctrl_b",
4555         "scifb2_data_c",
4556 };
4557
4558 static const char * const scif_clk_groups[] = {
4559         "scif_clk",
4560         "scif_clk_b",
4561 };
4562
4563 static const char * const sdhi0_groups[] = {
4564         "sdhi0_data1",
4565         "sdhi0_data4",
4566         "sdhi0_ctrl",
4567         "sdhi0_cd",
4568         "sdhi0_wp",
4569 };
4570
4571 static const char * const sdhi1_groups[] = {
4572         "sdhi1_data1",
4573         "sdhi1_data4",
4574         "sdhi1_ctrl",
4575         "sdhi1_cd",
4576         "sdhi1_wp",
4577 };
4578
4579 static const char * const sdhi2_groups[] = {
4580         "sdhi2_data1",
4581         "sdhi2_data4",
4582         "sdhi2_ctrl",
4583         "sdhi2_cd",
4584         "sdhi2_wp",
4585 };
4586
4587 static const char * const sdhi3_groups[] = {
4588         "sdhi3_data1",
4589         "sdhi3_data4",
4590         "sdhi3_ctrl",
4591         "sdhi3_cd",
4592         "sdhi3_wp",
4593 };
4594
4595 static const char * const ssi_groups[] = {
4596         "ssi0_data",
4597         "ssi0129_ctrl",
4598         "ssi1_data",
4599         "ssi1_ctrl",
4600         "ssi2_data",
4601         "ssi2_ctrl",
4602         "ssi3_data",
4603         "ssi34_ctrl",
4604         "ssi4_data",
4605         "ssi4_ctrl",
4606         "ssi5",
4607         "ssi5_b",
4608         "ssi5_c",
4609         "ssi6",
4610         "ssi6_b",
4611         "ssi7_data",
4612         "ssi7_b_data",
4613         "ssi7_c_data",
4614         "ssi78_ctrl",
4615         "ssi78_b_ctrl",
4616         "ssi78_c_ctrl",
4617         "ssi8_data",
4618         "ssi8_b_data",
4619         "ssi8_c_data",
4620         "ssi9_data",
4621         "ssi9_ctrl",
4622 };
4623
4624 static const char * const tpu0_groups[] = {
4625         "tpu0_to0",
4626         "tpu0_to1",
4627         "tpu0_to2",
4628         "tpu0_to3",
4629 };
4630
4631 static const char * const usb0_groups[] = {
4632         "usb0",
4633         "usb0_ovc_vbus",
4634 };
4635
4636 static const char * const usb1_groups[] = {
4637         "usb1",
4638 };
4639
4640 static const char * const usb2_groups[] = {
4641         "usb2",
4642 };
4643
4644 static const char * const vin0_groups[] = {
4645         "vin0_data24",
4646         "vin0_data20",
4647         "vin0_data18",
4648         "vin0_data16",
4649         "vin0_data12",
4650         "vin0_data10",
4651         "vin0_data8",
4652         "vin0_data4",
4653         "vin0_sync",
4654         "vin0_field",
4655         "vin0_clkenb",
4656         "vin0_clk",
4657 };
4658
4659 static const char * const vin1_groups[] = {
4660         "vin1_data24",
4661         "vin1_data20",
4662         "vin1_data18",
4663         "vin1_data16",
4664         "vin1_data12",
4665         "vin1_data10",
4666         "vin1_data8",
4667         "vin1_data4",
4668         "vin1_sync",
4669         "vin1_field",
4670         "vin1_clkenb",
4671         "vin1_clk",
4672 };
4673
4674 static const char * const vin2_groups[] = {
4675         "vin2_data24",
4676         "vin2_data18",
4677         "vin2_data16",
4678         "vin2_data8",
4679         "vin2_data4",
4680         "vin2_sync",
4681         "vin2_field",
4682         "vin2_clkenb",
4683         "vin2_clk",
4684 };
4685
4686 static const char * const vin3_groups[] = {
4687         "vin3_data8",
4688         "vin3_sync",
4689         "vin3_field",
4690         "vin3_clkenb",
4691         "vin3_clk",
4692 };
4693
4694 static const struct sh_pfc_function pinmux_functions[] = {
4695         SH_PFC_FUNCTION(audio_clk),
4696         SH_PFC_FUNCTION(avb),
4697         SH_PFC_FUNCTION(du),
4698         SH_PFC_FUNCTION(du0),
4699         SH_PFC_FUNCTION(du1),
4700         SH_PFC_FUNCTION(du2),
4701         SH_PFC_FUNCTION(eth),
4702         SH_PFC_FUNCTION(hscif0),
4703         SH_PFC_FUNCTION(hscif1),
4704         SH_PFC_FUNCTION(i2c0),
4705         SH_PFC_FUNCTION(i2c1),
4706         SH_PFC_FUNCTION(i2c2),
4707         SH_PFC_FUNCTION(i2c3),
4708         SH_PFC_FUNCTION(iic0),
4709         SH_PFC_FUNCTION(iic1),
4710         SH_PFC_FUNCTION(iic2),
4711         SH_PFC_FUNCTION(iic3),
4712         SH_PFC_FUNCTION(intc),
4713         SH_PFC_FUNCTION(mlb),
4714         SH_PFC_FUNCTION(mmc0),
4715         SH_PFC_FUNCTION(mmc1),
4716         SH_PFC_FUNCTION(msiof0),
4717         SH_PFC_FUNCTION(msiof1),
4718         SH_PFC_FUNCTION(msiof2),
4719         SH_PFC_FUNCTION(msiof3),
4720         SH_PFC_FUNCTION(pwm0),
4721         SH_PFC_FUNCTION(pwm1),
4722         SH_PFC_FUNCTION(pwm2),
4723         SH_PFC_FUNCTION(pwm3),
4724         SH_PFC_FUNCTION(pwm4),
4725         SH_PFC_FUNCTION(pwm5),
4726         SH_PFC_FUNCTION(pwm6),
4727         SH_PFC_FUNCTION(qspi),
4728         SH_PFC_FUNCTION(scif0),
4729         SH_PFC_FUNCTION(scif1),
4730         SH_PFC_FUNCTION(scif2),
4731         SH_PFC_FUNCTION(scifa0),
4732         SH_PFC_FUNCTION(scifa1),
4733         SH_PFC_FUNCTION(scifa2),
4734         SH_PFC_FUNCTION(scifb0),
4735         SH_PFC_FUNCTION(scifb1),
4736         SH_PFC_FUNCTION(scifb2),
4737         SH_PFC_FUNCTION(scif_clk),
4738         SH_PFC_FUNCTION(sdhi0),
4739         SH_PFC_FUNCTION(sdhi1),
4740         SH_PFC_FUNCTION(sdhi2),
4741         SH_PFC_FUNCTION(sdhi3),
4742         SH_PFC_FUNCTION(ssi),
4743         SH_PFC_FUNCTION(tpu0),
4744         SH_PFC_FUNCTION(usb0),
4745         SH_PFC_FUNCTION(usb1),
4746         SH_PFC_FUNCTION(usb2),
4747         SH_PFC_FUNCTION(vin0),
4748         SH_PFC_FUNCTION(vin1),
4749         SH_PFC_FUNCTION(vin2),
4750         SH_PFC_FUNCTION(vin3),
4751 };
4752
4753 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4754         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4755                 GP_0_31_FN, FN_IP3_17_15,
4756                 GP_0_30_FN, FN_IP3_14_12,
4757                 GP_0_29_FN, FN_IP3_11_8,
4758                 GP_0_28_FN, FN_IP3_7_4,
4759                 GP_0_27_FN, FN_IP3_3_0,
4760                 GP_0_26_FN, FN_IP2_28_26,
4761                 GP_0_25_FN, FN_IP2_25_22,
4762                 GP_0_24_FN, FN_IP2_21_18,
4763                 GP_0_23_FN, FN_IP2_17_15,
4764                 GP_0_22_FN, FN_IP2_14_12,
4765                 GP_0_21_FN, FN_IP2_11_9,
4766                 GP_0_20_FN, FN_IP2_8_6,
4767                 GP_0_19_FN, FN_IP2_5_3,
4768                 GP_0_18_FN, FN_IP2_2_0,
4769                 GP_0_17_FN, FN_IP1_29_28,
4770                 GP_0_16_FN, FN_IP1_27_26,
4771                 GP_0_15_FN, FN_IP1_25_22,
4772                 GP_0_14_FN, FN_IP1_21_18,
4773                 GP_0_13_FN, FN_IP1_17_15,
4774                 GP_0_12_FN, FN_IP1_14_12,
4775                 GP_0_11_FN, FN_IP1_11_8,
4776                 GP_0_10_FN, FN_IP1_7_4,
4777                 GP_0_9_FN, FN_IP1_3_0,
4778                 GP_0_8_FN, FN_IP0_30_27,
4779                 GP_0_7_FN, FN_IP0_26_23,
4780                 GP_0_6_FN, FN_IP0_22_20,
4781                 GP_0_5_FN, FN_IP0_19_16,
4782                 GP_0_4_FN, FN_IP0_15_12,
4783                 GP_0_3_FN, FN_IP0_11_9,
4784                 GP_0_2_FN, FN_IP0_8_6,
4785                 GP_0_1_FN, FN_IP0_5_3,
4786                 GP_0_0_FN, FN_IP0_2_0 }
4787         },
4788         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4789                 0, 0,
4790                 0, 0,
4791                 GP_1_29_FN, FN_IP6_13_11,
4792                 GP_1_28_FN, FN_IP6_10_9,
4793                 GP_1_27_FN, FN_IP6_8_6,
4794                 GP_1_26_FN, FN_IP6_5_3,
4795                 GP_1_25_FN, FN_IP6_2_0,
4796                 GP_1_24_FN, FN_IP5_29_27,
4797                 GP_1_23_FN, FN_IP5_26_24,
4798                 GP_1_22_FN, FN_IP5_23_21,
4799                 GP_1_21_FN, FN_IP5_20_18,
4800                 GP_1_20_FN, FN_IP5_17_15,
4801                 GP_1_19_FN, FN_IP5_14_13,
4802                 GP_1_18_FN, FN_IP5_12_10,
4803                 GP_1_17_FN, FN_IP5_9_6,
4804                 GP_1_16_FN, FN_IP5_5_3,
4805                 GP_1_15_FN, FN_IP5_2_0,
4806                 GP_1_14_FN, FN_IP4_29_27,
4807                 GP_1_13_FN, FN_IP4_26_24,
4808                 GP_1_12_FN, FN_IP4_23_21,
4809                 GP_1_11_FN, FN_IP4_20_18,
4810                 GP_1_10_FN, FN_IP4_17_15,
4811                 GP_1_9_FN, FN_IP4_14_12,
4812                 GP_1_8_FN, FN_IP4_11_9,
4813                 GP_1_7_FN, FN_IP4_8_6,
4814                 GP_1_6_FN, FN_IP4_5_3,
4815                 GP_1_5_FN, FN_IP4_2_0,
4816                 GP_1_4_FN, FN_IP3_31_29,
4817                 GP_1_3_FN, FN_IP3_28_26,
4818                 GP_1_2_FN, FN_IP3_25_23,
4819                 GP_1_1_FN, FN_IP3_22_20,
4820                 GP_1_0_FN, FN_IP3_19_18, }
4821         },
4822         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4823                 0, 0,
4824                 0, 0,
4825                 GP_2_29_FN, FN_IP7_15_13,
4826                 GP_2_28_FN, FN_IP7_12_10,
4827                 GP_2_27_FN, FN_IP7_9_8,
4828                 GP_2_26_FN, FN_IP7_7_6,
4829                 GP_2_25_FN, FN_IP7_5_3,
4830                 GP_2_24_FN, FN_IP7_2_0,
4831                 GP_2_23_FN, FN_IP6_31_29,
4832                 GP_2_22_FN, FN_IP6_28_26,
4833                 GP_2_21_FN, FN_IP6_25_23,
4834                 GP_2_20_FN, FN_IP6_22_20,
4835                 GP_2_19_FN, FN_IP6_19_17,
4836                 GP_2_18_FN, FN_IP6_16_14,
4837                 GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
4838                 GP_2_16_FN, FN_IP8_27,
4839                 GP_2_15_FN, FN_IP8_26,
4840                 GP_2_14_FN, FN_IP8_25_24,
4841                 GP_2_13_FN, FN_IP8_23_22,
4842                 GP_2_12_FN, FN_IP8_21_20,
4843                 GP_2_11_FN, FN_IP8_19_18,
4844                 GP_2_10_FN, FN_IP8_17_16,
4845                 GP_2_9_FN, FN_IP8_15_14,
4846                 GP_2_8_FN, FN_IP8_13_12,
4847                 GP_2_7_FN, FN_IP8_11_10,
4848                 GP_2_6_FN, FN_IP8_9_8,
4849                 GP_2_5_FN, FN_IP8_7_6,
4850                 GP_2_4_FN, FN_IP8_5_4,
4851                 GP_2_3_FN, FN_IP8_3_2,
4852                 GP_2_2_FN, FN_IP8_1_0,
4853                 GP_2_1_FN, FN_IP7_30_29,
4854                 GP_2_0_FN, FN_IP7_28_27 }
4855         },
4856         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4857                 GP_3_31_FN, FN_IP11_21_18,
4858                 GP_3_30_FN, FN_IP11_17_15,
4859                 GP_3_29_FN, FN_IP11_14_13,
4860                 GP_3_28_FN, FN_IP11_12_11,
4861                 GP_3_27_FN, FN_IP11_10_9,
4862                 GP_3_26_FN, FN_IP11_8_7,
4863                 GP_3_25_FN, FN_IP11_6_5,
4864                 GP_3_24_FN, FN_IP11_4,
4865                 GP_3_23_FN, FN_IP11_3_0,
4866                 GP_3_22_FN, FN_IP10_29_26,
4867                 GP_3_21_FN, FN_IP10_25_23,
4868                 GP_3_20_FN, FN_IP10_22_19,
4869                 GP_3_19_FN, FN_IP10_18_15,
4870                 GP_3_18_FN, FN_IP10_14_11,
4871                 GP_3_17_FN, FN_IP10_10_7,
4872                 GP_3_16_FN, FN_IP10_6_4,
4873                 GP_3_15_FN, FN_IP10_3_0,
4874                 GP_3_14_FN, FN_IP9_31_28,
4875                 GP_3_13_FN, FN_IP9_27_26,
4876                 GP_3_12_FN, FN_IP9_25_24,
4877                 GP_3_11_FN, FN_IP9_23_22,
4878                 GP_3_10_FN, FN_IP9_21_20,
4879                 GP_3_9_FN, FN_IP9_19_18,
4880                 GP_3_8_FN, FN_IP9_17_16,
4881                 GP_3_7_FN, FN_IP9_15_12,
4882                 GP_3_6_FN, FN_IP9_11_8,
4883                 GP_3_5_FN, FN_IP9_7_6,
4884                 GP_3_4_FN, FN_IP9_5_4,
4885                 GP_3_3_FN, FN_IP9_3_2,
4886                 GP_3_2_FN, FN_IP9_1_0,
4887                 GP_3_1_FN, FN_IP8_30_29,
4888                 GP_3_0_FN, FN_IP8_28 }
4889         },
4890         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4891                 GP_4_31_FN, FN_IP14_18_16,
4892                 GP_4_30_FN, FN_IP14_15_12,
4893                 GP_4_29_FN, FN_IP14_11_9,
4894                 GP_4_28_FN, FN_IP14_8_6,
4895                 GP_4_27_FN, FN_IP14_5_3,
4896                 GP_4_26_FN, FN_IP14_2_0,
4897                 GP_4_25_FN, FN_IP13_30_29,
4898                 GP_4_24_FN, FN_IP13_28_26,
4899                 GP_4_23_FN, FN_IP13_25_23,
4900                 GP_4_22_FN, FN_IP13_22_19,
4901                 GP_4_21_FN, FN_IP13_18_16,
4902                 GP_4_20_FN, FN_IP13_15_13,
4903                 GP_4_19_FN, FN_IP13_12_10,
4904                 GP_4_18_FN, FN_IP13_9_7,
4905                 GP_4_17_FN, FN_IP13_6_3,
4906                 GP_4_16_FN, FN_IP13_2_0,
4907                 GP_4_15_FN, FN_IP12_30_28,
4908                 GP_4_14_FN, FN_IP12_27_25,
4909                 GP_4_13_FN, FN_IP12_24_23,
4910                 GP_4_12_FN, FN_IP12_22_20,
4911                 GP_4_11_FN, FN_IP12_19_17,
4912                 GP_4_10_FN, FN_IP12_16_14,
4913                 GP_4_9_FN, FN_IP12_13_11,
4914                 GP_4_8_FN, FN_IP12_10_8,
4915                 GP_4_7_FN, FN_IP12_7_6,
4916                 GP_4_6_FN, FN_IP12_5_4,
4917                 GP_4_5_FN, FN_IP12_3_2,
4918                 GP_4_4_FN, FN_IP12_1_0,
4919                 GP_4_3_FN, FN_IP11_31_30,
4920                 GP_4_2_FN, FN_IP11_29_27,
4921                 GP_4_1_FN, FN_IP11_26_24,
4922                 GP_4_0_FN, FN_IP11_23_22 }
4923         },
4924         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4925                 GP_5_31_FN, FN_IP7_24_22,
4926                 GP_5_30_FN, FN_IP7_21_19,
4927                 GP_5_29_FN, FN_IP7_18_16,
4928                 GP_5_28_FN, FN_DU_DOTCLKIN2,
4929                 GP_5_27_FN, FN_IP7_26_25,
4930                 GP_5_26_FN, FN_DU_DOTCLKIN0,
4931                 GP_5_25_FN, FN_AVS2,
4932                 GP_5_24_FN, FN_AVS1,
4933                 GP_5_23_FN, FN_USB2_OVC,
4934                 GP_5_22_FN, FN_USB2_PWEN,
4935                 GP_5_21_FN, FN_IP16_7,
4936                 GP_5_20_FN, FN_IP16_6,
4937                 GP_5_19_FN, FN_USB0_OVC_VBUS,
4938                 GP_5_18_FN, FN_USB0_PWEN,
4939                 GP_5_17_FN, FN_IP16_5_3,
4940                 GP_5_16_FN, FN_IP16_2_0,
4941                 GP_5_15_FN, FN_IP15_29_28,
4942                 GP_5_14_FN, FN_IP15_27_26,
4943                 GP_5_13_FN, FN_IP15_25_23,
4944                 GP_5_12_FN, FN_IP15_22_20,
4945                 GP_5_11_FN, FN_IP15_19_18,
4946                 GP_5_10_FN, FN_IP15_17_16,
4947                 GP_5_9_FN, FN_IP15_15_14,
4948                 GP_5_8_FN, FN_IP15_13_12,
4949                 GP_5_7_FN, FN_IP15_11_9,
4950                 GP_5_6_FN, FN_IP15_8_6,
4951                 GP_5_5_FN, FN_IP15_5_3,
4952                 GP_5_4_FN, FN_IP15_2_0,
4953                 GP_5_3_FN, FN_IP14_30_28,
4954                 GP_5_2_FN, FN_IP14_27_25,
4955                 GP_5_1_FN, FN_IP14_24_22,
4956                 GP_5_0_FN, FN_IP14_21_19 }
4957         },
4958         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4959                              1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
4960                 /* IP0_31 [1] */
4961                 0, 0,
4962                 /* IP0_30_27 [4] */
4963                 FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, 0,
4964                 FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
4965                 0, 0, 0, 0, 0, 0, 0, 0, 0,
4966                 /* IP0_26_23 [4] */
4967                 FN_D7, FN_AD_DI_B, FN_IIC2_SDA_C,
4968                 FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_I2C2_SDA_C,
4969                 FN_TCLK1, 0, 0, 0, 0, 0, 0, 0, 0,
4970                 /* IP0_22_20 [3] */
4971                 FN_D6, FN_IIC2_SCL_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
4972                 FN_I2C2_SCL_C, 0, 0,
4973                 /* IP0_19_16 [4] */
4974                 FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
4975                 FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
4976                 0, 0, 0, 0, 0, 0, 0, 0, 0,
4977                 /* IP0_15_12 [4] */
4978                 FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
4979                 FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
4980                 0, 0, 0, 0, 0, 0, 0, 0, 0,
4981                 /* IP0_11_9 [3] */
4982                 FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
4983                 0, 0, 0,
4984                 /* IP0_8_6 [3] */
4985                 FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
4986                 0, 0, 0,
4987                 /* IP0_5_3 [3] */
4988                 FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
4989                 0, 0, 0,
4990                 /* IP0_2_0 [3] */
4991                 FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
4992                 0, 0, 0, }
4993         },
4994         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4995                              2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
4996                 /* IP1_31_30 [2] */
4997                 0, 0, 0, 0,
4998                 /* IP1_29_28 [2] */
4999                 FN_A1, FN_PWM4, 0, 0,
5000                 /* IP1_27_26 [2] */
5001                 FN_A0, FN_PWM3, 0, 0,
5002                 /* IP1_25_22 [4] */
5003                 FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
5004                 FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
5005                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5006                 /* IP1_21_18 [4] */
5007                 FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
5008                 FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
5009                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5010                 /* IP1_17_15 [3] */
5011                 FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
5012                 FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
5013                 0, 0, 0,
5014                 /* IP1_14_12 [3] */
5015                 FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
5016                 FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
5017                 0, 0,
5018                 /* IP1_11_8 [4] */
5019                 FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, 0,
5020                 FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
5021                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5022                 /* IP1_7_4 [4] */
5023                 FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, 0,
5024                 FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
5025                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5026                 /* IP1_3_0 [4] */
5027                 FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, 0,
5028                 FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
5029                 0, 0, 0, 0, 0, 0, 0, 0, 0, }
5030         },
5031         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
5032                              3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
5033                 /* IP2_31_29 [3] */
5034                 0, 0, 0, 0, 0, 0, 0, 0,
5035                 /* IP2_28_26 [3] */
5036                 FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
5037                 FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
5038                 /* IP2_25_22 [4] */
5039                 FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
5040                 FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_TX2_B, FN_VI2_DATA1_VI2_B1_B,
5041                 0, 0, 0, 0, 0, 0, 0, 0,
5042                 /* IP2_21_18 [4] */
5043                 FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
5044                 FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_RX2_B, FN_VI2_DATA0_VI2_B0_B,
5045                 0, 0, 0, 0, 0, 0, 0, 0,
5046                 /* IP2_17_15 [3] */
5047                 FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
5048                 0, 0, 0, 0,
5049                 /* IP2_14_12 [3] */
5050                 FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
5051                 /* IP2_11_9 [3] */
5052                 FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
5053                 /* IP2_8_6 [3] */
5054                 FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
5055                 /* IP2_5_3 [3] */
5056                 FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
5057                 /* IP2_2_0 [3] */
5058                 FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
5059         },
5060         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
5061                              3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
5062                 /* IP3_31_29 [3] */
5063                 FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
5064                 0, 0, 0,
5065                 /* IP3_28_26 [3] */
5066                 FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
5067                 0, 0, 0, 0,
5068                 /* IP3_25_23 [3] */
5069                 FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
5070                 /* IP3_22_20 [3] */
5071                 FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
5072                 /* IP3_19_18 [2] */
5073                 FN_A16, FN_ATAWR1_N, 0, 0,
5074                 /* IP3_17_15 [3] */
5075                 FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
5076                 0, 0, 0, 0,
5077                 /* IP3_14_12 [3] */
5078                 FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
5079                 0, 0, 0, 0,
5080                 /* IP3_11_8 [4] */
5081                 FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
5082                 FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
5083                 FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
5084                 /* IP3_7_4 [4] */
5085                 FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
5086                 FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
5087                 0, 0, 0, 0, 0, 0, 0, 0, 0,
5088                 /* IP3_3_0 [4] */
5089                 FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
5090                 FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
5091                 0, 0, 0, 0, 0, 0, 0, 0, }
5092         },
5093         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
5094                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
5095                 /* IP4_31_30 [2] */
5096                 0, 0, 0, 0,
5097                 /* IP4_29_27 [3] */
5098                 FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
5099                 FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
5100                 /* IP4_26_24 [3] */
5101                 FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
5102                 FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
5103                 /* IP4_23_21 [3] */
5104                 FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
5105                 FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
5106                 /* IP4_20_18 [3] */
5107                 FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
5108                 FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
5109                 /* IP4_17_15 [3] */
5110                 FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
5111                 0, 0, 0,
5112                 /* IP4_14_12 [3] */
5113                 FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
5114                 FN_VI2_FIELD_B, 0, 0,
5115                 /* IP4_11_9 [3] */
5116                 FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
5117                 FN_VI2_CLKENB_B, 0, 0,
5118                 /* IP4_8_6 [3] */
5119                 FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
5120                 /* IP4_5_3 [3] */
5121                 FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
5122                 /* IP4_2_0 [3] */
5123                 FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
5124                 }
5125         },
5126         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
5127                              2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
5128                 /* IP5_31_30 [2] */
5129                 0, 0, 0, 0,
5130                 /* IP5_29_27 [3] */
5131                 FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
5132                 FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
5133                 /* IP5_26_24 [3] */
5134                 FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
5135                 FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
5136                 FN_MSIOF0_SCK_B, 0,
5137                 /* IP5_23_21 [3] */
5138                 FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
5139                 FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B, FN_IERX_C,
5140                 /* IP5_20_18 [3] */
5141                 FN_WE0_N, FN_IECLK, FN_CAN_CLK,
5142                 FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
5143                 /* IP5_17_15 [3] */
5144                 FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
5145                 FN_INTC_IRQ4_N, 0, 0,
5146                 /* IP5_14_13 [2] */
5147                 FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
5148                 /* IP5_12_10 [3] */
5149                 FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
5150                 0, 0,
5151                 /* IP5_9_6 [4] */
5152                 FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
5153                 FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_IIC1_SDA, FN_INTC_EN1_N,
5154                 FN_I2C1_SDA, 0, 0, 0, 0, 0, 0,
5155                 /* IP5_5_3 [3] */
5156                 FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
5157                 FN_VI2_HSYNC_N, FN_IIC1_SCL, FN_VI2_HSYNC_N_B,
5158                 FN_INTC_EN0_N, FN_I2C1_SCL,
5159                 /* IP5_2_0 [3] */
5160                 FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
5161                 FN_VI2_R3, 0, 0, }
5162         },
5163         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
5164                              3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
5165                 /* IP6_31_29 [3] */
5166                 FN_ETH_REF_CLK, 0, FN_HCTS0_N_E,
5167                 FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
5168                 /* IP6_28_26 [3] */
5169                 FN_ETH_LINK, 0, FN_HTX0_E,
5170                 FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
5171                 /* IP6_25_23 [3] */
5172                 FN_ETH_RXD1, 0, FN_HRX0_E, FN_STP_ISSYNC_0_B,
5173                 FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
5174                 /* IP6_22_20 [3] */
5175                 FN_ETH_RXD0, 0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
5176                 FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
5177                 /* IP6_19_17 [3] */
5178                 FN_ETH_RX_ER, 0, FN_STP_ISD_0_B,
5179                 FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_IIC2_SDA_E, FN_I2C2_SDA_E, 0,
5180                 /* IP6_16_14 [3] */
5181                 FN_ETH_CRS_DV, 0, FN_STP_ISCLK_0_B,
5182                 FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_IIC2_SCL_E,
5183                 FN_I2C2_SCL_E, 0,
5184                 /* IP6_13_11 [3] */
5185                 FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
5186                 FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
5187                 /* IP6_10_9 [2] */
5188                 FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
5189                 /* IP6_8_6 [3] */
5190                 FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
5191                 FN_SSI_SDATA8_C, 0, 0, 0,
5192                 /* IP6_5_3 [3] */
5193                 FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
5194                 FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
5195                 /* IP6_2_0 [3] */
5196                 FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
5197                 FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
5198         },
5199         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
5200                              1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
5201                 /* IP7_31 [1] */
5202                 0, 0,
5203                 /* IP7_30_29 [2] */
5204                 FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2, 0,
5205                 /* IP7_28_27 [2] */
5206                 FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, 0,
5207                 /* IP7_26_25 [2] */
5208                 FN_DU_DOTCLKIN1, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
5209                 /* IP7_24_22 [3] */
5210                 FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
5211                 0, 0, 0,
5212                 /* IP7_21_19 [3] */
5213                 FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
5214                 FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
5215                 /* IP7_18_16 [3] */
5216                 FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
5217                 FN_GLO_SS_C, 0, 0, 0,
5218                 /* IP7_15_13 [3] */
5219                 FN_ETH_MDC, 0, FN_STP_ISD_1_B,
5220                 FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
5221                 /* IP7_12_10 [3] */
5222                 FN_ETH_TXD0, 0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
5223                 FN_GLO_SCLK_C, 0, 0, 0,
5224                 /* IP7_9_8 [2] */
5225                 FN_ETH_MAGIC, 0, FN_SIM0_RST_C, 0,
5226                 /* IP7_7_6 [2] */
5227                 FN_ETH_TX_EN, 0, FN_SIM0_CLK_C, FN_HRTS0_N_F,
5228                 /* IP7_5_3 [3] */
5229                 FN_ETH_TXD1, 0, FN_HTX0_F, FN_BPFCLK_G, 0, 0, 0, 0,
5230                 /* IP7_2_0 [3] */
5231                 FN_ETH_MDIO, 0, FN_HRTS0_N_E,
5232                 FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
5233         },
5234         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
5235                              1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
5236                              2, 2, 2, 2, 2, 2, 2) {
5237                 /* IP8_31 [1] */
5238                 0, 0,
5239                 /* IP8_30_29 [2] */
5240                 FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
5241                 /* IP8_28 [1] */
5242                 FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
5243                 /* IP8_27 [1] */
5244                 FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
5245                 /* IP8_26 [1] */
5246                 FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
5247                 /* IP8_25_24 [2] */
5248                 FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
5249                 FN_AVB_MAGIC, 0,
5250                 /* IP8_23_22 [2] */
5251                 FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
5252                 /* IP8_21_20 [2] */
5253                 FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO, 0,
5254                 /* IP8_19_18 [2] */
5255                 FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, 0,
5256                 /* IP8_17_16 [2] */
5257                 FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, 0,
5258                 /* IP8_15_14 [2] */
5259                 FN_VI1_CLK, FN_AVB_RX_DV, 0, 0,
5260                 /* IP8_13_12 [2] */
5261                 FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, 0, 0,
5262                 /* IP8_11_10 [2] */
5263                 FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, 0, 0,
5264                 /* IP8_9_8 [2] */
5265                 FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
5266                 /* IP8_7_6 [2] */
5267                 FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
5268                 /* IP8_5_4 [2] */
5269                 FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
5270                 /* IP8_3_2 [2] */
5271                 FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
5272                 /* IP8_1_0 [2] */
5273                 FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, 0, }
5274         },
5275         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
5276                              4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
5277                 /* IP9_31_28 [4] */
5278                 FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
5279                 FN_GLO_SS, FN_VI0_CLK_B, FN_IIC2_SCL_D, FN_I2C2_SCL_D,
5280                 FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
5281                 /* IP9_27_26 [2] */
5282                 FN_SD1_DAT3, FN_AVB_RXD0, 0, FN_SCIFB0_RTS_N_B,
5283                 /* IP9_25_24 [2] */
5284                 FN_SD1_DAT2, FN_AVB_COL, 0, FN_SCIFB0_CTS_N_B,
5285                 /* IP9_23_22 [2] */
5286                 FN_SD1_DAT1, FN_AVB_LINK, 0, FN_SCIFB0_TXD_B,
5287                 /* IP9_21_20 [2] */
5288                 FN_SD1_DAT0, FN_AVB_TX_CLK, 0, FN_SCIFB0_RXD_B,
5289                 /* IP9_19_18 [2] */
5290                 FN_SD1_CMD, FN_AVB_TX_ER, 0, FN_SCIFB0_SCK_B,
5291                 /* IP9_17_16 [2] */
5292                 FN_SD1_CLK, FN_AVB_TX_EN, 0, 0,
5293                 /* IP9_15_12 [4] */
5294                 FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
5295                 FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_IIC1_SDA_B,
5296                 FN_I2C1_SDA_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
5297                 /* IP9_11_8 [4] */
5298                 FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
5299                 FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_IIC1_SCL_B,
5300                 FN_I2C1_SCL_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
5301                 /* IP9_7_6 [2] */
5302                 FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
5303                 /* IP9_5_4 [2] */
5304                 FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
5305                 /* IP9_3_2 [2] */
5306                 FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
5307                 /* IP9_1_0 [2] */
5308                 FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
5309         },
5310         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
5311                              2, 4, 3, 4, 4, 4, 4, 3, 4) {
5312                 /* IP10_31_30 [2] */
5313                 0, 0, 0, 0,
5314                 /* IP10_29_26 [4] */
5315                 FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
5316                 FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
5317                 FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
5318                 /* IP10_25_23 [3] */
5319                 FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
5320                 FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
5321                 /* IP10_22_19 [4] */
5322                 FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, 0,
5323                 FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
5324                 FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
5325                 /* IP10_18_15 [4] */
5326                 FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, 0,
5327                 FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
5328                 FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
5329                 0, 0, 0, 0, 0, 0,
5330                 /* IP10_14_11 [4] */
5331                 FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
5332                 FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
5333                 FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
5334                 0, 0, 0, 0, 0, 0, 0,
5335                 /* IP10_10_7 [4] */
5336                 FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
5337                 FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
5338                 FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
5339                 0, 0, 0, 0, 0, 0, 0,
5340                 /* IP10_6_4 [3] */
5341                 FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
5342                 FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
5343                 FN_VI3_DATA0_B, 0,
5344                 /* IP10_3_0 [4] */
5345                 FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
5346                 FN_GLO_RFON, FN_VI1_CLK_B, FN_IIC2_SDA_D, FN_I2C2_SDA_D,
5347                 FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
5348         },
5349         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
5350                              2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
5351                 /* IP11_31_30 [2] */
5352                 FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
5353                 /* IP11_29_27 [3] */
5354                 FN_MLB_DAT, 0, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
5355                 0, 0, 0,
5356                 /* IP11_26_24 [3] */
5357                 FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_IIC2_SDA_B, FN_I2C2_SDA_B,
5358                 0, 0, 0,
5359                 /* IP11_23_22 [2] */
5360                 FN_MLB_CLK, FN_IIC2_SCL_B, FN_I2C2_SCL_B, 0,
5361                 /* IP11_21_18 [4] */
5362                 FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
5363                 0, FN_FMIN_E, 0, FN_FMIN_F, 0, 0, 0, 0, 0, 0, 0,
5364                 /* IP11_17_15 [3] */
5365                 FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
5366                 FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
5367                 /* IP11_14_13 [2] */
5368                 FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
5369                 /* IP11_12_11 [2] */
5370                 FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
5371                 /* IP11_10_9 [2] */
5372                 FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
5373                 /* IP11_8_7 [2] */
5374                 FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
5375                 /* IP11_6_5 [2] */
5376                 FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
5377                 /* IP11_4 [1] */
5378                 FN_SD3_CLK, FN_MMC1_CLK,
5379                 /* IP11_3_0 [4] */
5380                 FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
5381                 FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
5382                 FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
5383         },
5384         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
5385                              1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
5386                 /* IP12_31 [1] */
5387                 0, 0,
5388                 /* IP12_30_28 [3] */
5389                 FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
5390                 FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
5391                 FN_CAN_DEBUGOUT4, 0, 0,
5392                 /* IP12_27_25 [3] */
5393                 FN_SSI_SCK5, FN_SCIFB1_SCK,
5394                 FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
5395                 FN_CAN_DEBUGOUT3, 0, 0,
5396                 /* IP12_24_23 [2] */
5397                 FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
5398                 FN_CAN_DEBUGOUT2,
5399                 /* IP12_22_20 [3] */
5400                 FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
5401                 FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
5402                 /* IP12_19_17 [3] */
5403                 FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
5404                 FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
5405                 /* IP12_16_14 [3] */
5406                 FN_SSI_SDATA3, FN_STP_ISCLK_0,
5407                 FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
5408                 /* IP12_13_11 [3] */
5409                 FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
5410                 FN_CAN_STEP0, 0, 0, 0,
5411                 /* IP12_10_8 [3] */
5412                 FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
5413                 FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
5414                 /* IP12_7_6 [2] */
5415                 FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
5416                 /* IP12_5_4 [2] */
5417                 FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
5418                 /* IP12_3_2 [2] */
5419                 FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
5420                 /* IP12_1_0 [2] */
5421                 FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
5422         },
5423         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
5424                              1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
5425                 /* IP13_31 [1] */
5426                 0, 0,
5427                 /* IP13_30_29 [2] */
5428                 FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
5429                 /* IP13_28_26 [3] */
5430                 FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
5431                 FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
5432                 /* IP13_25_23 [3] */
5433                 FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
5434                 FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
5435                 /* IP13_22_19 [4] */
5436                 FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
5437                 FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
5438                 0, FN_SSI_SDATA7_B, FN_FMIN_G, 0, 0, 0, 0, 0,
5439                 /* IP13_18_16 [3] */
5440                 FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
5441                 FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
5442                 /* IP13_15_13 [3] */
5443                 FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
5444                 FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
5445                 /* IP13_12_10 [3] */
5446                 FN_SSI_SDATA6, FN_FMIN_D, 0, FN_DU2_DR5, FN_LCDOUT5,
5447                 FN_CAN_DEBUGOUT8, 0, 0,
5448                 /* IP13_9_7 [3] */
5449                 FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
5450                 FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
5451                 /* IP13_6_3 [4] */
5452                 FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, 0,
5453                 FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
5454                 FN_BPFCLK_F, 0, 0, 0, 0, 0, 0, 0, 0,
5455                 /* IP13_2_0 [3] */
5456                 FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
5457                 FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
5458         },
5459         { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
5460                              1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
5461                 /* IP14_30 [1] */
5462                 0, 0,
5463                 /* IP14_30_28 [3] */
5464                 FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N,
5465                 FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
5466                 FN_HRTS0_N_C, 0,
5467                 /* IP14_27_25 [3] */
5468                 FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
5469                 FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
5470                 /* IP14_24_22 [3] */
5471                 FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
5472                 FN_LCDOUT9, 0, 0, 0,
5473                 /* IP14_21_19 [3] */
5474                 FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
5475                 FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
5476                 /* IP14_18_16 [3] */
5477                 FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N,
5478                 FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
5479                 /* IP14_15_12 [4] */
5480                 FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
5481                 FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_IIC1_SCL_C, FN_I2C1_SCL_C,
5482                 0, 0, 0, 0, 0, 0, 0,
5483                 /* IP14_11_9 [3] */
5484                 FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
5485                 0, 0, 0,
5486                 /* IP14_8_6 [3] */
5487                 FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
5488                 0, 0, 0,
5489                 /* IP14_5_3 [3] */
5490                 FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
5491                 FN_LCDOUT10, FN_IIC1_SDA_C, FN_I2C1_SDA_C,
5492                 /* IP14_2_0 [3] */
5493                 FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
5494                 FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
5495                 FN_REMOCON, 0, }
5496         },
5497         { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
5498                              2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
5499                 /* IP15_31_30 [2] */
5500                 0, 0, 0, 0,
5501                 /* IP15_29_28 [2] */
5502                 FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
5503                 /* IP15_27_26 [2] */
5504                 FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
5505                 /* IP15_25_23 [3] */
5506                 FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
5507                 FN_DU2_DB7, FN_LCDOUT23, FN_HRX0_C, 0,
5508                 /* IP15_22_20 [3] */
5509                 FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
5510                 FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
5511                 /* IP15_19_18 [2] */
5512                 FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
5513                 /* IP15_17_16 [2] */
5514                 FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
5515                 /* IP15_15_14 [2] */
5516                 FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
5517                 /* IP15_13_12 [2] */
5518                 FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
5519                 /* IP15_11_9 [3] */
5520                 FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
5521                 0, 0, 0,
5522                 /* IP15_8_6 [3] */
5523                 FN_SCIFA2_TXD, FN_BPFCLK, FN_RX2, FN_DU2_DB1, FN_LCDOUT17,
5524                 FN_IIC2_SDA, FN_I2C2_SDA, 0,
5525                 /* IP15_5_3 [3] */
5526                 FN_SCIFA2_RXD, FN_FMIN, FN_TX2, FN_DU2_DB0, FN_LCDOUT16,
5527                 FN_IIC2_SCL, FN_I2C2_SCL, 0,
5528                 /* IP15_2_0 [3] */
5529                 FN_SCIFA2_SCK, FN_FMCLK, FN_SCK2, FN_MSIOF3_SCK, FN_DU2_DG7,
5530                 FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
5531         },
5532         { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
5533                              4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
5534                 /* IP16_31_28 [4] */
5535                 0, 0, 0, 0, 0, 0, 0, 0,
5536                 0, 0, 0, 0, 0, 0, 0, 0,
5537                 /* IP16_27_24 [4] */
5538                 0, 0, 0, 0, 0, 0, 0, 0,
5539                 0, 0, 0, 0, 0, 0, 0, 0,
5540                 /* IP16_23_20 [4] */
5541                 0, 0, 0, 0, 0, 0, 0, 0,
5542                 0, 0, 0, 0, 0, 0, 0, 0,
5543                 /* IP16_19_16 [4] */
5544                 0, 0, 0, 0, 0, 0, 0, 0,
5545                 0, 0, 0, 0, 0, 0, 0, 0,
5546                 /* IP16_15_12 [4] */
5547                 0, 0, 0, 0, 0, 0, 0, 0,
5548                 0, 0, 0, 0, 0, 0, 0, 0,
5549                 /* IP16_11_8 [4] */
5550                 0, 0, 0, 0, 0, 0, 0, 0,
5551                 0, 0, 0, 0, 0, 0, 0, 0,
5552                 /* IP16_7 [1] */
5553                 FN_USB1_OVC, FN_TCLK1_B,
5554                 /* IP16_6 [1] */
5555                 FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
5556                 /* IP16_5_3 [3] */
5557                 FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
5558                 FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_SCIFA2_RXD_B, 0,
5559                 /* IP16_2_0 [3] */
5560                 FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
5561                 FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
5562         },
5563         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
5564                              3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
5565                              2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
5566                 /* SEL_SCIF1 [3] */
5567                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
5568                 FN_SEL_SCIF1_4, 0, 0, 0,
5569                 /* SEL_SCIFB [2] */
5570                 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
5571                 /* SEL_SCIFB2 [2] */
5572                 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
5573                 /* SEL_SCIFB1 [3] */
5574                 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
5575                 FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
5576                 FN_SEL_SCIFB1_6, 0,
5577                 /* SEL_SCIFA1 [2] */
5578                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
5579                 FN_SEL_SCIFA1_3,
5580                 /* SEL_SCIF0 [1] */
5581                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
5582                 /* SEL_SCIFA [1] */
5583                 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
5584                 /* SEL_SOF1 [1] */
5585                 FN_SEL_SOF1_0, FN_SEL_SOF1_1,
5586                 /* SEL_SSI7 [2] */
5587                 FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
5588                 /* SEL_SSI6 [1] */
5589                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
5590                 /* SEL_SSI5 [2] */
5591                 FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
5592                 /* SEL_VI3 [1] */
5593                 FN_SEL_VI3_0, FN_SEL_VI3_1,
5594                 /* SEL_VI2 [1] */
5595                 FN_SEL_VI2_0, FN_SEL_VI2_1,
5596                 /* SEL_VI1 [1] */
5597                 FN_SEL_VI1_0, FN_SEL_VI1_1,
5598                 /* SEL_VI0 [1] */
5599                 FN_SEL_VI0_0, FN_SEL_VI0_1,
5600                 /* SEL_TSIF1 [2] */
5601                 FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
5602                 /* RESERVED [1] */
5603                 0, 0,
5604                 /* SEL_LBS [1] */
5605                 FN_SEL_LBS_0, FN_SEL_LBS_1,
5606                 /* SEL_TSIF0 [2] */
5607                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
5608                 /* SEL_SOF3 [1] */
5609                 FN_SEL_SOF3_0, FN_SEL_SOF3_1,
5610                 /* SEL_SOF0 [1] */
5611                 FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
5612         },
5613         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
5614                              3, 1, 1, 1, 2, 1, 2, 1, 2,
5615                              1, 1, 1, 3, 3, 2, 3, 2, 2) {
5616                 /* RESERVED [3] */
5617                 0, 0, 0, 0, 0, 0, 0, 0,
5618                 /* SEL_TMU1 [1] */
5619                 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
5620                 /* SEL_HSCIF1 [1] */
5621                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
5622                 /* SEL_SCIFCLK [1] */
5623                 FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
5624                 /* SEL_CAN0 [2] */
5625                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
5626                 /* SEL_CANCLK [1] */
5627                 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
5628                 /* SEL_SCIFA2 [2] */
5629                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
5630                 /* SEL_CAN1 [1] */
5631                 FN_SEL_CAN1_0, FN_SEL_CAN1_1,
5632                 /* RESERVED [2] */
5633                 0, 0, 0, 0,
5634                 /* SEL_SCIF2 [1] */
5635                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1,
5636                 /* SEL_ADI [1] */
5637                 FN_SEL_ADI_0, FN_SEL_ADI_1,
5638                 /* SEL_SSP [1] */
5639                 FN_SEL_SSP_0, FN_SEL_SSP_1,
5640                 /* SEL_FM [3] */
5641                 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
5642                 FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
5643                 /* SEL_HSCIF0 [3] */
5644                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
5645                 FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
5646                 /* SEL_GPS [2] */
5647                 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
5648                 /* RESERVED [3] */
5649                 0, 0, 0, 0, 0, 0, 0, 0,
5650                 /* SEL_SIM [2] */
5651                 FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
5652                 /* SEL_SSI8 [2] */
5653                 FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
5654         },
5655         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
5656                              1, 1, 2, 4, 4, 2, 2,
5657                              4, 2, 3, 2, 3, 2) {
5658                 /* SEL_IICDVFS [1] */
5659                 FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
5660                 /* SEL_IIC0 [1] */
5661                 FN_SEL_IIC0_0, FN_SEL_IIC0_1,
5662                 /* RESERVED [2] */
5663                 0, 0, 0, 0,
5664                 /* RESERVED [4] */
5665                 0, 0, 0, 0, 0, 0, 0, 0,
5666                 0, 0, 0, 0, 0, 0, 0, 0,
5667                 /* RESERVED [4] */
5668                 0, 0, 0, 0, 0, 0, 0, 0,
5669                 0, 0, 0, 0, 0, 0, 0, 0,
5670                 /* RESERVED [2] */
5671                 0, 0, 0, 0,
5672                 /* SEL_IEB [2] */
5673                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
5674                 /* RESERVED [4] */
5675                 0, 0, 0, 0, 0, 0, 0, 0,
5676                 0, 0, 0, 0, 0, 0, 0, 0,
5677                 /* RESERVED [2] */
5678                 0, 0, 0, 0,
5679                 /* SEL_IIC2 [3] */
5680                 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
5681                 FN_SEL_IIC2_4, 0, 0, 0,
5682                 /* SEL_IIC1 [2] */
5683                 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
5684                 /* SEL_I2C2 [3] */
5685                 FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
5686                 FN_SEL_I2C2_4, 0, 0, 0,
5687                 /* SEL_I2C1 [2] */
5688                 FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
5689         },
5690         { },
5691 };
5692
5693 const struct sh_pfc_soc_info r8a7790_pinmux_info = {
5694         .name = "r8a77900_pfc",
5695         .unlock_reg = 0xe6060000, /* PMMR */
5696
5697         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
5698
5699         .pins = pinmux_pins,
5700         .nr_pins = ARRAY_SIZE(pinmux_pins),
5701         .groups = pinmux_groups,
5702         .nr_groups = ARRAY_SIZE(pinmux_groups),
5703         .functions = pinmux_functions,
5704         .nr_functions = ARRAY_SIZE(pinmux_functions),
5705
5706         .cfg_regs = pinmux_config_regs,
5707
5708         .pinmux_data = pinmux_data,
5709         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
5710 };