drivers/pinctrl/sh-pfc/pfc-r8a7794.c

   1 /*
   2  * r8a7794 processor support - PFC hardware block.
   3  *
   4  * Copyright (C) 2014-2015 Renesas Electronics Corporation
   5  * Copyright (C) 2015 Renesas Solutions Corp.
   6  * Copyright (C) 2015-2016 Cogent Embedded, Inc., <source@cogentembedded.com>
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License version 2
  10  * as published by the Free Software Foundation.
  11  */
  12
  13 #include <linux/kernel.h>
  14
  15 #include "core.h"
  16 #include "sh_pfc.h"
  17
  18 #define CPU_ALL_PORT(fn, sfx)                                           \
  19         PORT_GP_32(0, fn, sfx),                                         \
  20         PORT_GP_26(1, fn, sfx),                                         \
  21         PORT_GP_32(2, fn, sfx),                                         \
  22         PORT_GP_32(3, fn, sfx),                                         \
  23         PORT_GP_32(4, fn, sfx),                                         \
  24         PORT_GP_28(5, fn, sfx),                                         \
  25         PORT_GP_26(6, fn, sfx)
  26
  27 enum {
  28         PINMUX_RESERVED = 0,
  29
  30         PINMUX_DATA_BEGIN,
  31         GP_ALL(DATA),
  32         PINMUX_DATA_END,
  33
  34         PINMUX_FUNCTION_BEGIN,
  35         GP_ALL(FN),
  36
  37         /* GPSR0 */
  38         FN_IP0_23_22, FN_IP0_24, FN_IP0_25, FN_IP0_27_26, FN_IP0_29_28,
  39         FN_IP0_31_30, FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6,
  40         FN_IP1_10_8, FN_IP1_12_11, FN_IP1_14_13, FN_IP1_17_15, FN_IP1_19_18,
  41         FN_IP1_21_20, FN_IP1_23_22, FN_IP1_24, FN_A2, FN_IP1_26, FN_IP1_27,
  42         FN_IP1_29_28, FN_IP1_31_30, FN_IP2_1_0, FN_IP2_3_2, FN_IP2_5_4,
  43         FN_IP2_7_6, FN_IP2_9_8, FN_IP2_11_10, FN_IP2_13_12, FN_IP2_15_14,
  44         FN_IP2_17_16,
  45
  46         /* GPSR1 */
  47         FN_IP2_20_18, FN_IP2_23_21, FN_IP2_26_24, FN_IP2_29_27, FN_IP2_31_30,
  48         FN_IP3_1_0, FN_IP3_3_2, FN_IP3_5_4, FN_IP3_7_6, FN_IP3_9_8, FN_IP3_10,
  49         FN_IP3_11, FN_IP3_12, FN_IP3_14_13, FN_IP3_17_15, FN_IP3_20_18,
  50         FN_IP3_23_21, FN_IP3_26_24, FN_IP3_29_27, FN_IP3_30, FN_IP3_31,
  51         FN_WE0_N, FN_WE1_N, FN_IP4_1_0 , FN_IP7_31, FN_DACK0,
  52
  53         /* GPSR2 */
  54         FN_IP4_4_2, FN_IP4_7_5, FN_IP4_9_8, FN_IP4_11_10, FN_IP4_13_12,
  55         FN_IP4_15_14, FN_IP4_17_16, FN_IP4_19_18, FN_IP4_22_20, FN_IP4_25_23,
  56         FN_IP4_27_26, FN_IP4_29_28, FN_IP4_31_30, FN_IP5_1_0, FN_IP5_3_2,
  57         FN_IP5_5_4, FN_IP5_8_6, FN_IP5_11_9, FN_IP5_13_12, FN_IP5_15_14,
  58         FN_IP5_17_16, FN_IP5_19_18, FN_IP5_21_20, FN_IP5_23_22, FN_IP5_25_24,
  59         FN_IP5_27_26, FN_IP5_29_28, FN_IP5_31_30, FN_IP6_1_0, FN_IP6_3_2,
  60         FN_IP6_5_4, FN_IP6_7_6,
  61
  62         /* GPSR3 */
  63         FN_IP6_8, FN_IP6_9, FN_IP6_10, FN_IP6_11, FN_IP6_12, FN_IP6_13,
  64         FN_IP6_14, FN_IP6_15, FN_IP6_16, FN_IP6_19_17, FN_IP6_22_20,
  65         FN_IP6_25_23, FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3,
  66         FN_IP7_8_6, FN_IP7_11_9, FN_IP7_14_12, FN_IP7_17_15, FN_IP7_20_18,
  67         FN_IP7_23_21, FN_IP7_26_24, FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3,
  68         FN_IP8_8_6, FN_IP8_11_9, FN_IP8_14_12, FN_IP8_16_15, FN_IP8_19_17,
  69         FN_IP8_22_20,
  70
  71         /* GPSR4 */
  72         FN_IP8_25_23, FN_IP8_28_26, FN_IP8_31_29, FN_IP9_2_0, FN_IP9_5_3,
  73         FN_IP9_8_6, FN_IP9_11_9, FN_IP9_14_12, FN_IP9_16_15, FN_IP9_18_17,
  74         FN_IP9_21_19, FN_IP9_24_22, FN_IP9_27_25, FN_IP9_30_28, FN_IP10_2_0,
  75         FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_17_15,
  76         FN_IP10_20_18, FN_IP10_23_21, FN_IP10_26_24, FN_IP10_29_27,
  77         FN_IP10_31_30, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_7_6, FN_IP11_10_8,
  78         FN_IP11_13_11, FN_IP11_15_14, FN_IP11_17_16,
  79
  80         /* GPSR5 */
  81         FN_IP11_20_18, FN_IP11_23_21, FN_IP11_26_24, FN_IP11_29_27, FN_IP12_2_0,
  82         FN_IP12_5_3, FN_IP12_8_6, FN_IP12_10_9, FN_IP12_12_11, FN_IP12_14_13,
  83         FN_IP12_17_15, FN_IP12_20_18, FN_IP12_23_21, FN_IP12_26_24,
  84         FN_IP12_29_27, FN_IP13_2_0, FN_IP13_5_3, FN_IP13_8_6, FN_IP13_11_9,
  85         FN_IP13_14_12, FN_IP13_17_15, FN_IP13_20_18, FN_IP13_23_21,
  86         FN_IP13_26_24, FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN, FN_USB1_OVC,
  87
  88         /* GPSR6 */
  89         FN_SD0_CLK, FN_SD0_CMD, FN_SD0_DATA0, FN_SD0_DATA1, FN_SD0_DATA2,
  90         FN_SD0_DATA3, FN_SD0_CD, FN_SD0_WP, FN_SD1_CLK, FN_SD1_CMD,
  91         FN_SD1_DATA0, FN_SD1_DATA1, FN_SD1_DATA2, FN_SD1_DATA3, FN_IP0_0,
  92         FN_IP0_9_8, FN_IP0_10, FN_IP0_11, FN_IP0_12, FN_IP0_13, FN_IP0_14,
  93         FN_IP0_15, FN_IP0_16, FN_IP0_17, FN_IP0_19_18, FN_IP0_21_20,
  94
  95         /* IPSR0 */
  96         FN_SD1_CD, FN_CAN0_RX, FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, FN_MMC_CLK,
  97         FN_SD2_CLK, FN_MMC_CMD, FN_SD2_CMD, FN_MMC_D0, FN_SD2_DATA0, FN_MMC_D1,
  98         FN_SD2_DATA1, FN_MMC_D2, FN_SD2_DATA2, FN_MMC_D3, FN_SD2_DATA3,
  99         FN_MMC_D4, FN_SD2_CD, FN_MMC_D5, FN_SD2_WP, FN_MMC_D6, FN_SCIF0_RXD,
 100         FN_I2C2_SCL_B, FN_CAN1_RX, FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B,
 101         FN_CAN1_TX, FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, FN_D1, FN_SCIFA3_RXD_B,
 102         FN_D2, FN_SCIFA3_TXD_B, FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, FN_D4,
 103         FN_I2C3_SDA_B, FN_SCIF5_TXD_B, FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D,
 104
 105         /* IPSR1 */
 106         FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, FN_D7, FN_IRQ3, FN_TCLK1,
 107         FN_PWM6_B, FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, FN_D9, FN_HSCIF2_HTX,
 108         FN_I2C1_SDA_B, FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6,
 109         FN_PWM5_C, FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
 110         FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D, FN_D13,
 111         FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B, FN_D14, FN_SCIFA1_RXD,
 112         FN_IIC0_SCL_B, FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, FN_A0,
 113         FN_SCIFB1_SCK, FN_PWM3_B, FN_A1, FN_SCIFB1_TXD, FN_A3, FN_SCIFB0_SCK,
 114         FN_A4, FN_SCIFB0_TXD, FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
 115         FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
 116
 117         /* IPSR2 */
 118         FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, FN_A8, FN_MSIOF1_RXD,
 119         FN_SCIFA0_RXD_B, FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, FN_A10,
 120         FN_MSIOF1_SCK, FN_IIC1_SCL_B, FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B,
 121         FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, FN_A13, FN_MSIOF1_SS2,
 122         FN_SCIFA5_TXD_B, FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
 123         FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1, FN_A16,
 124         FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN, FN_VSP, FN_CAN_CLK_C,
 125         FN_TPUTO2_B, FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
 126         FN_AVB_AVTP_CAPTURE_B, FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E,
 127         FN_CAN1_TX_B, FN_AVB_AVTP_MATCH_B, FN_A19, FN_MSIOF2_SS2, FN_PWM4,
 128         FN_TPUTO2, FN_MOUT0, FN_A20, FN_SPCLK, FN_MOUT1,
 129
 130         /* IPSR3 */
 131         FN_A21, FN_MOSI_IO0, FN_MOUT2, FN_A22, FN_MISO_IO1, FN_MOUT5,
 132         FN_ATADIR1_N, FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N, FN_A24, FN_IO3,
 133         FN_EX_WAIT2, FN_A25, FN_SSL, FN_ATARD1_N, FN_CS0_N, FN_VI1_DATA8,
 134         FN_CS1_N_A26, FN_VI1_DATA9, FN_EX_CS0_N, FN_VI1_DATA10, FN_EX_CS1_N,
 135         FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11, FN_EX_CS2_N, FN_PWM0,
 136         FN_SCIF4_RXD_C, FN_TS_SDATA_B, FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD,
 137         FN_SDATA_B, FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
 138         FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B, FN_EX_CS4_N,
 139         FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B, FN_RIF0_D0, FN_FMCLK,
 140         FN_SCIFB2_CTS_N, FN_SCKZ_B, FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E,
 141         FN_TS_SPSYNC_B, FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
 142         FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N, FN_MTS_N_B,
 143         FN_RD_N, FN_ATACS11_N, FN_RD_WR_N, FN_ATAG1_N,
 144
 145         /* IPSR4 */
 146         FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, FN_DU0_DR0,
 147         FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D, FN_CC50_STATE0,
 148         FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D, FN_CC50_STATE1,
 149         FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, FN_DU0_DR3, FN_LCDOUT19,
 150         FN_CC50_STATE3, FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, FN_DU0_DR5,
 151         FN_LCDOUT21, FN_CC50_STATE5, FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6,
 152         FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, FN_DU0_DG0, FN_LCDOUT8,
 153         FN_SCIFA0_RXD_C, FN_I2C3_SCL_D, FN_CC50_STATE8, FN_DU0_DG1, FN_LCDOUT9,
 154         FN_SCIFA0_TXD_C, FN_I2C3_SDA_D, FN_CC50_STATE9, FN_DU0_DG2, FN_LCDOUT10,
 155         FN_CC50_STATE10, FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, FN_DU0_DG4,
 156         FN_LCDOUT12, FN_CC50_STATE12,
 157
 158         /* IPSR5 */
 159         FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, FN_DU0_DG6, FN_LCDOUT14,
 160         FN_CC50_STATE14, FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, FN_DU0_DB0,
 161         FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D, FN_CAN0_RX_C,
 162         FN_CC50_STATE16, FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
 163         FN_CAN0_TX_C, FN_CC50_STATE17, FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18,
 164         FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, FN_DU0_DB4, FN_LCDOUT4,
 165         FN_CC50_STATE20, FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, FN_DU0_DB6,
 166         FN_LCDOUT6, FN_CC50_STATE22, FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23,
 167         FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, FN_DU0_DOTCLKOUT0,
 168         FN_QCLK, FN_CC50_STATE25, FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE,
 169         FN_CC50_STATE26, FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27,
 170
 171         /* IPSR6 */
 172         FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28,
 173         FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
 174         FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, FN_DU0_CDE, FN_QPOLB,
 175         FN_CC50_STATE31, FN_VI0_CLK, FN_AVB_RX_CLK, FN_VI0_DATA0_VI0_B0,
 176         FN_AVB_RX_DV, FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0, FN_VI0_DATA2_VI0_B2,
 177         FN_AVB_RXD1, FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2, FN_VI0_DATA4_VI0_B4,
 178         FN_AVB_RXD3, FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4, FN_VI0_DATA6_VI0_B6,
 179         FN_AVB_RXD5, FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6, FN_VI0_CLKENB,
 180         FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C, FN_AVB_RXD7, FN_VI0_FIELD,
 181         FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C, FN_AVB_RX_ER, FN_VI0_HSYNC_N,
 182         FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C, FN_AVB_COL, FN_VI0_VSYNC_N,
 183         FN_SCIF0_TXD_B, FN_I2C0_SDA_C, FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN,
 184         FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D, FN_AVB_TX_CLK,
 185         FN_ADIDATA, FN_AD_DI,
 186
 187         /* IPSR7 */
 188         FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D, FN_AVB_TXD0,
 189         FN_ADICS_SAMP, FN_AD_DO, FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B,
 190         FN_CAN0_RX_B, FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, FN_ETH_RXD0, FN_VI0_G3,
 191         FN_MSIOF2_SYNC_B, FN_CAN0_TX_B, FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N,
 192         FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D, FN_AVB_TXD3,
 193         FN_ADICHS1, FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
 194         FN_AVB_TXD4, FN_ADICHS2, FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C,
 195         FN_AVB_TXD5, FN_SSI_SCK5_B, FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C,
 196         FN_IIC1_SCL_D, FN_AVB_TXD6, FN_SSI_WS5_B, FN_ETH_TX_EN, FN_VI0_R0,
 197         FN_SCIF2_TXD_C, FN_IIC1_SDA_D, FN_AVB_TXD7, FN_SSI_SDATA5_B,
 198         FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER, FN_SSI_SCK6_B,
 199         FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E, FN_AVB_GTX_CLK,
 200         FN_SSI_WS6_B, FN_DREQ0_N, FN_SCIFB1_RXD,
 201
 202         /* IPSR8 */
 203         FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E, FN_AVB_MDC,
 204         FN_SSI_SDATA6_B, FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C,
 205         FN_AUDIO_CLKA_B, FN_AVB_MDIO, FN_SSI_SCK78_B, FN_HSCIF0_HTX,
 206         FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B, FN_AVB_LINK, FN_SSI_WS78_B,
 207         FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
 208         FN_AVB_MAGIC, FN_SSI_SDATA7_B, FN_HSCIF0_HRTS_N, FN_VI0_R7,
 209         FN_SCIF0_TXD_D, FN_I2C0_SDA_E, FN_AVB_PHY_INT, FN_SSI_SDATA8_B,
 210         FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
 211         FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B, FN_AVB_GTXREFCLK,
 212         FN_CAN1_RX_D, FN_TPUTO0_B, FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0,
 213         FN_CAN_CLK, FN_DVC_MUTE, FN_CAN1_TX_D, FN_I2C1_SCL, FN_SCIF4_RXD,
 214         FN_PWM5_B, FN_DU1_DR0, FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B,
 215         FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1, FN_RIF1_CLK_B,
 216         FN_TS_SCK_D, FN_BPFCLK_C, FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C,
 217         FN_DU1_DR2, FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
 218
 219         /* IPSR9 */
 220         FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3, FN_RIF1_D1_B,
 221         FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, FN_MSIOF0_SCK, FN_IRQ0,
 222         FN_TS_SDATA, FN_DU1_DR4, FN_RIF1_SYNC, FN_TPUTO1_C, FN_MSIOF0_SYNC,
 223         FN_PWM1, FN_TS_SCK, FN_DU1_DR5, FN_RIF1_CLK, FN_BPFCLK_B, FN_MSIOF0_SS1,
 224         FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6, FN_RIF1_D0, FN_FMCLK_B,
 225         FN_RDS_CLK_B, FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
 226         FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, FN_HSCIF1_HRX, FN_I2C4_SCL,
 227         FN_PWM6, FN_DU1_DG0, FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
 228         FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2, FN_REMOCON_B,
 229         FN_SPEEDIN_B, FN_VSP_B, FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK,
 230         FN_DU1_DG3, FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32,
 231         FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4, FN_SSI_WS1_B,
 232         FN_CAN_STEP0, FN_CC50_STATE33, FN_SCIF1_SCK, FN_PWM3, FN_TCLK2,
 233         FN_DU1_DG5, FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34,
 234
 235         /* IPSR10 */
 236         FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B, FN_CAN_DEBUGOUT0,
 237         FN_CC50_STATE35, FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
 238         FN_CAN_DEBUGOUT1, FN_CC50_STATE36, FN_SCIF2_RXD, FN_IIC1_SCL,
 239         FN_DU1_DB0, FN_SSI_SDATA2_B, FN_USB0_EXTLP, FN_CAN_DEBUGOUT2,
 240         FN_CC50_STATE37, FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
 241         FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, FN_SCIF2_SCK, FN_IRQ1,
 242         FN_DU1_DB2, FN_SSI_WS9_B, FN_USB0_IDIN, FN_CAN_DEBUGOUT4,
 243         FN_CC50_STATE39, FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
 244         FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
 245         FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4, FN_AUDIO_CLKA_C,
 246         FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C, FN_SCIF3_TXD,
 247         FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5, FN_AUDIO_CLKB_C, FN_SSI_WS4_B,
 248         FN_CAN_DEBUGOUT7, FN_RDS_DATA_C, FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6,
 249         FN_AUDIO_CLKC_C, FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, FN_I2C2_SDA,
 250         FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C, FN_CAN_DEBUGOUT9,
 251         FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
 252
 253         /* IPSR11 */
 254         FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
 255         FN_CAN_DEBUGOUT11, FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C,
 256         FN_DU1_DOTCLKOUT1, FN_CAN_DEBUGOUT12, FN_SSI_SCK6, FN_SCIFA1_SCK_B,
 257         FN_DU1_EXHSYNC_DU1_HSYNC, FN_CAN_DEBUGOUT13, FN_SSI_WS6,
 258         FN_SCIFA1_RXD_B, FN_I2C4_SCL_C, FN_DU1_EXVSYNC_DU1_VSYNC,
 259         FN_CAN_DEBUGOUT14, FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
 260         FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, FN_SSI_SCK78,
 261         FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP, FN_SSI_WS78,
 262         FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE, FN_SSI_SDATA7,
 263         FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D, FN_CAN_CLK_D, FN_PCMOE_N,
 264         FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
 265         FN_AD_DI_B, FN_PCMWE_N, FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D,
 266         FN_ADICS_SAMP_B, FN_AD_DO_B, FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B,
 267         FN_ADICLK_B, FN_AD_CLK_B,
 268
 269         /* IPSR12 */
 270         FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
 271         FN_AD_NCS_N_B, FN_DREQ1_N_B, FN_SSI_WS34, FN_MSIOF1_SS1_B,
 272         FN_SCIFA1_RXD_C, FN_ADICHS1_B, FN_CAN1_RX_C, FN_DACK1_B, FN_SSI_SDATA3,
 273         FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B, FN_CAN1_TX_C,
 274         FN_DREQ2_N, FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX, FN_SSI_WS4,
 275         FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX, FN_SSI_SDATA4, FN_MLB_DAT,
 276         FN_IERX_B, FN_IRD_SCK, FN_SSI_SDATA8, FN_SCIF1_SCK_B,
 277         FN_PWM1_B, FN_IRQ9, FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, FN_SSI_SCK1,
 278         FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK, FN_CAN0_RX_D,
 279         FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, FN_SSI_WS1, FN_SCIF1_TXD_B,
 280         FN_IIC1_SDA_C, FN_VI1_DATA0, FN_CAN0_TX_D, FN_AVB_AVTP_MATCH,
 281         FN_ETH_RX_ER_B, FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_SDATA, FN_VI1_DATA1,
 282         FN_ATAG0_N, FN_ETH_RXD0_B, FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2,
 283         FN_MDATA, FN_ATAWR0_N, FN_ETH_RXD1_B,
 284
 285         /* IPSR13 */
 286         FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3, FN_SCKZ,
 287         FN_ATACS00_N, FN_ETH_LINK_B, FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B,
 288         FN_SCIFA0_TXD_D, FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B,
 289         FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5, FN_MTS_N,
 290         FN_EX_WAIT1, FN_ETH_TXD1_B, FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E,
 291         FN_VI1_DATA6, FN_ATARD0_N, FN_ETH_TX_EN_B, FN_SSI_SDATA9,
 292         FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7, FN_ATADIR0_N,
 293         FN_ETH_MAGIC_B, FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D,
 294         FN_VI1_CLKENB, FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B,
 295         FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
 296         FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B, FN_AUDIO_CLKC,
 297         FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N, FN_TS_SDEN_C,
 298         FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D, FN_AUDIO_CLKOUT, FN_I2C4_SDA_B,
 299         FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N, FN_TS_SPSYNC_C, FN_RIF0_D1_B,
 300         FN_FMIN_E, FN_RDS_DATA_D,
 301
 302         /* MOD_SEL */
 303         FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
 304         FN_SEL_ADI_0, FN_SEL_ADI_1, FN_SEL_CAN_0, FN_SEL_CAN_1,
 305         FN_SEL_CAN_2, FN_SEL_CAN_3, FN_SEL_DARC_0, FN_SEL_DARC_1,
 306         FN_SEL_DARC_2, FN_SEL_DARC_3, FN_SEL_DARC_4, FN_SEL_DR0_0,
 307         FN_SEL_DR0_1, FN_SEL_DR1_0, FN_SEL_DR1_1, FN_SEL_DR2_0, FN_SEL_DR2_1,
 308         FN_SEL_DR3_0, FN_SEL_DR3_1, FN_SEL_ETH_0, FN_SEL_ETH_1, FN_SEL_FSN_0,
 309         FN_SEL_FSN_1, FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2,
 310         FN_SEL_I2C00_3, FN_SEL_I2C00_4, FN_SEL_I2C01_0, FN_SEL_I2C01_1,
 311         FN_SEL_I2C01_2, FN_SEL_I2C01_3, FN_SEL_I2C01_4, FN_SEL_I2C02_0,
 312         FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3, FN_SEL_I2C02_4,
 313         FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
 314         FN_SEL_I2C03_4, FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2,
 315         FN_SEL_I2C04_3, FN_SEL_I2C04_4, FN_SEL_IIC00_0, FN_SEL_IIC00_1,
 316         FN_SEL_IIC00_2, FN_SEL_IIC00_3, FN_SEL_AVB_0, FN_SEL_AVB_1,
 317
 318         /* MOD_SEL2 */
 319         FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, FN_SEL_IIC01_0,
 320         FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3, FN_SEL_LBS_0,
 321         FN_SEL_LBS_1, FN_SEL_MSI1_0, FN_SEL_MSI1_1, FN_SEL_MSI2_0,
 322         FN_SEL_MSI2_1, FN_SEL_RAD_0, FN_SEL_RAD_1, FN_SEL_RCN_0,
 323         FN_SEL_RCN_1, FN_SEL_RSP_0, FN_SEL_RSP_1, FN_SEL_SCIFA0_0,
 324         FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2, FN_SEL_SCIFA0_3, FN_SEL_SCIFA1_0,
 325         FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
 326         FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1,
 327         FN_SEL_SCIFA4_2, FN_SEL_SCIFA4_3, FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1,
 328         FN_SEL_SCIFA5_2, FN_SEL_SCIFA5_3, FN_SEL_SPDM_0, FN_SEL_SPDM_1,
 329         FN_SEL_TMU_0, FN_SEL_TMU_1, FN_SEL_TSIF0_0, FN_SEL_TSIF0_1,
 330         FN_SEL_TSIF0_2, FN_SEL_TSIF0_3, FN_SEL_CAN0_0, FN_SEL_CAN0_1,
 331         FN_SEL_CAN0_2, FN_SEL_CAN0_3, FN_SEL_CAN1_0, FN_SEL_CAN1_1,
 332         FN_SEL_CAN1_2, FN_SEL_CAN1_3, FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
 333         FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_RDS_0, FN_SEL_RDS_1,
 334         FN_SEL_RDS_2, FN_SEL_RDS_3,
 335
 336         /* MOD_SEL3 */
 337         FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
 338         FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF2_0,
 339         FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
 340         FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
 341         FN_SEL_SCIF4_4, FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2,
 342         FN_SEL_SCIF5_3, FN_SEL_SSI1_0, FN_SEL_SSI1_1, FN_SEL_SSI2_0,
 343         FN_SEL_SSI2_1, FN_SEL_SSI4_0, FN_SEL_SSI4_1, FN_SEL_SSI5_0,
 344         FN_SEL_SSI5_1, FN_SEL_SSI6_0, FN_SEL_SSI6_1, FN_SEL_SSI7_0,
 345         FN_SEL_SSI7_1, FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI9_0,
 346         FN_SEL_SSI9_1,
 347         PINMUX_FUNCTION_END,
 348
 349         PINMUX_MARK_BEGIN,
 350         A2_MARK, WE0_N_MARK, WE1_N_MARK, DACK0_MARK,
 351
 352         USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
 353
 354         SD0_CLK_MARK, SD0_CMD_MARK, SD0_DATA0_MARK, SD0_DATA1_MARK,
 355         SD0_DATA2_MARK, SD0_DATA3_MARK, SD0_CD_MARK, SD0_WP_MARK,
 356
 357         SD1_CLK_MARK, SD1_CMD_MARK, SD1_DATA0_MARK, SD1_DATA1_MARK,
 358         SD1_DATA2_MARK, SD1_DATA3_MARK,
 359
 360         /* IPSR0 */
 361         SD1_CD_MARK, CAN0_RX_MARK, SD1_WP_MARK, IRQ7_MARK, CAN0_TX_MARK,
 362         MMC_CLK_MARK, SD2_CLK_MARK, MMC_CMD_MARK, SD2_CMD_MARK, MMC_D0_MARK,
 363         SD2_DATA0_MARK, MMC_D1_MARK, SD2_DATA1_MARK, MMC_D2_MARK,
 364         SD2_DATA2_MARK, MMC_D3_MARK, SD2_DATA3_MARK, MMC_D4_MARK, SD2_CD_MARK,
 365         MMC_D5_MARK, SD2_WP_MARK, MMC_D6_MARK, SCIF0_RXD_MARK, I2C2_SCL_B_MARK,
 366         CAN1_RX_MARK, MMC_D7_MARK, SCIF0_TXD_MARK, I2C2_SDA_B_MARK,
 367         CAN1_TX_MARK, D0_MARK, SCIFA3_SCK_B_MARK, IRQ4_MARK, D1_MARK,
 368         SCIFA3_RXD_B_MARK, D2_MARK, SCIFA3_TXD_B_MARK, D3_MARK, I2C3_SCL_B_MARK,
 369         SCIF5_RXD_B_MARK, D4_MARK, I2C3_SDA_B_MARK, SCIF5_TXD_B_MARK, D5_MARK,
 370         SCIF4_RXD_B_MARK, I2C0_SCL_D_MARK,
 371
 372         /* IPSR1 */
 373         D6_MARK, SCIF4_TXD_B_MARK, I2C0_SDA_D_MARK, D7_MARK, IRQ3_MARK,
 374         TCLK1_MARK, PWM6_B_MARK, D8_MARK, HSCIF2_HRX_MARK, I2C1_SCL_B_MARK,
 375         D9_MARK, HSCIF2_HTX_MARK, I2C1_SDA_B_MARK, D10_MARK,
 376         HSCIF2_HSCK_MARK, SCIF1_SCK_C_MARK, IRQ6_MARK, PWM5_C_MARK,
 377         D11_MARK, HSCIF2_HCTS_N_MARK, SCIF1_RXD_C_MARK, I2C1_SCL_D_MARK,
 378         D12_MARK, HSCIF2_HRTS_N_MARK, SCIF1_TXD_C_MARK, I2C1_SDA_D_MARK,
 379         D13_MARK, SCIFA1_SCK_MARK, TANS1_MARK, PWM2_C_MARK, TCLK2_B_MARK,
 380         D14_MARK, SCIFA1_RXD_MARK, IIC0_SCL_B_MARK, D15_MARK, SCIFA1_TXD_MARK,
 381         IIC0_SDA_B_MARK, A0_MARK, SCIFB1_SCK_MARK, PWM3_B_MARK, A1_MARK,
 382         SCIFB1_TXD_MARK, A3_MARK, SCIFB0_SCK_MARK, A4_MARK, SCIFB0_TXD_MARK,
 383         A5_MARK, SCIFB0_RXD_MARK, PWM4_B_MARK, TPUTO3_C_MARK, A6_MARK,
 384         SCIFB0_CTS_N_MARK, SCIFA4_RXD_B_MARK, TPUTO2_C_MARK,
 385
 386         /* IPSR2 */
 387         A7_MARK, SCIFB0_RTS_N_MARK, SCIFA4_TXD_B_MARK, A8_MARK, MSIOF1_RXD_MARK,
 388         SCIFA0_RXD_B_MARK, A9_MARK, MSIOF1_TXD_MARK, SCIFA0_TXD_B_MARK,
 389         A10_MARK, MSIOF1_SCK_MARK, IIC1_SCL_B_MARK, A11_MARK, MSIOF1_SYNC_MARK,
 390         IIC1_SDA_B_MARK, A12_MARK, MSIOF1_SS1_MARK, SCIFA5_RXD_B_MARK,
 391         A13_MARK, MSIOF1_SS2_MARK, SCIFA5_TXD_B_MARK, A14_MARK, MSIOF2_RXD_MARK,
 392         HSCIF0_HRX_B_MARK, DREQ1_N_MARK, A15_MARK, MSIOF2_TXD_MARK,
 393         HSCIF0_HTX_B_MARK, DACK1_MARK, A16_MARK, MSIOF2_SCK_MARK,
 394         HSCIF0_HSCK_B_MARK, SPEEDIN_MARK, VSP_MARK, CAN_CLK_C_MARK,
 395         TPUTO2_B_MARK, A17_MARK, MSIOF2_SYNC_MARK, SCIF4_RXD_E_MARK,
 396         CAN1_RX_B_MARK, AVB_AVTP_CAPTURE_B_MARK, A18_MARK, MSIOF2_SS1_MARK,
 397         SCIF4_TXD_E_MARK, CAN1_TX_B_MARK, AVB_AVTP_MATCH_B_MARK, A19_MARK,
 398         MSIOF2_SS2_MARK, PWM4_MARK, TPUTO2_MARK, MOUT0_MARK, A20_MARK,
 399         SPCLK_MARK, MOUT1_MARK,
 400
 401         /* IPSR3 */
 402         A21_MARK, MOSI_IO0_MARK, MOUT2_MARK, A22_MARK, MISO_IO1_MARK,
 403         MOUT5_MARK, ATADIR1_N_MARK, A23_MARK, IO2_MARK, MOUT6_MARK,
 404         ATAWR1_N_MARK, A24_MARK, IO3_MARK, EX_WAIT2_MARK, A25_MARK, SSL_MARK,
 405         ATARD1_N_MARK, CS0_N_MARK, VI1_DATA8_MARK, CS1_N_A26_MARK,
 406         VI1_DATA9_MARK, EX_CS0_N_MARK, VI1_DATA10_MARK, EX_CS1_N_MARK,
 407         TPUTO3_B_MARK, SCIFB2_RXD_MARK, VI1_DATA11_MARK, EX_CS2_N_MARK,
 408         PWM0_MARK, SCIF4_RXD_C_MARK, TS_SDATA_B_MARK, RIF0_SYNC_MARK,
 409         TPUTO3_MARK, SCIFB2_TXD_MARK, SDATA_B_MARK, EX_CS3_N_MARK,
 410         SCIFA2_SCK_MARK, SCIF4_TXD_C_MARK, TS_SCK_B_MARK, RIF0_CLK_MARK,
 411         BPFCLK_MARK, SCIFB2_SCK_MARK, MDATA_B_MARK, EX_CS4_N_MARK,
 412         SCIFA2_RXD_MARK, I2C2_SCL_E_MARK, TS_SDEN_B_MARK, RIF0_D0_MARK,
 413         FMCLK_MARK, SCIFB2_CTS_N_MARK, SCKZ_B_MARK, EX_CS5_N_MARK,
 414         SCIFA2_TXD_MARK, I2C2_SDA_E_MARK, TS_SPSYNC_B_MARK, RIF0_D1_MARK,
 415         FMIN_MARK, SCIFB2_RTS_N_MARK, STM_N_B_MARK, BS_N_MARK, DRACK0_MARK,
 416         PWM1_C_MARK, TPUTO0_C_MARK, ATACS01_N_MARK, MTS_N_B_MARK, RD_N_MARK,
 417         ATACS11_N_MARK, RD_WR_N_MARK, ATAG1_N_MARK,
 418
 419         /* IPSR4 */
 420         EX_WAIT0_MARK, CAN_CLK_B_MARK, SCIF_CLK_MARK, PWMFSW0_MARK,
 421         DU0_DR0_MARK, LCDOUT16_MARK, SCIF5_RXD_C_MARK, I2C2_SCL_D_MARK,
 422         CC50_STATE0_MARK, DU0_DR1_MARK, LCDOUT17_MARK, SCIF5_TXD_C_MARK,
 423         I2C2_SDA_D_MARK, CC50_STATE1_MARK, DU0_DR2_MARK, LCDOUT18_MARK,
 424         CC50_STATE2_MARK, DU0_DR3_MARK, LCDOUT19_MARK, CC50_STATE3_MARK,
 425         DU0_DR4_MARK, LCDOUT20_MARK, CC50_STATE4_MARK, DU0_DR5_MARK,
 426         LCDOUT21_MARK, CC50_STATE5_MARK, DU0_DR6_MARK, LCDOUT22_MARK,
 427         CC50_STATE6_MARK, DU0_DR7_MARK, LCDOUT23_MARK, CC50_STATE7_MARK,
 428         DU0_DG0_MARK, LCDOUT8_MARK, SCIFA0_RXD_C_MARK, I2C3_SCL_D_MARK,
 429         CC50_STATE8_MARK, DU0_DG1_MARK, LCDOUT9_MARK, SCIFA0_TXD_C_MARK,
 430         I2C3_SDA_D_MARK, CC50_STATE9_MARK, DU0_DG2_MARK, LCDOUT10_MARK,
 431         CC50_STATE10_MARK, DU0_DG3_MARK, LCDOUT11_MARK, CC50_STATE11_MARK,
 432         DU0_DG4_MARK, LCDOUT12_MARK, CC50_STATE12_MARK,
 433
 434         /* IPSR5 */
 435         DU0_DG5_MARK, LCDOUT13_MARK, CC50_STATE13_MARK, DU0_DG6_MARK,
 436         LCDOUT14_MARK, CC50_STATE14_MARK, DU0_DG7_MARK, LCDOUT15_MARK,
 437         CC50_STATE15_MARK, DU0_DB0_MARK, LCDOUT0_MARK, SCIFA4_RXD_C_MARK,
 438         I2C4_SCL_D_MARK, CAN0_RX_C_MARK, CC50_STATE16_MARK, DU0_DB1_MARK,
 439         LCDOUT1_MARK, SCIFA4_TXD_C_MARK, I2C4_SDA_D_MARK, CAN0_TX_C_MARK,
 440         CC50_STATE17_MARK, DU0_DB2_MARK, LCDOUT2_MARK, CC50_STATE18_MARK,
 441         DU0_DB3_MARK, LCDOUT3_MARK, CC50_STATE19_MARK, DU0_DB4_MARK,
 442         LCDOUT4_MARK, CC50_STATE20_MARK, DU0_DB5_MARK, LCDOUT5_MARK,
 443         CC50_STATE21_MARK, DU0_DB6_MARK, LCDOUT6_MARK, CC50_STATE22_MARK,
 444         DU0_DB7_MARK, LCDOUT7_MARK, CC50_STATE23_MARK, DU0_DOTCLKIN_MARK,
 445         QSTVA_QVS_MARK, CC50_STATE24_MARK, DU0_DOTCLKOUT0_MARK,
 446         QCLK_MARK, CC50_STATE25_MARK, DU0_DOTCLKOUT1_MARK, QSTVB_QVE_MARK,
 447         CC50_STATE26_MARK, DU0_EXHSYNC_DU0_HSYNC_MARK, QSTH_QHS_MARK,
 448         CC50_STATE27_MARK,
 449
 450         /* IPSR6 */
 451         DU0_EXVSYNC_DU0_VSYNC_MARK, QSTB_QHE_MARK, CC50_STATE28_MARK,
 452         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK, CC50_STATE29_MARK,
 453         DU0_DISP_MARK, QPOLA_MARK, CC50_STATE30_MARK, DU0_CDE_MARK, QPOLB_MARK,
 454         CC50_STATE31_MARK, VI0_CLK_MARK, AVB_RX_CLK_MARK, VI0_DATA0_VI0_B0_MARK,
 455         AVB_RX_DV_MARK, VI0_DATA1_VI0_B1_MARK, AVB_RXD0_MARK,
 456         VI0_DATA2_VI0_B2_MARK, AVB_RXD1_MARK, VI0_DATA3_VI0_B3_MARK,
 457         AVB_RXD2_MARK, VI0_DATA4_VI0_B4_MARK, AVB_RXD3_MARK,
 458         VI0_DATA5_VI0_B5_MARK, AVB_RXD4_MARK, VI0_DATA6_VI0_B6_MARK,
 459         AVB_RXD5_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RXD6_MARK, VI0_CLKENB_MARK,
 460         I2C3_SCL_MARK, SCIFA5_RXD_C_MARK, IETX_C_MARK, AVB_RXD7_MARK,
 461         VI0_FIELD_MARK, I2C3_SDA_MARK, SCIFA5_TXD_C_MARK, IECLK_C_MARK,
 462         AVB_RX_ER_MARK, VI0_HSYNC_N_MARK, SCIF0_RXD_B_MARK, I2C0_SCL_C_MARK,
 463         IERX_C_MARK, AVB_COL_MARK, VI0_VSYNC_N_MARK, SCIF0_TXD_B_MARK,
 464         I2C0_SDA_C_MARK, AUDIO_CLKOUT_B_MARK, AVB_TX_EN_MARK, ETH_MDIO_MARK,
 465         VI0_G0_MARK, MSIOF2_RXD_B_MARK, IIC0_SCL_D_MARK, AVB_TX_CLK_MARK,
 466         ADIDATA_MARK, AD_DI_MARK,
 467
 468         /* IPSR7 */
 469         ETH_CRS_DV_MARK, VI0_G1_MARK, MSIOF2_TXD_B_MARK, IIC0_SDA_D_MARK,
 470         AVB_TXD0_MARK, ADICS_SAMP_MARK, AD_DO_MARK, ETH_RX_ER_MARK, VI0_G2_MARK,
 471         MSIOF2_SCK_B_MARK, CAN0_RX_B_MARK, AVB_TXD1_MARK, ADICLK_MARK,
 472         AD_CLK_MARK, ETH_RXD0_MARK, VI0_G3_MARK, MSIOF2_SYNC_B_MARK,
 473         CAN0_TX_B_MARK, AVB_TXD2_MARK, ADICHS0_MARK, AD_NCS_N_MARK,
 474         ETH_RXD1_MARK, VI0_G4_MARK, MSIOF2_SS1_B_MARK, SCIF4_RXD_D_MARK,
 475         AVB_TXD3_MARK, ADICHS1_MARK, ETH_LINK_MARK, VI0_G5_MARK,
 476         MSIOF2_SS2_B_MARK, SCIF4_TXD_D_MARK, AVB_TXD4_MARK, ADICHS2_MARK,
 477         ETH_REFCLK_MARK, VI0_G6_MARK, SCIF2_SCK_C_MARK, AVB_TXD5_MARK,
 478         SSI_SCK5_B_MARK, ETH_TXD1_MARK, VI0_G7_MARK, SCIF2_RXD_C_MARK,
 479         IIC1_SCL_D_MARK, AVB_TXD6_MARK, SSI_WS5_B_MARK, ETH_TX_EN_MARK,
 480         VI0_R0_MARK, SCIF2_TXD_C_MARK, IIC1_SDA_D_MARK, AVB_TXD7_MARK,
 481         SSI_SDATA5_B_MARK, ETH_MAGIC_MARK, VI0_R1_MARK, SCIF3_SCK_B_MARK,
 482         AVB_TX_ER_MARK, SSI_SCK6_B_MARK, ETH_TXD0_MARK, VI0_R2_MARK,
 483         SCIF3_RXD_B_MARK, I2C4_SCL_E_MARK, AVB_GTX_CLK_MARK, SSI_WS6_B_MARK,
 484         DREQ0_N_MARK, SCIFB1_RXD_MARK,
 485
 486         /* IPSR8 */
 487         ETH_MDC_MARK, VI0_R3_MARK, SCIF3_TXD_B_MARK, I2C4_SDA_E_MARK,
 488         AVB_MDC_MARK, SSI_SDATA6_B_MARK, HSCIF0_HRX_MARK, VI0_R4_MARK,
 489         I2C1_SCL_C_MARK, AUDIO_CLKA_B_MARK, AVB_MDIO_MARK, SSI_SCK78_B_MARK,
 490         HSCIF0_HTX_MARK, VI0_R5_MARK, I2C1_SDA_C_MARK, AUDIO_CLKB_B_MARK,
 491         AVB_LINK_MARK, SSI_WS78_B_MARK, HSCIF0_HCTS_N_MARK, VI0_R6_MARK,
 492         SCIF0_RXD_D_MARK, I2C0_SCL_E_MARK, AVB_MAGIC_MARK, SSI_SDATA7_B_MARK,
 493         HSCIF0_HRTS_N_MARK, VI0_R7_MARK, SCIF0_TXD_D_MARK, I2C0_SDA_E_MARK,
 494         AVB_PHY_INT_MARK, SSI_SDATA8_B_MARK,
 495         HSCIF0_HSCK_MARK, SCIF_CLK_B_MARK, AVB_CRS_MARK, AUDIO_CLKC_B_MARK,
 496         I2C0_SCL_MARK, SCIF0_RXD_C_MARK, PWM5_MARK, TCLK1_B_MARK,
 497         AVB_GTXREFCLK_MARK, CAN1_RX_D_MARK, TPUTO0_B_MARK, I2C0_SDA_MARK,
 498         SCIF0_TXD_C_MARK, TPUTO0_MARK, CAN_CLK_MARK, DVC_MUTE_MARK,
 499         CAN1_TX_D_MARK, I2C1_SCL_MARK, SCIF4_RXD_MARK, PWM5_B_MARK,
 500         DU1_DR0_MARK, RIF1_SYNC_B_MARK, TS_SDATA_D_MARK, TPUTO1_B_MARK,
 501         I2C1_SDA_MARK, SCIF4_TXD_MARK, IRQ5_MARK, DU1_DR1_MARK, RIF1_CLK_B_MARK,
 502         TS_SCK_D_MARK, BPFCLK_C_MARK, MSIOF0_RXD_MARK, SCIF5_RXD_MARK,
 503         I2C2_SCL_C_MARK, DU1_DR2_MARK, RIF1_D0_B_MARK, TS_SDEN_D_MARK,
 504         FMCLK_C_MARK, RDS_CLK_MARK,
 505
 506         /* IPSR9 */
 507         MSIOF0_TXD_MARK, SCIF5_TXD_MARK, I2C2_SDA_C_MARK, DU1_DR3_MARK,
 508         RIF1_D1_B_MARK, TS_SPSYNC_D_MARK, FMIN_C_MARK, RDS_DATA_MARK,
 509         MSIOF0_SCK_MARK, IRQ0_MARK, TS_SDATA_MARK, DU1_DR4_MARK, RIF1_SYNC_MARK,
 510         TPUTO1_C_MARK, MSIOF0_SYNC_MARK, PWM1_MARK, TS_SCK_MARK, DU1_DR5_MARK,
 511         RIF1_CLK_MARK, BPFCLK_B_MARK, MSIOF0_SS1_MARK, SCIFA0_RXD_MARK,
 512         TS_SDEN_MARK, DU1_DR6_MARK, RIF1_D0_MARK, FMCLK_B_MARK, RDS_CLK_B_MARK,
 513         MSIOF0_SS2_MARK, SCIFA0_TXD_MARK, TS_SPSYNC_MARK, DU1_DR7_MARK,
 514         RIF1_D1_MARK, FMIN_B_MARK, RDS_DATA_B_MARK, HSCIF1_HRX_MARK,
 515         I2C4_SCL_MARK, PWM6_MARK, DU1_DG0_MARK, HSCIF1_HTX_MARK,
 516         I2C4_SDA_MARK, TPUTO1_MARK, DU1_DG1_MARK, HSCIF1_HSCK_MARK,
 517         PWM2_MARK, IETX_MARK, DU1_DG2_MARK, REMOCON_B_MARK, SPEEDIN_B_MARK,
 518         VSP_B_MARK, HSCIF1_HCTS_N_MARK, SCIFA4_RXD_MARK, IECLK_MARK,
 519         DU1_DG3_MARK, SSI_SCK1_B_MARK, CAN_DEBUG_HW_TRIGGER_MARK,
 520         CC50_STATE32_MARK, HSCIF1_HRTS_N_MARK, SCIFA4_TXD_MARK, IERX_MARK,
 521         DU1_DG4_MARK, SSI_WS1_B_MARK, CAN_STEP0_MARK, CC50_STATE33_MARK,
 522         SCIF1_SCK_MARK, PWM3_MARK, TCLK2_MARK, DU1_DG5_MARK, SSI_SDATA1_B_MARK,
 523         CAN_TXCLK_MARK, CC50_STATE34_MARK,
 524
 525         /* IPSR10 */
 526         SCIF1_RXD_MARK, IIC0_SCL_MARK, DU1_DG6_MARK, SSI_SCK2_B_MARK,
 527         CAN_DEBUGOUT0_MARK, CC50_STATE35_MARK, SCIF1_TXD_MARK, IIC0_SDA_MARK,
 528         DU1_DG7_MARK, SSI_WS2_B_MARK, CAN_DEBUGOUT1_MARK, CC50_STATE36_MARK,
 529         SCIF2_RXD_MARK, IIC1_SCL_MARK, DU1_DB0_MARK, SSI_SDATA2_B_MARK,
 530         USB0_EXTLP_MARK, CAN_DEBUGOUT2_MARK, CC50_STATE37_MARK, SCIF2_TXD_MARK,
 531         IIC1_SDA_MARK, DU1_DB1_MARK, SSI_SCK9_B_MARK, USB0_OVC1_MARK,
 532         CAN_DEBUGOUT3_MARK, CC50_STATE38_MARK, SCIF2_SCK_MARK, IRQ1_MARK,
 533         DU1_DB2_MARK, SSI_WS9_B_MARK, USB0_IDIN_MARK, CAN_DEBUGOUT4_MARK,
 534         CC50_STATE39_MARK, SCIF3_SCK_MARK, IRQ2_MARK, BPFCLK_D_MARK,
 535         DU1_DB3_MARK, SSI_SDATA9_B_MARK, TANS2_MARK, CAN_DEBUGOUT5_MARK,
 536         CC50_OSCOUT_MARK, SCIF3_RXD_MARK, I2C1_SCL_E_MARK, FMCLK_D_MARK,
 537         DU1_DB4_MARK, AUDIO_CLKA_C_MARK, SSI_SCK4_B_MARK, CAN_DEBUGOUT6_MARK,
 538         RDS_CLK_C_MARK, SCIF3_TXD_MARK, I2C1_SDA_E_MARK, FMIN_D_MARK,
 539         DU1_DB5_MARK, AUDIO_CLKB_C_MARK, SSI_WS4_B_MARK, CAN_DEBUGOUT7_MARK,
 540         RDS_DATA_C_MARK, I2C2_SCL_MARK, SCIFA5_RXD_MARK, DU1_DB6_MARK,
 541         AUDIO_CLKC_C_MARK, SSI_SDATA4_B_MARK, CAN_DEBUGOUT8_MARK, I2C2_SDA_MARK,
 542         SCIFA5_TXD_MARK, DU1_DB7_MARK, AUDIO_CLKOUT_C_MARK, CAN_DEBUGOUT9_MARK,
 543         SSI_SCK5_MARK, SCIFA3_SCK_MARK, DU1_DOTCLKIN_MARK, CAN_DEBUGOUT10_MARK,
 544
 545         /* IPSR11 */
 546         SSI_WS5_MARK, SCIFA3_RXD_MARK, I2C3_SCL_C_MARK, DU1_DOTCLKOUT0_MARK,
 547         CAN_DEBUGOUT11_MARK, SSI_SDATA5_MARK, SCIFA3_TXD_MARK, I2C3_SDA_C_MARK,
 548         DU1_DOTCLKOUT1_MARK, CAN_DEBUGOUT12_MARK, SSI_SCK6_MARK,
 549         SCIFA1_SCK_B_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK, CAN_DEBUGOUT13_MARK,
 550         SSI_WS6_MARK, SCIFA1_RXD_B_MARK, I2C4_SCL_C_MARK,
 551         DU1_EXVSYNC_DU1_VSYNC_MARK, CAN_DEBUGOUT14_MARK, SSI_SDATA6_MARK,
 552         SCIFA1_TXD_B_MARK, I2C4_SDA_C_MARK, DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
 553         CAN_DEBUGOUT15_MARK, SSI_SCK78_MARK, SCIFA2_SCK_B_MARK, IIC0_SDA_C_MARK,
 554         DU1_DISP_MARK, SSI_WS78_MARK, SCIFA2_RXD_B_MARK, IIC0_SCL_C_MARK,
 555         DU1_CDE_MARK, SSI_SDATA7_MARK, SCIFA2_TXD_B_MARK, IRQ8_MARK,
 556         AUDIO_CLKA_D_MARK, CAN_CLK_D_MARK, PCMOE_N_MARK, SSI_SCK0129_MARK,
 557         MSIOF1_RXD_B_MARK, SCIF5_RXD_D_MARK, ADIDATA_B_MARK, AD_DI_B_MARK,
 558         PCMWE_N_MARK, SSI_WS0129_MARK, MSIOF1_TXD_B_MARK, SCIF5_TXD_D_MARK,
 559         ADICS_SAMP_B_MARK, AD_DO_B_MARK, SSI_SDATA0_MARK, MSIOF1_SCK_B_MARK,
 560         PWM0_B_MARK, ADICLK_B_MARK, AD_CLK_B_MARK,
 561
 562         /* IPSR12 */
 563         SSI_SCK34_MARK, MSIOF1_SYNC_B_MARK, SCIFA1_SCK_C_MARK, ADICHS0_B_MARK,
 564         AD_NCS_N_B_MARK, DREQ1_N_B_MARK, SSI_WS34_MARK, MSIOF1_SS1_B_MARK,
 565         SCIFA1_RXD_C_MARK, ADICHS1_B_MARK, CAN1_RX_C_MARK, DACK1_B_MARK,
 566         SSI_SDATA3_MARK, MSIOF1_SS2_B_MARK, SCIFA1_TXD_C_MARK, ADICHS2_B_MARK,
 567         CAN1_TX_C_MARK, DREQ2_N_MARK, SSI_SCK4_MARK, MLB_CLK_MARK, IETX_B_MARK,
 568         IRD_TX_MARK, SSI_WS4_MARK, MLB_SIG_MARK, IECLK_B_MARK, IRD_RX_MARK,
 569         SSI_SDATA4_MARK, MLB_DAT_MARK, IERX_B_MARK, IRD_SCK_MARK,
 570         SSI_SDATA8_MARK, SCIF1_SCK_B_MARK, PWM1_B_MARK, IRQ9_MARK, REMOCON_MARK,
 571         DACK2_MARK, ETH_MDIO_B_MARK, SSI_SCK1_MARK, SCIF1_RXD_B_MARK,
 572         IIC1_SCL_C_MARK, VI1_CLK_MARK, CAN0_RX_D_MARK, AVB_AVTP_CAPTURE_MARK,
 573         ETH_CRS_DV_B_MARK, SSI_WS1_MARK, SCIF1_TXD_B_MARK, IIC1_SDA_C_MARK,
 574         VI1_DATA0_MARK, CAN0_TX_D_MARK, AVB_AVTP_MATCH_MARK, ETH_RX_ER_B_MARK,
 575         SSI_SDATA1_MARK, HSCIF1_HRX_B_MARK, VI1_DATA1_MARK, SDATA_MARK,
 576         ATAG0_N_MARK, ETH_RXD0_B_MARK, SSI_SCK2_MARK, HSCIF1_HTX_B_MARK,
 577         VI1_DATA2_MARK, MDATA_MARK, ATAWR0_N_MARK, ETH_RXD1_B_MARK,
 578
 579         /* IPSR13 */
 580         SSI_WS2_MARK, HSCIF1_HCTS_N_B_MARK, SCIFA0_RXD_D_MARK, VI1_DATA3_MARK,
 581         SCKZ_MARK, ATACS00_N_MARK, ETH_LINK_B_MARK, SSI_SDATA2_MARK,
 582         HSCIF1_HRTS_N_B_MARK, SCIFA0_TXD_D_MARK, VI1_DATA4_MARK, STM_N_MARK,
 583         ATACS10_N_MARK, ETH_REFCLK_B_MARK, SSI_SCK9_MARK, SCIF2_SCK_B_MARK,
 584         PWM2_B_MARK, VI1_DATA5_MARK, MTS_N_MARK, EX_WAIT1_MARK,
 585         ETH_TXD1_B_MARK, SSI_WS9_MARK, SCIF2_RXD_B_MARK, I2C3_SCL_E_MARK,
 586         VI1_DATA6_MARK, ATARD0_N_MARK, ETH_TX_EN_B_MARK, SSI_SDATA9_MARK,
 587         SCIF2_TXD_B_MARK, I2C3_SDA_E_MARK, VI1_DATA7_MARK, ATADIR0_N_MARK,
 588         ETH_MAGIC_B_MARK, AUDIO_CLKA_MARK, I2C0_SCL_B_MARK, SCIFA4_RXD_D_MARK,
 589         VI1_CLKENB_MARK, TS_SDATA_C_MARK, RIF0_SYNC_B_MARK, ETH_TXD0_B_MARK,
 590         AUDIO_CLKB_MARK, I2C0_SDA_B_MARK, SCIFA4_TXD_D_MARK, VI1_FIELD_MARK,
 591         TS_SCK_C_MARK, RIF0_CLK_B_MARK, BPFCLK_E_MARK, ETH_MDC_B_MARK,
 592         AUDIO_CLKC_MARK, I2C4_SCL_B_MARK, SCIFA5_RXD_D_MARK, VI1_HSYNC_N_MARK,
 593         TS_SDEN_C_MARK, RIF0_D0_B_MARK, FMCLK_E_MARK, RDS_CLK_D_MARK,
 594         AUDIO_CLKOUT_MARK, I2C4_SDA_B_MARK, SCIFA5_TXD_D_MARK, VI1_VSYNC_N_MARK,
 595         TS_SPSYNC_C_MARK, RIF0_D1_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK,
 596         PINMUX_MARK_END,
 597 };
 598
 599 static const u16 pinmux_data[] = {
 600         PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
 601
 602         PINMUX_SINGLE(A2),
 603         PINMUX_SINGLE(WE0_N),
 604         PINMUX_SINGLE(WE1_N),
 605         PINMUX_SINGLE(DACK0),
 606         PINMUX_SINGLE(USB0_PWEN),
 607         PINMUX_SINGLE(USB0_OVC),
 608         PINMUX_SINGLE(USB1_PWEN),
 609         PINMUX_SINGLE(USB1_OVC),
 610         PINMUX_SINGLE(SD0_CLK),
 611         PINMUX_SINGLE(SD0_CMD),
 612         PINMUX_SINGLE(SD0_DATA0),
 613         PINMUX_SINGLE(SD0_DATA1),
 614         PINMUX_SINGLE(SD0_DATA2),
 615         PINMUX_SINGLE(SD0_DATA3),
 616         PINMUX_SINGLE(SD0_CD),
 617         PINMUX_SINGLE(SD0_WP),
 618         PINMUX_SINGLE(SD1_CLK),
 619         PINMUX_SINGLE(SD1_CMD),
 620         PINMUX_SINGLE(SD1_DATA0),
 621         PINMUX_SINGLE(SD1_DATA1),
 622         PINMUX_SINGLE(SD1_DATA2),
 623         PINMUX_SINGLE(SD1_DATA3),
 624
 625         /* IPSR0 */
 626         PINMUX_IPSR_GPSR(IP0_0, SD1_CD),
 627         PINMUX_IPSR_MSEL(IP0_0, CAN0_RX, SEL_CAN0_0),
 628         PINMUX_IPSR_GPSR(IP0_9_8, SD1_WP),
 629         PINMUX_IPSR_GPSR(IP0_9_8, IRQ7),
 630         PINMUX_IPSR_MSEL(IP0_9_8, CAN0_TX, SEL_CAN0_0),
 631         PINMUX_IPSR_GPSR(IP0_10, MMC_CLK),
 632         PINMUX_IPSR_GPSR(IP0_10, SD2_CLK),
 633         PINMUX_IPSR_GPSR(IP0_11, MMC_CMD),
 634         PINMUX_IPSR_GPSR(IP0_11, SD2_CMD),
 635         PINMUX_IPSR_GPSR(IP0_12, MMC_D0),
 636         PINMUX_IPSR_GPSR(IP0_12, SD2_DATA0),
 637         PINMUX_IPSR_GPSR(IP0_13, MMC_D1),
 638         PINMUX_IPSR_GPSR(IP0_13, SD2_DATA1),
 639         PINMUX_IPSR_GPSR(IP0_14, MMC_D2),
 640         PINMUX_IPSR_GPSR(IP0_14, SD2_DATA2),
 641         PINMUX_IPSR_GPSR(IP0_15, MMC_D3),
 642         PINMUX_IPSR_GPSR(IP0_15, SD2_DATA3),
 643         PINMUX_IPSR_GPSR(IP0_16, MMC_D4),
 644         PINMUX_IPSR_GPSR(IP0_16, SD2_CD),
 645         PINMUX_IPSR_GPSR(IP0_17, MMC_D5),
 646         PINMUX_IPSR_GPSR(IP0_17, SD2_WP),
 647         PINMUX_IPSR_GPSR(IP0_19_18, MMC_D6),
 648         PINMUX_IPSR_MSEL(IP0_19_18, SCIF0_RXD, SEL_SCIF0_0),
 649         PINMUX_IPSR_MSEL(IP0_19_18, I2C2_SCL_B, SEL_I2C02_1),
 650         PINMUX_IPSR_MSEL(IP0_19_18, CAN1_RX, SEL_CAN1_0),
 651         PINMUX_IPSR_GPSR(IP0_21_20, MMC_D7),
 652         PINMUX_IPSR_MSEL(IP0_21_20, SCIF0_TXD, SEL_SCIF0_0),
 653         PINMUX_IPSR_MSEL(IP0_21_20, I2C2_SDA_B, SEL_I2C02_1),
 654         PINMUX_IPSR_MSEL(IP0_21_20, CAN1_TX, SEL_CAN1_0),
 655         PINMUX_IPSR_GPSR(IP0_23_22, D0),
 656         PINMUX_IPSR_MSEL(IP0_23_22, SCIFA3_SCK_B, SEL_SCIFA3_1),
 657         PINMUX_IPSR_GPSR(IP0_23_22, IRQ4),
 658         PINMUX_IPSR_GPSR(IP0_24, D1),
 659         PINMUX_IPSR_MSEL(IP0_24, SCIFA3_RXD_B, SEL_SCIFA3_1),
 660         PINMUX_IPSR_GPSR(IP0_25, D2),
 661         PINMUX_IPSR_MSEL(IP0_25, SCIFA3_TXD_B, SEL_SCIFA3_1),
 662         PINMUX_IPSR_GPSR(IP0_27_26, D3),
 663         PINMUX_IPSR_MSEL(IP0_27_26, I2C3_SCL_B, SEL_I2C03_1),
 664         PINMUX_IPSR_MSEL(IP0_27_26, SCIF5_RXD_B, SEL_SCIF5_1),
 665         PINMUX_IPSR_GPSR(IP0_29_28, D4),
 666         PINMUX_IPSR_MSEL(IP0_29_28, I2C3_SDA_B, SEL_I2C03_1),
 667         PINMUX_IPSR_MSEL(IP0_29_28, SCIF5_TXD_B, SEL_SCIF5_1),
 668         PINMUX_IPSR_GPSR(IP0_31_30, D5),
 669         PINMUX_IPSR_MSEL(IP0_31_30, SCIF4_RXD_B, SEL_SCIF4_1),
 670         PINMUX_IPSR_MSEL(IP0_31_30, I2C0_SCL_D, SEL_I2C00_3),
 671
 672         /* IPSR1 */
 673         PINMUX_IPSR_GPSR(IP1_1_0, D6),
 674         PINMUX_IPSR_MSEL(IP1_1_0, SCIF4_TXD_B, SEL_SCIF4_1),
 675         PINMUX_IPSR_MSEL(IP1_1_0, I2C0_SDA_D, SEL_I2C00_3),
 676         PINMUX_IPSR_GPSR(IP1_3_2, D7),
 677         PINMUX_IPSR_GPSR(IP1_3_2, IRQ3),
 678         PINMUX_IPSR_MSEL(IP1_3_2, TCLK1, SEL_TMU_0),
 679         PINMUX_IPSR_GPSR(IP1_3_2, PWM6_B),
 680         PINMUX_IPSR_GPSR(IP1_5_4, D8),
 681         PINMUX_IPSR_GPSR(IP1_5_4, HSCIF2_HRX),
 682         PINMUX_IPSR_MSEL(IP1_5_4, I2C1_SCL_B, SEL_I2C01_1),
 683         PINMUX_IPSR_GPSR(IP1_7_6, D9),
 684         PINMUX_IPSR_GPSR(IP1_7_6, HSCIF2_HTX),
 685         PINMUX_IPSR_MSEL(IP1_7_6, I2C1_SDA_B, SEL_I2C01_1),
 686         PINMUX_IPSR_GPSR(IP1_10_8, D10),
 687         PINMUX_IPSR_GPSR(IP1_10_8, HSCIF2_HSCK),
 688         PINMUX_IPSR_MSEL(IP1_10_8, SCIF1_SCK_C, SEL_SCIF1_2),
 689         PINMUX_IPSR_GPSR(IP1_10_8, IRQ6),
 690         PINMUX_IPSR_GPSR(IP1_10_8, PWM5_C),
 691         PINMUX_IPSR_GPSR(IP1_12_11, D11),
 692         PINMUX_IPSR_GPSR(IP1_12_11, HSCIF2_HCTS_N),
 693         PINMUX_IPSR_MSEL(IP1_12_11, SCIF1_RXD_C, SEL_SCIF1_2),
 694         PINMUX_IPSR_MSEL(IP1_12_11, I2C1_SCL_D, SEL_I2C01_3),
 695         PINMUX_IPSR_GPSR(IP1_14_13, D12),
 696         PINMUX_IPSR_GPSR(IP1_14_13, HSCIF2_HRTS_N),
 697         PINMUX_IPSR_MSEL(IP1_14_13, SCIF1_TXD_C, SEL_SCIF1_2),
 698         PINMUX_IPSR_MSEL(IP1_14_13, I2C1_SDA_D, SEL_I2C01_3),
 699         PINMUX_IPSR_GPSR(IP1_17_15, D13),
 700         PINMUX_IPSR_MSEL(IP1_17_15, SCIFA1_SCK, SEL_SCIFA1_0),
 701         PINMUX_IPSR_GPSR(IP1_17_15, TANS1),
 702         PINMUX_IPSR_GPSR(IP1_17_15, PWM2_C),
 703         PINMUX_IPSR_MSEL(IP1_17_15, TCLK2_B, SEL_TMU_1),
 704         PINMUX_IPSR_GPSR(IP1_19_18, D14),
 705         PINMUX_IPSR_MSEL(IP1_19_18, SCIFA1_RXD, SEL_SCIFA1_0),
 706         PINMUX_IPSR_MSEL(IP1_19_18, IIC0_SCL_B, SEL_IIC00_1),
 707         PINMUX_IPSR_GPSR(IP1_21_20, D15),
 708         PINMUX_IPSR_MSEL(IP1_21_20, SCIFA1_TXD, SEL_SCIFA1_0),
 709         PINMUX_IPSR_MSEL(IP1_21_20, IIC0_SDA_B, SEL_IIC00_1),
 710         PINMUX_IPSR_GPSR(IP1_23_22, A0),
 711         PINMUX_IPSR_GPSR(IP1_23_22, SCIFB1_SCK),
 712         PINMUX_IPSR_GPSR(IP1_23_22, PWM3_B),
 713         PINMUX_IPSR_GPSR(IP1_24, A1),
 714         PINMUX_IPSR_GPSR(IP1_24, SCIFB1_TXD),
 715         PINMUX_IPSR_GPSR(IP1_26, A3),
 716         PINMUX_IPSR_GPSR(IP1_26, SCIFB0_SCK),
 717         PINMUX_IPSR_GPSR(IP1_27, A4),
 718         PINMUX_IPSR_GPSR(IP1_27, SCIFB0_TXD),
 719         PINMUX_IPSR_GPSR(IP1_29_28, A5),
 720         PINMUX_IPSR_GPSR(IP1_29_28, SCIFB0_RXD),
 721         PINMUX_IPSR_GPSR(IP1_29_28, PWM4_B),
 722         PINMUX_IPSR_GPSR(IP1_29_28, TPUTO3_C),
 723         PINMUX_IPSR_GPSR(IP1_31_30, A6),
 724         PINMUX_IPSR_GPSR(IP1_31_30, SCIFB0_CTS_N),
 725         PINMUX_IPSR_MSEL(IP1_31_30, SCIFA4_RXD_B, SEL_SCIFA4_1),
 726         PINMUX_IPSR_GPSR(IP1_31_30, TPUTO2_C),
 727
 728         /* IPSR2 */
 729         PINMUX_IPSR_GPSR(IP2_1_0, A7),
 730         PINMUX_IPSR_GPSR(IP2_1_0, SCIFB0_RTS_N),
 731         PINMUX_IPSR_MSEL(IP2_1_0, SCIFA4_TXD_B, SEL_SCIFA4_1),
 732         PINMUX_IPSR_GPSR(IP2_3_2, A8),
 733         PINMUX_IPSR_MSEL(IP2_3_2, MSIOF1_RXD, SEL_MSI1_0),
 734         PINMUX_IPSR_MSEL(IP2_3_2, SCIFA0_RXD_B, SEL_SCIFA0_1),
 735         PINMUX_IPSR_GPSR(IP2_5_4, A9),
 736         PINMUX_IPSR_MSEL(IP2_5_4, MSIOF1_TXD, SEL_MSI1_0),
 737         PINMUX_IPSR_MSEL(IP2_5_4, SCIFA0_TXD_B, SEL_SCIFA0_1),
 738         PINMUX_IPSR_GPSR(IP2_7_6, A10),
 739         PINMUX_IPSR_MSEL(IP2_7_6, MSIOF1_SCK, SEL_MSI1_0),
 740         PINMUX_IPSR_MSEL(IP2_7_6, IIC1_SCL_B, SEL_IIC01_1),
 741         PINMUX_IPSR_GPSR(IP2_9_8, A11),
 742         PINMUX_IPSR_MSEL(IP2_9_8, MSIOF1_SYNC, SEL_MSI1_0),
 743         PINMUX_IPSR_MSEL(IP2_9_8, IIC1_SDA_B, SEL_IIC01_1),
 744         PINMUX_IPSR_GPSR(IP2_11_10, A12),
 745         PINMUX_IPSR_MSEL(IP2_11_10, MSIOF1_SS1, SEL_MSI1_0),
 746         PINMUX_IPSR_MSEL(IP2_11_10, SCIFA5_RXD_B, SEL_SCIFA5_1),
 747         PINMUX_IPSR_GPSR(IP2_13_12, A13),
 748         PINMUX_IPSR_MSEL(IP2_13_12, MSIOF1_SS2, SEL_MSI1_0),
 749         PINMUX_IPSR_MSEL(IP2_13_12, SCIFA5_TXD_B, SEL_SCIFA5_1),
 750         PINMUX_IPSR_GPSR(IP2_15_14, A14),
 751         PINMUX_IPSR_MSEL(IP2_15_14, MSIOF2_RXD, SEL_MSI2_0),
 752         PINMUX_IPSR_MSEL(IP2_15_14, HSCIF0_HRX_B, SEL_HSCIF0_1),
 753         PINMUX_IPSR_MSEL(IP2_15_14, DREQ1_N, SEL_LBS_0),
 754         PINMUX_IPSR_GPSR(IP2_17_16, A15),
 755         PINMUX_IPSR_MSEL(IP2_17_16, MSIOF2_TXD, SEL_MSI2_0),
 756         PINMUX_IPSR_MSEL(IP2_17_16, HSCIF0_HTX_B, SEL_HSCIF0_1),
 757         PINMUX_IPSR_MSEL(IP2_17_16, DACK1, SEL_LBS_0),
 758         PINMUX_IPSR_GPSR(IP2_20_18, A16),
 759         PINMUX_IPSR_MSEL(IP2_20_18, MSIOF2_SCK, SEL_MSI2_0),
 760         PINMUX_IPSR_MSEL(IP2_20_18, HSCIF0_HSCK_B, SEL_HSCIF0_1),
 761         PINMUX_IPSR_MSEL(IP2_20_18, SPEEDIN, SEL_RSP_0),
 762         PINMUX_IPSR_MSEL(IP2_20_18, VSP, SEL_SPDM_0),
 763         PINMUX_IPSR_MSEL(IP2_20_18, CAN_CLK_C, SEL_CAN_2),
 764         PINMUX_IPSR_GPSR(IP2_20_18, TPUTO2_B),
 765         PINMUX_IPSR_GPSR(IP2_23_21, A17),
 766         PINMUX_IPSR_MSEL(IP2_23_21, MSIOF2_SYNC, SEL_MSI2_0),
 767         PINMUX_IPSR_MSEL(IP2_23_21, SCIF4_RXD_E, SEL_SCIF4_4),
 768         PINMUX_IPSR_MSEL(IP2_23_21, CAN1_RX_B, SEL_CAN1_1),
 769         PINMUX_IPSR_MSEL(IP2_23_21, AVB_AVTP_CAPTURE_B, SEL_AVB_1),
 770         PINMUX_IPSR_GPSR(IP2_26_24, A18),
 771         PINMUX_IPSR_MSEL(IP2_26_24, MSIOF2_SS1, SEL_MSI2_0),
 772         PINMUX_IPSR_MSEL(IP2_26_24, SCIF4_TXD_E, SEL_SCIF4_4),
 773         PINMUX_IPSR_MSEL(IP2_26_24, CAN1_TX_B, SEL_CAN1_1),
 774         PINMUX_IPSR_MSEL(IP2_26_24, AVB_AVTP_MATCH_B, SEL_AVB_1),
 775         PINMUX_IPSR_GPSR(IP2_29_27, A19),
 776         PINMUX_IPSR_MSEL(IP2_29_27, MSIOF2_SS2, SEL_MSI2_0),
 777         PINMUX_IPSR_GPSR(IP2_29_27, PWM4),
 778         PINMUX_IPSR_GPSR(IP2_29_27, TPUTO2),
 779         PINMUX_IPSR_GPSR(IP2_29_27, MOUT0),
 780         PINMUX_IPSR_GPSR(IP2_31_30, A20),
 781         PINMUX_IPSR_GPSR(IP2_31_30, SPCLK),
 782         PINMUX_IPSR_GPSR(IP2_29_27, MOUT1),
 783
 784         /* IPSR3 */
 785         PINMUX_IPSR_GPSR(IP3_1_0, A21),
 786         PINMUX_IPSR_GPSR(IP3_1_0, MOSI_IO0),
 787         PINMUX_IPSR_GPSR(IP3_1_0, MOUT2),
 788         PINMUX_IPSR_GPSR(IP3_3_2, A22),
 789         PINMUX_IPSR_GPSR(IP3_3_2, MISO_IO1),
 790         PINMUX_IPSR_GPSR(IP3_3_2, MOUT5),
 791         PINMUX_IPSR_GPSR(IP3_3_2, ATADIR1_N),
 792         PINMUX_IPSR_GPSR(IP3_5_4, A23),
 793         PINMUX_IPSR_GPSR(IP3_5_4, IO2),
 794         PINMUX_IPSR_GPSR(IP3_5_4, MOUT6),
 795         PINMUX_IPSR_GPSR(IP3_5_4, ATAWR1_N),
 796         PINMUX_IPSR_GPSR(IP3_7_6, A24),
 797         PINMUX_IPSR_GPSR(IP3_7_6, IO3),
 798         PINMUX_IPSR_GPSR(IP3_7_6, EX_WAIT2),
 799         PINMUX_IPSR_GPSR(IP3_9_8, A25),
 800         PINMUX_IPSR_GPSR(IP3_9_8, SSL),
 801         PINMUX_IPSR_GPSR(IP3_9_8, ATARD1_N),
 802         PINMUX_IPSR_GPSR(IP3_10, CS0_N),
 803         PINMUX_IPSR_GPSR(IP3_10, VI1_DATA8),
 804         PINMUX_IPSR_GPSR(IP3_11, CS1_N_A26),
 805         PINMUX_IPSR_GPSR(IP3_11, VI1_DATA9),
 806         PINMUX_IPSR_GPSR(IP3_12, EX_CS0_N),
 807         PINMUX_IPSR_GPSR(IP3_12, VI1_DATA10),
 808         PINMUX_IPSR_GPSR(IP3_14_13, EX_CS1_N),
 809         PINMUX_IPSR_GPSR(IP3_14_13, TPUTO3_B),
 810         PINMUX_IPSR_GPSR(IP3_14_13, SCIFB2_RXD),
 811         PINMUX_IPSR_GPSR(IP3_14_13, VI1_DATA11),
 812         PINMUX_IPSR_GPSR(IP3_17_15, EX_CS2_N),
 813         PINMUX_IPSR_GPSR(IP3_17_15, PWM0),
 814         PINMUX_IPSR_MSEL(IP3_17_15, SCIF4_RXD_C, SEL_SCIF4_2),
 815         PINMUX_IPSR_MSEL(IP3_17_15, TS_SDATA_B, SEL_TSIF0_1),
 816         PINMUX_IPSR_MSEL(IP3_17_15, RIF0_SYNC, SEL_DR0_0),
 817         PINMUX_IPSR_GPSR(IP3_17_15, TPUTO3),
 818         PINMUX_IPSR_GPSR(IP3_17_15, SCIFB2_TXD),
 819         PINMUX_IPSR_MSEL(IP3_17_15, SDATA_B, SEL_FSN_1),
 820         PINMUX_IPSR_GPSR(IP3_20_18, EX_CS3_N),
 821         PINMUX_IPSR_MSEL(IP3_20_18, SCIFA2_SCK, SEL_SCIFA2_0),
 822         PINMUX_IPSR_MSEL(IP3_20_18, SCIF4_TXD_C, SEL_SCIF4_2),
 823         PINMUX_IPSR_MSEL(IP3_20_18, TS_SCK_B, SEL_TSIF0_1),
 824         PINMUX_IPSR_MSEL(IP3_20_18, RIF0_CLK, SEL_DR0_0),
 825         PINMUX_IPSR_MSEL(IP3_20_18, BPFCLK, SEL_DARC_0),
 826         PINMUX_IPSR_GPSR(IP3_20_18, SCIFB2_SCK),
 827         PINMUX_IPSR_MSEL(IP3_20_18, MDATA_B, SEL_FSN_1),
 828         PINMUX_IPSR_GPSR(IP3_23_21, EX_CS4_N),
 829         PINMUX_IPSR_MSEL(IP3_23_21, SCIFA2_RXD, SEL_SCIFA2_0),
 830         PINMUX_IPSR_MSEL(IP3_23_21, I2C2_SCL_E, SEL_I2C02_4),
 831         PINMUX_IPSR_MSEL(IP3_23_21, TS_SDEN_B, SEL_TSIF0_1),
 832         PINMUX_IPSR_MSEL(IP3_23_21, RIF0_D0, SEL_DR0_0),
 833         PINMUX_IPSR_MSEL(IP3_23_21, FMCLK, SEL_DARC_0),
 834         PINMUX_IPSR_GPSR(IP3_23_21, SCIFB2_CTS_N),
 835         PINMUX_IPSR_MSEL(IP3_23_21, SCKZ_B, SEL_FSN_1),
 836         PINMUX_IPSR_GPSR(IP3_26_24, EX_CS5_N),
 837         PINMUX_IPSR_MSEL(IP3_26_24, SCIFA2_TXD, SEL_SCIFA2_0),
 838         PINMUX_IPSR_MSEL(IP3_26_24, I2C2_SDA_E, SEL_I2C02_4),
 839         PINMUX_IPSR_MSEL(IP3_26_24, TS_SPSYNC_B, SEL_TSIF0_1),
 840         PINMUX_IPSR_MSEL(IP3_26_24, RIF0_D1, SEL_DR1_0),
 841         PINMUX_IPSR_MSEL(IP3_26_24, FMIN, SEL_DARC_0),
 842         PINMUX_IPSR_GPSR(IP3_26_24, SCIFB2_RTS_N),
 843         PINMUX_IPSR_MSEL(IP3_26_24, STM_N_B, SEL_FSN_1),
 844         PINMUX_IPSR_GPSR(IP3_29_27, BS_N),
 845         PINMUX_IPSR_GPSR(IP3_29_27, DRACK0),
 846         PINMUX_IPSR_GPSR(IP3_29_27, PWM1_C),
 847         PINMUX_IPSR_GPSR(IP3_29_27, TPUTO0_C),
 848         PINMUX_IPSR_GPSR(IP3_29_27, ATACS01_N),
 849         PINMUX_IPSR_MSEL(IP3_29_27, MTS_N_B, SEL_FSN_1),
 850         PINMUX_IPSR_GPSR(IP3_30, RD_N),
 851         PINMUX_IPSR_GPSR(IP3_30, ATACS11_N),
 852         PINMUX_IPSR_GPSR(IP3_31, RD_WR_N),
 853         PINMUX_IPSR_GPSR(IP3_31, ATAG1_N),
 854
 855         /* IPSR4 */
 856         PINMUX_IPSR_GPSR(IP4_1_0, EX_WAIT0),
 857         PINMUX_IPSR_MSEL(IP4_1_0, CAN_CLK_B, SEL_CAN_1),
 858         PINMUX_IPSR_MSEL(IP4_1_0, SCIF_CLK, SEL_SCIF0_0),
 859         PINMUX_IPSR_GPSR(IP4_1_0, PWMFSW0),
 860         PINMUX_IPSR_GPSR(IP4_4_2, DU0_DR0),
 861         PINMUX_IPSR_GPSR(IP4_4_2, LCDOUT16),
 862         PINMUX_IPSR_MSEL(IP4_4_2, SCIF5_RXD_C, SEL_SCIF5_2),
 863         PINMUX_IPSR_MSEL(IP4_4_2, I2C2_SCL_D, SEL_I2C02_3),
 864         PINMUX_IPSR_GPSR(IP4_4_2, CC50_STATE0),
 865         PINMUX_IPSR_GPSR(IP4_7_5, DU0_DR1),
 866         PINMUX_IPSR_GPSR(IP4_7_5, LCDOUT17),
 867         PINMUX_IPSR_MSEL(IP4_7_5, SCIF5_TXD_C, SEL_SCIF5_2),
 868         PINMUX_IPSR_MSEL(IP4_7_5, I2C2_SDA_D, SEL_I2C02_3),
 869         PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE1),
 870         PINMUX_IPSR_GPSR(IP4_9_8, DU0_DR2),
 871         PINMUX_IPSR_GPSR(IP4_9_8, LCDOUT18),
 872         PINMUX_IPSR_GPSR(IP4_9_8, CC50_STATE2),
 873         PINMUX_IPSR_GPSR(IP4_11_10, DU0_DR3),
 874         PINMUX_IPSR_GPSR(IP4_11_10, LCDOUT19),
 875         PINMUX_IPSR_GPSR(IP4_11_10, CC50_STATE3),
 876         PINMUX_IPSR_GPSR(IP4_13_12, DU0_DR4),
 877         PINMUX_IPSR_GPSR(IP4_13_12, LCDOUT20),
 878         PINMUX_IPSR_GPSR(IP4_13_12, CC50_STATE4),
 879         PINMUX_IPSR_GPSR(IP4_15_14, DU0_DR5),
 880         PINMUX_IPSR_GPSR(IP4_15_14, LCDOUT21),
 881         PINMUX_IPSR_GPSR(IP4_15_14, CC50_STATE5),
 882         PINMUX_IPSR_GPSR(IP4_17_16, DU0_DR6),
 883         PINMUX_IPSR_GPSR(IP4_17_16, LCDOUT22),
 884         PINMUX_IPSR_GPSR(IP4_17_16, CC50_STATE6),
 885         PINMUX_IPSR_GPSR(IP4_19_18, DU0_DR7),
 886         PINMUX_IPSR_GPSR(IP4_19_18, LCDOUT23),
 887         PINMUX_IPSR_GPSR(IP4_19_18, CC50_STATE7),
 888         PINMUX_IPSR_GPSR(IP4_22_20, DU0_DG0),
 889         PINMUX_IPSR_GPSR(IP4_22_20, LCDOUT8),
 890         PINMUX_IPSR_MSEL(IP4_22_20, SCIFA0_RXD_C, SEL_SCIFA0_2),
 891         PINMUX_IPSR_MSEL(IP4_22_20, I2C3_SCL_D, SEL_I2C03_3),
 892         PINMUX_IPSR_GPSR(IP4_22_20, CC50_STATE8),
 893         PINMUX_IPSR_GPSR(IP4_25_23, DU0_DG1),
 894         PINMUX_IPSR_GPSR(IP4_25_23, LCDOUT9),
 895         PINMUX_IPSR_MSEL(IP4_25_23, SCIFA0_TXD_C, SEL_SCIFA0_2),
 896         PINMUX_IPSR_MSEL(IP4_25_23, I2C3_SDA_D, SEL_I2C03_3),
 897         PINMUX_IPSR_GPSR(IP4_25_23, CC50_STATE9),
 898         PINMUX_IPSR_GPSR(IP4_27_26, DU0_DG2),
 899         PINMUX_IPSR_GPSR(IP4_27_26, LCDOUT10),
 900         PINMUX_IPSR_GPSR(IP4_27_26, CC50_STATE10),
 901         PINMUX_IPSR_GPSR(IP4_29_28, DU0_DG3),
 902         PINMUX_IPSR_GPSR(IP4_29_28, LCDOUT11),
 903         PINMUX_IPSR_GPSR(IP4_29_28, CC50_STATE11),
 904         PINMUX_IPSR_GPSR(IP4_31_30, DU0_DG4),
 905         PINMUX_IPSR_GPSR(IP4_31_30, LCDOUT12),
 906         PINMUX_IPSR_GPSR(IP4_31_30, CC50_STATE12),
 907
 908         /* IPSR5 */
 909         PINMUX_IPSR_GPSR(IP5_1_0, DU0_DG5),
 910         PINMUX_IPSR_GPSR(IP5_1_0, LCDOUT13),
 911         PINMUX_IPSR_GPSR(IP5_1_0, CC50_STATE13),
 912         PINMUX_IPSR_GPSR(IP5_3_2, DU0_DG6),
 913         PINMUX_IPSR_GPSR(IP5_3_2, LCDOUT14),
 914         PINMUX_IPSR_GPSR(IP5_3_2, CC50_STATE14),
 915         PINMUX_IPSR_GPSR(IP5_5_4, DU0_DG7),
 916         PINMUX_IPSR_GPSR(IP5_5_4, LCDOUT15),
 917         PINMUX_IPSR_GPSR(IP5_5_4, CC50_STATE15),
 918         PINMUX_IPSR_GPSR(IP5_8_6, DU0_DB0),
 919         PINMUX_IPSR_GPSR(IP5_8_6, LCDOUT0),
 920         PINMUX_IPSR_MSEL(IP5_8_6, SCIFA4_RXD_C, SEL_SCIFA4_2),
 921         PINMUX_IPSR_MSEL(IP5_8_6, I2C4_SCL_D, SEL_I2C04_3),
 922         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_RX_C, SEL_CAN0_2),
 923         PINMUX_IPSR_GPSR(IP5_8_6, CC50_STATE16),
 924         PINMUX_IPSR_GPSR(IP5_11_9, DU0_DB1),
 925         PINMUX_IPSR_GPSR(IP5_11_9, LCDOUT1),
 926         PINMUX_IPSR_MSEL(IP5_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
 927         PINMUX_IPSR_MSEL(IP5_11_9, I2C4_SDA_D, SEL_I2C04_3),
 928         PINMUX_IPSR_MSEL(IP5_11_9, CAN0_TX_C, SEL_CAN0_2),
 929         PINMUX_IPSR_GPSR(IP5_11_9, CC50_STATE17),
 930         PINMUX_IPSR_GPSR(IP5_13_12, DU0_DB2),
 931         PINMUX_IPSR_GPSR(IP5_13_12, LCDOUT2),
 932         PINMUX_IPSR_GPSR(IP5_13_12, CC50_STATE18),
 933         PINMUX_IPSR_GPSR(IP5_15_14, DU0_DB3),
 934         PINMUX_IPSR_GPSR(IP5_15_14, LCDOUT3),
 935         PINMUX_IPSR_GPSR(IP5_15_14, CC50_STATE19),
 936         PINMUX_IPSR_GPSR(IP5_17_16, DU0_DB4),
 937         PINMUX_IPSR_GPSR(IP5_17_16, LCDOUT4),
 938         PINMUX_IPSR_GPSR(IP5_17_16, CC50_STATE20),
 939         PINMUX_IPSR_GPSR(IP5_19_18, DU0_DB5),
 940         PINMUX_IPSR_GPSR(IP5_19_18, LCDOUT5),
 941         PINMUX_IPSR_GPSR(IP5_19_18, CC50_STATE21),
 942         PINMUX_IPSR_GPSR(IP5_21_20, DU0_DB6),
 943         PINMUX_IPSR_GPSR(IP5_21_20, LCDOUT6),
 944         PINMUX_IPSR_GPSR(IP5_21_20, CC50_STATE22),
 945         PINMUX_IPSR_GPSR(IP5_23_22, DU0_DB7),
 946         PINMUX_IPSR_GPSR(IP5_23_22, LCDOUT7),
 947         PINMUX_IPSR_GPSR(IP5_23_22, CC50_STATE23),
 948         PINMUX_IPSR_GPSR(IP5_25_24, DU0_DOTCLKIN),
 949         PINMUX_IPSR_GPSR(IP5_25_24, QSTVA_QVS),
 950         PINMUX_IPSR_GPSR(IP5_25_24, CC50_STATE24),
 951         PINMUX_IPSR_GPSR(IP5_27_26, DU0_DOTCLKOUT0),
 952         PINMUX_IPSR_GPSR(IP5_27_26, QCLK),
 953         PINMUX_IPSR_GPSR(IP5_27_26, CC50_STATE25),
 954         PINMUX_IPSR_GPSR(IP5_29_28, DU0_DOTCLKOUT1),
 955         PINMUX_IPSR_GPSR(IP5_29_28, QSTVB_QVE),
 956         PINMUX_IPSR_GPSR(IP5_29_28, CC50_STATE26),
 957         PINMUX_IPSR_GPSR(IP5_31_30, DU0_EXHSYNC_DU0_HSYNC),
 958         PINMUX_IPSR_GPSR(IP5_31_30, QSTH_QHS),
 959         PINMUX_IPSR_GPSR(IP5_31_30, CC50_STATE27),
 960
 961         /* IPSR6 */
 962         PINMUX_IPSR_GPSR(IP6_1_0, DU0_EXVSYNC_DU0_VSYNC),
 963         PINMUX_IPSR_GPSR(IP6_1_0, QSTB_QHE),
 964         PINMUX_IPSR_GPSR(IP6_1_0, CC50_STATE28),
 965         PINMUX_IPSR_GPSR(IP6_3_2, DU0_EXODDF_DU0_ODDF_DISP_CDE),
 966         PINMUX_IPSR_GPSR(IP6_3_2, QCPV_QDE),
 967         PINMUX_IPSR_GPSR(IP6_3_2, CC50_STATE29),
 968         PINMUX_IPSR_GPSR(IP6_5_4, DU0_DISP),
 969         PINMUX_IPSR_GPSR(IP6_5_4, QPOLA),
 970         PINMUX_IPSR_GPSR(IP6_5_4, CC50_STATE30),
 971         PINMUX_IPSR_GPSR(IP6_7_6, DU0_CDE),
 972         PINMUX_IPSR_GPSR(IP6_7_6, QPOLB),
 973         PINMUX_IPSR_GPSR(IP6_7_6, CC50_STATE31),
 974         PINMUX_IPSR_GPSR(IP6_8, VI0_CLK),
 975         PINMUX_IPSR_GPSR(IP6_8, AVB_RX_CLK),
 976         PINMUX_IPSR_GPSR(IP6_9, VI0_DATA0_VI0_B0),
 977         PINMUX_IPSR_GPSR(IP6_9, AVB_RX_DV),
 978         PINMUX_IPSR_GPSR(IP6_10, VI0_DATA1_VI0_B1),
 979         PINMUX_IPSR_GPSR(IP6_10, AVB_RXD0),
 980         PINMUX_IPSR_GPSR(IP6_11, VI0_DATA2_VI0_B2),
 981         PINMUX_IPSR_GPSR(IP6_11, AVB_RXD1),
 982         PINMUX_IPSR_GPSR(IP6_12, VI0_DATA3_VI0_B3),
 983         PINMUX_IPSR_GPSR(IP6_12, AVB_RXD2),
 984         PINMUX_IPSR_GPSR(IP6_13, VI0_DATA4_VI0_B4),
 985         PINMUX_IPSR_GPSR(IP6_13, AVB_RXD3),
 986         PINMUX_IPSR_GPSR(IP6_14, VI0_DATA5_VI0_B5),
 987         PINMUX_IPSR_GPSR(IP6_14, AVB_RXD4),
 988         PINMUX_IPSR_GPSR(IP6_15, VI0_DATA6_VI0_B6),
 989         PINMUX_IPSR_GPSR(IP6_15, AVB_RXD5),
 990         PINMUX_IPSR_GPSR(IP6_16, VI0_DATA7_VI0_B7),
 991         PINMUX_IPSR_GPSR(IP6_16, AVB_RXD6),
 992         PINMUX_IPSR_GPSR(IP6_19_17, VI0_CLKENB),
 993         PINMUX_IPSR_MSEL(IP6_19_17, I2C3_SCL, SEL_I2C03_0),
 994         PINMUX_IPSR_MSEL(IP6_19_17, SCIFA5_RXD_C, SEL_SCIFA5_2),
 995         PINMUX_IPSR_MSEL(IP6_19_17, IETX_C, SEL_IEB_2),
 996         PINMUX_IPSR_GPSR(IP6_19_17, AVB_RXD7),
 997         PINMUX_IPSR_GPSR(IP6_22_20, VI0_FIELD),
 998         PINMUX_IPSR_MSEL(IP6_22_20, I2C3_SDA, SEL_I2C03_0),
 999         PINMUX_IPSR_MSEL(IP6_22_20, SCIFA5_TXD_C, SEL_SCIFA5_2),
1000         PINMUX_IPSR_MSEL(IP6_22_20, IECLK_C, SEL_IEB_2),
1001         PINMUX_IPSR_GPSR(IP6_22_20, AVB_RX_ER),
1002         PINMUX_IPSR_GPSR(IP6_25_23, VI0_HSYNC_N),
1003         PINMUX_IPSR_MSEL(IP6_25_23, SCIF0_RXD_B, SEL_SCIF0_1),
1004         PINMUX_IPSR_MSEL(IP6_25_23, I2C0_SCL_C, SEL_I2C00_2),
1005         PINMUX_IPSR_MSEL(IP6_25_23, IERX_C, SEL_IEB_2),
1006         PINMUX_IPSR_GPSR(IP6_25_23, AVB_COL),
1007         PINMUX_IPSR_GPSR(IP6_28_26, VI0_VSYNC_N),
1008         PINMUX_IPSR_MSEL(IP6_28_26, SCIF0_TXD_B, SEL_SCIF0_1),
1009         PINMUX_IPSR_MSEL(IP6_28_26, I2C0_SDA_C, SEL_I2C00_2),
1010         PINMUX_IPSR_MSEL(IP6_28_26, AUDIO_CLKOUT_B, SEL_ADG_1),
1011         PINMUX_IPSR_GPSR(IP6_28_26, AVB_TX_EN),
1012         PINMUX_IPSR_MSEL(IP6_31_29, ETH_MDIO, SEL_ETH_0),
1013         PINMUX_IPSR_GPSR(IP6_31_29, VI0_G0),
1014         PINMUX_IPSR_MSEL(IP6_31_29, MSIOF2_RXD_B, SEL_MSI2_1),
1015         PINMUX_IPSR_MSEL(IP6_31_29, IIC0_SCL_D, SEL_IIC00_3),
1016         PINMUX_IPSR_GPSR(IP6_31_29, AVB_TX_CLK),
1017         PINMUX_IPSR_MSEL(IP6_31_29, ADIDATA, SEL_RAD_0),
1018         PINMUX_IPSR_MSEL(IP6_31_29, AD_DI, SEL_ADI_0),
1019
1020         /* IPSR7 */
1021         PINMUX_IPSR_MSEL(IP7_2_0, ETH_CRS_DV, SEL_ETH_0),
1022         PINMUX_IPSR_GPSR(IP7_2_0, VI0_G1),
1023         PINMUX_IPSR_MSEL(IP7_2_0, MSIOF2_TXD_B, SEL_MSI2_1),
1024         PINMUX_IPSR_MSEL(IP7_2_0, IIC0_SDA_D, SEL_IIC00_3),
1025         PINMUX_IPSR_GPSR(IP7_2_0, AVB_TXD0),
1026         PINMUX_IPSR_MSEL(IP7_2_0, ADICS_SAMP, SEL_RAD_0),
1027         PINMUX_IPSR_MSEL(IP7_2_0, AD_DO, SEL_ADI_0),
1028         PINMUX_IPSR_MSEL(IP7_5_3, ETH_RX_ER, SEL_ETH_0),
1029         PINMUX_IPSR_GPSR(IP7_5_3, VI0_G2),
1030         PINMUX_IPSR_MSEL(IP7_5_3, MSIOF2_SCK_B, SEL_MSI2_1),
1031         PINMUX_IPSR_MSEL(IP7_5_3, CAN0_RX_B, SEL_CAN0_1),
1032         PINMUX_IPSR_GPSR(IP7_5_3, AVB_TXD1),
1033         PINMUX_IPSR_MSEL(IP7_5_3, ADICLK, SEL_RAD_0),
1034         PINMUX_IPSR_MSEL(IP7_5_3, AD_CLK, SEL_ADI_0),
1035         PINMUX_IPSR_MSEL(IP7_8_6, ETH_RXD0, SEL_ETH_0),
1036         PINMUX_IPSR_GPSR(IP7_8_6, VI0_G3),
1037         PINMUX_IPSR_MSEL(IP7_8_6, MSIOF2_SYNC_B, SEL_MSI2_1),
1038         PINMUX_IPSR_MSEL(IP7_8_6, CAN0_TX_B, SEL_CAN0_1),
1039         PINMUX_IPSR_GPSR(IP7_8_6, AVB_TXD2),
1040         PINMUX_IPSR_MSEL(IP7_8_6, ADICHS0, SEL_RAD_0),
1041         PINMUX_IPSR_MSEL(IP7_8_6, AD_NCS_N, SEL_ADI_0),
1042         PINMUX_IPSR_MSEL(IP7_11_9, ETH_RXD1, SEL_ETH_0),
1043         PINMUX_IPSR_GPSR(IP7_11_9, VI0_G4),
1044         PINMUX_IPSR_MSEL(IP7_11_9, MSIOF2_SS1_B, SEL_MSI2_1),
1045         PINMUX_IPSR_MSEL(IP7_11_9, SCIF4_RXD_D, SEL_SCIF4_3),
1046         PINMUX_IPSR_GPSR(IP7_11_9, AVB_TXD3),
1047         PINMUX_IPSR_MSEL(IP7_11_9, ADICHS1, SEL_RAD_0),
1048         PINMUX_IPSR_MSEL(IP7_14_12, ETH_LINK, SEL_ETH_0),
1049         PINMUX_IPSR_GPSR(IP7_14_12, VI0_G5),
1050         PINMUX_IPSR_MSEL(IP7_14_12, MSIOF2_SS2_B, SEL_MSI2_1),
1051         PINMUX_IPSR_MSEL(IP7_14_12, SCIF4_TXD_D, SEL_SCIF4_3),
1052         PINMUX_IPSR_GPSR(IP7_14_12, AVB_TXD4),
1053         PINMUX_IPSR_MSEL(IP7_14_12, ADICHS2, SEL_RAD_0),
1054         PINMUX_IPSR_MSEL(IP7_17_15, ETH_REFCLK, SEL_ETH_0),
1055         PINMUX_IPSR_GPSR(IP7_17_15, VI0_G6),
1056         PINMUX_IPSR_MSEL(IP7_17_15, SCIF2_SCK_C, SEL_SCIF2_2),
1057         PINMUX_IPSR_GPSR(IP7_17_15, AVB_TXD5),
1058         PINMUX_IPSR_MSEL(IP7_17_15, SSI_SCK5_B, SEL_SSI5_1),
1059         PINMUX_IPSR_MSEL(IP7_20_18, ETH_TXD1, SEL_ETH_0),
1060         PINMUX_IPSR_GPSR(IP7_20_18, VI0_G7),
1061         PINMUX_IPSR_MSEL(IP7_20_18, SCIF2_RXD_C, SEL_SCIF2_2),
1062         PINMUX_IPSR_MSEL(IP7_20_18, IIC1_SCL_D, SEL_IIC01_3),
1063         PINMUX_IPSR_GPSR(IP7_20_18, AVB_TXD6),
1064         PINMUX_IPSR_MSEL(IP7_20_18, SSI_WS5_B, SEL_SSI5_1),
1065         PINMUX_IPSR_MSEL(IP7_23_21, ETH_TX_EN, SEL_ETH_0),
1066         PINMUX_IPSR_GPSR(IP7_23_21, VI0_R0),
1067         PINMUX_IPSR_MSEL(IP7_23_21, SCIF2_TXD_C, SEL_SCIF2_2),
1068         PINMUX_IPSR_MSEL(IP7_23_21, IIC1_SDA_D, SEL_IIC01_3),
1069         PINMUX_IPSR_GPSR(IP7_23_21, AVB_TXD7),
1070         PINMUX_IPSR_MSEL(IP7_23_21, SSI_SDATA5_B, SEL_SSI5_1),
1071         PINMUX_IPSR_MSEL(IP7_26_24, ETH_MAGIC, SEL_ETH_0),
1072         PINMUX_IPSR_GPSR(IP7_26_24, VI0_R1),
1073         PINMUX_IPSR_MSEL(IP7_26_24, SCIF3_SCK_B, SEL_SCIF3_1),
1074         PINMUX_IPSR_GPSR(IP7_26_24, AVB_TX_ER),
1075         PINMUX_IPSR_MSEL(IP7_26_24, SSI_SCK6_B, SEL_SSI6_1),
1076         PINMUX_IPSR_MSEL(IP7_29_27, ETH_TXD0, SEL_ETH_0),
1077         PINMUX_IPSR_GPSR(IP7_29_27, VI0_R2),
1078         PINMUX_IPSR_MSEL(IP7_29_27, SCIF3_RXD_B, SEL_SCIF3_1),
1079         PINMUX_IPSR_MSEL(IP7_29_27, I2C4_SCL_E, SEL_I2C04_4),
1080         PINMUX_IPSR_GPSR(IP7_29_27, AVB_GTX_CLK),
1081         PINMUX_IPSR_MSEL(IP7_29_27, SSI_WS6_B, SEL_SSI6_1),
1082         PINMUX_IPSR_GPSR(IP7_31, DREQ0_N),
1083         PINMUX_IPSR_GPSR(IP7_31, SCIFB1_RXD),
1084
1085         /* IPSR8 */
1086         PINMUX_IPSR_MSEL(IP8_2_0, ETH_MDC, SEL_ETH_0),
1087         PINMUX_IPSR_GPSR(IP8_2_0, VI0_R3),
1088         PINMUX_IPSR_MSEL(IP8_2_0, SCIF3_TXD_B, SEL_SCIF3_1),
1089         PINMUX_IPSR_MSEL(IP8_2_0, I2C4_SDA_E, SEL_I2C04_4),
1090         PINMUX_IPSR_GPSR(IP8_2_0, AVB_MDC),
1091         PINMUX_IPSR_MSEL(IP8_2_0, SSI_SDATA6_B, SEL_SSI6_1),
1092         PINMUX_IPSR_MSEL(IP8_5_3, HSCIF0_HRX, SEL_HSCIF0_0),
1093         PINMUX_IPSR_GPSR(IP8_5_3, VI0_R4),
1094         PINMUX_IPSR_MSEL(IP8_5_3, I2C1_SCL_C, SEL_I2C01_2),
1095         PINMUX_IPSR_MSEL(IP8_5_3, AUDIO_CLKA_B, SEL_ADG_1),
1096         PINMUX_IPSR_GPSR(IP8_5_3, AVB_MDIO),
1097         PINMUX_IPSR_MSEL(IP8_5_3, SSI_SCK78_B, SEL_SSI7_1),
1098         PINMUX_IPSR_MSEL(IP8_8_6, HSCIF0_HTX, SEL_HSCIF0_0),
1099         PINMUX_IPSR_GPSR(IP8_8_6, VI0_R5),
1100         PINMUX_IPSR_MSEL(IP8_8_6, I2C1_SDA_C, SEL_I2C01_2),
1101         PINMUX_IPSR_MSEL(IP8_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1102         PINMUX_IPSR_GPSR(IP8_5_3, AVB_LINK),
1103         PINMUX_IPSR_MSEL(IP8_8_6, SSI_WS78_B, SEL_SSI7_1),
1104         PINMUX_IPSR_GPSR(IP8_11_9, HSCIF0_HCTS_N),
1105         PINMUX_IPSR_GPSR(IP8_11_9, VI0_R6),
1106         PINMUX_IPSR_MSEL(IP8_11_9, SCIF0_RXD_D, SEL_SCIF0_3),
1107         PINMUX_IPSR_MSEL(IP8_11_9, I2C0_SCL_E, SEL_I2C00_4),
1108         PINMUX_IPSR_GPSR(IP8_11_9, AVB_MAGIC),
1109         PINMUX_IPSR_MSEL(IP8_11_9, SSI_SDATA7_B, SEL_SSI7_1),
1110         PINMUX_IPSR_GPSR(IP8_14_12, HSCIF0_HRTS_N),
1111         PINMUX_IPSR_GPSR(IP8_14_12, VI0_R7),
1112         PINMUX_IPSR_MSEL(IP8_14_12, SCIF0_TXD_D, SEL_SCIF0_3),
1113         PINMUX_IPSR_MSEL(IP8_14_12, I2C0_SDA_E, SEL_I2C00_4),
1114         PINMUX_IPSR_GPSR(IP8_14_12, AVB_PHY_INT),
1115         PINMUX_IPSR_MSEL(IP8_14_12, SSI_SDATA8_B, SEL_SSI8_1),
1116         PINMUX_IPSR_MSEL(IP8_16_15, HSCIF0_HSCK, SEL_HSCIF0_0),
1117         PINMUX_IPSR_MSEL(IP8_16_15, SCIF_CLK_B, SEL_SCIF0_1),
1118         PINMUX_IPSR_GPSR(IP8_16_15, AVB_CRS),
1119         PINMUX_IPSR_MSEL(IP8_16_15, AUDIO_CLKC_B, SEL_ADG_1),
1120         PINMUX_IPSR_MSEL(IP8_19_17, I2C0_SCL, SEL_I2C00_0),
1121         PINMUX_IPSR_MSEL(IP8_19_17, SCIF0_RXD_C, SEL_SCIF0_2),
1122         PINMUX_IPSR_GPSR(IP8_19_17, PWM5),
1123         PINMUX_IPSR_MSEL(IP8_19_17, TCLK1_B, SEL_TMU_1),
1124         PINMUX_IPSR_GPSR(IP8_19_17, AVB_GTXREFCLK),
1125         PINMUX_IPSR_MSEL(IP8_19_17, CAN1_RX_D, SEL_CAN1_3),
1126         PINMUX_IPSR_GPSR(IP8_19_17, TPUTO0_B),
1127         PINMUX_IPSR_MSEL(IP8_22_20, I2C0_SDA, SEL_I2C00_0),
1128         PINMUX_IPSR_MSEL(IP8_22_20, SCIF0_TXD_C, SEL_SCIF0_2),
1129         PINMUX_IPSR_GPSR(IP8_22_20, TPUTO0),
1130         PINMUX_IPSR_MSEL(IP8_22_20, CAN_CLK, SEL_CAN_0),
1131         PINMUX_IPSR_GPSR(IP8_22_20, DVC_MUTE),
1132         PINMUX_IPSR_MSEL(IP8_22_20, CAN1_TX_D, SEL_CAN1_3),
1133         PINMUX_IPSR_MSEL(IP8_25_23, I2C1_SCL, SEL_I2C01_0),
1134         PINMUX_IPSR_MSEL(IP8_25_23, SCIF4_RXD, SEL_SCIF4_0),
1135         PINMUX_IPSR_GPSR(IP8_25_23, PWM5_B),
1136         PINMUX_IPSR_GPSR(IP8_25_23, DU1_DR0),
1137         PINMUX_IPSR_MSEL(IP8_25_23, RIF1_SYNC_B, SEL_DR2_1),
1138         PINMUX_IPSR_MSEL(IP8_25_23, TS_SDATA_D, SEL_TSIF0_3),
1139         PINMUX_IPSR_GPSR(IP8_25_23, TPUTO1_B),
1140         PINMUX_IPSR_MSEL(IP8_28_26, I2C1_SDA, SEL_I2C01_0),
1141         PINMUX_IPSR_MSEL(IP8_28_26, SCIF4_TXD, SEL_SCIF4_0),
1142         PINMUX_IPSR_GPSR(IP8_28_26, IRQ5),
1143         PINMUX_IPSR_GPSR(IP8_28_26, DU1_DR1),
1144         PINMUX_IPSR_MSEL(IP8_28_26, RIF1_CLK_B, SEL_DR2_1),
1145         PINMUX_IPSR_MSEL(IP8_28_26, TS_SCK_D, SEL_TSIF0_3),
1146         PINMUX_IPSR_MSEL(IP8_28_26, BPFCLK_C, SEL_DARC_2),
1147         PINMUX_IPSR_GPSR(IP8_31_29, MSIOF0_RXD),
1148         PINMUX_IPSR_MSEL(IP8_31_29, SCIF5_RXD, SEL_SCIF5_0),
1149         PINMUX_IPSR_MSEL(IP8_31_29, I2C2_SCL_C, SEL_I2C02_2),
1150         PINMUX_IPSR_GPSR(IP8_31_29, DU1_DR2),
1151         PINMUX_IPSR_MSEL(IP8_31_29, RIF1_D0_B, SEL_DR2_1),
1152         PINMUX_IPSR_MSEL(IP8_31_29, TS_SDEN_D, SEL_TSIF0_3),
1153         PINMUX_IPSR_MSEL(IP8_31_29, FMCLK_C, SEL_DARC_2),
1154         PINMUX_IPSR_MSEL(IP8_31_29, RDS_CLK, SEL_RDS_0),
1155
1156         /* IPSR9 */
1157         PINMUX_IPSR_GPSR(IP9_2_0, MSIOF0_TXD),
1158         PINMUX_IPSR_MSEL(IP9_2_0, SCIF5_TXD, SEL_SCIF5_0),
1159         PINMUX_IPSR_MSEL(IP9_2_0, I2C2_SDA_C, SEL_I2C02_2),
1160         PINMUX_IPSR_GPSR(IP9_2_0, DU1_DR3),
1161         PINMUX_IPSR_MSEL(IP9_2_0, RIF1_D1_B, SEL_DR3_1),
1162         PINMUX_IPSR_MSEL(IP9_2_0, TS_SPSYNC_D, SEL_TSIF0_3),
1163         PINMUX_IPSR_MSEL(IP9_2_0, FMIN_C, SEL_DARC_2),
1164         PINMUX_IPSR_MSEL(IP9_2_0, RDS_DATA, SEL_RDS_0),
1165         PINMUX_IPSR_GPSR(IP9_5_3, MSIOF0_SCK),
1166         PINMUX_IPSR_GPSR(IP9_5_3, IRQ0),
1167         PINMUX_IPSR_MSEL(IP9_5_3, TS_SDATA, SEL_TSIF0_0),
1168         PINMUX_IPSR_GPSR(IP9_5_3, DU1_DR4),
1169         PINMUX_IPSR_MSEL(IP9_5_3, RIF1_SYNC, SEL_DR2_0),
1170         PINMUX_IPSR_GPSR(IP9_5_3, TPUTO1_C),
1171         PINMUX_IPSR_GPSR(IP9_8_6, MSIOF0_SYNC),
1172         PINMUX_IPSR_GPSR(IP9_8_6, PWM1),
1173         PINMUX_IPSR_MSEL(IP9_8_6, TS_SCK, SEL_TSIF0_0),
1174         PINMUX_IPSR_GPSR(IP9_8_6, DU1_DR5),
1175         PINMUX_IPSR_MSEL(IP9_8_6, RIF1_CLK, SEL_DR2_0),
1176         PINMUX_IPSR_MSEL(IP9_8_6, BPFCLK_B, SEL_DARC_1),
1177         PINMUX_IPSR_GPSR(IP9_11_9, MSIOF0_SS1),
1178         PINMUX_IPSR_MSEL(IP9_11_9, SCIFA0_RXD, SEL_SCIFA0_0),
1179         PINMUX_IPSR_MSEL(IP9_11_9, TS_SDEN, SEL_TSIF0_0),
1180         PINMUX_IPSR_GPSR(IP9_11_9, DU1_DR6),
1181         PINMUX_IPSR_MSEL(IP9_11_9, RIF1_D0, SEL_DR2_0),
1182         PINMUX_IPSR_MSEL(IP9_11_9, FMCLK_B, SEL_DARC_1),
1183         PINMUX_IPSR_MSEL(IP9_11_9, RDS_CLK_B, SEL_RDS_1),
1184         PINMUX_IPSR_GPSR(IP9_14_12, MSIOF0_SS2),
1185         PINMUX_IPSR_MSEL(IP9_14_12, SCIFA0_TXD, SEL_SCIFA0_0),
1186         PINMUX_IPSR_MSEL(IP9_14_12, TS_SPSYNC, SEL_TSIF0_0),
1187         PINMUX_IPSR_GPSR(IP9_14_12, DU1_DR7),
1188         PINMUX_IPSR_MSEL(IP9_14_12, RIF1_D1, SEL_DR3_0),
1189         PINMUX_IPSR_MSEL(IP9_14_12, FMIN_B, SEL_DARC_1),
1190         PINMUX_IPSR_MSEL(IP9_14_12, RDS_DATA_B, SEL_RDS_1),
1191         PINMUX_IPSR_MSEL(IP9_16_15, HSCIF1_HRX, SEL_HSCIF1_0),
1192         PINMUX_IPSR_MSEL(IP9_16_15, I2C4_SCL, SEL_I2C04_0),
1193         PINMUX_IPSR_GPSR(IP9_16_15, PWM6),
1194         PINMUX_IPSR_GPSR(IP9_16_15, DU1_DG0),
1195         PINMUX_IPSR_MSEL(IP9_18_17, HSCIF1_HTX, SEL_HSCIF1_0),
1196         PINMUX_IPSR_MSEL(IP9_18_17, I2C4_SDA, SEL_I2C04_0),
1197         PINMUX_IPSR_GPSR(IP9_18_17, TPUTO1),
1198         PINMUX_IPSR_GPSR(IP9_18_17, DU1_DG1),
1199         PINMUX_IPSR_GPSR(IP9_21_19, HSCIF1_HSCK),
1200         PINMUX_IPSR_GPSR(IP9_21_19, PWM2),
1201         PINMUX_IPSR_MSEL(IP9_21_19, IETX, SEL_IEB_0),
1202         PINMUX_IPSR_GPSR(IP9_21_19, DU1_DG2),
1203         PINMUX_IPSR_MSEL(IP9_21_19, REMOCON_B, SEL_RCN_1),
1204         PINMUX_IPSR_MSEL(IP9_21_19, SPEEDIN_B, SEL_RSP_1),
1205         PINMUX_IPSR_MSEL(IP9_21_19, VSP_B, SEL_SPDM_1),
1206         PINMUX_IPSR_MSEL(IP9_24_22, HSCIF1_HCTS_N, SEL_HSCIF1_0),
1207         PINMUX_IPSR_MSEL(IP9_24_22, SCIFA4_RXD, SEL_SCIFA4_0),
1208         PINMUX_IPSR_MSEL(IP9_24_22, IECLK, SEL_IEB_0),
1209         PINMUX_IPSR_GPSR(IP9_24_22, DU1_DG3),
1210         PINMUX_IPSR_MSEL(IP9_24_22, SSI_SCK1_B, SEL_SSI1_1),
1211         PINMUX_IPSR_GPSR(IP9_24_22, CAN_DEBUG_HW_TRIGGER),
1212         PINMUX_IPSR_GPSR(IP9_24_22, CC50_STATE32),
1213         PINMUX_IPSR_MSEL(IP9_27_25, HSCIF1_HRTS_N, SEL_HSCIF1_0),
1214         PINMUX_IPSR_MSEL(IP9_27_25, SCIFA4_TXD, SEL_SCIFA4_0),
1215         PINMUX_IPSR_MSEL(IP9_27_25, IERX, SEL_IEB_0),
1216         PINMUX_IPSR_GPSR(IP9_27_25, DU1_DG4),
1217         PINMUX_IPSR_MSEL(IP9_27_25, SSI_WS1_B, SEL_SSI1_1),
1218         PINMUX_IPSR_GPSR(IP9_27_25, CAN_STEP0),
1219         PINMUX_IPSR_GPSR(IP9_27_25, CC50_STATE33),
1220         PINMUX_IPSR_MSEL(IP9_30_28, SCIF1_SCK, SEL_SCIF1_0),
1221         PINMUX_IPSR_GPSR(IP9_30_28, PWM3),
1222         PINMUX_IPSR_MSEL(IP9_30_28, TCLK2, SEL_TMU_0),
1223         PINMUX_IPSR_GPSR(IP9_30_28, DU1_DG5),
1224         PINMUX_IPSR_MSEL(IP9_30_28, SSI_SDATA1_B, SEL_SSI1_1),
1225         PINMUX_IPSR_GPSR(IP9_30_28, CAN_TXCLK),
1226         PINMUX_IPSR_GPSR(IP9_30_28, CC50_STATE34),
1227
1228         /* IPSR10 */
1229         PINMUX_IPSR_MSEL(IP10_2_0, SCIF1_RXD, SEL_SCIF1_0),
1230         PINMUX_IPSR_MSEL(IP10_2_0, IIC0_SCL, SEL_IIC00_0),
1231         PINMUX_IPSR_GPSR(IP10_2_0, DU1_DG6),
1232         PINMUX_IPSR_MSEL(IP10_2_0, SSI_SCK2_B, SEL_SSI2_1),
1233         PINMUX_IPSR_GPSR(IP10_2_0, CAN_DEBUGOUT0),
1234         PINMUX_IPSR_GPSR(IP10_2_0, CC50_STATE35),
1235         PINMUX_IPSR_MSEL(IP10_5_3, SCIF1_TXD, SEL_SCIF1_0),
1236         PINMUX_IPSR_MSEL(IP10_5_3, IIC0_SDA, SEL_IIC00_0),
1237         PINMUX_IPSR_GPSR(IP10_5_3, DU1_DG7),
1238         PINMUX_IPSR_MSEL(IP10_5_3, SSI_WS2_B, SEL_SSI2_1),
1239         PINMUX_IPSR_GPSR(IP10_5_3, CAN_DEBUGOUT1),
1240         PINMUX_IPSR_GPSR(IP10_5_3, CC50_STATE36),
1241         PINMUX_IPSR_MSEL(IP10_8_6, SCIF2_RXD, SEL_SCIF2_0),
1242         PINMUX_IPSR_MSEL(IP10_8_6, IIC1_SCL, SEL_IIC01_0),
1243         PINMUX_IPSR_GPSR(IP10_8_6, DU1_DB0),
1244         PINMUX_IPSR_MSEL(IP10_8_6, SSI_SDATA2_B, SEL_SSI2_1),
1245         PINMUX_IPSR_GPSR(IP10_8_6, USB0_EXTLP),
1246         PINMUX_IPSR_GPSR(IP10_8_6, CAN_DEBUGOUT2),
1247         PINMUX_IPSR_GPSR(IP10_8_6, CC50_STATE37),
1248         PINMUX_IPSR_MSEL(IP10_11_9, SCIF2_TXD, SEL_SCIF2_0),
1249         PINMUX_IPSR_MSEL(IP10_11_9, IIC1_SDA, SEL_IIC01_0),
1250         PINMUX_IPSR_GPSR(IP10_11_9, DU1_DB1),
1251         PINMUX_IPSR_MSEL(IP10_11_9, SSI_SCK9_B, SEL_SSI9_1),
1252         PINMUX_IPSR_GPSR(IP10_11_9, USB0_OVC1),
1253         PINMUX_IPSR_GPSR(IP10_11_9, CAN_DEBUGOUT3),
1254         PINMUX_IPSR_GPSR(IP10_11_9, CC50_STATE38),
1255         PINMUX_IPSR_MSEL(IP10_14_12, SCIF2_SCK, SEL_SCIF2_0),
1256         PINMUX_IPSR_GPSR(IP10_14_12, IRQ1),
1257         PINMUX_IPSR_GPSR(IP10_14_12, DU1_DB2),
1258         PINMUX_IPSR_MSEL(IP10_14_12, SSI_WS9_B, SEL_SSI9_1),
1259         PINMUX_IPSR_GPSR(IP10_14_12, USB0_IDIN),
1260         PINMUX_IPSR_GPSR(IP10_14_12, CAN_DEBUGOUT4),
1261         PINMUX_IPSR_GPSR(IP10_14_12, CC50_STATE39),
1262         PINMUX_IPSR_MSEL(IP10_17_15, SCIF3_SCK, SEL_SCIF3_0),
1263         PINMUX_IPSR_GPSR(IP10_17_15, IRQ2),
1264         PINMUX_IPSR_MSEL(IP10_17_15, BPFCLK_D, SEL_DARC_3),
1265         PINMUX_IPSR_GPSR(IP10_17_15, DU1_DB3),
1266         PINMUX_IPSR_MSEL(IP10_17_15, SSI_SDATA9_B, SEL_SSI9_1),
1267         PINMUX_IPSR_GPSR(IP10_17_15, TANS2),
1268         PINMUX_IPSR_GPSR(IP10_17_15, CAN_DEBUGOUT5),
1269         PINMUX_IPSR_GPSR(IP10_17_15, CC50_OSCOUT),
1270         PINMUX_IPSR_MSEL(IP10_20_18, SCIF3_RXD, SEL_SCIF3_0),
1271         PINMUX_IPSR_MSEL(IP10_20_18, I2C1_SCL_E, SEL_I2C01_4),
1272         PINMUX_IPSR_MSEL(IP10_20_18, FMCLK_D, SEL_DARC_3),
1273         PINMUX_IPSR_GPSR(IP10_20_18, DU1_DB4),
1274         PINMUX_IPSR_MSEL(IP10_20_18, AUDIO_CLKA_C, SEL_ADG_2),
1275         PINMUX_IPSR_MSEL(IP10_20_18, SSI_SCK4_B, SEL_SSI4_1),
1276         PINMUX_IPSR_GPSR(IP10_20_18, CAN_DEBUGOUT6),
1277         PINMUX_IPSR_MSEL(IP10_20_18, RDS_CLK_C, SEL_RDS_2),
1278         PINMUX_IPSR_MSEL(IP10_23_21, SCIF3_TXD, SEL_SCIF3_0),
1279         PINMUX_IPSR_MSEL(IP10_23_21, I2C1_SDA_E, SEL_I2C01_4),
1280         PINMUX_IPSR_MSEL(IP10_23_21, FMIN_D, SEL_DARC_3),
1281         PINMUX_IPSR_GPSR(IP10_23_21, DU1_DB5),
1282         PINMUX_IPSR_MSEL(IP10_23_21, AUDIO_CLKB_C, SEL_ADG_2),
1283         PINMUX_IPSR_MSEL(IP10_23_21, SSI_WS4_B, SEL_SSI4_1),
1284         PINMUX_IPSR_GPSR(IP10_23_21, CAN_DEBUGOUT7),
1285         PINMUX_IPSR_MSEL(IP10_23_21, RDS_DATA_C, SEL_RDS_2),
1286         PINMUX_IPSR_MSEL(IP10_26_24, I2C2_SCL, SEL_I2C02_0),
1287         PINMUX_IPSR_MSEL(IP10_26_24, SCIFA5_RXD, SEL_SCIFA5_0),
1288         PINMUX_IPSR_GPSR(IP10_26_24, DU1_DB6),
1289         PINMUX_IPSR_MSEL(IP10_26_24, AUDIO_CLKC_C, SEL_ADG_2),
1290         PINMUX_IPSR_MSEL(IP10_26_24, SSI_SDATA4_B, SEL_SSI4_1),
1291         PINMUX_IPSR_GPSR(IP10_26_24, CAN_DEBUGOUT8),
1292         PINMUX_IPSR_MSEL(IP10_29_27, I2C2_SDA, SEL_I2C02_0),
1293         PINMUX_IPSR_MSEL(IP10_29_27, SCIFA5_TXD, SEL_SCIFA5_0),
1294         PINMUX_IPSR_GPSR(IP10_29_27, DU1_DB7),
1295         PINMUX_IPSR_MSEL(IP10_29_27, AUDIO_CLKOUT_C, SEL_ADG_2),
1296         PINMUX_IPSR_GPSR(IP10_29_27, CAN_DEBUGOUT9),
1297         PINMUX_IPSR_MSEL(IP10_31_30, SSI_SCK5, SEL_SSI5_0),
1298         PINMUX_IPSR_MSEL(IP10_31_30, SCIFA3_SCK, SEL_SCIFA3_0),
1299         PINMUX_IPSR_GPSR(IP10_31_30, DU1_DOTCLKIN),
1300         PINMUX_IPSR_GPSR(IP10_31_30, CAN_DEBUGOUT10),
1301
1302         /* IPSR11 */
1303         PINMUX_IPSR_MSEL(IP11_2_0, SSI_WS5, SEL_SSI5_0),
1304         PINMUX_IPSR_MSEL(IP11_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1305         PINMUX_IPSR_MSEL(IP11_2_0, I2C3_SCL_C, SEL_I2C03_2),
1306         PINMUX_IPSR_GPSR(IP11_2_0, DU1_DOTCLKOUT0),
1307         PINMUX_IPSR_GPSR(IP11_2_0, CAN_DEBUGOUT11),
1308         PINMUX_IPSR_MSEL(IP11_5_3, SSI_SDATA5, SEL_SSI5_0),
1309         PINMUX_IPSR_MSEL(IP11_5_3, SCIFA3_TXD, SEL_SCIFA3_0),
1310         PINMUX_IPSR_MSEL(IP11_5_3, I2C3_SDA_C, SEL_I2C03_2),
1311         PINMUX_IPSR_GPSR(IP11_5_3, DU1_DOTCLKOUT1),
1312         PINMUX_IPSR_GPSR(IP11_5_3, CAN_DEBUGOUT12),
1313         PINMUX_IPSR_MSEL(IP11_7_6, SSI_SCK6, SEL_SSI6_0),
1314         PINMUX_IPSR_MSEL(IP11_7_6, SCIFA1_SCK_B, SEL_SCIFA1_1),
1315         PINMUX_IPSR_GPSR(IP11_7_6, DU1_EXHSYNC_DU1_HSYNC),
1316         PINMUX_IPSR_GPSR(IP11_7_6, CAN_DEBUGOUT13),
1317         PINMUX_IPSR_MSEL(IP11_10_8, SSI_WS6, SEL_SSI6_0),
1318         PINMUX_IPSR_MSEL(IP11_10_8, SCIFA1_RXD_B, SEL_SCIFA1_1),
1319         PINMUX_IPSR_MSEL(IP11_10_8, I2C4_SCL_C, SEL_I2C04_2),
1320         PINMUX_IPSR_GPSR(IP11_10_8, DU1_EXVSYNC_DU1_VSYNC),
1321         PINMUX_IPSR_GPSR(IP11_10_8, CAN_DEBUGOUT14),
1322         PINMUX_IPSR_MSEL(IP11_13_11, SSI_SDATA6, SEL_SSI6_0),
1323         PINMUX_IPSR_MSEL(IP11_13_11, SCIFA1_TXD_B, SEL_SCIFA1_1),
1324         PINMUX_IPSR_MSEL(IP11_13_11, I2C4_SDA_C, SEL_I2C04_2),
1325         PINMUX_IPSR_GPSR(IP11_13_11, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1326         PINMUX_IPSR_GPSR(IP11_13_11, CAN_DEBUGOUT15),
1327         PINMUX_IPSR_MSEL(IP11_15_14, SSI_SCK78, SEL_SSI7_0),
1328         PINMUX_IPSR_MSEL(IP11_15_14, SCIFA2_SCK_B, SEL_SCIFA2_1),
1329         PINMUX_IPSR_MSEL(IP11_15_14, IIC0_SDA_C, SEL_IIC00_2),
1330         PINMUX_IPSR_GPSR(IP11_15_14, DU1_DISP),
1331         PINMUX_IPSR_MSEL(IP11_17_16, SSI_WS78, SEL_SSI7_0),
1332         PINMUX_IPSR_MSEL(IP11_17_16, SCIFA2_RXD_B, SEL_SCIFA2_1),
1333         PINMUX_IPSR_MSEL(IP11_17_16, IIC0_SCL_C, SEL_IIC00_2),
1334         PINMUX_IPSR_GPSR(IP11_17_16, DU1_CDE),
1335         PINMUX_IPSR_MSEL(IP11_20_18, SSI_SDATA7, SEL_SSI7_0),
1336         PINMUX_IPSR_MSEL(IP11_20_18, SCIFA2_TXD_B, SEL_SCIFA2_1),
1337         PINMUX_IPSR_GPSR(IP11_20_18, IRQ8),
1338         PINMUX_IPSR_MSEL(IP11_20_18, AUDIO_CLKA_D, SEL_ADG_3),
1339         PINMUX_IPSR_MSEL(IP11_20_18, CAN_CLK_D, SEL_CAN_3),
1340         PINMUX_IPSR_GPSR(IP11_20_18, PCMOE_N),
1341         PINMUX_IPSR_GPSR(IP11_23_21, SSI_SCK0129),
1342         PINMUX_IPSR_MSEL(IP11_23_21, MSIOF1_RXD_B, SEL_MSI1_1),
1343         PINMUX_IPSR_MSEL(IP11_23_21, SCIF5_RXD_D, SEL_SCIF5_3),
1344         PINMUX_IPSR_MSEL(IP11_23_21, ADIDATA_B, SEL_RAD_1),
1345         PINMUX_IPSR_MSEL(IP11_23_21, AD_DI_B, SEL_ADI_1),
1346         PINMUX_IPSR_GPSR(IP11_23_21, PCMWE_N),
1347         PINMUX_IPSR_GPSR(IP11_26_24, SSI_WS0129),
1348         PINMUX_IPSR_MSEL(IP11_26_24, MSIOF1_TXD_B, SEL_MSI1_1),
1349         PINMUX_IPSR_MSEL(IP11_26_24, SCIF5_TXD_D, SEL_SCIF5_3),
1350         PINMUX_IPSR_MSEL(IP11_26_24, ADICS_SAMP_B, SEL_RAD_1),
1351         PINMUX_IPSR_MSEL(IP11_26_24, AD_DO_B, SEL_ADI_1),
1352         PINMUX_IPSR_GPSR(IP11_29_27, SSI_SDATA0),
1353         PINMUX_IPSR_MSEL(IP11_29_27, MSIOF1_SCK_B, SEL_MSI1_1),
1354         PINMUX_IPSR_GPSR(IP11_29_27, PWM0_B),
1355         PINMUX_IPSR_MSEL(IP11_29_27, ADICLK_B, SEL_RAD_1),
1356         PINMUX_IPSR_MSEL(IP11_29_27, AD_CLK_B, SEL_ADI_1),
1357
1358         /* IPSR12 */
1359         PINMUX_IPSR_GPSR(IP12_2_0, SSI_SCK34),
1360         PINMUX_IPSR_MSEL(IP12_2_0, MSIOF1_SYNC_B, SEL_MSI1_1),
1361         PINMUX_IPSR_MSEL(IP12_2_0, SCIFA1_SCK_C, SEL_SCIFA1_2),
1362         PINMUX_IPSR_MSEL(IP12_2_0, ADICHS0_B, SEL_RAD_1),
1363         PINMUX_IPSR_MSEL(IP12_2_0, AD_NCS_N_B, SEL_ADI_1),
1364         PINMUX_IPSR_MSEL(IP12_2_0, DREQ1_N_B, SEL_LBS_1),
1365         PINMUX_IPSR_GPSR(IP12_5_3, SSI_WS34),
1366         PINMUX_IPSR_MSEL(IP12_5_3, MSIOF1_SS1_B, SEL_MSI1_1),
1367         PINMUX_IPSR_MSEL(IP12_5_3, SCIFA1_RXD_C, SEL_SCIFA1_2),
1368         PINMUX_IPSR_MSEL(IP12_5_3, ADICHS1_B, SEL_RAD_1),
1369         PINMUX_IPSR_MSEL(IP12_5_3, CAN1_RX_C, SEL_CAN1_2),
1370         PINMUX_IPSR_MSEL(IP12_5_3, DACK1_B, SEL_LBS_1),
1371         PINMUX_IPSR_GPSR(IP12_8_6, SSI_SDATA3),
1372         PINMUX_IPSR_MSEL(IP12_8_6, MSIOF1_SS2_B, SEL_MSI1_1),
1373         PINMUX_IPSR_MSEL(IP12_8_6, SCIFA1_TXD_C, SEL_SCIFA1_2),
1374         PINMUX_IPSR_MSEL(IP12_8_6, ADICHS2_B, SEL_RAD_1),
1375         PINMUX_IPSR_MSEL(IP12_8_6, CAN1_TX_C, SEL_CAN1_2),
1376         PINMUX_IPSR_GPSR(IP12_8_6, DREQ2_N),
1377         PINMUX_IPSR_MSEL(IP12_10_9, SSI_SCK4, SEL_SSI4_0),
1378         PINMUX_IPSR_GPSR(IP12_10_9, MLB_CLK),
1379         PINMUX_IPSR_MSEL(IP12_10_9, IETX_B, SEL_IEB_1),
1380         PINMUX_IPSR_GPSR(IP12_10_9, IRD_TX),
1381         PINMUX_IPSR_MSEL(IP12_12_11, SSI_WS4, SEL_SSI4_0),
1382         PINMUX_IPSR_GPSR(IP12_12_11, MLB_SIG),
1383         PINMUX_IPSR_MSEL(IP12_12_11, IECLK_B, SEL_IEB_1),
1384         PINMUX_IPSR_GPSR(IP12_12_11, IRD_RX),
1385         PINMUX_IPSR_MSEL(IP12_14_13, SSI_SDATA4, SEL_SSI4_0),
1386         PINMUX_IPSR_GPSR(IP12_14_13, MLB_DAT),
1387         PINMUX_IPSR_MSEL(IP12_14_13, IERX_B, SEL_IEB_1),
1388         PINMUX_IPSR_GPSR(IP12_14_13, IRD_SCK),
1389         PINMUX_IPSR_MSEL(IP12_17_15, SSI_SDATA8, SEL_SSI8_0),
1390         PINMUX_IPSR_MSEL(IP12_17_15, SCIF1_SCK_B, SEL_SCIF1_1),
1391         PINMUX_IPSR_GPSR(IP12_17_15, PWM1_B),
1392         PINMUX_IPSR_GPSR(IP12_17_15, IRQ9),
1393         PINMUX_IPSR_MSEL(IP12_17_15, REMOCON, SEL_RCN_0),
1394         PINMUX_IPSR_GPSR(IP12_17_15, DACK2),
1395         PINMUX_IPSR_MSEL(IP12_17_15, ETH_MDIO_B, SEL_ETH_1),
1396         PINMUX_IPSR_MSEL(IP12_20_18, SSI_SCK1, SEL_SSI1_0),
1397         PINMUX_IPSR_MSEL(IP12_20_18, SCIF1_RXD_B, SEL_SCIF1_1),
1398         PINMUX_IPSR_MSEL(IP12_20_18, IIC1_SCL_C, SEL_IIC01_2),
1399         PINMUX_IPSR_GPSR(IP12_20_18, VI1_CLK),
1400         PINMUX_IPSR_MSEL(IP12_20_18, CAN0_RX_D, SEL_CAN0_3),
1401         PINMUX_IPSR_MSEL(IP12_20_18, AVB_AVTP_CAPTURE, SEL_AVB_0),
1402         PINMUX_IPSR_MSEL(IP12_20_18, ETH_CRS_DV_B, SEL_ETH_1),
1403         PINMUX_IPSR_MSEL(IP12_23_21, SSI_WS1, SEL_SSI1_0),
1404         PINMUX_IPSR_MSEL(IP12_23_21, SCIF1_TXD_B, SEL_SCIF1_1),
1405         PINMUX_IPSR_MSEL(IP12_23_21, IIC1_SDA_C, SEL_IIC01_2),
1406         PINMUX_IPSR_GPSR(IP12_23_21, VI1_DATA0),
1407         PINMUX_IPSR_MSEL(IP12_23_21, CAN0_TX_D, SEL_CAN0_3),
1408         PINMUX_IPSR_MSEL(IP12_23_21, AVB_AVTP_MATCH, SEL_AVB_0),
1409         PINMUX_IPSR_MSEL(IP12_23_21, ETH_RX_ER_B, SEL_ETH_1),
1410         PINMUX_IPSR_MSEL(IP12_26_24, SSI_SDATA1, SEL_SSI1_0),
1411         PINMUX_IPSR_MSEL(IP12_26_24, HSCIF1_HRX_B, SEL_HSCIF1_1),
1412         PINMUX_IPSR_GPSR(IP12_26_24, VI1_DATA1),
1413         PINMUX_IPSR_MSEL(IP12_26_24, SDATA, SEL_FSN_0),
1414         PINMUX_IPSR_GPSR(IP12_26_24, ATAG0_N),
1415         PINMUX_IPSR_MSEL(IP12_26_24, ETH_RXD0_B, SEL_ETH_1),
1416         PINMUX_IPSR_MSEL(IP12_29_27, SSI_SCK2, SEL_SSI2_0),
1417         PINMUX_IPSR_MSEL(IP12_29_27, HSCIF1_HTX_B, SEL_HSCIF1_1),
1418         PINMUX_IPSR_GPSR(IP12_29_27, VI1_DATA2),
1419         PINMUX_IPSR_MSEL(IP12_29_27, MDATA, SEL_FSN_0),
1420         PINMUX_IPSR_GPSR(IP12_29_27, ATAWR0_N),
1421         PINMUX_IPSR_MSEL(IP12_29_27, ETH_RXD1_B, SEL_ETH_1),
1422
1423         /* IPSR13 */
1424         PINMUX_IPSR_MSEL(IP13_2_0, SSI_WS2, SEL_SSI2_0),
1425         PINMUX_IPSR_MSEL(IP13_2_0, HSCIF1_HCTS_N_B, SEL_HSCIF1_1),
1426         PINMUX_IPSR_MSEL(IP13_2_0, SCIFA0_RXD_D, SEL_SCIFA0_3),
1427         PINMUX_IPSR_GPSR(IP13_2_0, VI1_DATA3),
1428         PINMUX_IPSR_MSEL(IP13_2_0, SCKZ, SEL_FSN_0),
1429         PINMUX_IPSR_GPSR(IP13_2_0, ATACS00_N),
1430         PINMUX_IPSR_MSEL(IP13_2_0, ETH_LINK_B, SEL_ETH_1),
1431         PINMUX_IPSR_MSEL(IP13_5_3, SSI_SDATA2, SEL_SSI2_0),
1432         PINMUX_IPSR_MSEL(IP13_5_3, HSCIF1_HRTS_N_B, SEL_HSCIF1_1),
1433         PINMUX_IPSR_MSEL(IP13_5_3, SCIFA0_TXD_D, SEL_SCIFA0_3),
1434         PINMUX_IPSR_GPSR(IP13_5_3, VI1_DATA4),
1435         PINMUX_IPSR_MSEL(IP13_5_3, STM_N, SEL_FSN_0),
1436         PINMUX_IPSR_GPSR(IP13_5_3, ATACS10_N),
1437         PINMUX_IPSR_MSEL(IP13_5_3, ETH_REFCLK_B, SEL_ETH_1),
1438         PINMUX_IPSR_MSEL(IP13_8_6, SSI_SCK9, SEL_SSI9_0),
1439         PINMUX_IPSR_MSEL(IP13_8_6, SCIF2_SCK_B, SEL_SCIF2_1),
1440         PINMUX_IPSR_GPSR(IP13_8_6, PWM2_B),
1441         PINMUX_IPSR_GPSR(IP13_8_6, VI1_DATA5),
1442         PINMUX_IPSR_MSEL(IP13_8_6, MTS_N, SEL_FSN_0),
1443         PINMUX_IPSR_GPSR(IP13_8_6, EX_WAIT1),
1444         PINMUX_IPSR_MSEL(IP13_8_6, ETH_TXD1_B, SEL_ETH_1),
1445         PINMUX_IPSR_MSEL(IP13_11_9, SSI_WS9, SEL_SSI9_0),
1446         PINMUX_IPSR_MSEL(IP13_11_9, SCIF2_RXD_B, SEL_SCIF2_1),
1447         PINMUX_IPSR_MSEL(IP13_11_9, I2C3_SCL_E, SEL_I2C03_4),
1448         PINMUX_IPSR_GPSR(IP13_11_9, VI1_DATA6),
1449         PINMUX_IPSR_GPSR(IP13_11_9, ATARD0_N),
1450         PINMUX_IPSR_MSEL(IP13_11_9, ETH_TX_EN_B, SEL_ETH_1),
1451         PINMUX_IPSR_MSEL(IP13_14_12, SSI_SDATA9, SEL_SSI9_0),
1452         PINMUX_IPSR_MSEL(IP13_14_12, SCIF2_TXD_B, SEL_SCIF2_1),
1453         PINMUX_IPSR_MSEL(IP13_14_12, I2C3_SDA_E, SEL_I2C03_4),
1454         PINMUX_IPSR_GPSR(IP13_14_12, VI1_DATA7),
1455         PINMUX_IPSR_GPSR(IP13_14_12, ATADIR0_N),
1456         PINMUX_IPSR_MSEL(IP13_14_12, ETH_MAGIC_B, SEL_ETH_1),
1457         PINMUX_IPSR_MSEL(IP13_17_15, AUDIO_CLKA, SEL_ADG_0),
1458         PINMUX_IPSR_MSEL(IP13_17_15, I2C0_SCL_B, SEL_I2C00_1),
1459         PINMUX_IPSR_MSEL(IP13_17_15, SCIFA4_RXD_D, SEL_SCIFA4_3),
1460         PINMUX_IPSR_GPSR(IP13_17_15, VI1_CLKENB),
1461         PINMUX_IPSR_MSEL(IP13_17_15, TS_SDATA_C, SEL_TSIF0_2),
1462         PINMUX_IPSR_MSEL(IP13_17_15, RIF0_SYNC_B, SEL_DR0_1),
1463         PINMUX_IPSR_MSEL(IP13_17_15, ETH_TXD0_B, SEL_ETH_1),
1464         PINMUX_IPSR_MSEL(IP13_20_18, AUDIO_CLKB, SEL_ADG_0),
1465         PINMUX_IPSR_MSEL(IP13_20_18, I2C0_SDA_B, SEL_I2C00_1),
1466         PINMUX_IPSR_MSEL(IP13_20_18, SCIFA4_TXD_D, SEL_SCIFA4_3),
1467         PINMUX_IPSR_GPSR(IP13_20_18, VI1_FIELD),
1468         PINMUX_IPSR_MSEL(IP13_20_18, TS_SCK_C, SEL_TSIF0_2),
1469         PINMUX_IPSR_MSEL(IP13_20_18, RIF0_CLK_B, SEL_DR0_1),
1470         PINMUX_IPSR_MSEL(IP13_20_18, BPFCLK_E, SEL_DARC_4),
1471         PINMUX_IPSR_MSEL(IP13_20_18, ETH_MDC_B, SEL_ETH_1),
1472         PINMUX_IPSR_MSEL(IP13_23_21, AUDIO_CLKC, SEL_ADG_0),
1473         PINMUX_IPSR_MSEL(IP13_23_21, I2C4_SCL_B, SEL_I2C04_1),
1474         PINMUX_IPSR_MSEL(IP13_23_21, SCIFA5_RXD_D, SEL_SCIFA5_3),
1475         PINMUX_IPSR_GPSR(IP13_23_21, VI1_HSYNC_N),
1476         PINMUX_IPSR_MSEL(IP13_23_21, TS_SDEN_C, SEL_TSIF0_2),
1477         PINMUX_IPSR_MSEL(IP13_23_21, RIF0_D0_B, SEL_DR0_1),
1478         PINMUX_IPSR_MSEL(IP13_23_21, FMCLK_E, SEL_DARC_4),
1479         PINMUX_IPSR_MSEL(IP13_23_21, RDS_CLK_D, SEL_RDS_3),
1480         PINMUX_IPSR_MSEL(IP13_26_24, AUDIO_CLKOUT, SEL_ADG_0),
1481         PINMUX_IPSR_MSEL(IP13_26_24, I2C4_SDA_B, SEL_I2C04_1),
1482         PINMUX_IPSR_MSEL(IP13_26_24, SCIFA5_TXD_D, SEL_SCIFA5_3),
1483         PINMUX_IPSR_GPSR(IP13_26_24, VI1_VSYNC_N),
1484         PINMUX_IPSR_MSEL(IP13_26_24, TS_SPSYNC_C, SEL_TSIF0_2),
1485         PINMUX_IPSR_MSEL(IP13_26_24, RIF0_D1_B, SEL_DR1_1),
1486         PINMUX_IPSR_MSEL(IP13_26_24, FMIN_E, SEL_DARC_4),
1487         PINMUX_IPSR_MSEL(IP13_26_24, RDS_DATA_D, SEL_RDS_3),
1488 };
1489
1490 static const struct sh_pfc_pin pinmux_pins[] = {
1491         PINMUX_GPIO_GP_ALL(),
1492 };
1493
1494 /* - Audio Clock ------------------------------------------------------------ */
1495 static const unsigned int audio_clka_pins[] = {
1496         /* CLKA */
1497         RCAR_GP_PIN(5, 20),
1498 };
1499 static const unsigned int audio_clka_mux[] = {
1500         AUDIO_CLKA_MARK,
1501 };
1502 static const unsigned int audio_clka_b_pins[] = {
1503         /* CLKA */
1504         RCAR_GP_PIN(3, 25),
1505 };
1506 static const unsigned int audio_clka_b_mux[] = {
1507         AUDIO_CLKA_B_MARK,
1508 };
1509 static const unsigned int audio_clka_c_pins[] = {
1510         /* CLKA */
1511         RCAR_GP_PIN(4, 20),
1512 };
1513 static const unsigned int audio_clka_c_mux[] = {
1514         AUDIO_CLKA_C_MARK,
1515 };
1516 static const unsigned int audio_clka_d_pins[] = {
1517         /* CLKA */
1518         RCAR_GP_PIN(5, 0),
1519 };
1520 static const unsigned int audio_clka_d_mux[] = {
1521         AUDIO_CLKA_D_MARK,
1522 };
1523 static const unsigned int audio_clkb_pins[] = {
1524         /* CLKB */
1525         RCAR_GP_PIN(5, 21),
1526 };
1527 static const unsigned int audio_clkb_mux[] = {
1528         AUDIO_CLKB_MARK,
1529 };
1530 static const unsigned int audio_clkb_b_pins[] = {
1531         /* CLKB */
1532         RCAR_GP_PIN(3, 26),
1533 };
1534 static const unsigned int audio_clkb_b_mux[] = {
1535         AUDIO_CLKB_B_MARK,
1536 };
1537 static const unsigned int audio_clkb_c_pins[] = {
1538         /* CLKB */
1539         RCAR_GP_PIN(4, 21),
1540 };
1541 static const unsigned int audio_clkb_c_mux[] = {
1542         AUDIO_CLKB_C_MARK,
1543 };
1544 static const unsigned int audio_clkc_pins[] = {
1545         /* CLKC */
1546         RCAR_GP_PIN(5, 22),
1547 };
1548 static const unsigned int audio_clkc_mux[] = {
1549         AUDIO_CLKC_MARK,
1550 };
1551 static const unsigned int audio_clkc_b_pins[] = {
1552         /* CLKC */
1553         RCAR_GP_PIN(3, 29),
1554 };
1555 static const unsigned int audio_clkc_b_mux[] = {
1556         AUDIO_CLKC_B_MARK,
1557 };
1558 static const unsigned int audio_clkc_c_pins[] = {
1559         /* CLKC */
1560         RCAR_GP_PIN(4, 22),
1561 };
1562 static const unsigned int audio_clkc_c_mux[] = {
1563         AUDIO_CLKC_C_MARK,
1564 };
1565 static const unsigned int audio_clkout_pins[] = {
1566         /* CLKOUT */
1567         RCAR_GP_PIN(5, 23),
1568 };
1569 static const unsigned int audio_clkout_mux[] = {
1570         AUDIO_CLKOUT_MARK,
1571 };
1572 static const unsigned int audio_clkout_b_pins[] = {
1573         /* CLKOUT */
1574         RCAR_GP_PIN(3, 12),
1575 };
1576 static const unsigned int audio_clkout_b_mux[] = {
1577         AUDIO_CLKOUT_B_MARK,
1578 };
1579 static const unsigned int audio_clkout_c_pins[] = {
1580         /* CLKOUT */
1581         RCAR_GP_PIN(4, 23),
1582 };
1583 static const unsigned int audio_clkout_c_mux[] = {
1584         AUDIO_CLKOUT_C_MARK,
1585 };
1586 /* - AVB -------------------------------------------------------------------- */
1587 static const unsigned int avb_link_pins[] = {
1588         RCAR_GP_PIN(3, 26),
1589 };
1590 static const unsigned int avb_link_mux[] = {
1591         AVB_LINK_MARK,
1592 };
1593 static const unsigned int avb_magic_pins[] = {
1594         RCAR_GP_PIN(3, 27),
1595 };
1596 static const unsigned int avb_magic_mux[] = {
1597         AVB_MAGIC_MARK,
1598 };
1599 static const unsigned int avb_phy_int_pins[] = {
1600         RCAR_GP_PIN(3, 28),
1601 };
1602 static const unsigned int avb_phy_int_mux[] = {
1603         AVB_PHY_INT_MARK,
1604 };
1605 static const unsigned int avb_mdio_pins[] = {
1606         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
1607 };
1608 static const unsigned int avb_mdio_mux[] = {
1609         AVB_MDC_MARK, AVB_MDIO_MARK,
1610 };
1611 static const unsigned int avb_mii_pins[] = {
1612         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1613         RCAR_GP_PIN(3, 17),
1614
1615         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1616         RCAR_GP_PIN(3, 5),
1617
1618         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1619         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22),
1620         RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 11),
1621 };
1622 static const unsigned int avb_mii_mux[] = {
1623         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1624         AVB_TXD3_MARK,
1625
1626         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1627         AVB_RXD3_MARK,
1628
1629         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1630         AVB_CRS_MARK, AVB_TX_EN_MARK, AVB_TX_ER_MARK,
1631         AVB_TX_CLK_MARK, AVB_COL_MARK,
1632 };
1633 static const unsigned int avb_gmii_pins[] = {
1634         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
1635         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
1636         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
1637
1638         RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
1639         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
1640         RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
1641
1642         RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
1643         RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 30),
1644         RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 13),
1645         RCAR_GP_PIN(3, 11),
1646 };
1647 static const unsigned int avb_gmii_mux[] = {
1648         AVB_TXD0_MARK, AVB_TXD1_MARK, AVB_TXD2_MARK,
1649         AVB_TXD3_MARK, AVB_TXD4_MARK, AVB_TXD5_MARK,
1650         AVB_TXD6_MARK, AVB_TXD7_MARK,
1651
1652         AVB_RXD0_MARK, AVB_RXD1_MARK, AVB_RXD2_MARK,
1653         AVB_RXD3_MARK, AVB_RXD4_MARK, AVB_RXD5_MARK,
1654         AVB_RXD6_MARK, AVB_RXD7_MARK,
1655
1656         AVB_RX_ER_MARK, AVB_RX_CLK_MARK, AVB_RX_DV_MARK,
1657         AVB_CRS_MARK, AVB_GTX_CLK_MARK, AVB_GTXREFCLK_MARK,
1658         AVB_TX_EN_MARK, AVB_TX_ER_MARK, AVB_TX_CLK_MARK,
1659         AVB_COL_MARK,
1660 };
1661 static const unsigned int avb_avtp_capture_pins[] = {
1662         RCAR_GP_PIN(5, 11),
1663 };
1664 static const unsigned int avb_avtp_capture_mux[] = {
1665         AVB_AVTP_CAPTURE_MARK,
1666 };
1667 static const unsigned int avb_avtp_match_pins[] = {
1668         RCAR_GP_PIN(5, 12),
1669 };
1670 static const unsigned int avb_avtp_match_mux[] = {
1671         AVB_AVTP_MATCH_MARK,
1672 };
1673 static const unsigned int avb_avtp_capture_b_pins[] = {
1674         RCAR_GP_PIN(1, 1),
1675 };
1676 static const unsigned int avb_avtp_capture_b_mux[] = {
1677         AVB_AVTP_CAPTURE_B_MARK,
1678 };
1679 static const unsigned int avb_avtp_match_b_pins[] = {
1680         RCAR_GP_PIN(1, 2),
1681 };
1682 static const unsigned int avb_avtp_match_b_mux[] = {
1683         AVB_AVTP_MATCH_B_MARK,
1684 };
1685 /* - ETH -------------------------------------------------------------------- */
1686 static const unsigned int eth_link_pins[] = {
1687         /* LINK */
1688         RCAR_GP_PIN(3, 18),
1689 };
1690 static const unsigned int eth_link_mux[] = {
1691         ETH_LINK_MARK,
1692 };
1693 static const unsigned int eth_magic_pins[] = {
1694         /* MAGIC */
1695         RCAR_GP_PIN(3, 22),
1696 };
1697 static const unsigned int eth_magic_mux[] = {
1698         ETH_MAGIC_MARK,
1699 };
1700 static const unsigned int eth_mdio_pins[] = {
1701         /* MDC, MDIO */
1702         RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 13),
1703 };
1704 static const unsigned int eth_mdio_mux[] = {
1705         ETH_MDC_MARK, ETH_MDIO_MARK,
1706 };
1707 static const unsigned int eth_rmii_pins[] = {
1708         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1709         RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 15),
1710         RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 20),
1711         RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 19),
1712 };
1713 static const unsigned int eth_rmii_mux[] = {
1714         ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1715         ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1716 };
1717 static const unsigned int eth_link_b_pins[] = {
1718         /* LINK */
1719         RCAR_GP_PIN(5, 15),
1720 };
1721 static const unsigned int eth_link_b_mux[] = {
1722         ETH_LINK_B_MARK,
1723 };
1724 static const unsigned int eth_magic_b_pins[] = {
1725         /* MAGIC */
1726         RCAR_GP_PIN(5, 19),
1727 };
1728 static const unsigned int eth_magic_b_mux[] = {
1729         ETH_MAGIC_B_MARK,
1730 };
1731 static const unsigned int eth_mdio_b_pins[] = {
1732         /* MDC, MDIO */
1733         RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 10),
1734 };
1735 static const unsigned int eth_mdio_b_mux[] = {
1736         ETH_MDC_B_MARK, ETH_MDIO_B_MARK,
1737 };
1738 static const unsigned int eth_rmii_b_pins[] = {
1739         /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1740         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 12),
1741         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 17),
1742         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 16),
1743 };
1744 static const unsigned int eth_rmii_b_mux[] = {
1745         ETH_RXD0_B_MARK, ETH_RXD1_B_MARK, ETH_RX_ER_B_MARK, ETH_CRS_DV_B_MARK,
1746         ETH_TXD0_B_MARK, ETH_TXD1_B_MARK, ETH_TX_EN_B_MARK, ETH_REFCLK_B_MARK,
1747 };
1748 /* - HSCIF0 ----------------------------------------------------------------- */
1749 static const unsigned int hscif0_data_pins[] = {
1750         /* RX, TX */
1751         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1752 };
1753 static const unsigned int hscif0_data_mux[] = {
1754         HSCIF0_HRX_MARK, HSCIF0_HTX_MARK,
1755 };
1756 static const unsigned int hscif0_clk_pins[] = {
1757         /* SCK */
1758         RCAR_GP_PIN(3, 29),
1759 };
1760 static const unsigned int hscif0_clk_mux[] = {
1761         HSCIF0_HSCK_MARK,
1762 };
1763 static const unsigned int hscif0_ctrl_pins[] = {
1764         /* RTS, CTS */
1765         RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1766 };
1767 static const unsigned int hscif0_ctrl_mux[] = {
1768         HSCIF0_HRTS_N_MARK, HSCIF0_HCTS_N_MARK,
1769 };
1770 static const unsigned int hscif0_data_b_pins[] = {
1771         /* RX, TX */
1772         RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 31),
1773 };
1774 static const unsigned int hscif0_data_b_mux[] = {
1775         HSCIF0_HRX_B_MARK, HSCIF0_HTX_B_MARK,
1776 };
1777 static const unsigned int hscif0_clk_b_pins[] = {
1778         /* SCK */
1779         RCAR_GP_PIN(1, 0),
1780 };
1781 static const unsigned int hscif0_clk_b_mux[] = {
1782         HSCIF0_HSCK_B_MARK,
1783 };
1784 /* - HSCIF1 ----------------------------------------------------------------- */
1785 static const unsigned int hscif1_data_pins[] = {
1786         /* RX, TX */
1787         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1788 };
1789 static const unsigned int hscif1_data_mux[] = {
1790         HSCIF1_HRX_MARK, HSCIF1_HTX_MARK,
1791 };
1792 static const unsigned int hscif1_clk_pins[] = {
1793         /* SCK */
1794         RCAR_GP_PIN(4, 10),
1795 };
1796 static const unsigned int hscif1_clk_mux[] = {
1797         HSCIF1_HSCK_MARK,
1798 };
1799 static const unsigned int hscif1_ctrl_pins[] = {
1800         /* RTS, CTS */
1801         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
1802 };
1803 static const unsigned int hscif1_ctrl_mux[] = {
1804         HSCIF1_HRTS_N_MARK, HSCIF1_HCTS_N_MARK,
1805 };
1806 static const unsigned int hscif1_data_b_pins[] = {
1807         /* RX, TX */
1808         RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1809 };
1810 static const unsigned int hscif1_data_b_mux[] = {
1811         HSCIF1_HRX_B_MARK, HSCIF1_HTX_B_MARK,
1812 };
1813 static const unsigned int hscif1_ctrl_b_pins[] = {
1814         /* RTS, CTS */
1815         RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 15),
1816 };
1817 static const unsigned int hscif1_ctrl_b_mux[] = {
1818         HSCIF1_HRTS_N_B_MARK, HSCIF1_HCTS_N_B_MARK,
1819 };
1820 /* - HSCIF2 ----------------------------------------------------------------- */
1821 static const unsigned int hscif2_data_pins[] = {
1822         /* RX, TX */
1823         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1824 };
1825 static const unsigned int hscif2_data_mux[] = {
1826         HSCIF2_HRX_MARK, HSCIF2_HTX_MARK,
1827 };
1828 static const unsigned int hscif2_clk_pins[] = {
1829         /* SCK */
1830         RCAR_GP_PIN(0, 10),
1831 };
1832 static const unsigned int hscif2_clk_mux[] = {
1833         HSCIF2_HSCK_MARK,
1834 };
1835 static const unsigned int hscif2_ctrl_pins[] = {
1836         /* RTS, CTS */
1837         RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
1838 };
1839 static const unsigned int hscif2_ctrl_mux[] = {
1840         HSCIF2_HRTS_N_MARK, HSCIF2_HCTS_N_MARK,
1841 };
1842 /* - I2C0 ------------------------------------------------------------------- */
1843 static const unsigned int i2c0_pins[] = {
1844         /* SCL, SDA */
1845         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
1846 };
1847 static const unsigned int i2c0_mux[] = {
1848         I2C0_SCL_MARK, I2C0_SDA_MARK,
1849 };
1850 static const unsigned int i2c0_b_pins[] = {
1851         /* SCL, SDA */
1852         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
1853 };
1854 static const unsigned int i2c0_b_mux[] = {
1855         I2C0_SCL_B_MARK, I2C0_SDA_B_MARK,
1856 };
1857 static const unsigned int i2c0_c_pins[] = {
1858         /* SCL, SDA */
1859         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
1860 };
1861 static const unsigned int i2c0_c_mux[] = {
1862         I2C0_SCL_C_MARK, I2C0_SDA_C_MARK,
1863 };
1864 static const unsigned int i2c0_d_pins[] = {
1865         /* SCL, SDA */
1866         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
1867 };
1868 static const unsigned int i2c0_d_mux[] = {
1869         I2C0_SCL_D_MARK, I2C0_SDA_D_MARK,
1870 };
1871 static const unsigned int i2c0_e_pins[] = {
1872         /* SCL, SDA */
1873         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
1874 };
1875 static const unsigned int i2c0_e_mux[] = {
1876         I2C0_SCL_E_MARK, I2C0_SDA_E_MARK,
1877 };
1878 /* - I2C1 ------------------------------------------------------------------- */
1879 static const unsigned int i2c1_pins[] = {
1880         /* SCL, SDA */
1881         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
1882 };
1883 static const unsigned int i2c1_mux[] = {
1884         I2C1_SCL_MARK, I2C1_SDA_MARK,
1885 };
1886 static const unsigned int i2c1_b_pins[] = {
1887         /* SCL, SDA */
1888         RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
1889 };
1890 static const unsigned int i2c1_b_mux[] = {
1891         I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
1892 };
1893 static const unsigned int i2c1_c_pins[] = {
1894         /* SCL, SDA */
1895         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
1896 };
1897 static const unsigned int i2c1_c_mux[] = {
1898         I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
1899 };
1900 static const unsigned int i2c1_d_pins[] = {
1901         /* SCL, SDA */
1902         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
1903 };
1904 static const unsigned int i2c1_d_mux[] = {
1905         I2C1_SCL_D_MARK, I2C1_SDA_D_MARK,
1906 };
1907 static const unsigned int i2c1_e_pins[] = {
1908         /* SCL, SDA */
1909         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
1910 };
1911 static const unsigned int i2c1_e_mux[] = {
1912         I2C1_SCL_E_MARK, I2C1_SDA_E_MARK,
1913 };
1914 /* - I2C2 ------------------------------------------------------------------- */
1915 static const unsigned int i2c2_pins[] = {
1916         /* SCL, SDA */
1917         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
1918 };
1919 static const unsigned int i2c2_mux[] = {
1920         I2C2_SCL_MARK, I2C2_SDA_MARK,
1921 };
1922 static const unsigned int i2c2_b_pins[] = {
1923         /* SCL, SDA */
1924         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
1925 };
1926 static const unsigned int i2c2_b_mux[] = {
1927         I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
1928 };
1929 static const unsigned int i2c2_c_pins[] = {
1930         /* SCL, SDA */
1931         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
1932 };
1933 static const unsigned int i2c2_c_mux[] = {
1934         I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
1935 };
1936 static const unsigned int i2c2_d_pins[] = {
1937         /* SCL, SDA */
1938         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
1939 };
1940 static const unsigned int i2c2_d_mux[] = {
1941         I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
1942 };
1943 static const unsigned int i2c2_e_pins[] = {
1944         /* SCL, SDA */
1945         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
1946 };
1947 static const unsigned int i2c2_e_mux[] = {
1948         I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
1949 };
1950 /* - I2C3 ------------------------------------------------------------------- */
1951 static const unsigned int i2c3_pins[] = {
1952         /* SCL, SDA */
1953         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
1954 };
1955 static const unsigned int i2c3_mux[] = {
1956         I2C3_SCL_MARK, I2C3_SDA_MARK,
1957 };
1958 static const unsigned int i2c3_b_pins[] = {
1959         /* SCL, SDA */
1960         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
1961 };
1962 static const unsigned int i2c3_b_mux[] = {
1963         I2C3_SCL_B_MARK, I2C3_SDA_B_MARK,
1964 };
1965 static const unsigned int i2c3_c_pins[] = {
1966         /* SCL, SDA */
1967         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1968 };
1969 static const unsigned int i2c3_c_mux[] = {
1970         I2C3_SCL_C_MARK, I2C3_SDA_C_MARK,
1971 };
1972 static const unsigned int i2c3_d_pins[] = {
1973         /* SCL, SDA */
1974         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
1975 };
1976 static const unsigned int i2c3_d_mux[] = {
1977         I2C3_SCL_D_MARK, I2C3_SDA_D_MARK,
1978 };
1979 static const unsigned int i2c3_e_pins[] = {
1980         /* SCL, SDA */
1981         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
1982 };
1983 static const unsigned int i2c3_e_mux[] = {
1984         I2C3_SCL_E_MARK, I2C3_SDA_E_MARK,
1985 };
1986 /* - I2C4 ------------------------------------------------------------------- */
1987 static const unsigned int i2c4_pins[] = {
1988         /* SCL, SDA */
1989         RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
1990 };
1991 static const unsigned int i2c4_mux[] = {
1992         I2C4_SCL_MARK, I2C4_SDA_MARK,
1993 };
1994 static const unsigned int i2c4_b_pins[] = {
1995         /* SCL, SDA */
1996         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
1997 };
1998 static const unsigned int i2c4_b_mux[] = {
1999         I2C4_SCL_B_MARK, I2C4_SDA_B_MARK,
2000 };
2001 static const unsigned int i2c4_c_pins[] = {
2002         /* SCL, SDA */
2003         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2004 };
2005 static const unsigned int i2c4_c_mux[] = {
2006         I2C4_SCL_C_MARK, I2C4_SDA_C_MARK,
2007 };
2008 static const unsigned int i2c4_d_pins[] = {
2009         /* SCL, SDA */
2010         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2011 };
2012 static const unsigned int i2c4_d_mux[] = {
2013         I2C4_SCL_D_MARK, I2C4_SDA_D_MARK,
2014 };
2015 static const unsigned int i2c4_e_pins[] = {
2016         /* SCL, SDA */
2017         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2018 };
2019 static const unsigned int i2c4_e_mux[] = {
2020         I2C4_SCL_E_MARK, I2C4_SDA_E_MARK,
2021 };
2022 /* - INTC ------------------------------------------------------------------- */
2023 static const unsigned int intc_irq0_pins[] = {
2024         /* IRQ0 */
2025         RCAR_GP_PIN(4, 4),
2026 };
2027 static const unsigned int intc_irq0_mux[] = {
2028         IRQ0_MARK,
2029 };
2030 static const unsigned int intc_irq1_pins[] = {
2031         /* IRQ1 */
2032         RCAR_GP_PIN(4, 18),
2033 };
2034 static const unsigned int intc_irq1_mux[] = {
2035         IRQ1_MARK,
2036 };
2037 static const unsigned int intc_irq2_pins[] = {
2038         /* IRQ2 */
2039         RCAR_GP_PIN(4, 19),
2040 };
2041 static const unsigned int intc_irq2_mux[] = {
2042         IRQ2_MARK,
2043 };
2044 static const unsigned int intc_irq3_pins[] = {
2045         /* IRQ3 */
2046         RCAR_GP_PIN(0, 7),
2047 };
2048 static const unsigned int intc_irq3_mux[] = {
2049         IRQ3_MARK,
2050 };
2051 static const unsigned int intc_irq4_pins[] = {
2052         /* IRQ4 */
2053         RCAR_GP_PIN(0, 0),
2054 };
2055 static const unsigned int intc_irq4_mux[] = {
2056         IRQ4_MARK,
2057 };
2058 static const unsigned int intc_irq5_pins[] = {
2059         /* IRQ5 */
2060         RCAR_GP_PIN(4, 1),
2061 };
2062 static const unsigned int intc_irq5_mux[] = {
2063         IRQ5_MARK,
2064 };
2065 static const unsigned int intc_irq6_pins[] = {
2066         /* IRQ6 */
2067         RCAR_GP_PIN(0, 10),
2068 };
2069 static const unsigned int intc_irq6_mux[] = {
2070         IRQ6_MARK,
2071 };
2072 static const unsigned int intc_irq7_pins[] = {
2073         /* IRQ7 */
2074         RCAR_GP_PIN(6, 15),
2075 };
2076 static const unsigned int intc_irq7_mux[] = {
2077         IRQ7_MARK,
2078 };
2079 static const unsigned int intc_irq8_pins[] = {
2080         /* IRQ8 */
2081         RCAR_GP_PIN(5, 0),
2082 };
2083 static const unsigned int intc_irq8_mux[] = {
2084         IRQ8_MARK,
2085 };
2086 static const unsigned int intc_irq9_pins[] = {
2087         /* IRQ9 */
2088         RCAR_GP_PIN(5, 10),
2089 };
2090 static const unsigned int intc_irq9_mux[] = {
2091         IRQ9_MARK,
2092 };
2093 /* - MMCIF ------------------------------------------------------------------ */
2094 static const unsigned int mmc_data1_pins[] = {
2095         /* D[0] */
2096         RCAR_GP_PIN(6, 18),
2097 };
2098 static const unsigned int mmc_data1_mux[] = {
2099         MMC_D0_MARK,
2100 };
2101 static const unsigned int mmc_data4_pins[] = {
2102         /* D[0:3] */
2103         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2104         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2105 };
2106 static const unsigned int mmc_data4_mux[] = {
2107         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2108 };
2109 static const unsigned int mmc_data8_pins[] = {
2110         /* D[0:7] */
2111         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2112         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2113         RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
2114         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2115 };
2116 static const unsigned int mmc_data8_mux[] = {
2117         MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
2118         MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
2119 };
2120 static const unsigned int mmc_ctrl_pins[] = {
2121         /* CLK, CMD */
2122         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2123 };
2124 static const unsigned int mmc_ctrl_mux[] = {
2125         MMC_CLK_MARK, MMC_CMD_MARK,
2126 };
2127 /* - MSIOF0 ----------------------------------------------------------------- */
2128 static const unsigned int msiof0_clk_pins[] = {
2129         /* SCK */
2130         RCAR_GP_PIN(4, 4),
2131 };
2132 static const unsigned int msiof0_clk_mux[] = {
2133         MSIOF0_SCK_MARK,
2134 };
2135 static const unsigned int msiof0_sync_pins[] = {
2136         /* SYNC */
2137         RCAR_GP_PIN(4, 5),
2138 };
2139 static const unsigned int msiof0_sync_mux[] = {
2140         MSIOF0_SYNC_MARK,
2141 };
2142 static const unsigned int msiof0_ss1_pins[] = {
2143         /* SS1 */
2144         RCAR_GP_PIN(4, 6),
2145 };
2146 static const unsigned int msiof0_ss1_mux[] = {
2147         MSIOF0_SS1_MARK,
2148 };
2149 static const unsigned int msiof0_ss2_pins[] = {
2150         /* SS2 */
2151         RCAR_GP_PIN(4, 7),
2152 };
2153 static const unsigned int msiof0_ss2_mux[] = {
2154         MSIOF0_SS2_MARK,
2155 };
2156 static const unsigned int msiof0_rx_pins[] = {
2157         /* RXD */
2158         RCAR_GP_PIN(4, 2),
2159 };
2160 static const unsigned int msiof0_rx_mux[] = {
2161         MSIOF0_RXD_MARK,
2162 };
2163 static const unsigned int msiof0_tx_pins[] = {
2164         /* TXD */
2165         RCAR_GP_PIN(4, 3),
2166 };
2167 static const unsigned int msiof0_tx_mux[] = {
2168         MSIOF0_TXD_MARK,
2169 };
2170 /* - MSIOF1 ----------------------------------------------------------------- */
2171 static const unsigned int msiof1_clk_pins[] = {
2172         /* SCK */
2173         RCAR_GP_PIN(0, 26),
2174 };
2175 static const unsigned int msiof1_clk_mux[] = {
2176         MSIOF1_SCK_MARK,
2177 };
2178 static const unsigned int msiof1_sync_pins[] = {
2179         /* SYNC */
2180         RCAR_GP_PIN(0, 27),
2181 };
2182 static const unsigned int msiof1_sync_mux[] = {
2183         MSIOF1_SYNC_MARK,
2184 };
2185 static const unsigned int msiof1_ss1_pins[] = {
2186         /* SS1 */
2187         RCAR_GP_PIN(0, 28),
2188 };
2189 static const unsigned int msiof1_ss1_mux[] = {
2190         MSIOF1_SS1_MARK,
2191 };
2192 static const unsigned int msiof1_ss2_pins[] = {
2193         /* SS2 */
2194         RCAR_GP_PIN(0, 29),
2195 };
2196 static const unsigned int msiof1_ss2_mux[] = {
2197         MSIOF1_SS2_MARK,
2198 };
2199 static const unsigned int msiof1_rx_pins[] = {
2200         /* RXD */
2201         RCAR_GP_PIN(0, 24),
2202 };
2203 static const unsigned int msiof1_rx_mux[] = {
2204         MSIOF1_RXD_MARK,
2205 };
2206 static const unsigned int msiof1_tx_pins[] = {
2207         /* TXD */
2208         RCAR_GP_PIN(0, 25),
2209 };
2210 static const unsigned int msiof1_tx_mux[] = {
2211         MSIOF1_TXD_MARK,
2212 };
2213 static const unsigned int msiof1_clk_b_pins[] = {
2214         /* SCK */
2215         RCAR_GP_PIN(5, 3),
2216 };
2217 static const unsigned int msiof1_clk_b_mux[] = {
2218         MSIOF1_SCK_B_MARK,
2219 };
2220 static const unsigned int msiof1_sync_b_pins[] = {
2221         /* SYNC */
2222         RCAR_GP_PIN(5, 4),
2223 };
2224 static const unsigned int msiof1_sync_b_mux[] = {
2225         MSIOF1_SYNC_B_MARK,
2226 };
2227 static const unsigned int msiof1_ss1_b_pins[] = {
2228         /* SS1 */
2229         RCAR_GP_PIN(5, 5),
2230 };
2231 static const unsigned int msiof1_ss1_b_mux[] = {
2232         MSIOF1_SS1_B_MARK,
2233 };
2234 static const unsigned int msiof1_ss2_b_pins[] = {
2235         /* SS2 */
2236         RCAR_GP_PIN(5, 6),
2237 };
2238 static const unsigned int msiof1_ss2_b_mux[] = {
2239         MSIOF1_SS2_B_MARK,
2240 };
2241 static const unsigned int msiof1_rx_b_pins[] = {
2242         /* RXD */
2243         RCAR_GP_PIN(5, 1),
2244 };
2245 static const unsigned int msiof1_rx_b_mux[] = {
2246         MSIOF1_RXD_B_MARK,
2247 };
2248 static const unsigned int msiof1_tx_b_pins[] = {
2249         /* TXD */
2250         RCAR_GP_PIN(5, 2),
2251 };
2252 static const unsigned int msiof1_tx_b_mux[] = {
2253         MSIOF1_TXD_B_MARK,
2254 };
2255 /* - MSIOF2 ----------------------------------------------------------------- */
2256 static const unsigned int msiof2_clk_pins[] = {
2257         /* SCK */
2258         RCAR_GP_PIN(1, 0),
2259 };
2260 static const unsigned int msiof2_clk_mux[] = {
2261         MSIOF2_SCK_MARK,
2262 };
2263 static const unsigned int msiof2_sync_pins[] = {
2264         /* SYNC */
2265         RCAR_GP_PIN(1, 1),
2266 };
2267 static const unsigned int msiof2_sync_mux[] = {
2268         MSIOF2_SYNC_MARK,
2269 };
2270 static const unsigned int msiof2_ss1_pins[] = {
2271         /* SS1 */
2272         RCAR_GP_PIN(1, 2),
2273 };
2274 static const unsigned int msiof2_ss1_mux[] = {
2275         MSIOF2_SS1_MARK,
2276 };
2277 static const unsigned int msiof2_ss2_pins[] = {
2278         /* SS2 */
2279         RCAR_GP_PIN(1, 3),
2280 };
2281 static const unsigned int msiof2_ss2_mux[] = {
2282         MSIOF2_SS2_MARK,
2283 };
2284 static const unsigned int msiof2_rx_pins[] = {
2285         /* RXD */
2286         RCAR_GP_PIN(0, 30),
2287 };
2288 static const unsigned int msiof2_rx_mux[] = {
2289         MSIOF2_RXD_MARK,
2290 };
2291 static const unsigned int msiof2_tx_pins[] = {
2292         /* TXD */
2293         RCAR_GP_PIN(0, 31),
2294 };
2295 static const unsigned int msiof2_tx_mux[] = {
2296         MSIOF2_TXD_MARK,
2297 };
2298 static const unsigned int msiof2_clk_b_pins[] = {
2299         /* SCK */
2300         RCAR_GP_PIN(3, 15),
2301 };
2302 static const unsigned int msiof2_clk_b_mux[] = {
2303         MSIOF2_SCK_B_MARK,
2304 };
2305 static const unsigned int msiof2_sync_b_pins[] = {
2306         /* SYNC */
2307         RCAR_GP_PIN(3, 16),
2308 };
2309 static const unsigned int msiof2_sync_b_mux[] = {
2310         MSIOF2_SYNC_B_MARK,
2311 };
2312 static const unsigned int msiof2_ss1_b_pins[] = {
2313         /* SS1 */
2314         RCAR_GP_PIN(3, 17),
2315 };
2316 static const unsigned int msiof2_ss1_b_mux[] = {
2317         MSIOF2_SS1_B_MARK,
2318 };
2319 static const unsigned int msiof2_ss2_b_pins[] = {
2320         /* SS2 */
2321         RCAR_GP_PIN(3, 18),
2322 };
2323 static const unsigned int msiof2_ss2_b_mux[] = {
2324         MSIOF2_SS2_B_MARK,
2325 };
2326 static const unsigned int msiof2_rx_b_pins[] = {
2327         /* RXD */
2328         RCAR_GP_PIN(3, 13),
2329 };
2330 static const unsigned int msiof2_rx_b_mux[] = {
2331         MSIOF2_RXD_B_MARK,
2332 };
2333 static const unsigned int msiof2_tx_b_pins[] = {
2334         /* TXD */
2335         RCAR_GP_PIN(3, 14),
2336 };
2337 static const unsigned int msiof2_tx_b_mux[] = {
2338         MSIOF2_TXD_B_MARK,
2339 };
2340 /* - QSPI ------------------------------------------------------------------- */
2341 static const unsigned int qspi_ctrl_pins[] = {
2342         /* SPCLK, SSL */
2343         RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 9),
2344 };
2345 static const unsigned int qspi_ctrl_mux[] = {
2346         SPCLK_MARK, SSL_MARK,
2347 };
2348 static const unsigned int qspi_data2_pins[] = {
2349         /* MOSI_IO0, MISO_IO1 */
2350         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
2351 };
2352 static const unsigned int qspi_data2_mux[] = {
2353         MOSI_IO0_MARK, MISO_IO1_MARK,
2354 };
2355 static const unsigned int qspi_data4_pins[] = {
2356         /* MOSI_IO0, MISO_IO1, IO2, IO3 */
2357         RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
2358         RCAR_GP_PIN(1, 8),
2359 };
2360 static const unsigned int qspi_data4_mux[] = {
2361         MOSI_IO0_MARK, MISO_IO1_MARK, IO2_MARK, IO3_MARK,
2362 };
2363 /* - SCIF0 ------------------------------------------------------------------ */
2364 static const unsigned int scif0_data_pins[] = {
2365         /* RX, TX */
2366         RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2367 };
2368 static const unsigned int scif0_data_mux[] = {
2369         SCIF0_RXD_MARK, SCIF0_TXD_MARK,
2370 };
2371 static const unsigned int scif0_data_b_pins[] = {
2372         /* RX, TX */
2373         RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12),
2374 };
2375 static const unsigned int scif0_data_b_mux[] = {
2376         SCIF0_RXD_B_MARK, SCIF0_TXD_B_MARK,
2377 };
2378 static const unsigned int scif0_data_c_pins[] = {
2379         /* RX, TX */
2380         RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
2381 };
2382 static const unsigned int scif0_data_c_mux[] = {
2383         SCIF0_RXD_C_MARK, SCIF0_TXD_C_MARK,
2384 };
2385 static const unsigned int scif0_data_d_pins[] = {
2386         /* RX, TX */
2387         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
2388 };
2389 static const unsigned int scif0_data_d_mux[] = {
2390         SCIF0_RXD_D_MARK, SCIF0_TXD_D_MARK,
2391 };
2392 /* - SCIF1 ------------------------------------------------------------------ */
2393 static const unsigned int scif1_data_pins[] = {
2394         /* RX, TX */
2395         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
2396 };
2397 static const unsigned int scif1_data_mux[] = {
2398         SCIF1_RXD_MARK, SCIF1_TXD_MARK,
2399 };
2400 static const unsigned int scif1_clk_pins[] = {
2401         /* SCK */
2402         RCAR_GP_PIN(4, 13),
2403 };
2404 static const unsigned int scif1_clk_mux[] = {
2405         SCIF1_SCK_MARK,
2406 };
2407 static const unsigned int scif1_data_b_pins[] = {
2408         /* RX, TX */
2409         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2410 };
2411 static const unsigned int scif1_data_b_mux[] = {
2412         SCIF1_RXD_B_MARK, SCIF1_TXD_B_MARK,
2413 };
2414 static const unsigned int scif1_clk_b_pins[] = {
2415         /* SCK */
2416         RCAR_GP_PIN(5, 10),
2417 };
2418 static const unsigned int scif1_clk_b_mux[] = {
2419         SCIF1_SCK_B_MARK,
2420 };
2421 static const unsigned int scif1_data_c_pins[] = {
2422         /* RX, TX */
2423         RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 12),
2424 };
2425 static const unsigned int scif1_data_c_mux[] = {
2426         SCIF1_RXD_C_MARK, SCIF1_TXD_C_MARK,
2427 };
2428 static const unsigned int scif1_clk_c_pins[] = {
2429         /* SCK */
2430         RCAR_GP_PIN(0, 10),
2431 };
2432 static const unsigned int scif1_clk_c_mux[] = {
2433         SCIF1_SCK_C_MARK,
2434 };
2435 /* - SCIF2 ------------------------------------------------------------------ */
2436 static const unsigned int scif2_data_pins[] = {
2437         /* RX, TX */
2438         RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2439 };
2440 static const unsigned int scif2_data_mux[] = {
2441         SCIF2_RXD_MARK, SCIF2_TXD_MARK,
2442 };
2443 static const unsigned int scif2_clk_pins[] = {
2444         /* SCK */
2445         RCAR_GP_PIN(4, 18),
2446 };
2447 static const unsigned int scif2_clk_mux[] = {
2448         SCIF2_SCK_MARK,
2449 };
2450 static const unsigned int scif2_data_b_pins[] = {
2451         /* RX, TX */
2452         RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
2453 };
2454 static const unsigned int scif2_data_b_mux[] = {
2455         SCIF2_RXD_B_MARK, SCIF2_TXD_B_MARK,
2456 };
2457 static const unsigned int scif2_clk_b_pins[] = {
2458         /* SCK */
2459         RCAR_GP_PIN(5, 17),
2460 };
2461 static const unsigned int scif2_clk_b_mux[] = {
2462         SCIF2_SCK_B_MARK,
2463 };
2464 static const unsigned int scif2_data_c_pins[] = {
2465         /* RX, TX */
2466         RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
2467 };
2468 static const unsigned int scif2_data_c_mux[] = {
2469         SCIF2_RXD_C_MARK, SCIF2_TXD_C_MARK,
2470 };
2471 static const unsigned int scif2_clk_c_pins[] = {
2472         /* SCK */
2473         RCAR_GP_PIN(3, 19),
2474 };
2475 static const unsigned int scif2_clk_c_mux[] = {
2476         SCIF2_SCK_C_MARK,
2477 };
2478 /* - SCIF3 ------------------------------------------------------------------ */
2479 static const unsigned int scif3_data_pins[] = {
2480         /* RX, TX */
2481         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
2482 };
2483 static const unsigned int scif3_data_mux[] = {
2484         SCIF3_RXD_MARK, SCIF3_TXD_MARK,
2485 };
2486 static const unsigned int scif3_clk_pins[] = {
2487         /* SCK */
2488         RCAR_GP_PIN(4, 19),
2489 };
2490 static const unsigned int scif3_clk_mux[] = {
2491         SCIF3_SCK_MARK,
2492 };
2493 static const unsigned int scif3_data_b_pins[] = {
2494         /* RX, TX */
2495         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
2496 };
2497 static const unsigned int scif3_data_b_mux[] = {
2498         SCIF3_RXD_B_MARK, SCIF3_TXD_B_MARK,
2499 };
2500 static const unsigned int scif3_clk_b_pins[] = {
2501         /* SCK */
2502         RCAR_GP_PIN(3, 22),
2503 };
2504 static const unsigned int scif3_clk_b_mux[] = {
2505         SCIF3_SCK_B_MARK,
2506 };
2507 /* - SCIF4 ------------------------------------------------------------------ */
2508 static const unsigned int scif4_data_pins[] = {
2509         /* RX, TX */
2510         RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2511 };
2512 static const unsigned int scif4_data_mux[] = {
2513         SCIF4_RXD_MARK, SCIF4_TXD_MARK,
2514 };
2515 static const unsigned int scif4_data_b_pins[] = {
2516         /* RX, TX */
2517         RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6),
2518 };
2519 static const unsigned int scif4_data_b_mux[] = {
2520         SCIF4_RXD_B_MARK, SCIF4_TXD_B_MARK,
2521 };
2522 static const unsigned int scif4_data_c_pins[] = {
2523         /* RX, TX */
2524         RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
2525 };
2526 static const unsigned int scif4_data_c_mux[] = {
2527         SCIF4_RXD_C_MARK, SCIF4_TXD_C_MARK,
2528 };
2529 static const unsigned int scif4_data_d_pins[] = {
2530         /* RX, TX */
2531         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
2532 };
2533 static const unsigned int scif4_data_d_mux[] = {
2534         SCIF4_RXD_D_MARK, SCIF4_TXD_D_MARK,
2535 };
2536 static const unsigned int scif4_data_e_pins[] = {
2537         /* RX, TX */
2538         RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 2),
2539 };
2540 static const unsigned int scif4_data_e_mux[] = {
2541         SCIF4_RXD_E_MARK, SCIF4_TXD_E_MARK,
2542 };
2543 /* - SCIF5 ------------------------------------------------------------------ */
2544 static const unsigned int scif5_data_pins[] = {
2545         /* RX, TX */
2546         RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 3),
2547 };
2548 static const unsigned int scif5_data_mux[] = {
2549         SCIF5_RXD_MARK, SCIF5_TXD_MARK,
2550 };
2551 static const unsigned int scif5_data_b_pins[] = {
2552         /* RX, TX */
2553         RCAR_GP_PIN(0, 3), RCAR_GP_PIN(0, 4),
2554 };
2555 static const unsigned int scif5_data_b_mux[] = {
2556         SCIF5_RXD_B_MARK, SCIF5_TXD_B_MARK,
2557 };
2558 static const unsigned int scif5_data_c_pins[] = {
2559         /* RX, TX */
2560         RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 11),
2561 };
2562 static const unsigned int scif5_data_c_mux[] = {
2563         SCIF5_RXD_C_MARK, SCIF5_TXD_C_MARK,
2564 };
2565 static const unsigned int scif5_data_d_pins[] = {
2566         /* RX, TX */
2567         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2568 };
2569 static const unsigned int scif5_data_d_mux[] = {
2570         SCIF5_RXD_D_MARK, SCIF5_TXD_D_MARK,
2571 };
2572 /* - SCIFA0 ----------------------------------------------------------------- */
2573 static const unsigned int scifa0_data_pins[] = {
2574         /* RXD, TXD */
2575         RCAR_GP_PIN(4, 6), RCAR_GP_PIN(4, 7),
2576 };
2577 static const unsigned int scifa0_data_mux[] = {
2578         SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2579 };
2580 static const unsigned int scifa0_data_b_pins[] = {
2581         /* RXD, TXD */
2582         RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
2583 };
2584 static const unsigned int scifa0_data_b_mux[] = {
2585         SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2586 };
2587 static const unsigned int scifa0_data_c_pins[] = {
2588         /* RXD, TXD */
2589         RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
2590 };
2591 static const unsigned int scifa0_data_c_mux[] = {
2592         SCIFA0_RXD_C_MARK, SCIFA0_TXD_C_MARK
2593 };
2594 static const unsigned int scifa0_data_d_pins[] = {
2595         /* RXD, TXD */
2596         RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
2597 };
2598 static const unsigned int scifa0_data_d_mux[] = {
2599         SCIFA0_RXD_D_MARK, SCIFA0_TXD_D_MARK
2600 };
2601 /* - SCIFA1 ----------------------------------------------------------------- */
2602 static const unsigned int scifa1_data_pins[] = {
2603         /* RXD, TXD */
2604         RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
2605 };
2606 static const unsigned int scifa1_data_mux[] = {
2607         SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2608 };
2609 static const unsigned int scifa1_clk_pins[] = {
2610         /* SCK */
2611         RCAR_GP_PIN(0, 13),
2612 };
2613 static const unsigned int scifa1_clk_mux[] = {
2614         SCIFA1_SCK_MARK,
2615 };
2616 static const unsigned int scifa1_data_b_pins[] = {
2617         /* RXD, TXD */
2618         RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
2619 };
2620 static const unsigned int scifa1_data_b_mux[] = {
2621         SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2622 };
2623 static const unsigned int scifa1_clk_b_pins[] = {
2624         /* SCK */
2625         RCAR_GP_PIN(4, 27),
2626 };
2627 static const unsigned int scifa1_clk_b_mux[] = {
2628         SCIFA1_SCK_B_MARK,
2629 };
2630 static const unsigned int scifa1_data_c_pins[] = {
2631         /* RXD, TXD */
2632         RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2633 };
2634 static const unsigned int scifa1_data_c_mux[] = {
2635         SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2636 };
2637 static const unsigned int scifa1_clk_c_pins[] = {
2638         /* SCK */
2639         RCAR_GP_PIN(5, 4),
2640 };
2641 static const unsigned int scifa1_clk_c_mux[] = {
2642         SCIFA1_SCK_C_MARK,
2643 };
2644 /* - SCIFA2 ----------------------------------------------------------------- */
2645 static const unsigned int scifa2_data_pins[] = {
2646         /* RXD, TXD */
2647         RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2648 };
2649 static const unsigned int scifa2_data_mux[] = {
2650         SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2651 };
2652 static const unsigned int scifa2_clk_pins[] = {
2653         /* SCK */
2654         RCAR_GP_PIN(1, 15),
2655 };
2656 static const unsigned int scifa2_clk_mux[] = {
2657         SCIFA2_SCK_MARK,
2658 };
2659 static const unsigned int scifa2_data_b_pins[] = {
2660         /* RXD, TXD */
2661         RCAR_GP_PIN(4, 31), RCAR_GP_PIN(5, 0),
2662 };
2663 static const unsigned int scifa2_data_b_mux[] = {
2664         SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2665 };
2666 static const unsigned int scifa2_clk_b_pins[] = {
2667         /* SCK */
2668         RCAR_GP_PIN(4, 30),
2669 };
2670 static const unsigned int scifa2_clk_b_mux[] = {
2671         SCIFA2_SCK_B_MARK,
2672 };
2673 /* - SCIFA3 ----------------------------------------------------------------- */
2674 static const unsigned int scifa3_data_pins[] = {
2675         /* RXD, TXD */
2676         RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2677 };
2678 static const unsigned int scifa3_data_mux[] = {
2679         SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2680 };
2681 static const unsigned int scifa3_clk_pins[] = {
2682         /* SCK */
2683         RCAR_GP_PIN(4, 24),
2684 };
2685 static const unsigned int scifa3_clk_mux[] = {
2686         SCIFA3_SCK_MARK,
2687 };
2688 static const unsigned int scifa3_data_b_pins[] = {
2689         /* RXD, TXD */
2690         RCAR_GP_PIN(0, 1), RCAR_GP_PIN(0, 2),
2691 };
2692 static const unsigned int scifa3_data_b_mux[] = {
2693         SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2694 };
2695 static const unsigned int scifa3_clk_b_pins[] = {
2696         /* SCK */
2697         RCAR_GP_PIN(0, 0),
2698 };
2699 static const unsigned int scifa3_clk_b_mux[] = {
2700         SCIFA3_SCK_B_MARK,
2701 };
2702 /* - SCIFA4 ----------------------------------------------------------------- */
2703 static const unsigned int scifa4_data_pins[] = {
2704         /* RXD, TXD */
2705         RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 12),
2706 };
2707 static const unsigned int scifa4_data_mux[] = {
2708         SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2709 };
2710 static const unsigned int scifa4_data_b_pins[] = {
2711         /* RXD, TXD */
2712         RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 23),
2713 };
2714 static const unsigned int scifa4_data_b_mux[] = {
2715         SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2716 };
2717 static const unsigned int scifa4_data_c_pins[] = {
2718         /* RXD, TXD */
2719         RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
2720 };
2721 static const unsigned int scifa4_data_c_mux[] = {
2722         SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2723 };
2724 static const unsigned int scifa4_data_d_pins[] = {
2725         /* RXD, TXD */
2726         RCAR_GP_PIN(5, 20), RCAR_GP_PIN(5, 21),
2727 };
2728 static const unsigned int scifa4_data_d_mux[] = {
2729         SCIFA4_RXD_D_MARK, SCIFA4_TXD_D_MARK,
2730 };
2731 /* - SCIFA5 ----------------------------------------------------------------- */
2732 static const unsigned int scifa5_data_pins[] = {
2733         /* RXD, TXD */
2734         RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
2735 };
2736 static const unsigned int scifa5_data_mux[] = {
2737         SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2738 };
2739 static const unsigned int scifa5_data_b_pins[] = {
2740         /* RXD, TXD */
2741         RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 29),
2742 };
2743 static const unsigned int scifa5_data_b_mux[] = {
2744         SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2745 };
2746 static const unsigned int scifa5_data_c_pins[] = {
2747         /* RXD, TXD */
2748         RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 10),
2749 };
2750 static const unsigned int scifa5_data_c_mux[] = {
2751         SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2752 };
2753 static const unsigned int scifa5_data_d_pins[] = {
2754         /* RXD, TXD */
2755         RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 23),
2756 };
2757 static const unsigned int scifa5_data_d_mux[] = {
2758         SCIFA5_RXD_D_MARK, SCIFA5_TXD_D_MARK,
2759 };
2760 /* - SCIFB0 ----------------------------------------------------------------- */
2761 static const unsigned int scifb0_data_pins[] = {
2762         /* RXD, TXD */
2763         RCAR_GP_PIN(0, 21), RCAR_GP_PIN(0, 20),
2764 };
2765 static const unsigned int scifb0_data_mux[] = {
2766         SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2767 };
2768 static const unsigned int scifb0_clk_pins[] = {
2769         /* SCK */
2770         RCAR_GP_PIN(0, 19),
2771 };
2772 static const unsigned int scifb0_clk_mux[] = {
2773         SCIFB0_SCK_MARK,
2774 };
2775 static const unsigned int scifb0_ctrl_pins[] = {
2776         /* RTS, CTS */
2777         RCAR_GP_PIN(0, 23), RCAR_GP_PIN(0, 22),
2778 };
2779 static const unsigned int scifb0_ctrl_mux[] = {
2780         SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2781 };
2782 /* - SCIFB1 ----------------------------------------------------------------- */
2783 static const unsigned int scifb1_data_pins[] = {
2784         /* RXD, TXD */
2785         RCAR_GP_PIN(1, 24), RCAR_GP_PIN(0, 17),
2786 };
2787 static const unsigned int scifb1_data_mux[] = {
2788         SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2789 };
2790 static const unsigned int scifb1_clk_pins[] = {
2791         /* SCK */
2792         RCAR_GP_PIN(0, 16),
2793 };
2794 static const unsigned int scifb1_clk_mux[] = {
2795         SCIFB1_SCK_MARK,
2796 };
2797 /* - SCIFB2 ----------------------------------------------------------------- */
2798 static const unsigned int scifb2_data_pins[] = {
2799         /* RXD, TXD */
2800         RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 14),
2801 };
2802 static const unsigned int scifb2_data_mux[] = {
2803         SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2804 };
2805 static const unsigned int scifb2_clk_pins[] = {
2806         /* SCK */
2807         RCAR_GP_PIN(1, 15),
2808 };
2809 static const unsigned int scifb2_clk_mux[] = {
2810         SCIFB2_SCK_MARK,
2811 };
2812 static const unsigned int scifb2_ctrl_pins[] = {
2813         /* RTS, CTS */
2814         RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16),
2815 };
2816 static const unsigned int scifb2_ctrl_mux[] = {
2817         SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2818 };
2819 /* - SCIF Clock ------------------------------------------------------------- */
2820 static const unsigned int scif_clk_pins[] = {
2821         /* SCIF_CLK */
2822         RCAR_GP_PIN(1, 23),
2823 };
2824 static const unsigned int scif_clk_mux[] = {
2825         SCIF_CLK_MARK,
2826 };
2827 static const unsigned int scif_clk_b_pins[] = {
2828         /* SCIF_CLK */
2829         RCAR_GP_PIN(3, 29),
2830 };
2831 static const unsigned int scif_clk_b_mux[] = {
2832         SCIF_CLK_B_MARK,
2833 };
2834 /* - SDHI0 ------------------------------------------------------------------ */
2835 static const unsigned int sdhi0_data1_pins[] = {
2836         /* D0 */
2837         RCAR_GP_PIN(6, 2),
2838 };
2839 static const unsigned int sdhi0_data1_mux[] = {
2840         SD0_DATA0_MARK,
2841 };
2842 static const unsigned int sdhi0_data4_pins[] = {
2843         /* D[0:3] */
2844         RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2845         RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
2846 };
2847 static const unsigned int sdhi0_data4_mux[] = {
2848         SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
2849 };
2850 static const unsigned int sdhi0_ctrl_pins[] = {
2851         /* CLK, CMD */
2852         RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2853 };
2854 static const unsigned int sdhi0_ctrl_mux[] = {
2855         SD0_CLK_MARK, SD0_CMD_MARK,
2856 };
2857 static const unsigned int sdhi0_cd_pins[] = {
2858         /* CD */
2859         RCAR_GP_PIN(6, 6),
2860 };
2861 static const unsigned int sdhi0_cd_mux[] = {
2862         SD0_CD_MARK,
2863 };
2864 static const unsigned int sdhi0_wp_pins[] = {
2865         /* WP */
2866         RCAR_GP_PIN(6, 7),
2867 };
2868 static const unsigned int sdhi0_wp_mux[] = {
2869         SD0_WP_MARK,
2870 };
2871 /* - SDHI1 ------------------------------------------------------------------ */
2872 static const unsigned int sdhi1_data1_pins[] = {
2873         /* D0 */
2874         RCAR_GP_PIN(6, 10),
2875 };
2876 static const unsigned int sdhi1_data1_mux[] = {
2877         SD1_DATA0_MARK,
2878 };
2879 static const unsigned int sdhi1_data4_pins[] = {
2880         /* D[0:3] */
2881         RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
2882         RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
2883 };
2884 static const unsigned int sdhi1_data4_mux[] = {
2885         SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
2886 };
2887 static const unsigned int sdhi1_ctrl_pins[] = {
2888         /* CLK, CMD */
2889         RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2890 };
2891 static const unsigned int sdhi1_ctrl_mux[] = {
2892         SD1_CLK_MARK, SD1_CMD_MARK,
2893 };
2894 static const unsigned int sdhi1_cd_pins[] = {
2895         /* CD */
2896         RCAR_GP_PIN(6, 14),
2897 };
2898 static const unsigned int sdhi1_cd_mux[] = {
2899         SD1_CD_MARK,
2900 };
2901 static const unsigned int sdhi1_wp_pins[] = {
2902         /* WP */
2903         RCAR_GP_PIN(6, 15),
2904 };
2905 static const unsigned int sdhi1_wp_mux[] = {
2906         SD1_WP_MARK,
2907 };
2908 /* - SDHI2 ------------------------------------------------------------------ */
2909 static const unsigned int sdhi2_data1_pins[] = {
2910         /* D0 */
2911         RCAR_GP_PIN(6, 18),
2912 };
2913 static const unsigned int sdhi2_data1_mux[] = {
2914         SD2_DATA0_MARK,
2915 };
2916 static const unsigned int sdhi2_data4_pins[] = {
2917         /* D[0:3] */
2918         RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2919         RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2920 };
2921 static const unsigned int sdhi2_data4_mux[] = {
2922         SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
2923 };
2924 static const unsigned int sdhi2_ctrl_pins[] = {
2925         /* CLK, CMD */
2926         RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2927 };
2928 static const unsigned int sdhi2_ctrl_mux[] = {
2929         SD2_CLK_MARK, SD2_CMD_MARK,
2930 };
2931 static const unsigned int sdhi2_cd_pins[] = {
2932         /* CD */
2933         RCAR_GP_PIN(6, 22),
2934 };
2935 static const unsigned int sdhi2_cd_mux[] = {
2936         SD2_CD_MARK,
2937 };
2938 static const unsigned int sdhi2_wp_pins[] = {
2939         /* WP */
2940         RCAR_GP_PIN(6, 23),
2941 };
2942 static const unsigned int sdhi2_wp_mux[] = {
2943         SD2_WP_MARK,
2944 };
2945 /* - SSI -------------------------------------------------------------------- */
2946 static const unsigned int ssi0_data_pins[] = {
2947         /* SDATA0 */
2948         RCAR_GP_PIN(5, 3),
2949 };
2950 static const unsigned int ssi0_data_mux[] = {
2951         SSI_SDATA0_MARK,
2952 };
2953 static const unsigned int ssi0129_ctrl_pins[] = {
2954         /* SCK0129, WS0129 */
2955         RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 2),
2956 };
2957 static const unsigned int ssi0129_ctrl_mux[] = {
2958         SSI_SCK0129_MARK, SSI_WS0129_MARK,
2959 };
2960 static const unsigned int ssi1_data_pins[] = {
2961         /* SDATA1 */
2962         RCAR_GP_PIN(5, 13),
2963 };
2964 static const unsigned int ssi1_data_mux[] = {
2965         SSI_SDATA1_MARK,
2966 };
2967 static const unsigned int ssi1_ctrl_pins[] = {
2968         /* SCK1, WS1 */
2969         RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2970 };
2971 static const unsigned int ssi1_ctrl_mux[] = {
2972         SSI_SCK1_MARK, SSI_WS1_MARK,
2973 };
2974 static const unsigned int ssi1_data_b_pins[] = {
2975         /* SDATA1 */
2976         RCAR_GP_PIN(4, 13),
2977 };
2978 static const unsigned int ssi1_data_b_mux[] = {
2979         SSI_SDATA1_B_MARK,
2980 };
2981 static const unsigned int ssi1_ctrl_b_pins[] = {
2982         /* SCK1, WS1 */
2983         RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2984 };
2985 static const unsigned int ssi1_ctrl_b_mux[] = {
2986         SSI_SCK1_B_MARK, SSI_WS1_B_MARK,
2987 };
2988 static const unsigned int ssi2_data_pins[] = {
2989         /* SDATA2 */
2990         RCAR_GP_PIN(5, 16),
2991 };
2992 static const unsigned int ssi2_data_mux[] = {
2993         SSI_SDATA2_MARK,
2994 };
2995 static const unsigned int ssi2_ctrl_pins[] = {
2996         /* SCK2, WS2 */
2997         RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
2998 };
2999 static const unsigned int ssi2_ctrl_mux[] = {
3000         SSI_SCK2_MARK, SSI_WS2_MARK,
3001 };
3002 static const unsigned int ssi2_data_b_pins[] = {
3003         /* SDATA2 */
3004         RCAR_GP_PIN(4, 16),
3005 };
3006 static const unsigned int ssi2_data_b_mux[] = {
3007         SSI_SDATA2_B_MARK,
3008 };
3009 static const unsigned int ssi2_ctrl_b_pins[] = {
3010         /* SCK2, WS2 */
3011         RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3012 };
3013 static const unsigned int ssi2_ctrl_b_mux[] = {
3014         SSI_SCK2_B_MARK, SSI_WS2_B_MARK,
3015 };
3016 static const unsigned int ssi3_data_pins[] = {
3017         /* SDATA3 */
3018         RCAR_GP_PIN(5, 6),
3019 };
3020 static const unsigned int ssi3_data_mux[] = {
3021         SSI_SDATA3_MARK
3022 };
3023 static const unsigned int ssi34_ctrl_pins[] = {
3024         /* SCK34, WS34 */
3025         RCAR_GP_PIN(5, 4), RCAR_GP_PIN(5, 5),
3026 };
3027 static const unsigned int ssi34_ctrl_mux[] = {
3028         SSI_SCK34_MARK, SSI_WS34_MARK,
3029 };
3030 static const unsigned int ssi4_data_pins[] = {
3031         /* SDATA4 */
3032         RCAR_GP_PIN(5, 9),
3033 };
3034 static const unsigned int ssi4_data_mux[] = {
3035         SSI_SDATA4_MARK,
3036 };
3037 static const unsigned int ssi4_ctrl_pins[] = {
3038         /* SCK4, WS4 */
3039         RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
3040 };
3041 static const unsigned int ssi4_ctrl_mux[] = {
3042         SSI_SCK4_MARK, SSI_WS4_MARK,
3043 };
3044 static const unsigned int ssi4_data_b_pins[] = {
3045         /* SDATA4 */
3046         RCAR_GP_PIN(4, 22),
3047 };
3048 static const unsigned int ssi4_data_b_mux[] = {
3049         SSI_SDATA4_B_MARK,
3050 };
3051 static const unsigned int ssi4_ctrl_b_pins[] = {
3052         /* SCK4, WS4 */
3053         RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3054 };
3055 static const unsigned int ssi4_ctrl_b_mux[] = {
3056         SSI_SCK4_B_MARK, SSI_WS4_B_MARK,
3057 };
3058 static const unsigned int ssi5_data_pins[] = {
3059         /* SDATA5 */
3060         RCAR_GP_PIN(4, 26),
3061 };
3062 static const unsigned int ssi5_data_mux[] = {
3063         SSI_SDATA5_MARK,
3064 };
3065 static const unsigned int ssi5_ctrl_pins[] = {
3066         /* SCK5, WS5 */
3067         RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3068 };
3069 static const unsigned int ssi5_ctrl_mux[] = {
3070         SSI_SCK5_MARK, SSI_WS5_MARK,
3071 };
3072 static const unsigned int ssi5_data_b_pins[] = {
3073         /* SDATA5 */
3074         RCAR_GP_PIN(3, 21),
3075 };
3076 static const unsigned int ssi5_data_b_mux[] = {
3077         SSI_SDATA5_B_MARK,
3078 };
3079 static const unsigned int ssi5_ctrl_b_pins[] = {
3080         /* SCK5, WS5 */
3081         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3082 };
3083 static const unsigned int ssi5_ctrl_b_mux[] = {
3084         SSI_SCK5_B_MARK, SSI_WS5_B_MARK,
3085 };
3086 static const unsigned int ssi6_data_pins[] = {
3087         /* SDATA6 */
3088         RCAR_GP_PIN(4, 29),
3089 };
3090 static const unsigned int ssi6_data_mux[] = {
3091         SSI_SDATA6_MARK,
3092 };
3093 static const unsigned int ssi6_ctrl_pins[] = {
3094         /* SCK6, WS6 */
3095         RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
3096 };
3097 static const unsigned int ssi6_ctrl_mux[] = {
3098         SSI_SCK6_MARK, SSI_WS6_MARK,
3099 };
3100 static const unsigned int ssi6_data_b_pins[] = {
3101         /* SDATA6 */
3102         RCAR_GP_PIN(3, 24),
3103 };
3104 static const unsigned int ssi6_data_b_mux[] = {
3105         SSI_SDATA6_B_MARK,
3106 };
3107 static const unsigned int ssi6_ctrl_b_pins[] = {
3108         /* SCK6, WS6 */
3109         RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
3110 };
3111 static const unsigned int ssi6_ctrl_b_mux[] = {
3112         SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3113 };
3114 static const unsigned int ssi7_data_pins[] = {
3115         /* SDATA7 */
3116         RCAR_GP_PIN(5, 0),
3117 };
3118 static const unsigned int ssi7_data_mux[] = {
3119         SSI_SDATA7_MARK,
3120 };
3121 static const unsigned int ssi78_ctrl_pins[] = {
3122         /* SCK78, WS78 */
3123         RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 31),
3124 };
3125 static const unsigned int ssi78_ctrl_mux[] = {
3126         SSI_SCK78_MARK, SSI_WS78_MARK,
3127 };
3128 static const unsigned int ssi7_data_b_pins[] = {
3129         /* SDATA7 */
3130         RCAR_GP_PIN(3, 27),
3131 };
3132 static const unsigned int ssi7_data_b_mux[] = {
3133         SSI_SDATA7_B_MARK,
3134 };
3135 static const unsigned int ssi78_ctrl_b_pins[] = {
3136         /* SCK78, WS78 */
3137         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3138 };
3139 static const unsigned int ssi78_ctrl_b_mux[] = {
3140         SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3141 };
3142 static const unsigned int ssi8_data_pins[] = {
3143         /* SDATA8 */
3144         RCAR_GP_PIN(5, 10),
3145 };
3146 static const unsigned int ssi8_data_mux[] = {
3147         SSI_SDATA8_MARK,
3148 };
3149 static const unsigned int ssi8_data_b_pins[] = {
3150         /* SDATA8 */
3151         RCAR_GP_PIN(3, 28),
3152 };
3153 static const unsigned int ssi8_data_b_mux[] = {
3154         SSI_SDATA8_B_MARK,
3155 };
3156 static const unsigned int ssi9_data_pins[] = {
3157         /* SDATA9 */
3158         RCAR_GP_PIN(5, 19),
3159 };
3160 static const unsigned int ssi9_data_mux[] = {
3161         SSI_SDATA9_MARK,
3162 };
3163 static const unsigned int ssi9_ctrl_pins[] = {
3164         /* SCK9, WS9 */
3165         RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
3166 };
3167 static const unsigned int ssi9_ctrl_mux[] = {
3168         SSI_SCK9_MARK, SSI_WS9_MARK,
3169 };
3170 static const unsigned int ssi9_data_b_pins[] = {
3171         /* SDATA9 */
3172         RCAR_GP_PIN(4, 19),
3173 };
3174 static const unsigned int ssi9_data_b_mux[] = {
3175         SSI_SDATA9_B_MARK,
3176 };
3177 static const unsigned int ssi9_ctrl_b_pins[] = {
3178         /* SCK9, WS9 */
3179         RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3180 };
3181 static const unsigned int ssi9_ctrl_b_mux[] = {
3182         SSI_SCK9_B_MARK, SSI_WS9_B_MARK,
3183 };
3184 /* - USB0 ------------------------------------------------------------------- */
3185 static const unsigned int usb0_pins[] = {
3186         RCAR_GP_PIN(5, 24), /* PWEN */
3187         RCAR_GP_PIN(5, 25), /* OVC */
3188 };
3189 static const unsigned int usb0_mux[] = {
3190         USB0_PWEN_MARK,
3191         USB0_OVC_MARK,
3192 };
3193 /* - USB1 ------------------------------------------------------------------- */
3194 static const unsigned int usb1_pins[] = {
3195         RCAR_GP_PIN(5, 26), /* PWEN */
3196         RCAR_GP_PIN(5, 27), /* OVC */
3197 };
3198 static const unsigned int usb1_mux[] = {
3199         USB1_PWEN_MARK,
3200         USB1_OVC_MARK,
3201 };
3202 /* - VIN0 ------------------------------------------------------------------- */
3203 static const union vin_data vin0_data_pins = {
3204         .data24 = {
3205                 /* B */
3206                 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2),
3207                 RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3208                 RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3209                 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3210                 /* G */
3211                 RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
3212                 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3213                 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3214                 RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3215                 /* R */
3216                 RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22),
3217                 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3218                 RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3219                 RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3220         },
3221 };
3222 static const union vin_data vin0_data_mux = {
3223         .data24 = {
3224                 /* B */
3225                 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3226                 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3227                 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3228                 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3229                 /* G */
3230                 VI0_G0_MARK, VI0_G1_MARK,
3231                 VI0_G2_MARK, VI0_G3_MARK,
3232                 VI0_G4_MARK, VI0_G5_MARK,
3233                 VI0_G6_MARK, VI0_G7_MARK,
3234                 /* R */
3235                 VI0_R0_MARK, VI0_R1_MARK,
3236                 VI0_R2_MARK, VI0_R3_MARK,
3237                 VI0_R4_MARK, VI0_R5_MARK,
3238                 VI0_R6_MARK, VI0_R7_MARK,
3239         },
3240 };
3241 static const unsigned int vin0_data18_pins[] = {
3242         /* B */
3243         RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4),
3244         RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
3245         RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
3246         /* G */
3247         RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
3248         RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 18),
3249         RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
3250         /* R */
3251         RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 24),
3252         RCAR_GP_PIN(3, 25), RCAR_GP_PIN(3, 26),
3253         RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28),
3254 };
3255 static const unsigned int vin0_data18_mux[] = {
3256         /* B */
3257         VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3258         VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3259         VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3260         /* G */
3261         VI0_G2_MARK, VI0_G3_MARK,
3262         VI0_G4_MARK, VI0_G5_MARK,
3263         VI0_G6_MARK, VI0_G7_MARK,
3264         /* R */
3265         VI0_R2_MARK, VI0_R3_MARK,
3266         VI0_R4_MARK, VI0_R5_MARK,
3267         VI0_R6_MARK, VI0_R7_MARK,
3268 };
3269 static const unsigned int vin0_sync_pins[] = {
3270         RCAR_GP_PIN(3, 11), /* HSYNC */
3271         RCAR_GP_PIN(3, 12), /* VSYNC */
3272 };
3273 static const unsigned int vin0_sync_mux[] = {
3274         VI0_HSYNC_N_MARK,
3275         VI0_VSYNC_N_MARK,
3276 };
3277 static const unsigned int vin0_field_pins[] = {
3278         RCAR_GP_PIN(3, 10),
3279 };
3280 static const unsigned int vin0_field_mux[] = {
3281         VI0_FIELD_MARK,
3282 };
3283 static const unsigned int vin0_clkenb_pins[] = {
3284         RCAR_GP_PIN(3, 9),
3285 };
3286 static const unsigned int vin0_clkenb_mux[] = {
3287         VI0_CLKENB_MARK,
3288 };
3289 static const unsigned int vin0_clk_pins[] = {
3290         RCAR_GP_PIN(3, 0),
3291 };
3292 static const unsigned int vin0_clk_mux[] = {
3293         VI0_CLK_MARK,
3294 };
3295 /* - VIN1 ------------------------------------------------------------------- */
3296 static const union vin_data vin1_data_pins = {
3297         .data12 = {
3298                 RCAR_GP_PIN(5, 12), RCAR_GP_PIN(5, 13),
3299                 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 15),
3300                 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17),
3301                 RCAR_GP_PIN(5, 18), RCAR_GP_PIN(5, 19),
3302                 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
3303                 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3304         },
3305 };
3306 static const union vin_data vin1_data_mux = {
3307         .data12 = {
3308                 VI1_DATA0_MARK, VI1_DATA1_MARK,
3309                 VI1_DATA2_MARK, VI1_DATA3_MARK,
3310                 VI1_DATA4_MARK, VI1_DATA5_MARK,
3311                 VI1_DATA6_MARK, VI1_DATA7_MARK,
3312                 VI1_DATA8_MARK, VI1_DATA9_MARK,
3313                 VI1_DATA10_MARK, VI1_DATA11_MARK,
3314         },
3315 };
3316 static const unsigned int vin1_sync_pins[] = {
3317         RCAR_GP_PIN(5, 22), /* HSYNC */
3318         RCAR_GP_PIN(5, 23), /* VSYNC */
3319 };
3320 static const unsigned int vin1_sync_mux[] = {
3321         VI1_HSYNC_N_MARK,
3322         VI1_VSYNC_N_MARK,
3323 };
3324 static const unsigned int vin1_field_pins[] = {
3325         RCAR_GP_PIN(5, 21),
3326 };
3327 static const unsigned int vin1_field_mux[] = {
3328         VI1_FIELD_MARK,
3329 };
3330 static const unsigned int vin1_clkenb_pins[] = {
3331         RCAR_GP_PIN(5, 20),
3332 };
3333 static const unsigned int vin1_clkenb_mux[] = {
3334         VI1_CLKENB_MARK,
3335 };
3336 static const unsigned int vin1_clk_pins[] = {
3337         RCAR_GP_PIN(5, 11),
3338 };
3339 static const unsigned int vin1_clk_mux[] = {
3340         VI1_CLK_MARK,
3341 };
3342
3343 static const struct sh_pfc_pin_group pinmux_groups[] = {
3344         SH_PFC_PIN_GROUP(audio_clka),
3345         SH_PFC_PIN_GROUP(audio_clka_b),
3346         SH_PFC_PIN_GROUP(audio_clka_c),
3347         SH_PFC_PIN_GROUP(audio_clka_d),
3348         SH_PFC_PIN_GROUP(audio_clkb),
3349         SH_PFC_PIN_GROUP(audio_clkb_b),
3350         SH_PFC_PIN_GROUP(audio_clkb_c),
3351         SH_PFC_PIN_GROUP(audio_clkc),
3352         SH_PFC_PIN_GROUP(audio_clkc_b),
3353         SH_PFC_PIN_GROUP(audio_clkc_c),
3354         SH_PFC_PIN_GROUP(audio_clkout),
3355         SH_PFC_PIN_GROUP(audio_clkout_b),
3356         SH_PFC_PIN_GROUP(audio_clkout_c),
3357         SH_PFC_PIN_GROUP(avb_link),
3358         SH_PFC_PIN_GROUP(avb_magic),
3359         SH_PFC_PIN_GROUP(avb_phy_int),
3360         SH_PFC_PIN_GROUP(avb_mdio),
3361         SH_PFC_PIN_GROUP(avb_mii),
3362         SH_PFC_PIN_GROUP(avb_gmii),
3363         SH_PFC_PIN_GROUP(avb_avtp_capture),
3364         SH_PFC_PIN_GROUP(avb_avtp_match),
3365         SH_PFC_PIN_GROUP(avb_avtp_capture_b),
3366         SH_PFC_PIN_GROUP(avb_avtp_match_b),
3367         SH_PFC_PIN_GROUP(eth_link),
3368         SH_PFC_PIN_GROUP(eth_magic),
3369         SH_PFC_PIN_GROUP(eth_mdio),
3370         SH_PFC_PIN_GROUP(eth_rmii),
3371         SH_PFC_PIN_GROUP(eth_link_b),
3372         SH_PFC_PIN_GROUP(eth_magic_b),
3373         SH_PFC_PIN_GROUP(eth_mdio_b),
3374         SH_PFC_PIN_GROUP(eth_rmii_b),
3375         SH_PFC_PIN_GROUP(hscif0_data),
3376         SH_PFC_PIN_GROUP(hscif0_clk),
3377         SH_PFC_PIN_GROUP(hscif0_ctrl),
3378         SH_PFC_PIN_GROUP(hscif0_data_b),
3379         SH_PFC_PIN_GROUP(hscif0_clk_b),
3380         SH_PFC_PIN_GROUP(hscif1_data),
3381         SH_PFC_PIN_GROUP(hscif1_clk),
3382         SH_PFC_PIN_GROUP(hscif1_ctrl),
3383         SH_PFC_PIN_GROUP(hscif1_data_b),
3384         SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3385         SH_PFC_PIN_GROUP(hscif2_data),
3386         SH_PFC_PIN_GROUP(hscif2_clk),
3387         SH_PFC_PIN_GROUP(hscif2_ctrl),
3388         SH_PFC_PIN_GROUP(i2c0),
3389         SH_PFC_PIN_GROUP(i2c0_b),
3390         SH_PFC_PIN_GROUP(i2c0_c),
3391         SH_PFC_PIN_GROUP(i2c0_d),
3392         SH_PFC_PIN_GROUP(i2c0_e),
3393         SH_PFC_PIN_GROUP(i2c1),
3394         SH_PFC_PIN_GROUP(i2c1_b),
3395         SH_PFC_PIN_GROUP(i2c1_c),
3396         SH_PFC_PIN_GROUP(i2c1_d),
3397         SH_PFC_PIN_GROUP(i2c1_e),
3398         SH_PFC_PIN_GROUP(i2c2),
3399         SH_PFC_PIN_GROUP(i2c2_b),
3400         SH_PFC_PIN_GROUP(i2c2_c),
3401         SH_PFC_PIN_GROUP(i2c2_d),
3402         SH_PFC_PIN_GROUP(i2c2_e),
3403         SH_PFC_PIN_GROUP(i2c3),
3404         SH_PFC_PIN_GROUP(i2c3_b),
3405         SH_PFC_PIN_GROUP(i2c3_c),
3406         SH_PFC_PIN_GROUP(i2c3_d),
3407         SH_PFC_PIN_GROUP(i2c3_e),
3408         SH_PFC_PIN_GROUP(i2c4),
3409         SH_PFC_PIN_GROUP(i2c4_b),
3410         SH_PFC_PIN_GROUP(i2c4_c),
3411         SH_PFC_PIN_GROUP(i2c4_d),
3412         SH_PFC_PIN_GROUP(i2c4_e),
3413         SH_PFC_PIN_GROUP(intc_irq0),
3414         SH_PFC_PIN_GROUP(intc_irq1),
3415         SH_PFC_PIN_GROUP(intc_irq2),
3416         SH_PFC_PIN_GROUP(intc_irq3),
3417         SH_PFC_PIN_GROUP(intc_irq4),
3418         SH_PFC_PIN_GROUP(intc_irq5),
3419         SH_PFC_PIN_GROUP(intc_irq6),
3420         SH_PFC_PIN_GROUP(intc_irq7),
3421         SH_PFC_PIN_GROUP(intc_irq8),
3422         SH_PFC_PIN_GROUP(intc_irq9),
3423         SH_PFC_PIN_GROUP(mmc_data1),
3424         SH_PFC_PIN_GROUP(mmc_data4),
3425         SH_PFC_PIN_GROUP(mmc_data8),
3426         SH_PFC_PIN_GROUP(mmc_ctrl),
3427         SH_PFC_PIN_GROUP(msiof0_clk),
3428         SH_PFC_PIN_GROUP(msiof0_sync),
3429         SH_PFC_PIN_GROUP(msiof0_ss1),
3430         SH_PFC_PIN_GROUP(msiof0_ss2),
3431         SH_PFC_PIN_GROUP(msiof0_rx),
3432         SH_PFC_PIN_GROUP(msiof0_tx),
3433         SH_PFC_PIN_GROUP(msiof1_clk),
3434         SH_PFC_PIN_GROUP(msiof1_sync),
3435         SH_PFC_PIN_GROUP(msiof1_ss1),
3436         SH_PFC_PIN_GROUP(msiof1_ss2),
3437         SH_PFC_PIN_GROUP(msiof1_rx),
3438         SH_PFC_PIN_GROUP(msiof1_tx),
3439         SH_PFC_PIN_GROUP(msiof1_clk_b),
3440         SH_PFC_PIN_GROUP(msiof1_sync_b),
3441         SH_PFC_PIN_GROUP(msiof1_ss1_b),
3442         SH_PFC_PIN_GROUP(msiof1_ss2_b),
3443         SH_PFC_PIN_GROUP(msiof1_rx_b),
3444         SH_PFC_PIN_GROUP(msiof1_tx_b),
3445         SH_PFC_PIN_GROUP(msiof2_clk),
3446         SH_PFC_PIN_GROUP(msiof2_sync),
3447         SH_PFC_PIN_GROUP(msiof2_ss1),
3448         SH_PFC_PIN_GROUP(msiof2_ss2),
3449         SH_PFC_PIN_GROUP(msiof2_rx),
3450         SH_PFC_PIN_GROUP(msiof2_tx),
3451         SH_PFC_PIN_GROUP(msiof2_clk_b),
3452         SH_PFC_PIN_GROUP(msiof2_sync_b),
3453         SH_PFC_PIN_GROUP(msiof2_ss1_b),
3454         SH_PFC_PIN_GROUP(msiof2_ss2_b),
3455         SH_PFC_PIN_GROUP(msiof2_rx_b),
3456         SH_PFC_PIN_GROUP(msiof2_tx_b),
3457         SH_PFC_PIN_GROUP(qspi_ctrl),
3458         SH_PFC_PIN_GROUP(qspi_data2),
3459         SH_PFC_PIN_GROUP(qspi_data4),
3460         SH_PFC_PIN_GROUP(scif0_data),
3461         SH_PFC_PIN_GROUP(scif0_data_b),
3462         SH_PFC_PIN_GROUP(scif0_data_c),
3463         SH_PFC_PIN_GROUP(scif0_data_d),
3464         SH_PFC_PIN_GROUP(scif1_data),
3465         SH_PFC_PIN_GROUP(scif1_clk),
3466         SH_PFC_PIN_GROUP(scif1_data_b),
3467         SH_PFC_PIN_GROUP(scif1_clk_b),
3468         SH_PFC_PIN_GROUP(scif1_data_c),
3469         SH_PFC_PIN_GROUP(scif1_clk_c),
3470         SH_PFC_PIN_GROUP(scif2_data),
3471         SH_PFC_PIN_GROUP(scif2_clk),
3472         SH_PFC_PIN_GROUP(scif2_data_b),
3473         SH_PFC_PIN_GROUP(scif2_clk_b),
3474         SH_PFC_PIN_GROUP(scif2_data_c),
3475         SH_PFC_PIN_GROUP(scif2_clk_c),
3476         SH_PFC_PIN_GROUP(scif3_data),
3477         SH_PFC_PIN_GROUP(scif3_clk),
3478         SH_PFC_PIN_GROUP(scif3_data_b),
3479         SH_PFC_PIN_GROUP(scif3_clk_b),
3480         SH_PFC_PIN_GROUP(scif4_data),
3481         SH_PFC_PIN_GROUP(scif4_data_b),
3482         SH_PFC_PIN_GROUP(scif4_data_c),
3483         SH_PFC_PIN_GROUP(scif4_data_d),
3484         SH_PFC_PIN_GROUP(scif4_data_e),
3485         SH_PFC_PIN_GROUP(scif5_data),
3486         SH_PFC_PIN_GROUP(scif5_data_b),
3487         SH_PFC_PIN_GROUP(scif5_data_c),
3488         SH_PFC_PIN_GROUP(scif5_data_d),
3489         SH_PFC_PIN_GROUP(scifa0_data),
3490         SH_PFC_PIN_GROUP(scifa0_data_b),
3491         SH_PFC_PIN_GROUP(scifa0_data_c),
3492         SH_PFC_PIN_GROUP(scifa0_data_d),
3493         SH_PFC_PIN_GROUP(scifa1_data),
3494         SH_PFC_PIN_GROUP(scifa1_clk),
3495         SH_PFC_PIN_GROUP(scifa1_data_b),
3496         SH_PFC_PIN_GROUP(scifa1_clk_b),
3497         SH_PFC_PIN_GROUP(scifa1_data_c),
3498         SH_PFC_PIN_GROUP(scifa1_clk_c),
3499         SH_PFC_PIN_GROUP(scifa2_data),
3500         SH_PFC_PIN_GROUP(scifa2_clk),
3501         SH_PFC_PIN_GROUP(scifa2_data_b),
3502         SH_PFC_PIN_GROUP(scifa2_clk_b),
3503         SH_PFC_PIN_GROUP(scifa3_data),
3504         SH_PFC_PIN_GROUP(scifa3_clk),
3505         SH_PFC_PIN_GROUP(scifa3_data_b),
3506         SH_PFC_PIN_GROUP(scifa3_clk_b),
3507         SH_PFC_PIN_GROUP(scifa4_data),
3508         SH_PFC_PIN_GROUP(scifa4_data_b),
3509         SH_PFC_PIN_GROUP(scifa4_data_c),
3510         SH_PFC_PIN_GROUP(scifa4_data_d),
3511         SH_PFC_PIN_GROUP(scifa5_data),
3512         SH_PFC_PIN_GROUP(scifa5_data_b),
3513         SH_PFC_PIN_GROUP(scifa5_data_c),
3514         SH_PFC_PIN_GROUP(scifa5_data_d),
3515         SH_PFC_PIN_GROUP(scifb0_data),
3516         SH_PFC_PIN_GROUP(scifb0_clk),
3517         SH_PFC_PIN_GROUP(scifb0_ctrl),
3518         SH_PFC_PIN_GROUP(scifb1_data),
3519         SH_PFC_PIN_GROUP(scifb1_clk),
3520         SH_PFC_PIN_GROUP(scifb2_data),
3521         SH_PFC_PIN_GROUP(scifb2_clk),
3522         SH_PFC_PIN_GROUP(scifb2_ctrl),
3523         SH_PFC_PIN_GROUP(scif_clk),
3524         SH_PFC_PIN_GROUP(scif_clk_b),
3525         SH_PFC_PIN_GROUP(sdhi0_data1),
3526         SH_PFC_PIN_GROUP(sdhi0_data4),
3527         SH_PFC_PIN_GROUP(sdhi0_ctrl),
3528         SH_PFC_PIN_GROUP(sdhi0_cd),
3529         SH_PFC_PIN_GROUP(sdhi0_wp),
3530         SH_PFC_PIN_GROUP(sdhi1_data1),
3531         SH_PFC_PIN_GROUP(sdhi1_data4),
3532         SH_PFC_PIN_GROUP(sdhi1_ctrl),
3533         SH_PFC_PIN_GROUP(sdhi1_cd),
3534         SH_PFC_PIN_GROUP(sdhi1_wp),
3535         SH_PFC_PIN_GROUP(sdhi2_data1),
3536         SH_PFC_PIN_GROUP(sdhi2_data4),
3537         SH_PFC_PIN_GROUP(sdhi2_ctrl),
3538         SH_PFC_PIN_GROUP(sdhi2_cd),
3539         SH_PFC_PIN_GROUP(sdhi2_wp),
3540         SH_PFC_PIN_GROUP(ssi0_data),
3541         SH_PFC_PIN_GROUP(ssi0129_ctrl),
3542         SH_PFC_PIN_GROUP(ssi1_data),
3543         SH_PFC_PIN_GROUP(ssi1_ctrl),
3544         SH_PFC_PIN_GROUP(ssi1_data_b),
3545         SH_PFC_PIN_GROUP(ssi1_ctrl_b),
3546         SH_PFC_PIN_GROUP(ssi2_data),
3547         SH_PFC_PIN_GROUP(ssi2_ctrl),
3548         SH_PFC_PIN_GROUP(ssi2_data_b),
3549         SH_PFC_PIN_GROUP(ssi2_ctrl_b),
3550         SH_PFC_PIN_GROUP(ssi3_data),
3551         SH_PFC_PIN_GROUP(ssi34_ctrl),
3552         SH_PFC_PIN_GROUP(ssi4_data),
3553         SH_PFC_PIN_GROUP(ssi4_ctrl),
3554         SH_PFC_PIN_GROUP(ssi4_data_b),
3555         SH_PFC_PIN_GROUP(ssi4_ctrl_b),
3556         SH_PFC_PIN_GROUP(ssi5_data),
3557         SH_PFC_PIN_GROUP(ssi5_ctrl),
3558         SH_PFC_PIN_GROUP(ssi5_data_b),
3559         SH_PFC_PIN_GROUP(ssi5_ctrl_b),
3560         SH_PFC_PIN_GROUP(ssi6_data),
3561         SH_PFC_PIN_GROUP(ssi6_ctrl),
3562         SH_PFC_PIN_GROUP(ssi6_data_b),
3563         SH_PFC_PIN_GROUP(ssi6_ctrl_b),
3564         SH_PFC_PIN_GROUP(ssi7_data),
3565         SH_PFC_PIN_GROUP(ssi78_ctrl),
3566         SH_PFC_PIN_GROUP(ssi7_data_b),
3567         SH_PFC_PIN_GROUP(ssi78_ctrl_b),
3568         SH_PFC_PIN_GROUP(ssi8_data),
3569         SH_PFC_PIN_GROUP(ssi8_data_b),
3570         SH_PFC_PIN_GROUP(ssi9_data),
3571         SH_PFC_PIN_GROUP(ssi9_ctrl),
3572         SH_PFC_PIN_GROUP(ssi9_data_b),
3573         SH_PFC_PIN_GROUP(ssi9_ctrl_b),
3574         SH_PFC_PIN_GROUP(usb0),
3575         SH_PFC_PIN_GROUP(usb1),
3576         VIN_DATA_PIN_GROUP(vin0_data, 24),
3577         VIN_DATA_PIN_GROUP(vin0_data, 20),
3578         SH_PFC_PIN_GROUP(vin0_data18),
3579         VIN_DATA_PIN_GROUP(vin0_data, 16),
3580         VIN_DATA_PIN_GROUP(vin0_data, 12),
3581         VIN_DATA_PIN_GROUP(vin0_data, 10),
3582         VIN_DATA_PIN_GROUP(vin0_data, 8),
3583         SH_PFC_PIN_GROUP(vin0_sync),
3584         SH_PFC_PIN_GROUP(vin0_field),
3585         SH_PFC_PIN_GROUP(vin0_clkenb),
3586         SH_PFC_PIN_GROUP(vin0_clk),
3587         VIN_DATA_PIN_GROUP(vin1_data, 12),
3588         VIN_DATA_PIN_GROUP(vin1_data, 10),
3589         VIN_DATA_PIN_GROUP(vin1_data, 8),
3590         SH_PFC_PIN_GROUP(vin1_sync),
3591         SH_PFC_PIN_GROUP(vin1_field),
3592         SH_PFC_PIN_GROUP(vin1_clkenb),
3593         SH_PFC_PIN_GROUP(vin1_clk),
3594 };
3595
3596 static const char * const audio_clk_groups[] = {
3597         "audio_clka",
3598         "audio_clka_b",
3599         "audio_clka_c",
3600         "audio_clka_d",
3601         "audio_clkb",
3602         "audio_clkb_b",
3603         "audio_clkb_c",
3604         "audio_clkc",
3605         "audio_clkc_b",
3606         "audio_clkc_c",
3607         "audio_clkout",
3608         "audio_clkout_b",
3609         "audio_clkout_c",
3610 };
3611
3612 static const char * const avb_groups[] = {
3613         "avb_link",
3614         "avb_magic",
3615         "avb_phy_int",
3616         "avb_mdio",
3617         "avb_mii",
3618         "avb_gmii",
3619         "avb_avtp_capture",
3620         "avb_avtp_match",
3621         "avb_avtp_capture_b",
3622         "avb_avtp_match_b",
3623 };
3624
3625 static const char * const eth_groups[] = {
3626         "eth_link",
3627         "eth_magic",
3628         "eth_mdio",
3629         "eth_rmii",
3630         "eth_link_b",
3631         "eth_magic_b",
3632         "eth_mdio_b",
3633         "eth_rmii_b",
3634 };
3635
3636 static const char * const hscif0_groups[] = {
3637         "hscif0_data",
3638         "hscif0_clk",
3639         "hscif0_ctrl",
3640         "hscif0_data_b",
3641         "hscif0_clk_b",
3642 };
3643
3644 static const char * const hscif1_groups[] = {
3645         "hscif1_data",
3646         "hscif1_clk",
3647         "hscif1_ctrl",
3648         "hscif1_data_b",
3649         "hscif1_ctrl_b",
3650 };
3651
3652 static const char * const hscif2_groups[] = {
3653         "hscif2_data",
3654         "hscif2_clk",
3655         "hscif2_ctrl",
3656 };
3657
3658 static const char * const i2c0_groups[] = {
3659         "i2c0",
3660         "i2c0_b",
3661         "i2c0_c",
3662         "i2c0_d",
3663         "i2c0_e",
3664 };
3665
3666 static const char * const i2c1_groups[] = {
3667         "i2c1",
3668         "i2c1_b",
3669         "i2c1_c",
3670         "i2c1_d",
3671         "i2c1_e",
3672 };
3673
3674 static const char * const i2c2_groups[] = {
3675         "i2c2",
3676         "i2c2_b",
3677         "i2c2_c",
3678         "i2c2_d",
3679         "i2c2_e",
3680 };
3681
3682 static const char * const i2c3_groups[] = {
3683         "i2c3",
3684         "i2c3_b",
3685         "i2c3_c",
3686         "i2c3_d",
3687         "i2c3_e",
3688 };
3689
3690 static const char * const i2c4_groups[] = {
3691         "i2c4",
3692         "i2c4_b",
3693         "i2c4_c",
3694         "i2c4_d",
3695         "i2c4_e",
3696 };
3697
3698 static const char * const intc_groups[] = {
3699         "intc_irq0",
3700         "intc_irq1",
3701         "intc_irq2",
3702         "intc_irq3",
3703         "intc_irq4",
3704         "intc_irq5",
3705         "intc_irq6",
3706         "intc_irq7",
3707         "intc_irq8",
3708         "intc_irq9",
3709 };
3710
3711 static const char * const mmc_groups[] = {
3712         "mmc_data1",
3713         "mmc_data4",
3714         "mmc_data8",
3715         "mmc_ctrl",
3716 };
3717
3718 static const char * const msiof0_groups[] = {
3719         "msiof0_clk",
3720         "msiof0_sync",
3721         "msiof0_ss1",
3722         "msiof0_ss2",
3723         "msiof0_rx",
3724         "msiof0_tx",
3725 };
3726
3727 static const char * const msiof1_groups[] = {
3728         "msiof1_clk",
3729         "msiof1_sync",
3730         "msiof1_ss1",
3731         "msiof1_ss2",
3732         "msiof1_rx",
3733         "msiof1_tx",
3734         "msiof1_clk_b",
3735         "msiof1_sync_b",
3736         "msiof1_ss1_b",
3737         "msiof1_ss2_b",
3738         "msiof1_rx_b",
3739         "msiof1_tx_b",
3740 };
3741
3742 static const char * const msiof2_groups[] = {
3743         "msiof2_clk",
3744         "msiof2_sync",
3745         "msiof2_ss1",
3746         "msiof2_ss2",
3747         "msiof2_rx",
3748         "msiof2_tx",
3749         "msiof2_clk_b",
3750         "msiof2_sync_b",
3751         "msiof2_ss1_b",
3752         "msiof2_ss2_b",
3753         "msiof2_rx_b",
3754         "msiof2_tx_b",
3755 };
3756
3757 static const char * const qspi_groups[] = {
3758         "qspi_ctrl",
3759         "qspi_data2",
3760         "qspi_data4",
3761 };
3762
3763 static const char * const scif0_groups[] = {
3764         "scif0_data",
3765         "scif0_data_b",
3766         "scif0_data_c",
3767         "scif0_data_d",
3768 };
3769
3770 static const char * const scif1_groups[] = {
3771         "scif1_data",
3772         "scif1_clk",
3773         "scif1_data_b",
3774         "scif1_clk_b",
3775         "scif1_data_c",
3776         "scif1_clk_c",
3777 };
3778
3779 static const char * const scif2_groups[] = {
3780         "scif2_data",
3781         "scif2_clk",
3782         "scif2_data_b",
3783         "scif2_clk_b",
3784         "scif2_data_c",
3785         "scif2_clk_c",
3786 };
3787
3788 static const char * const scif3_groups[] = {
3789         "scif3_data",
3790         "scif3_clk",
3791         "scif3_data_b",
3792         "scif3_clk_b",
3793 };
3794
3795 static const char * const scif4_groups[] = {
3796         "scif4_data",
3797         "scif4_data_b",
3798         "scif4_data_c",
3799         "scif4_data_d",
3800         "scif4_data_e",
3801 };
3802
3803 static const char * const scif5_groups[] = {
3804         "scif5_data",
3805         "scif5_data_b",
3806         "scif5_data_c",
3807         "scif5_data_d",
3808 };
3809
3810 static const char * const scifa0_groups[] = {
3811         "scifa0_data",
3812         "scifa0_data_b",
3813         "scifa0_data_c",
3814         "scifa0_data_d",
3815 };
3816
3817 static const char * const scifa1_groups[] = {
3818         "scifa1_data",
3819         "scifa1_clk",
3820         "scifa1_data_b",
3821         "scifa1_clk_b",
3822         "scifa1_data_c",
3823         "scifa1_clk_c",
3824 };
3825
3826 static const char * const scifa2_groups[] = {
3827         "scifa2_data",
3828         "scifa2_clk",
3829         "scifa2_data_b",
3830         "scifa2_clk_b",
3831 };
3832
3833 static const char * const scifa3_groups[] = {
3834         "scifa3_data",
3835         "scifa3_clk",
3836         "scifa3_data_b",
3837         "scifa3_clk_b",
3838 };
3839
3840 static const char * const scifa4_groups[] = {
3841         "scifa4_data",
3842         "scifa4_data_b",
3843         "scifa4_data_c",
3844         "scifa4_data_d",
3845 };
3846
3847 static const char * const scifa5_groups[] = {
3848         "scifa5_data",
3849         "scifa5_data_b",
3850         "scifa5_data_c",
3851         "scifa5_data_d",
3852 };
3853
3854 static const char * const scifb0_groups[] = {
3855         "scifb0_data",
3856         "scifb0_clk",
3857         "scifb0_ctrl",
3858 };
3859
3860 static const char * const scifb1_groups[] = {
3861         "scifb1_data",
3862         "scifb1_clk",
3863 };
3864
3865 static const char * const scifb2_groups[] = {
3866         "scifb2_data",
3867         "scifb2_clk",
3868         "scifb2_ctrl",
3869 };
3870
3871 static const char * const scif_clk_groups[] = {
3872         "scif_clk",
3873         "scif_clk_b",
3874 };
3875
3876 static const char * const sdhi0_groups[] = {
3877         "sdhi0_data1",
3878         "sdhi0_data4",
3879         "sdhi0_ctrl",
3880         "sdhi0_cd",
3881         "sdhi0_wp",
3882 };
3883
3884 static const char * const sdhi1_groups[] = {
3885         "sdhi1_data1",
3886         "sdhi1_data4",
3887         "sdhi1_ctrl",
3888         "sdhi1_cd",
3889         "sdhi1_wp",
3890 };
3891
3892 static const char * const sdhi2_groups[] = {
3893         "sdhi2_data1",
3894         "sdhi2_data4",
3895         "sdhi2_ctrl",
3896         "sdhi2_cd",
3897         "sdhi2_wp",
3898 };
3899
3900 static const char * const ssi_groups[] = {
3901         "ssi0_data",
3902         "ssi0129_ctrl",
3903         "ssi1_data",
3904         "ssi1_ctrl",
3905         "ssi1_data_b",
3906         "ssi1_ctrl_b",
3907         "ssi2_data",
3908         "ssi2_ctrl",
3909         "ssi2_data_b",
3910         "ssi2_ctrl_b",
3911         "ssi3_data",
3912         "ssi34_ctrl",
3913         "ssi4_data",
3914         "ssi4_ctrl",
3915         "ssi4_data_b",
3916         "ssi4_ctrl_b",
3917         "ssi5_data",
3918         "ssi5_ctrl",
3919         "ssi5_data_b",
3920         "ssi5_ctrl_b",
3921         "ssi6_data",
3922         "ssi6_ctrl",
3923         "ssi6_data_b",
3924         "ssi6_ctrl_b",
3925         "ssi7_data",
3926         "ssi78_ctrl",
3927         "ssi7_data_b",
3928         "ssi78_ctrl_b",
3929         "ssi8_data",
3930         "ssi8_data_b",
3931         "ssi9_data",
3932         "ssi9_ctrl",
3933         "ssi9_data_b",
3934         "ssi9_ctrl_b",
3935 };
3936
3937 static const char * const usb0_groups[] = {
3938         "usb0",
3939 };
3940
3941 static const char * const usb1_groups[] = {
3942         "usb1",
3943 };
3944
3945 static const char * const vin0_groups[] = {
3946         "vin0_data24",
3947         "vin0_data20",
3948         "vin0_data18",
3949         "vin0_data16",
3950         "vin0_data12",
3951         "vin0_data10",
3952         "vin0_data8",
3953         "vin0_sync",
3954         "vin0_field",
3955         "vin0_clkenb",
3956         "vin0_clk",
3957 };
3958
3959 static const char * const vin1_groups[] = {
3960         "vin1_data12",
3961         "vin1_data10",
3962         "vin1_data8",
3963         "vin1_sync",
3964         "vin1_field",
3965         "vin1_clkenb",
3966         "vin1_clk",
3967 };
3968
3969 static const struct sh_pfc_function pinmux_functions[] = {
3970         SH_PFC_FUNCTION(audio_clk),
3971         SH_PFC_FUNCTION(avb),
3972         SH_PFC_FUNCTION(eth),
3973         SH_PFC_FUNCTION(hscif0),
3974         SH_PFC_FUNCTION(hscif1),
3975         SH_PFC_FUNCTION(hscif2),
3976         SH_PFC_FUNCTION(i2c0),
3977         SH_PFC_FUNCTION(i2c1),
3978         SH_PFC_FUNCTION(i2c2),
3979         SH_PFC_FUNCTION(i2c3),
3980         SH_PFC_FUNCTION(i2c4),
3981         SH_PFC_FUNCTION(intc),
3982         SH_PFC_FUNCTION(mmc),
3983         SH_PFC_FUNCTION(msiof0),
3984         SH_PFC_FUNCTION(msiof1),
3985         SH_PFC_FUNCTION(msiof2),
3986         SH_PFC_FUNCTION(qspi),
3987         SH_PFC_FUNCTION(scif0),
3988         SH_PFC_FUNCTION(scif1),
3989         SH_PFC_FUNCTION(scif2),
3990         SH_PFC_FUNCTION(scif3),
3991         SH_PFC_FUNCTION(scif4),
3992         SH_PFC_FUNCTION(scif5),
3993         SH_PFC_FUNCTION(scifa0),
3994         SH_PFC_FUNCTION(scifa1),
3995         SH_PFC_FUNCTION(scifa2),
3996         SH_PFC_FUNCTION(scifa3),
3997         SH_PFC_FUNCTION(scifa4),
3998         SH_PFC_FUNCTION(scifa5),
3999         SH_PFC_FUNCTION(scifb0),
4000         SH_PFC_FUNCTION(scifb1),
4001         SH_PFC_FUNCTION(scifb2),
4002         SH_PFC_FUNCTION(scif_clk),
4003         SH_PFC_FUNCTION(sdhi0),
4004         SH_PFC_FUNCTION(sdhi1),
4005         SH_PFC_FUNCTION(sdhi2),
4006         SH_PFC_FUNCTION(ssi),
4007         SH_PFC_FUNCTION(usb0),
4008         SH_PFC_FUNCTION(usb1),
4009         SH_PFC_FUNCTION(vin0),
4010         SH_PFC_FUNCTION(vin1),
4011 };
4012
4013 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4014         { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4015                 GP_0_31_FN, FN_IP2_17_16,
4016                 GP_0_30_FN, FN_IP2_15_14,
4017                 GP_0_29_FN, FN_IP2_13_12,
4018                 GP_0_28_FN, FN_IP2_11_10,
4019                 GP_0_27_FN, FN_IP2_9_8,
4020                 GP_0_26_FN, FN_IP2_7_6,
4021                 GP_0_25_FN, FN_IP2_5_4,
4022                 GP_0_24_FN, FN_IP2_3_2,
4023                 GP_0_23_FN, FN_IP2_1_0,
4024                 GP_0_22_FN, FN_IP1_31_30,
4025                 GP_0_21_FN, FN_IP1_29_28,
4026                 GP_0_20_FN, FN_IP1_27,
4027                 GP_0_19_FN, FN_IP1_26,
4028                 GP_0_18_FN, FN_A2,
4029                 GP_0_17_FN, FN_IP1_24,
4030                 GP_0_16_FN, FN_IP1_23_22,
4031                 GP_0_15_FN, FN_IP1_21_20,
4032                 GP_0_14_FN, FN_IP1_19_18,
4033                 GP_0_13_FN, FN_IP1_17_15,
4034                 GP_0_12_FN, FN_IP1_14_13,
4035                 GP_0_11_FN, FN_IP1_12_11,
4036                 GP_0_10_FN, FN_IP1_10_8,
4037                 GP_0_9_FN, FN_IP1_7_6,
4038                 GP_0_8_FN, FN_IP1_5_4,
4039                 GP_0_7_FN, FN_IP1_3_2,
4040                 GP_0_6_FN, FN_IP1_1_0,
4041                 GP_0_5_FN, FN_IP0_31_30,
4042                 GP_0_4_FN, FN_IP0_29_28,
4043                 GP_0_3_FN, FN_IP0_27_26,
4044                 GP_0_2_FN, FN_IP0_25,
4045                 GP_0_1_FN, FN_IP0_24,
4046                 GP_0_0_FN, FN_IP0_23_22, }
4047         },
4048         { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
4049                 0, 0,
4050                 0, 0,
4051                 0, 0,
4052                 0, 0,
4053                 0, 0,
4054                 0, 0,
4055                 GP_1_25_FN, FN_DACK0,
4056                 GP_1_24_FN, FN_IP7_31,
4057                 GP_1_23_FN, FN_IP4_1_0,
4058                 GP_1_22_FN, FN_WE1_N,
4059                 GP_1_21_FN, FN_WE0_N,
4060                 GP_1_20_FN, FN_IP3_31,
4061                 GP_1_19_FN, FN_IP3_30,
4062                 GP_1_18_FN, FN_IP3_29_27,
4063                 GP_1_17_FN, FN_IP3_26_24,
4064                 GP_1_16_FN, FN_IP3_23_21,
4065                 GP_1_15_FN, FN_IP3_20_18,
4066                 GP_1_14_FN, FN_IP3_17_15,
4067                 GP_1_13_FN, FN_IP3_14_13,
4068                 GP_1_12_FN, FN_IP3_12,
4069                 GP_1_11_FN, FN_IP3_11,
4070                 GP_1_10_FN, FN_IP3_10,
4071                 GP_1_9_FN, FN_IP3_9_8,
4072                 GP_1_8_FN, FN_IP3_7_6,
4073                 GP_1_7_FN, FN_IP3_5_4,
4074                 GP_1_6_FN, FN_IP3_3_2,
4075                 GP_1_5_FN, FN_IP3_1_0,
4076                 GP_1_4_FN, FN_IP2_31_30,
4077                 GP_1_3_FN, FN_IP2_29_27,
4078                 GP_1_2_FN, FN_IP2_26_24,
4079                 GP_1_1_FN, FN_IP2_23_21,
4080                 GP_1_0_FN, FN_IP2_20_18, }
4081         },
4082         { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
4083                 GP_2_31_FN, FN_IP6_7_6,
4084                 GP_2_30_FN, FN_IP6_5_4,
4085                 GP_2_29_FN, FN_IP6_3_2,
4086                 GP_2_28_FN, FN_IP6_1_0,
4087                 GP_2_27_FN, FN_IP5_31_30,
4088                 GP_2_26_FN, FN_IP5_29_28,
4089                 GP_2_25_FN, FN_IP5_27_26,
4090                 GP_2_24_FN, FN_IP5_25_24,
4091                 GP_2_23_FN, FN_IP5_23_22,
4092                 GP_2_22_FN, FN_IP5_21_20,
4093                 GP_2_21_FN, FN_IP5_19_18,
4094                 GP_2_20_FN, FN_IP5_17_16,
4095                 GP_2_19_FN, FN_IP5_15_14,
4096                 GP_2_18_FN, FN_IP5_13_12,
4097                 GP_2_17_FN, FN_IP5_11_9,
4098                 GP_2_16_FN, FN_IP5_8_6,
4099                 GP_2_15_FN, FN_IP5_5_4,
4100                 GP_2_14_FN, FN_IP5_3_2,
4101                 GP_2_13_FN, FN_IP5_1_0,
4102                 GP_2_12_FN, FN_IP4_31_30,
4103                 GP_2_11_FN, FN_IP4_29_28,
4104                 GP_2_10_FN, FN_IP4_27_26,
4105                 GP_2_9_FN, FN_IP4_25_23,
4106                 GP_2_8_FN, FN_IP4_22_20,
4107                 GP_2_7_FN, FN_IP4_19_18,
4108                 GP_2_6_FN, FN_IP4_17_16,
4109                 GP_2_5_FN, FN_IP4_15_14,
4110                 GP_2_4_FN, FN_IP4_13_12,
4111                 GP_2_3_FN, FN_IP4_11_10,
4112                 GP_2_2_FN, FN_IP4_9_8,
4113                 GP_2_1_FN, FN_IP4_7_5,
4114                 GP_2_0_FN, FN_IP4_4_2 }
4115         },
4116         { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
4117                 GP_3_31_FN, FN_IP8_22_20,
4118                 GP_3_30_FN, FN_IP8_19_17,
4119                 GP_3_29_FN, FN_IP8_16_15,
4120                 GP_3_28_FN, FN_IP8_14_12,
4121                 GP_3_27_FN, FN_IP8_11_9,
4122                 GP_3_26_FN, FN_IP8_8_6,
4123                 GP_3_25_FN, FN_IP8_5_3,
4124                 GP_3_24_FN, FN_IP8_2_0,
4125                 GP_3_23_FN, FN_IP7_29_27,
4126                 GP_3_22_FN, FN_IP7_26_24,
4127                 GP_3_21_FN, FN_IP7_23_21,
4128                 GP_3_20_FN, FN_IP7_20_18,
4129                 GP_3_19_FN, FN_IP7_17_15,
4130                 GP_3_18_FN, FN_IP7_14_12,
4131                 GP_3_17_FN, FN_IP7_11_9,
4132                 GP_3_16_FN, FN_IP7_8_6,
4133                 GP_3_15_FN, FN_IP7_5_3,
4134                 GP_3_14_FN, FN_IP7_2_0,
4135                 GP_3_13_FN, FN_IP6_31_29,
4136                 GP_3_12_FN, FN_IP6_28_26,
4137                 GP_3_11_FN, FN_IP6_25_23,
4138                 GP_3_10_FN, FN_IP6_22_20,
4139                 GP_3_9_FN, FN_IP6_19_17,
4140                 GP_3_8_FN, FN_IP6_16,
4141                 GP_3_7_FN, FN_IP6_15,
4142                 GP_3_6_FN, FN_IP6_14,
4143                 GP_3_5_FN, FN_IP6_13,
4144                 GP_3_4_FN, FN_IP6_12,
4145                 GP_3_3_FN, FN_IP6_11,
4146                 GP_3_2_FN, FN_IP6_10,
4147                 GP_3_1_FN, FN_IP6_9,
4148                 GP_3_0_FN, FN_IP6_8 }
4149         },
4150         { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
4151                 GP_4_31_FN, FN_IP11_17_16,
4152                 GP_4_30_FN, FN_IP11_15_14,
4153                 GP_4_29_FN, FN_IP11_13_11,
4154                 GP_4_28_FN, FN_IP11_10_8,
4155                 GP_4_27_FN, FN_IP11_7_6,
4156                 GP_4_26_FN, FN_IP11_5_3,
4157                 GP_4_25_FN, FN_IP11_2_0,
4158                 GP_4_24_FN, FN_IP10_31_30,
4159                 GP_4_23_FN, FN_IP10_29_27,
4160                 GP_4_22_FN, FN_IP10_26_24,
4161                 GP_4_21_FN, FN_IP10_23_21,
4162                 GP_4_20_FN, FN_IP10_20_18,
4163                 GP_4_19_FN, FN_IP10_17_15,
4164                 GP_4_18_FN, FN_IP10_14_12,
4165                 GP_4_17_FN, FN_IP10_11_9,
4166                 GP_4_16_FN, FN_IP10_8_6,
4167                 GP_4_15_FN, FN_IP10_5_3,
4168                 GP_4_14_FN, FN_IP10_2_0,
4169                 GP_4_13_FN, FN_IP9_30_28,
4170                 GP_4_12_FN, FN_IP9_27_25,
4171                 GP_4_11_FN, FN_IP9_24_22,
4172                 GP_4_10_FN, FN_IP9_21_19,
4173                 GP_4_9_FN, FN_IP9_18_17,
4174                 GP_4_8_FN, FN_IP9_16_15,
4175                 GP_4_7_FN, FN_IP9_14_12,
4176                 GP_4_6_FN, FN_IP9_11_9,
4177                 GP_4_5_FN, FN_IP9_8_6,
4178                 GP_4_4_FN, FN_IP9_5_3,
4179                 GP_4_3_FN, FN_IP9_2_0,
4180                 GP_4_2_FN, FN_IP8_31_29,
4181                 GP_4_1_FN, FN_IP8_28_26,
4182                 GP_4_0_FN, FN_IP8_25_23 }
4183         },
4184         { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
4185                 0, 0,
4186                 0, 0,
4187                 0, 0,
4188                 0, 0,
4189                 GP_5_27_FN, FN_USB1_OVC,
4190                 GP_5_26_FN, FN_USB1_PWEN,
4191                 GP_5_25_FN, FN_USB0_OVC,
4192                 GP_5_24_FN, FN_USB0_PWEN,
4193                 GP_5_23_FN, FN_IP13_26_24,
4194                 GP_5_22_FN, FN_IP13_23_21,
4195                 GP_5_21_FN, FN_IP13_20_18,
4196                 GP_5_20_FN, FN_IP13_17_15,
4197                 GP_5_19_FN, FN_IP13_14_12,
4198                 GP_5_18_FN, FN_IP13_11_9,
4199                 GP_5_17_FN, FN_IP13_8_6,
4200                 GP_5_16_FN, FN_IP13_5_3,
4201                 GP_5_15_FN, FN_IP13_2_0,
4202                 GP_5_14_FN, FN_IP12_29_27,
4203                 GP_5_13_FN, FN_IP12_26_24,
4204                 GP_5_12_FN, FN_IP12_23_21,
4205                 GP_5_11_FN, FN_IP12_20_18,
4206                 GP_5_10_FN, FN_IP12_17_15,
4207                 GP_5_9_FN, FN_IP12_14_13,
4208                 GP_5_8_FN, FN_IP12_12_11,
4209                 GP_5_7_FN, FN_IP12_10_9,
4210                 GP_5_6_FN, FN_IP12_8_6,
4211                 GP_5_5_FN, FN_IP12_5_3,
4212                 GP_5_4_FN, FN_IP12_2_0,
4213                 GP_5_3_FN, FN_IP11_29_27,
4214                 GP_5_2_FN, FN_IP11_26_24,
4215                 GP_5_1_FN, FN_IP11_23_21,
4216                 GP_5_0_FN, FN_IP11_20_18 }
4217         },
4218         { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
4219                 0, 0,
4220                 0, 0,
4221                 0, 0,
4222                 0, 0,
4223                 0, 0,
4224                 0, 0,
4225                 GP_6_25_FN, FN_IP0_21_20,
4226                 GP_6_24_FN, FN_IP0_19_18,
4227                 GP_6_23_FN, FN_IP0_17,
4228                 GP_6_22_FN, FN_IP0_16,
4229                 GP_6_21_FN, FN_IP0_15,
4230                 GP_6_20_FN, FN_IP0_14,
4231                 GP_6_19_FN, FN_IP0_13,
4232                 GP_6_18_FN, FN_IP0_12,
4233                 GP_6_17_FN, FN_IP0_11,
4234                 GP_6_16_FN, FN_IP0_10,
4235                 GP_6_15_FN, FN_IP0_9_8,
4236                 GP_6_14_FN, FN_IP0_0,
4237                 GP_6_13_FN, FN_SD1_DATA3,
4238                 GP_6_12_FN, FN_SD1_DATA2,
4239                 GP_6_11_FN, FN_SD1_DATA1,
4240                 GP_6_10_FN, FN_SD1_DATA0,
4241                 GP_6_9_FN, FN_SD1_CMD,
4242                 GP_6_8_FN, FN_SD1_CLK,
4243                 GP_6_7_FN, FN_SD0_WP,
4244                 GP_6_6_FN, FN_SD0_CD,
4245                 GP_6_5_FN, FN_SD0_DATA3,
4246                 GP_6_4_FN, FN_SD0_DATA2,
4247                 GP_6_3_FN, FN_SD0_DATA1,
4248                 GP_6_2_FN, FN_SD0_DATA0,
4249                 GP_6_1_FN, FN_SD0_CMD,
4250                 GP_6_0_FN, FN_SD0_CLK }
4251         },
4252         { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
4253                              2, 2, 2, 1, 1, 2, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4254                              2, 1, 1, 1, 1, 1, 1, 1, 1) {
4255                 /* IP0_31_30 [2] */
4256                 FN_D5, FN_SCIF4_RXD_B, FN_I2C0_SCL_D, 0,
4257                 /* IP0_29_28 [2] */
4258                 FN_D4, FN_I2C3_SDA_B, FN_SCIF5_TXD_B, 0,
4259                 /* IP0_27_26 [2] */
4260                 FN_D3, FN_I2C3_SCL_B, FN_SCIF5_RXD_B, 0,
4261                 /* IP0_25 [1] */
4262                 FN_D2, FN_SCIFA3_TXD_B,
4263                 /* IP0_24 [1] */
4264                 FN_D1, FN_SCIFA3_RXD_B,
4265                 /* IP0_23_22 [2] */
4266                 FN_D0, FN_SCIFA3_SCK_B, FN_IRQ4, 0,
4267                 /* IP0_21_20 [2] */
4268                 FN_MMC_D7, FN_SCIF0_TXD, FN_I2C2_SDA_B, FN_CAN1_TX,
4269                 /* IP0_19_18 [2] */
4270                 FN_MMC_D6, FN_SCIF0_RXD, FN_I2C2_SCL_B, FN_CAN1_RX,
4271                 /* IP0_17 [1] */
4272                 FN_MMC_D5, FN_SD2_WP,
4273                 /* IP0_16 [1] */
4274                 FN_MMC_D4, FN_SD2_CD,
4275                 /* IP0_15 [1] */
4276                 FN_MMC_D3, FN_SD2_DATA3,
4277                 /* IP0_14 [1] */
4278                 FN_MMC_D2, FN_SD2_DATA2,
4279                 /* IP0_13 [1] */
4280                 FN_MMC_D1, FN_SD2_DATA1,
4281                 /* IP0_12 [1] */
4282                 FN_MMC_D0, FN_SD2_DATA0,
4283                 /* IP0_11 [1] */
4284                 FN_MMC_CMD, FN_SD2_CMD,
4285                 /* IP0_10 [1] */
4286                 FN_MMC_CLK, FN_SD2_CLK,
4287                 /* IP0_9_8 [2] */
4288                 FN_SD1_WP, FN_IRQ7, FN_CAN0_TX, 0,
4289                 /* IP0_7 [1] */
4290                 0, 0,
4291                 /* IP0_6 [1] */
4292                 0, 0,
4293                 /* IP0_5 [1] */
4294                 0, 0,
4295                 /* IP0_4 [1] */
4296                 0, 0,
4297                 /* IP0_3 [1] */
4298                 0, 0,
4299                 /* IP0_2 [1] */
4300                 0, 0,
4301                 /* IP0_1 [1] */
4302                 0, 0,
4303                 /* IP0_0 [1] */
4304                 FN_SD1_CD, FN_CAN0_RX, }
4305         },
4306         { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
4307                              2, 2, 1, 1, 1, 1, 2, 2, 2, 3, 2, 2, 3, 2, 2,
4308                              2, 2) {
4309                 /* IP1_31_30 [2] */
4310                 FN_A6, FN_SCIFB0_CTS_N, FN_SCIFA4_RXD_B, FN_TPUTO2_C,
4311                 /* IP1_29_28 [2] */
4312                 FN_A5, FN_SCIFB0_RXD, FN_PWM4_B, FN_TPUTO3_C,
4313                 /* IP1_27 [1] */
4314                 FN_A4, FN_SCIFB0_TXD,
4315                 /* IP1_26 [1] */
4316                 FN_A3, FN_SCIFB0_SCK,
4317                 /* IP1_25 [1] */
4318                 0, 0,
4319                 /* IP1_24 [1] */
4320                 FN_A1, FN_SCIFB1_TXD,
4321                 /* IP1_23_22 [2] */
4322                 FN_A0, FN_SCIFB1_SCK, FN_PWM3_B, 0,
4323                 /* IP1_21_20 [2] */
4324                 FN_D15, FN_SCIFA1_TXD, FN_IIC0_SDA_B, 0,
4325                 /* IP1_19_18 [2] */
4326                 FN_D14, FN_SCIFA1_RXD, FN_IIC0_SCL_B, 0,
4327                 /* IP1_17_15 [3] */
4328                 FN_D13, FN_SCIFA1_SCK, FN_TANS1, FN_PWM2_C, FN_TCLK2_B,
4329                 0, 0, 0,
4330                 /* IP1_14_13 [2] */
4331                 FN_D12, FN_HSCIF2_HRTS_N, FN_SCIF1_TXD_C, FN_I2C1_SDA_D,
4332                 /* IP1_12_11 [2] */
4333                 FN_D11, FN_HSCIF2_HCTS_N, FN_SCIF1_RXD_C, FN_I2C1_SCL_D,
4334                 /* IP1_10_8 [3] */
4335                 FN_D10, FN_HSCIF2_HSCK, FN_SCIF1_SCK_C, FN_IRQ6, FN_PWM5_C,
4336                 0, 0, 0,
4337                 /* IP1_7_6 [2] */
4338                 FN_D9, FN_HSCIF2_HTX, FN_I2C1_SDA_B, 0,
4339                 /* IP1_5_4 [2] */
4340                 FN_D8, FN_HSCIF2_HRX, FN_I2C1_SCL_B, 0,
4341                 /* IP1_3_2 [2] */
4342                 FN_D7, FN_IRQ3, FN_TCLK1, FN_PWM6_B,
4343                 /* IP1_1_0 [2] */
4344                 FN_D6, FN_SCIF4_TXD_B, FN_I2C0_SDA_D, 0, }
4345         },
4346         { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
4347                              2, 3, 3, 3, 3, 2, 2, 2, 2, 2, 2, 2, 2, 2) {
4348                 /* IP2_31_30 [2] */
4349                 FN_A20, FN_SPCLK, FN_MOUT1, 0,
4350                 /* IP2_29_27 [3] */
4351                 FN_A19, FN_MSIOF2_SS2, FN_PWM4, FN_TPUTO2,
4352                 FN_MOUT0, 0, 0, 0,
4353                 /* IP2_26_24 [3] */
4354                 FN_A18, FN_MSIOF2_SS1, FN_SCIF4_TXD_E, FN_CAN1_TX_B,
4355                 FN_AVB_AVTP_MATCH_B, 0, 0, 0,
4356                 /* IP2_23_21 [3] */
4357                 FN_A17, FN_MSIOF2_SYNC, FN_SCIF4_RXD_E, FN_CAN1_RX_B,
4358                 FN_AVB_AVTP_CAPTURE_B, 0, 0, 0,
4359                 /* IP2_20_18 [3] */
4360                 FN_A16, FN_MSIOF2_SCK, FN_HSCIF0_HSCK_B, FN_SPEEDIN,
4361                 FN_VSP, FN_CAN_CLK_C, FN_TPUTO2_B, 0,
4362                 /* IP2_17_16 [2] */
4363                 FN_A15, FN_MSIOF2_TXD, FN_HSCIF0_HTX_B, FN_DACK1,
4364                 /* IP2_15_14 [2] */
4365                 FN_A14, FN_MSIOF2_RXD, FN_HSCIF0_HRX_B, FN_DREQ1_N,
4366                 /* IP2_13_12 [2] */
4367                 FN_A13, FN_MSIOF1_SS2, FN_SCIFA5_TXD_B, 0,
4368                 /* IP2_11_10 [2] */
4369                 FN_A12, FN_MSIOF1_SS1, FN_SCIFA5_RXD_B, 0,
4370                 /* IP2_9_8 [2] */
4371                 FN_A11, FN_MSIOF1_SYNC, FN_IIC1_SDA_B, 0,
4372                 /* IP2_7_6 [2] */
4373                 FN_A10, FN_MSIOF1_SCK, FN_IIC1_SCL_B, 0,
4374                 /* IP2_5_4 [2] */
4375                 FN_A9, FN_MSIOF1_TXD, FN_SCIFA0_TXD_B, 0,
4376                 /* IP2_3_2 [2] */
4377                 FN_A8, FN_MSIOF1_RXD, FN_SCIFA0_RXD_B, 0,
4378                 /* IP2_1_0 [2] */
4379                 FN_A7, FN_SCIFB0_RTS_N, FN_SCIFA4_TXD_B, 0, }
4380         },
4381         { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
4382                              1, 1, 3, 3, 3, 3, 3, 2, 1, 1, 1, 2, 2, 2, 2, 2) {
4383                 /* IP3_31 [1] */
4384                 FN_RD_WR_N, FN_ATAG1_N,
4385                 /* IP3_30 [1] */
4386                 FN_RD_N, FN_ATACS11_N,
4387                 /* IP3_29_27 [3] */
4388                 FN_BS_N, FN_DRACK0, FN_PWM1_C, FN_TPUTO0_C, FN_ATACS01_N,
4389                 FN_MTS_N_B, 0, 0,
4390                 /* IP3_26_24 [3] */
4391                 FN_EX_CS5_N, FN_SCIFA2_TXD, FN_I2C2_SDA_E, FN_TS_SPSYNC_B,
4392                 FN_RIF0_D1, FN_FMIN, FN_SCIFB2_RTS_N, FN_STM_N_B,
4393                 /* IP3_23_21 [3] */
4394                 FN_EX_CS4_N, FN_SCIFA2_RXD, FN_I2C2_SCL_E, FN_TS_SDEN_B,
4395                 FN_RIF0_D0, FN_FMCLK, FN_SCIFB2_CTS_N, FN_SCKZ_B,
4396                 /* IP3_20_18 [3] */
4397                 FN_EX_CS3_N, FN_SCIFA2_SCK, FN_SCIF4_TXD_C, FN_TS_SCK_B,
4398                 FN_RIF0_CLK, FN_BPFCLK, FN_SCIFB2_SCK, FN_MDATA_B,
4399                 /* IP3_17_15 [3] */
4400                 FN_EX_CS2_N, FN_PWM0, FN_SCIF4_RXD_C, FN_TS_SDATA_B,
4401                 FN_RIF0_SYNC, FN_TPUTO3, FN_SCIFB2_TXD, FN_SDATA_B,
4402                 /* IP3_14_13 [2] */
4403                 FN_EX_CS1_N, FN_TPUTO3_B, FN_SCIFB2_RXD, FN_VI1_DATA11,
4404                 /* IP3_12 [1] */
4405                 FN_EX_CS0_N, FN_VI1_DATA10,
4406                 /* IP3_11 [1] */
4407                 FN_CS1_N_A26, FN_VI1_DATA9,
4408                 /* IP3_10 [1] */
4409                 FN_CS0_N, FN_VI1_DATA8,
4410                 /* IP3_9_8 [2] */
4411                 FN_A25, FN_SSL, FN_ATARD1_N, 0,
4412                 /* IP3_7_6 [2] */
4413                 FN_A24, FN_IO3, FN_EX_WAIT2, 0,
4414                 /* IP3_5_4 [2] */
4415                 FN_A23, FN_IO2, FN_MOUT6, FN_ATAWR1_N,
4416                 /* IP3_3_2 [2] */
4417                 FN_A22, FN_MISO_IO1, FN_MOUT5, FN_ATADIR1_N,
4418                 /* IP3_1_0 [2] */
4419                 FN_A21, FN_MOSI_IO0, FN_MOUT2, 0, }
4420         },
4421         { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
4422                              2, 2, 2, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 2) {
4423                 /* IP4_31_30 [2] */
4424                 FN_DU0_DG4, FN_LCDOUT12, FN_CC50_STATE12, 0,
4425                 /* IP4_29_28 [2] */
4426                 FN_DU0_DG3, FN_LCDOUT11, FN_CC50_STATE11, 0,
4427                 /* IP4_27_26 [2] */
4428                 FN_DU0_DG2, FN_LCDOUT10, FN_CC50_STATE10, 0,
4429                 /* IP4_25_23 [3] */
4430                 FN_DU0_DG1, FN_LCDOUT9, FN_SCIFA0_TXD_C, FN_I2C3_SDA_D,
4431                 FN_CC50_STATE9, 0, 0, 0,
4432                 /* IP4_22_20 [3] */
4433                 FN_DU0_DG0, FN_LCDOUT8, FN_SCIFA0_RXD_C, FN_I2C3_SCL_D,
4434                 FN_CC50_STATE8, 0, 0, 0,
4435                 /* IP4_19_18 [2] */
4436                 FN_DU0_DR7, FN_LCDOUT23, FN_CC50_STATE7, 0,
4437                 /* IP4_17_16 [2] */
4438                 FN_DU0_DR6, FN_LCDOUT22, FN_CC50_STATE6, 0,
4439                 /* IP4_15_14 [2] */
4440                 FN_DU0_DR5, FN_LCDOUT21, FN_CC50_STATE5, 0,
4441                 /* IP4_13_12 [2] */
4442                 FN_DU0_DR4, FN_LCDOUT20, FN_CC50_STATE4, 0,
4443                 /* IP4_11_10 [2] */
4444                 FN_DU0_DR3, FN_LCDOUT19, FN_CC50_STATE3, 0,
4445                 /* IP4_9_8 [2] */
4446                 FN_DU0_DR2, FN_LCDOUT18, FN_CC50_STATE2, 0,
4447                 /* IP4_7_5 [3] */
4448                 FN_DU0_DR1, FN_LCDOUT17, FN_SCIF5_TXD_C, FN_I2C2_SDA_D,
4449                 FN_CC50_STATE1, 0, 0, 0,
4450                 /* IP4_4_2 [3] */
4451                 FN_DU0_DR0, FN_LCDOUT16, FN_SCIF5_RXD_C, FN_I2C2_SCL_D,
4452                 FN_CC50_STATE0, 0, 0, 0,
4453                 /* IP4_1_0 [2] */
4454                 FN_EX_WAIT0, FN_CAN_CLK_B, FN_SCIF_CLK, FN_PWMFSW0, }
4455         },
4456         { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
4457                              2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 2, 2, 2) {
4458                 /* IP5_31_30 [2] */
4459                 FN_DU0_EXHSYNC_DU0_HSYNC, FN_QSTH_QHS, FN_CC50_STATE27, 0,
4460                 /* IP5_29_28 [2] */
4461                 FN_DU0_DOTCLKOUT1, FN_QSTVB_QVE, FN_CC50_STATE26, 0,
4462                 /* IP5_27_26 [2] */
4463                 FN_DU0_DOTCLKOUT0, FN_QCLK, FN_CC50_STATE25, 0,
4464                 /* IP5_25_24 [2] */
4465                 FN_DU0_DOTCLKIN, FN_QSTVA_QVS, FN_CC50_STATE24, 0,
4466                 /* IP5_23_22 [2] */
4467                 FN_DU0_DB7, FN_LCDOUT7, FN_CC50_STATE23, 0,
4468                 /* IP5_21_20 [2] */
4469                 FN_DU0_DB6, FN_LCDOUT6, FN_CC50_STATE22, 0,
4470                 /* IP5_19_18 [2] */
4471                 FN_DU0_DB5, FN_LCDOUT5, FN_CC50_STATE21, 0,
4472                 /* IP5_17_16 [2] */
4473                 FN_DU0_DB4, FN_LCDOUT4, FN_CC50_STATE20, 0,
4474                 /* IP5_15_14 [2] */
4475                 FN_DU0_DB3, FN_LCDOUT3, FN_CC50_STATE19, 0,
4476                 /* IP5_13_12 [2] */
4477                 FN_DU0_DB2, FN_LCDOUT2, FN_CC50_STATE18, 0,
4478                 /* IP5_11_9 [3] */
4479                 FN_DU0_DB1, FN_LCDOUT1, FN_SCIFA4_TXD_C, FN_I2C4_SDA_D,
4480                 FN_CAN0_TX_C, FN_CC50_STATE17, 0, 0,
4481                 /* IP5_8_6 [3] */
4482                 FN_DU0_DB0, FN_LCDOUT0, FN_SCIFA4_RXD_C, FN_I2C4_SCL_D,
4483                 FN_CAN0_RX_C, FN_CC50_STATE16, 0, 0,
4484                 /* IP5_5_4 [2] */
4485                 FN_DU0_DG7, FN_LCDOUT15, FN_CC50_STATE15, 0,
4486                 /* IP5_3_2 [2] */
4487                 FN_DU0_DG6, FN_LCDOUT14, FN_CC50_STATE14, 0,
4488                 /* IP5_1_0 [2] */
4489                 FN_DU0_DG5, FN_LCDOUT13, FN_CC50_STATE13, 0, }
4490         },
4491         { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
4492                              3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
4493                              2, 2) {
4494                 /* IP6_31_29 [3] */
4495                 FN_ETH_MDIO, FN_VI0_G0, FN_MSIOF2_RXD_B, FN_IIC0_SCL_D,
4496                 FN_AVB_TX_CLK, FN_ADIDATA, FN_AD_DI, 0,
4497                 /* IP6_28_26 [3] */
4498                 FN_VI0_VSYNC_N, FN_SCIF0_TXD_B, FN_I2C0_SDA_C,
4499                 FN_AUDIO_CLKOUT_B, FN_AVB_TX_EN, 0, 0, 0,
4500                 /* IP6_25_23 [3] */
4501                 FN_VI0_HSYNC_N, FN_SCIF0_RXD_B, FN_I2C0_SCL_C, FN_IERX_C,
4502                 FN_AVB_COL, 0, 0, 0,
4503                 /* IP6_22_20 [3] */
4504                 FN_VI0_FIELD, FN_I2C3_SDA, FN_SCIFA5_TXD_C, FN_IECLK_C,
4505                 FN_AVB_RX_ER, 0, 0, 0,
4506                 /* IP6_19_17 [3] */
4507                 FN_VI0_CLKENB, FN_I2C3_SCL, FN_SCIFA5_RXD_C, FN_IETX_C,
4508                 FN_AVB_RXD7, 0, 0, 0,
4509                 /* IP6_16 [1] */
4510                 FN_VI0_DATA7_VI0_B7, FN_AVB_RXD6,
4511                 /* IP6_15 [1] */
4512                 FN_VI0_DATA6_VI0_B6, FN_AVB_RXD5,
4513                 /* IP6_14 [1] */
4514                 FN_VI0_DATA5_VI0_B5, FN_AVB_RXD4,
4515                 /* IP6_13 [1] */
4516                 FN_VI0_DATA4_VI0_B4, FN_AVB_RXD3,
4517                 /* IP6_12 [1] */
4518                 FN_VI0_DATA3_VI0_B3, FN_AVB_RXD2,
4519                 /* IP6_11 [1] */
4520                 FN_VI0_DATA2_VI0_B2, FN_AVB_RXD1,
4521                 /* IP6_10 [1] */
4522                 FN_VI0_DATA1_VI0_B1, FN_AVB_RXD0,
4523                 /* IP6_9 [1] */
4524                 FN_VI0_DATA0_VI0_B0, FN_AVB_RX_DV,
4525                 /* IP6_8 [1] */
4526                 FN_VI0_CLK, FN_AVB_RX_CLK,
4527                 /* IP6_7_6 [2] */
4528                 FN_DU0_CDE, FN_QPOLB, FN_CC50_STATE31, 0,
4529                 /* IP6_5_4 [2] */
4530                 FN_DU0_DISP, FN_QPOLA, FN_CC50_STATE30, 0,
4531                 /* IP6_3_2 [2] */
4532                 FN_DU0_EXODDF_DU0_ODDF_DISP_CDE, FN_QCPV_QDE, FN_CC50_STATE29,
4533                 0,
4534                 /* IP6_1_0 [2] */
4535                 FN_DU0_EXVSYNC_DU0_VSYNC, FN_QSTB_QHE, FN_CC50_STATE28, 0, }
4536         },
4537         { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
4538                              1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4539                 /* IP7_31 [1] */
4540                 FN_DREQ0_N, FN_SCIFB1_RXD,
4541                 /* IP7_30 [1] */
4542                 0, 0,
4543                 /* IP7_29_27 [3] */
4544                 FN_ETH_TXD0, FN_VI0_R2, FN_SCIF3_RXD_B, FN_I2C4_SCL_E,
4545                 FN_AVB_GTX_CLK, FN_SSI_WS6_B, 0, 0,
4546                 /* IP7_26_24 [3] */
4547                 FN_ETH_MAGIC, FN_VI0_R1, FN_SCIF3_SCK_B, FN_AVB_TX_ER,
4548                 FN_SSI_SCK6_B, 0, 0, 0,
4549                 /* IP7_23_21 [3] */
4550                 FN_ETH_TX_EN, FN_VI0_R0, FN_SCIF2_TXD_C, FN_IIC1_SDA_D,
4551                 FN_AVB_TXD7, FN_SSI_SDATA5_B, 0, 0,
4552                 /* IP7_20_18 [3] */
4553                 FN_ETH_TXD1, FN_VI0_G7, FN_SCIF2_RXD_C, FN_IIC1_SCL_D,
4554                 FN_AVB_TXD6, FN_SSI_WS5_B, 0, 0,
4555                 /* IP7_17_15 [3] */
4556                 FN_ETH_REFCLK, FN_VI0_G6, FN_SCIF2_SCK_C, FN_AVB_TXD5,
4557                 FN_SSI_SCK5_B, 0, 0, 0,
4558                 /* IP7_14_12 [3] */
4559                 FN_ETH_LINK, FN_VI0_G5, FN_MSIOF2_SS2_B, FN_SCIF4_TXD_D,
4560                 FN_AVB_TXD4, FN_ADICHS2, 0, 0,
4561                 /* IP7_11_9 [3] */
4562                 FN_ETH_RXD1, FN_VI0_G4, FN_MSIOF2_SS1_B, FN_SCIF4_RXD_D,
4563                 FN_AVB_TXD3, FN_ADICHS1, 0, 0,
4564                 /* IP7_8_6 [3] */
4565                 FN_ETH_RXD0, FN_VI0_G3, FN_MSIOF2_SYNC_B, FN_CAN0_TX_B,
4566                 FN_AVB_TXD2, FN_ADICHS0, FN_AD_NCS_N, 0,
4567                 /* IP7_5_3 [3] */
4568                 FN_ETH_RX_ER, FN_VI0_G2, FN_MSIOF2_SCK_B, FN_CAN0_RX_B,
4569                 FN_AVB_TXD1, FN_ADICLK, FN_AD_CLK, 0,
4570                 /* IP7_2_0 [3] */
4571                 FN_ETH_CRS_DV, FN_VI0_G1, FN_MSIOF2_TXD_B, FN_IIC0_SDA_D,
4572                 FN_AVB_TXD0, FN_ADICS_SAMP, FN_AD_DO, 0, }
4573         },
4574         { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
4575                              3, 3, 3, 3, 3, 2, 3, 3, 3, 3, 3) {
4576                 /* IP8_31_29 [3] */
4577                 FN_MSIOF0_RXD, FN_SCIF5_RXD, FN_I2C2_SCL_C, FN_DU1_DR2,
4578                 FN_RIF1_D0_B, FN_TS_SDEN_D, FN_FMCLK_C, FN_RDS_CLK,
4579                 /* IP8_28_26 [3] */
4580                 FN_I2C1_SDA, FN_SCIF4_TXD, FN_IRQ5, FN_DU1_DR1,
4581                 FN_RIF1_CLK_B, FN_TS_SCK_D, FN_BPFCLK_C, 0,
4582                 /* IP8_25_23 [3] */
4583                 FN_I2C1_SCL, FN_SCIF4_RXD, FN_PWM5_B, FN_DU1_DR0,
4584                 FN_RIF1_SYNC_B, FN_TS_SDATA_D, FN_TPUTO1_B, 0,
4585                 /* IP8_22_20 [3] */
4586                 FN_I2C0_SDA, FN_SCIF0_TXD_C, FN_TPUTO0, FN_CAN_CLK,
4587                 FN_DVC_MUTE, FN_CAN1_TX_D, 0, 0,
4588                 /* IP8_19_17 [3] */
4589                 FN_I2C0_SCL, FN_SCIF0_RXD_C, FN_PWM5, FN_TCLK1_B,
4590                 FN_AVB_GTXREFCLK, FN_CAN1_RX_D, FN_TPUTO0_B, 0,
4591                 /* IP8_16_15 [2] */
4592                 FN_HSCIF0_HSCK, FN_SCIF_CLK_B, FN_AVB_CRS, FN_AUDIO_CLKC_B,
4593                 /* IP8_14_12 [3] */
4594                 FN_HSCIF0_HRTS_N, FN_VI0_R7, FN_SCIF0_TXD_D, FN_I2C0_SDA_E,
4595                 FN_AVB_PHY_INT, FN_SSI_SDATA8_B, 0, 0,
4596                 /* IP8_11_9 [3] */
4597                 FN_HSCIF0_HCTS_N, FN_VI0_R6, FN_SCIF0_RXD_D, FN_I2C0_SCL_E,
4598                 FN_AVB_MAGIC, FN_SSI_SDATA7_B, 0, 0,
4599                 /* IP8_8_6 [3] */
4600                 FN_HSCIF0_HTX, FN_VI0_R5, FN_I2C1_SDA_C, FN_AUDIO_CLKB_B,
4601                 FN_AVB_LINK, FN_SSI_WS78_B, 0, 0,
4602                 /* IP8_5_3 [3] */
4603                 FN_HSCIF0_HRX, FN_VI0_R4, FN_I2C1_SCL_C, FN_AUDIO_CLKA_B,
4604                 FN_AVB_MDIO, FN_SSI_SCK78_B, 0, 0,
4605                 /* IP8_2_0 [3] */
4606                 FN_ETH_MDC, FN_VI0_R3, FN_SCIF3_TXD_B, FN_I2C4_SDA_E,
4607                 FN_AVB_MDC, FN_SSI_SDATA6_B, 0, 0, }
4608         },
4609         { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
4610                              1, 3, 3, 3, 3, 2, 2, 3, 3, 3, 3, 3, 3) {
4611                 /* IP9_31 [1] */
4612                 0, 0,
4613                 /* IP9_30_28 [3] */
4614                 FN_SCIF1_SCK, FN_PWM3, FN_TCLK2, FN_DU1_DG5,
4615                 FN_SSI_SDATA1_B, FN_CAN_TXCLK, FN_CC50_STATE34, 0,
4616                 /* IP9_27_25 [3] */
4617                 FN_HSCIF1_HRTS_N, FN_SCIFA4_TXD, FN_IERX, FN_DU1_DG4,
4618                 FN_SSI_WS1_B, FN_CAN_STEP0, FN_CC50_STATE33, 0,
4619                 /* IP9_24_22 [3] */
4620                 FN_HSCIF1_HCTS_N, FN_SCIFA4_RXD, FN_IECLK, FN_DU1_DG3,
4621                 FN_SSI_SCK1_B, FN_CAN_DEBUG_HW_TRIGGER, FN_CC50_STATE32, 0,
4622                 /* IP9_21_19 [3] */
4623                 FN_HSCIF1_HSCK, FN_PWM2, FN_IETX, FN_DU1_DG2,
4624                 FN_REMOCON_B, FN_SPEEDIN_B, FN_VSP_B, 0,
4625                 /* IP9_18_17 [2] */
4626                 FN_HSCIF1_HTX, FN_I2C4_SDA, FN_TPUTO1, FN_DU1_DG1,
4627                 /* IP9_16_15 [2] */
4628                 FN_HSCIF1_HRX, FN_I2C4_SCL, FN_PWM6, FN_DU1_DG0,
4629                 /* IP9_14_12 [3] */
4630                 FN_MSIOF0_SS2, FN_SCIFA0_TXD, FN_TS_SPSYNC, FN_DU1_DR7,
4631                 FN_RIF1_D1, FN_FMIN_B, FN_RDS_DATA_B, 0,
4632                 /* IP9_11_9 [3] */
4633                 FN_MSIOF0_SS1, FN_SCIFA0_RXD, FN_TS_SDEN, FN_DU1_DR6,
4634                 FN_RIF1_D0, FN_FMCLK_B, FN_RDS_CLK_B, 0,
4635                 /* IP9_8_6 [3] */
4636                 FN_MSIOF0_SYNC, FN_PWM1, FN_TS_SCK, FN_DU1_DR5,
4637                 FN_RIF1_CLK, FN_BPFCLK_B, 0, 0,
4638                 /* IP9_5_3 [3] */
4639                 FN_MSIOF0_SCK, FN_IRQ0, FN_TS_SDATA, FN_DU1_DR4,
4640                 FN_RIF1_SYNC, FN_TPUTO1_C, 0, 0,
4641                 /* IP9_2_0 [3] */
4642                 FN_MSIOF0_TXD, FN_SCIF5_TXD, FN_I2C2_SDA_C, FN_DU1_DR3,
4643                 FN_RIF1_D1_B, FN_TS_SPSYNC_D, FN_FMIN_C, FN_RDS_DATA, }
4644         },
4645         { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
4646                              2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4647                 /* IP10_31_30 [2] */
4648                 FN_SSI_SCK5, FN_SCIFA3_SCK, FN_DU1_DOTCLKIN, FN_CAN_DEBUGOUT10,
4649                 /* IP10_29_27 [3] */
4650                 FN_I2C2_SDA, FN_SCIFA5_TXD, FN_DU1_DB7, FN_AUDIO_CLKOUT_C,
4651                 FN_CAN_DEBUGOUT9, 0, 0, 0,
4652                 /* IP10_26_24 [3] */
4653                 FN_I2C2_SCL, FN_SCIFA5_RXD, FN_DU1_DB6, FN_AUDIO_CLKC_C,
4654                 FN_SSI_SDATA4_B, FN_CAN_DEBUGOUT8, 0, 0,
4655                 /* IP10_23_21 [3] */
4656                 FN_SCIF3_TXD, FN_I2C1_SDA_E, FN_FMIN_D, FN_DU1_DB5,
4657                 FN_AUDIO_CLKB_C, FN_SSI_WS4_B, FN_CAN_DEBUGOUT7, FN_RDS_DATA_C,
4658                 /* IP10_20_18 [3] */
4659                 FN_SCIF3_RXD, FN_I2C1_SCL_E, FN_FMCLK_D, FN_DU1_DB4,
4660                 FN_AUDIO_CLKA_C, FN_SSI_SCK4_B, FN_CAN_DEBUGOUT6, FN_RDS_CLK_C,
4661                 /* IP10_17_15 [3] */
4662                 FN_SCIF3_SCK, FN_IRQ2, FN_BPFCLK_D, FN_DU1_DB3,
4663                 FN_SSI_SDATA9_B, FN_TANS2, FN_CAN_DEBUGOUT5, FN_CC50_OSCOUT,
4664                 /* IP10_14_12 [3] */
4665                 FN_SCIF2_SCK, FN_IRQ1, FN_DU1_DB2, FN_SSI_WS9_B,
4666                 FN_USB0_IDIN, FN_CAN_DEBUGOUT4, FN_CC50_STATE39, 0,
4667                 /* IP10_11_9 [3] */
4668                 FN_SCIF2_TXD, FN_IIC1_SDA, FN_DU1_DB1, FN_SSI_SCK9_B,
4669                 FN_USB0_OVC1, FN_CAN_DEBUGOUT3, FN_CC50_STATE38, 0,
4670                 /* IP10_8_6 [3] */
4671                 FN_SCIF2_RXD, FN_IIC1_SCL, FN_DU1_DB0, FN_SSI_SDATA2_B,
4672                 FN_USB0_EXTLP, FN_CAN_DEBUGOUT2, FN_CC50_STATE37, 0,
4673                 /* IP10_5_3 [3] */
4674                 FN_SCIF1_TXD, FN_IIC0_SDA, FN_DU1_DG7, FN_SSI_WS2_B,
4675                 FN_CAN_DEBUGOUT1, FN_CC50_STATE36, 0, 0,
4676                 /* IP10_2_0 [3] */
4677                 FN_SCIF1_RXD, FN_IIC0_SCL, FN_DU1_DG6, FN_SSI_SCK2_B,
4678                 FN_CAN_DEBUGOUT0, FN_CC50_STATE35, 0, 0, }
4679         },
4680         { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
4681                              2, 3, 3, 3, 3, 2, 2, 3, 3, 2, 3, 3) {
4682                 /* IP11_31_30 [2] */
4683                 0, 0, 0, 0,
4684                 /* IP11_29_27 [3] */
4685                 FN_SSI_SDATA0, FN_MSIOF1_SCK_B, FN_PWM0_B, FN_ADICLK_B,
4686                 FN_AD_CLK_B, 0, 0, 0,
4687                 /* IP11_26_24 [3] */
4688                 FN_SSI_WS0129, FN_MSIOF1_TXD_B, FN_SCIF5_TXD_D, FN_ADICS_SAMP_B,
4689                 FN_AD_DO_B, 0, 0, 0,
4690                 /* IP11_23_21 [3] */
4691                 FN_SSI_SCK0129, FN_MSIOF1_RXD_B, FN_SCIF5_RXD_D, FN_ADIDATA_B,
4692                 FN_AD_DI_B, FN_PCMWE_N, 0, 0,
4693                 /* IP11_20_18 [3] */
4694                 FN_SSI_SDATA7, FN_SCIFA2_TXD_B, FN_IRQ8, FN_AUDIO_CLKA_D,
4695                 FN_CAN_CLK_D, FN_PCMOE_N, 0, 0,
4696                 /* IP11_17_16 [2] */
4697                 FN_SSI_WS78, FN_SCIFA2_RXD_B, FN_IIC0_SCL_C, FN_DU1_CDE,
4698                 /* IP11_15_14 [2] */
4699                 FN_SSI_SCK78, FN_SCIFA2_SCK_B, FN_IIC0_SDA_C, FN_DU1_DISP,
4700                 /* IP11_13_11 [3] */
4701                 FN_SSI_SDATA6, FN_SCIFA1_TXD_B, FN_I2C4_SDA_C,
4702                 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_CAN_DEBUGOUT15, 0, 0, 0,
4703                 /* IP11_10_8 [3] */
4704                 FN_SSI_WS6, FN_SCIFA1_RXD_B, FN_I2C4_SCL_C,
4705                 FN_DU1_EXVSYNC_DU1_VSYNC, FN_CAN_DEBUGOUT14, 0, 0, 0,
4706                 /* IP11_7_6 [2] */
4707                 FN_SSI_SCK6, FN_SCIFA1_SCK_B, FN_DU1_EXHSYNC_DU1_HSYNC,
4708                 FN_CAN_DEBUGOUT13,
4709                 /* IP11_5_3 [3] */
4710                 FN_SSI_SDATA5, FN_SCIFA3_TXD, FN_I2C3_SDA_C, FN_DU1_DOTCLKOUT1,
4711                 FN_CAN_DEBUGOUT12, 0, 0, 0,
4712                 /* IP11_2_0 [3] */
4713                 FN_SSI_WS5, FN_SCIFA3_RXD, FN_I2C3_SCL_C, FN_DU1_DOTCLKOUT0,
4714                 FN_CAN_DEBUGOUT11, 0, 0, 0, }
4715         },
4716         { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
4717                              2, 3, 3, 3, 3, 3, 2, 2, 2, 3, 3, 3) {
4718                 /* IP12_31_30 [2] */
4719                 0, 0, 0, 0,
4720                 /* IP12_29_27 [3] */
4721                 FN_SSI_SCK2, FN_HSCIF1_HTX_B, FN_VI1_DATA2, FN_MDATA,
4722                 FN_ATAWR0_N, FN_ETH_RXD1_B, 0, 0,
4723                 /* IP12_26_24 [3] */
4724                 FN_SSI_SDATA1, FN_HSCIF1_HRX_B, FN_VI1_DATA1, FN_SDATA,
4725                 FN_ATAG0_N, FN_ETH_RXD0_B, 0, 0,
4726                 /* IP12_23_21 [3] */
4727                 FN_SSI_WS1, FN_SCIF1_TXD_B, FN_IIC1_SDA_C, FN_VI1_DATA0,
4728                 FN_CAN0_TX_D, FN_AVB_AVTP_MATCH, FN_ETH_RX_ER_B, 0,
4729                 /* IP12_20_18 [3] */
4730                 FN_SSI_SCK1, FN_SCIF1_RXD_B, FN_IIC1_SCL_C, FN_VI1_CLK,
4731                 FN_CAN0_RX_D, FN_AVB_AVTP_CAPTURE, FN_ETH_CRS_DV_B, 0,
4732                 /* IP12_17_15 [3] */
4733                 FN_SSI_SDATA8, FN_SCIF1_SCK_B, FN_PWM1_B, FN_IRQ9,
4734                 FN_REMOCON, FN_DACK2, FN_ETH_MDIO_B, 0,
4735                 /* IP12_14_13 [2] */
4736                 FN_SSI_SDATA4, FN_MLB_DAT, FN_IERX_B, FN_IRD_SCK,
4737                 /* IP12_12_11 [2] */
4738                 FN_SSI_WS4, FN_MLB_SIG, FN_IECLK_B, FN_IRD_RX,
4739                 /* IP12_10_9 [2] */
4740                 FN_SSI_SCK4, FN_MLB_CLK, FN_IETX_B, FN_IRD_TX,
4741                 /* IP12_8_6 [3] */
4742                 FN_SSI_SDATA3, FN_MSIOF1_SS2_B, FN_SCIFA1_TXD_C, FN_ADICHS2_B,
4743                 FN_CAN1_TX_C, FN_DREQ2_N, 0, 0,
4744                 /* IP12_5_3 [3] */
4745                 FN_SSI_WS34, FN_MSIOF1_SS1_B, FN_SCIFA1_RXD_C, FN_ADICHS1_B,
4746                 FN_CAN1_RX_C, FN_DACK1_B, 0, 0,
4747                 /* IP12_2_0 [3] */
4748                 FN_SSI_SCK34, FN_MSIOF1_SYNC_B, FN_SCIFA1_SCK_C, FN_ADICHS0_B,
4749                 FN_AD_NCS_N_B, FN_DREQ1_N_B, 0, 0, }
4750         },
4751         { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
4752                              1, 1, 1, 1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
4753                 /* IP13_31 [1] */
4754                 0, 0,
4755                 /* IP13_30 [1] */
4756                 0, 0,
4757                 /* IP13_29 [1] */
4758                 0, 0,
4759                 /* IP13_28 [1] */
4760                 0, 0,
4761                 /* IP13_27 [1] */
4762                 0, 0,
4763                 /* IP13_26_24 [3] */
4764                 FN_AUDIO_CLKOUT, FN_I2C4_SDA_B, FN_SCIFA5_TXD_D, FN_VI1_VSYNC_N,
4765                 FN_TS_SPSYNC_C, FN_RIF0_D1_B, FN_FMIN_E, FN_RDS_DATA_D,
4766                 /* IP13_23_21 [3] */
4767                 FN_AUDIO_CLKC, FN_I2C4_SCL_B, FN_SCIFA5_RXD_D, FN_VI1_HSYNC_N,
4768                 FN_TS_SDEN_C, FN_RIF0_D0_B, FN_FMCLK_E, FN_RDS_CLK_D,
4769                 /* IP13_20_18 [3] */
4770                 FN_AUDIO_CLKB, FN_I2C0_SDA_B, FN_SCIFA4_TXD_D, FN_VI1_FIELD,
4771                 FN_TS_SCK_C, FN_RIF0_CLK_B, FN_BPFCLK_E, FN_ETH_MDC_B,
4772                 /* IP13_17_15 [3] */
4773                 FN_AUDIO_CLKA, FN_I2C0_SCL_B, FN_SCIFA4_RXD_D, FN_VI1_CLKENB,
4774                 FN_TS_SDATA_C, FN_RIF0_SYNC_B, FN_ETH_TXD0_B, 0,
4775                 /* IP13_14_12 [3] */
4776                 FN_SSI_SDATA9, FN_SCIF2_TXD_B, FN_I2C3_SDA_E, FN_VI1_DATA7,
4777                 FN_ATADIR0_N, FN_ETH_MAGIC_B, 0, 0,
4778                 /* IP13_11_9 [3] */
4779                 FN_SSI_WS9, FN_SCIF2_RXD_B, FN_I2C3_SCL_E, FN_VI1_DATA6,
4780                 FN_ATARD0_N, FN_ETH_TX_EN_B, 0, 0,
4781                 /* IP13_8_6 [3] */
4782                 FN_SSI_SCK9, FN_SCIF2_SCK_B, FN_PWM2_B, FN_VI1_DATA5,
4783                 FN_MTS_N, FN_EX_WAIT1, FN_ETH_TXD1_B, 0,
4784                 /* IP13_5_3 [2] */
4785                 FN_SSI_SDATA2, FN_HSCIF1_HRTS_N_B, FN_SCIFA0_TXD_D,
4786                 FN_VI1_DATA4, FN_STM_N, FN_ATACS10_N, FN_ETH_REFCLK_B, 0,
4787                 /* IP13_2_0 [3] */
4788                 FN_SSI_WS2, FN_HSCIF1_HCTS_N_B, FN_SCIFA0_RXD_D, FN_VI1_DATA3,
4789                 FN_SCKZ, FN_ATACS00_N, FN_ETH_LINK_B, 0, }
4790         },
4791         { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4792                              2, 1, 2, 3, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 3,
4793                              2, 1) {
4794                 /* SEL_ADG [2] */
4795                 FN_SEL_ADG_0, FN_SEL_ADG_1, FN_SEL_ADG_2, FN_SEL_ADG_3,
4796                 /* SEL_ADI [1] */
4797                 FN_SEL_ADI_0, FN_SEL_ADI_1,
4798                 /* SEL_CAN [2] */
4799                 FN_SEL_CAN_0, FN_SEL_CAN_1, FN_SEL_CAN_2, FN_SEL_CAN_3,
4800                 /* SEL_DARC [3] */
4801                 FN_SEL_DARC_0, FN_SEL_DARC_1, FN_SEL_DARC_2, FN_SEL_DARC_3,
4802                 FN_SEL_DARC_4, 0, 0, 0,
4803                 /* SEL_DR0 [1] */
4804                 FN_SEL_DR0_0, FN_SEL_DR0_1,
4805                 /* SEL_DR1 [1] */
4806                 FN_SEL_DR1_0, FN_SEL_DR1_1,
4807                 /* SEL_DR2 [1] */
4808                 FN_SEL_DR2_0, FN_SEL_DR2_1,
4809                 /* SEL_DR3 [1] */
4810                 FN_SEL_DR3_0, FN_SEL_DR3_1,
4811                 /* SEL_ETH [1] */
4812                 FN_SEL_ETH_0, FN_SEL_ETH_1,
4813                 /* SLE_FSN [1] */
4814                 FN_SEL_FSN_0, FN_SEL_FSN_1,
4815                 /* SEL_IC200 [3] */
4816                 FN_SEL_I2C00_0, FN_SEL_I2C00_1, FN_SEL_I2C00_2, FN_SEL_I2C00_3,
4817                 FN_SEL_I2C00_4, 0, 0, 0,
4818                 /* SEL_I2C01 [3] */
4819                 FN_SEL_I2C01_0, FN_SEL_I2C01_1, FN_SEL_I2C01_2, FN_SEL_I2C01_3,
4820                 FN_SEL_I2C01_4, 0, 0, 0,
4821                 /* SEL_I2C02 [3] */
4822                 FN_SEL_I2C02_0, FN_SEL_I2C02_1, FN_SEL_I2C02_2, FN_SEL_I2C02_3,
4823                 FN_SEL_I2C02_4, 0, 0, 0,
4824                 /* SEL_I2C03 [3] */
4825                 FN_SEL_I2C03_0, FN_SEL_I2C03_1, FN_SEL_I2C03_2, FN_SEL_I2C03_3,
4826                 FN_SEL_I2C03_4, 0, 0, 0,
4827                 /* SEL_I2C04 [3] */
4828                 FN_SEL_I2C04_0, FN_SEL_I2C04_1, FN_SEL_I2C04_2, FN_SEL_I2C04_3,
4829                 FN_SEL_I2C04_4, 0, 0, 0,
4830                 /* SEL_IIC00 [2] */
4831                 FN_SEL_IIC00_0, FN_SEL_IIC00_1, FN_SEL_IIC00_2, FN_SEL_IIC00_3,
4832                 /* SEL_AVB [1] */
4833                 FN_SEL_AVB_0, FN_SEL_AVB_1, }
4834         },
4835         { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4836                              2, 2, 1, 1, 1, 1, 1, 1, 2, 2, 1, 1, 2, 2, 1, 1,
4837                              2, 2, 2, 1, 1, 2) {
4838                 /* SEL_IEB [2] */
4839                 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
4840                 /* SEL_IIC0 [2] */
4841                 FN_SEL_IIC01_0, FN_SEL_IIC01_1, FN_SEL_IIC01_2, FN_SEL_IIC01_3,
4842                 /* SEL_LBS [1] */
4843                 FN_SEL_LBS_0, FN_SEL_LBS_1,
4844                 /* SEL_MSI1 [1] */
4845                 FN_SEL_MSI1_0, FN_SEL_MSI1_1,
4846                 /* SEL_MSI2 [1] */
4847                 FN_SEL_MSI2_0, FN_SEL_MSI2_1,
4848                 /* SEL_RAD [1] */
4849                 FN_SEL_RAD_0, FN_SEL_RAD_1,
4850                 /* SEL_RCN [1] */
4851                 FN_SEL_RCN_0, FN_SEL_RCN_1,
4852                 /* SEL_RSP [1] */
4853                 FN_SEL_RSP_0, FN_SEL_RSP_1,
4854                 /* SEL_SCIFA0 [2] */
4855                 FN_SEL_SCIFA0_0, FN_SEL_SCIFA0_1, FN_SEL_SCIFA0_2,
4856                 FN_SEL_SCIFA0_3,
4857                 /* SEL_SCIFA1 [2] */
4858                 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
4859                 /* SEL_SCIFA2 [1] */
4860                 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
4861                 /* SEL_SCIFA3 [1] */
4862                 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1,
4863                 /* SEL_SCIFA4 [2] */
4864                 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
4865                 FN_SEL_SCIFA4_3,
4866                 /* SEL_SCIFA5 [2] */
4867                 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
4868                 FN_SEL_SCIFA5_3,
4869                 /* SEL_SPDM [1] */
4870                 FN_SEL_SPDM_0, FN_SEL_SPDM_1,
4871                 /* SEL_TMU [1] */
4872                 FN_SEL_TMU_0, FN_SEL_TMU_1,
4873                 /* SEL_TSIF0 [2] */
4874                 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4875                 /* SEL_CAN0 [2] */
4876                 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4877                 /* SEL_CAN1 [2] */
4878                 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
4879                 /* SEL_HSCIF0 [1] */
4880                 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1,
4881                 /* SEL_HSCIF1 [1] */
4882                 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
4883                 /* SEL_RDS [2] */
4884                 FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2, FN_SEL_RDS_3, }
4885         },
4886         { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4887                              2, 2, 2, 1, 3, 2, 1, 1, 1, 1, 1, 1, 1, 1,
4888                              1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1) {
4889                 /* SEL_SCIF0 [2] */
4890                 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
4891                 /* SEL_SCIF1 [2] */
4892                 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, 0,
4893                 /* SEL_SCIF2 [2] */
4894                 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, 0,
4895                 /* SEL_SCIF3 [1] */
4896                 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1,
4897                 /* SEL_SCIF4 [3] */
4898                 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, FN_SEL_SCIF4_3,
4899                 FN_SEL_SCIF4_4, 0, 0, 0,
4900                 /* SEL_SCIF5 [2] */
4901                 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1, FN_SEL_SCIF5_2, FN_SEL_SCIF5_3,
4902                 /* SEL_SSI1 [1] */
4903                 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
4904                 /* SEL_SSI2 [1] */
4905                 FN_SEL_SSI2_0, FN_SEL_SSI2_1,
4906                 /* SEL_SSI4 [1] */
4907                 FN_SEL_SSI4_0, FN_SEL_SSI4_1,
4908                 /* SEL_SSI5 [1] */
4909                 FN_SEL_SSI5_0, FN_SEL_SSI5_1,
4910                 /* SEL_SSI6 [1] */
4911                 FN_SEL_SSI6_0, FN_SEL_SSI6_1,
4912                 /* SEL_SSI7 [1] */
4913                 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
4914                 /* SEL_SSI8 [1] */
4915                 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
4916                 /* SEL_SSI9 [1] */
4917                 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
4918                 /* RESERVED [1] */
4919                 0, 0,
4920                 /* RESERVED [1] */
4921                 0, 0,
4922                 /* RESERVED [1] */
4923                 0, 0,
4924                 /* RESERVED [1] */
4925                 0, 0,
4926                 /* RESERVED [1] */
4927                 0, 0,
4928                 /* RESERVED [1] */
4929                 0, 0,
4930                 /* RESERVED [1] */
4931                 0, 0,
4932                 /* RESERVED [1] */
4933                 0, 0,
4934                 /* RESERVED [1] */
4935                 0, 0,
4936                 /* RESERVED [1] */
4937                 0, 0,
4938                 /* RESERVED [1] */
4939                 0, 0,
4940                 /* RESERVED [1] */
4941                 0, 0, }
4942         },
4943         { },
4944 };
4945
4946 const struct sh_pfc_soc_info r8a7794_pinmux_info = {
4947         .name = "r8a77940_pfc",
4948         .unlock_reg = 0xe6060000, /* PMMR */
4949
4950         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4951
4952         .pins = pinmux_pins,
4953         .nr_pins = ARRAY_SIZE(pinmux_pins),
4954         .groups = pinmux_groups,
4955         .nr_groups = ARRAY_SIZE(pinmux_groups),
4956         .functions = pinmux_functions,
4957         .nr_functions = ARRAY_SIZE(pinmux_functions),
4958
4959         .cfg_regs = pinmux_config_regs,
4960
4961         .pinmux_data = pinmux_data,
4962         .pinmux_data_size = ARRAY_SIZE(pinmux_data),
4963 };